2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
25 #include <linux/firmware.h>
30 #include "radeon_ucode.h"
33 static int ci_set_smc_sram_address(struct radeon_device *rdev,
34 u32 smc_address, u32 limit)
38 if ((smc_address + 3) > limit)
41 WREG32(SMC_IND_INDEX_0, smc_address);
42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
47 int ci_copy_bytes_to_smc(struct radeon_device *rdev,
48 u32 smc_start_address,
49 const u8 *src, u32 byte_count, u32 limit)
52 u32 data, original_data;
57 if (smc_start_address & 3)
59 if ((smc_start_address + byte_count) > limit)
62 addr = smc_start_address;
64 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
65 while (byte_count >= 4) {
66 /* SMC address space is BE */
67 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
69 ret = ci_set_smc_sram_address(rdev, addr, limit);
73 WREG32(SMC_IND_DATA_0, data);
80 /* RMW for the final bytes */
84 ret = ci_set_smc_sram_address(rdev, addr, limit);
88 original_data = RREG32(SMC_IND_DATA_0);
90 extra_shift = 8 * (4 - byte_count);
92 while (byte_count > 0) {
93 data = (data << 8) + *src++;
99 data |= (original_data & ~((~0UL) << extra_shift));
101 ret = ci_set_smc_sram_address(rdev, addr, limit);
105 WREG32(SMC_IND_DATA_0, data);
109 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
114 void ci_start_smc(struct radeon_device *rdev)
116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
122 void ci_reset_smc(struct radeon_device *rdev)
124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
130 int ci_program_jump_on_start(struct radeon_device *rdev)
132 static const u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };
134 return ci_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
137 void ci_stop_smc_clock(struct radeon_device *rdev)
139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
146 void ci_start_smc_clock(struct radeon_device *rdev)
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
155 bool ci_is_smc_running(struct radeon_device *rdev)
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
158 u32 pc_c = RREG32_SMC(SMC_PC_C);
160 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c))
166 PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
171 if (!ci_is_smc_running(rdev))
172 return PPSMC_Result_Failed;
174 WREG32(SMC_MESSAGE_0, msg);
176 for (i = 0; i < rdev->usec_timeout; i++) {
177 tmp = RREG32(SMC_RESP_0);
182 tmp = RREG32(SMC_RESP_0);
184 return (PPSMC_Result)tmp;
188 PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)
193 if (!ci_is_smc_running(rdev))
194 return PPSMC_Result_OK;
196 for (i = 0; i < rdev->usec_timeout; i++) {
197 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
198 if ((tmp & CKEN) == 0)
203 return PPSMC_Result_OK;
207 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit)
210 u32 ucode_start_address;
219 const struct smc_firmware_header_v1_0 *hdr =
220 (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data;
222 radeon_ucode_print_smc_hdr(&hdr->header);
224 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
225 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
227 (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
229 switch (rdev->family) {
231 ucode_start_address = BONAIRE_SMC_UCODE_START;
232 ucode_size = BONAIRE_SMC_UCODE_SIZE;
235 ucode_start_address = HAWAII_SMC_UCODE_START;
236 ucode_size = HAWAII_SMC_UCODE_SIZE;
239 DRM_ERROR("unknown asic in smc ucode loader\n");
243 src = (const u8 *)rdev->smc_fw->data;
249 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
250 WREG32(SMC_IND_INDEX_0, ucode_start_address);
251 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
252 while (ucode_size >= 4) {
253 /* SMC address space is BE */
254 data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
256 WREG32(SMC_IND_DATA_0, data);
261 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
262 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
267 int ci_read_smc_sram_dword(struct radeon_device *rdev,
268 u32 smc_address, u32 *value, u32 limit)
273 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
274 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
276 *value = RREG32(SMC_IND_DATA_0);
277 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
282 int ci_write_smc_sram_dword(struct radeon_device *rdev,
283 u32 smc_address, u32 value, u32 limit)
288 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
289 ret = ci_set_smc_sram_address(rdev, smc_address, limit);
291 WREG32(SMC_IND_DATA_0, value);
292 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);