2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
32 #include "cik_blit_shaders.h"
33 #include "radeon_ucode.h"
34 #include "clearstate_ci.h"
36 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
37 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
38 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
39 MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
40 MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
41 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
42 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
43 MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
44 MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
45 MODULE_FIRMWARE("radeon/HAWAII_me.bin");
46 MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
47 MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
48 MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
49 MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
50 MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
51 MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
52 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
53 MODULE_FIRMWARE("radeon/KAVERI_me.bin");
54 MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
55 MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
56 MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
57 MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
58 MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
59 MODULE_FIRMWARE("radeon/KABINI_me.bin");
60 MODULE_FIRMWARE("radeon/KABINI_ce.bin");
61 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
62 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
63 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
65 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
66 extern void r600_ih_ring_fini(struct radeon_device *rdev);
67 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
68 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
69 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
70 extern void sumo_rlc_fini(struct radeon_device *rdev);
71 extern int sumo_rlc_init(struct radeon_device *rdev);
72 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
73 extern void si_rlc_reset(struct radeon_device *rdev);
74 extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
75 extern int cik_sdma_resume(struct radeon_device *rdev);
76 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
77 extern void cik_sdma_fini(struct radeon_device *rdev);
78 static void cik_rlc_stop(struct radeon_device *rdev);
79 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
80 static void cik_program_aspm(struct radeon_device *rdev);
81 static void cik_init_pg(struct radeon_device *rdev);
82 static void cik_init_cg(struct radeon_device *rdev);
83 static void cik_fini_pg(struct radeon_device *rdev);
84 static void cik_fini_cg(struct radeon_device *rdev);
85 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
88 /* get temperature in millidegrees */
89 int ci_get_temp(struct radeon_device *rdev)
94 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
100 actual_temp = temp & 0x1ff;
102 actual_temp = actual_temp * 1000;
107 /* get temperature in millidegrees */
108 int kv_get_temp(struct radeon_device *rdev)
113 temp = RREG32_SMC(0xC0300E0C);
116 actual_temp = (temp / 8) - 49;
120 actual_temp = actual_temp * 1000;
126 * Indirect registers accessor
128 u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
133 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
134 WREG32(PCIE_INDEX, reg);
135 (void)RREG32(PCIE_INDEX);
136 r = RREG32(PCIE_DATA);
137 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
141 void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
145 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
146 WREG32(PCIE_INDEX, reg);
147 (void)RREG32(PCIE_INDEX);
148 WREG32(PCIE_DATA, v);
149 (void)RREG32(PCIE_DATA);
150 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
153 static const u32 spectre_rlc_save_restore_register_list[] =
155 (0x0e00 << 16) | (0xc12c >> 2),
157 (0x0e00 << 16) | (0xc140 >> 2),
159 (0x0e00 << 16) | (0xc150 >> 2),
161 (0x0e00 << 16) | (0xc15c >> 2),
163 (0x0e00 << 16) | (0xc168 >> 2),
165 (0x0e00 << 16) | (0xc170 >> 2),
167 (0x0e00 << 16) | (0xc178 >> 2),
169 (0x0e00 << 16) | (0xc204 >> 2),
171 (0x0e00 << 16) | (0xc2b4 >> 2),
173 (0x0e00 << 16) | (0xc2b8 >> 2),
175 (0x0e00 << 16) | (0xc2bc >> 2),
177 (0x0e00 << 16) | (0xc2c0 >> 2),
179 (0x0e00 << 16) | (0x8228 >> 2),
181 (0x0e00 << 16) | (0x829c >> 2),
183 (0x0e00 << 16) | (0x869c >> 2),
185 (0x0600 << 16) | (0x98f4 >> 2),
187 (0x0e00 << 16) | (0x98f8 >> 2),
189 (0x0e00 << 16) | (0x9900 >> 2),
191 (0x0e00 << 16) | (0xc260 >> 2),
193 (0x0e00 << 16) | (0x90e8 >> 2),
195 (0x0e00 << 16) | (0x3c000 >> 2),
197 (0x0e00 << 16) | (0x3c00c >> 2),
199 (0x0e00 << 16) | (0x8c1c >> 2),
201 (0x0e00 << 16) | (0x9700 >> 2),
203 (0x0e00 << 16) | (0xcd20 >> 2),
205 (0x4e00 << 16) | (0xcd20 >> 2),
207 (0x5e00 << 16) | (0xcd20 >> 2),
209 (0x6e00 << 16) | (0xcd20 >> 2),
211 (0x7e00 << 16) | (0xcd20 >> 2),
213 (0x8e00 << 16) | (0xcd20 >> 2),
215 (0x9e00 << 16) | (0xcd20 >> 2),
217 (0xae00 << 16) | (0xcd20 >> 2),
219 (0xbe00 << 16) | (0xcd20 >> 2),
221 (0x0e00 << 16) | (0x89bc >> 2),
223 (0x0e00 << 16) | (0x8900 >> 2),
226 (0x0e00 << 16) | (0xc130 >> 2),
228 (0x0e00 << 16) | (0xc134 >> 2),
230 (0x0e00 << 16) | (0xc1fc >> 2),
232 (0x0e00 << 16) | (0xc208 >> 2),
234 (0x0e00 << 16) | (0xc264 >> 2),
236 (0x0e00 << 16) | (0xc268 >> 2),
238 (0x0e00 << 16) | (0xc26c >> 2),
240 (0x0e00 << 16) | (0xc270 >> 2),
242 (0x0e00 << 16) | (0xc274 >> 2),
244 (0x0e00 << 16) | (0xc278 >> 2),
246 (0x0e00 << 16) | (0xc27c >> 2),
248 (0x0e00 << 16) | (0xc280 >> 2),
250 (0x0e00 << 16) | (0xc284 >> 2),
252 (0x0e00 << 16) | (0xc288 >> 2),
254 (0x0e00 << 16) | (0xc28c >> 2),
256 (0x0e00 << 16) | (0xc290 >> 2),
258 (0x0e00 << 16) | (0xc294 >> 2),
260 (0x0e00 << 16) | (0xc298 >> 2),
262 (0x0e00 << 16) | (0xc29c >> 2),
264 (0x0e00 << 16) | (0xc2a0 >> 2),
266 (0x0e00 << 16) | (0xc2a4 >> 2),
268 (0x0e00 << 16) | (0xc2a8 >> 2),
270 (0x0e00 << 16) | (0xc2ac >> 2),
272 (0x0e00 << 16) | (0xc2b0 >> 2),
274 (0x0e00 << 16) | (0x301d0 >> 2),
276 (0x0e00 << 16) | (0x30238 >> 2),
278 (0x0e00 << 16) | (0x30250 >> 2),
280 (0x0e00 << 16) | (0x30254 >> 2),
282 (0x0e00 << 16) | (0x30258 >> 2),
284 (0x0e00 << 16) | (0x3025c >> 2),
286 (0x4e00 << 16) | (0xc900 >> 2),
288 (0x5e00 << 16) | (0xc900 >> 2),
290 (0x6e00 << 16) | (0xc900 >> 2),
292 (0x7e00 << 16) | (0xc900 >> 2),
294 (0x8e00 << 16) | (0xc900 >> 2),
296 (0x9e00 << 16) | (0xc900 >> 2),
298 (0xae00 << 16) | (0xc900 >> 2),
300 (0xbe00 << 16) | (0xc900 >> 2),
302 (0x4e00 << 16) | (0xc904 >> 2),
304 (0x5e00 << 16) | (0xc904 >> 2),
306 (0x6e00 << 16) | (0xc904 >> 2),
308 (0x7e00 << 16) | (0xc904 >> 2),
310 (0x8e00 << 16) | (0xc904 >> 2),
312 (0x9e00 << 16) | (0xc904 >> 2),
314 (0xae00 << 16) | (0xc904 >> 2),
316 (0xbe00 << 16) | (0xc904 >> 2),
318 (0x4e00 << 16) | (0xc908 >> 2),
320 (0x5e00 << 16) | (0xc908 >> 2),
322 (0x6e00 << 16) | (0xc908 >> 2),
324 (0x7e00 << 16) | (0xc908 >> 2),
326 (0x8e00 << 16) | (0xc908 >> 2),
328 (0x9e00 << 16) | (0xc908 >> 2),
330 (0xae00 << 16) | (0xc908 >> 2),
332 (0xbe00 << 16) | (0xc908 >> 2),
334 (0x4e00 << 16) | (0xc90c >> 2),
336 (0x5e00 << 16) | (0xc90c >> 2),
338 (0x6e00 << 16) | (0xc90c >> 2),
340 (0x7e00 << 16) | (0xc90c >> 2),
342 (0x8e00 << 16) | (0xc90c >> 2),
344 (0x9e00 << 16) | (0xc90c >> 2),
346 (0xae00 << 16) | (0xc90c >> 2),
348 (0xbe00 << 16) | (0xc90c >> 2),
350 (0x4e00 << 16) | (0xc910 >> 2),
352 (0x5e00 << 16) | (0xc910 >> 2),
354 (0x6e00 << 16) | (0xc910 >> 2),
356 (0x7e00 << 16) | (0xc910 >> 2),
358 (0x8e00 << 16) | (0xc910 >> 2),
360 (0x9e00 << 16) | (0xc910 >> 2),
362 (0xae00 << 16) | (0xc910 >> 2),
364 (0xbe00 << 16) | (0xc910 >> 2),
366 (0x0e00 << 16) | (0xc99c >> 2),
368 (0x0e00 << 16) | (0x9834 >> 2),
370 (0x0000 << 16) | (0x30f00 >> 2),
372 (0x0001 << 16) | (0x30f00 >> 2),
374 (0x0000 << 16) | (0x30f04 >> 2),
376 (0x0001 << 16) | (0x30f04 >> 2),
378 (0x0000 << 16) | (0x30f08 >> 2),
380 (0x0001 << 16) | (0x30f08 >> 2),
382 (0x0000 << 16) | (0x30f0c >> 2),
384 (0x0001 << 16) | (0x30f0c >> 2),
386 (0x0600 << 16) | (0x9b7c >> 2),
388 (0x0e00 << 16) | (0x8a14 >> 2),
390 (0x0e00 << 16) | (0x8a18 >> 2),
392 (0x0600 << 16) | (0x30a00 >> 2),
394 (0x0e00 << 16) | (0x8bf0 >> 2),
396 (0x0e00 << 16) | (0x8bcc >> 2),
398 (0x0e00 << 16) | (0x8b24 >> 2),
400 (0x0e00 << 16) | (0x30a04 >> 2),
402 (0x0600 << 16) | (0x30a10 >> 2),
404 (0x0600 << 16) | (0x30a14 >> 2),
406 (0x0600 << 16) | (0x30a18 >> 2),
408 (0x0600 << 16) | (0x30a2c >> 2),
410 (0x0e00 << 16) | (0xc700 >> 2),
412 (0x0e00 << 16) | (0xc704 >> 2),
414 (0x0e00 << 16) | (0xc708 >> 2),
416 (0x0e00 << 16) | (0xc768 >> 2),
418 (0x0400 << 16) | (0xc770 >> 2),
420 (0x0400 << 16) | (0xc774 >> 2),
422 (0x0400 << 16) | (0xc778 >> 2),
424 (0x0400 << 16) | (0xc77c >> 2),
426 (0x0400 << 16) | (0xc780 >> 2),
428 (0x0400 << 16) | (0xc784 >> 2),
430 (0x0400 << 16) | (0xc788 >> 2),
432 (0x0400 << 16) | (0xc78c >> 2),
434 (0x0400 << 16) | (0xc798 >> 2),
436 (0x0400 << 16) | (0xc79c >> 2),
438 (0x0400 << 16) | (0xc7a0 >> 2),
440 (0x0400 << 16) | (0xc7a4 >> 2),
442 (0x0400 << 16) | (0xc7a8 >> 2),
444 (0x0400 << 16) | (0xc7ac >> 2),
446 (0x0400 << 16) | (0xc7b0 >> 2),
448 (0x0400 << 16) | (0xc7b4 >> 2),
450 (0x0e00 << 16) | (0x9100 >> 2),
452 (0x0e00 << 16) | (0x3c010 >> 2),
454 (0x0e00 << 16) | (0x92a8 >> 2),
456 (0x0e00 << 16) | (0x92ac >> 2),
458 (0x0e00 << 16) | (0x92b4 >> 2),
460 (0x0e00 << 16) | (0x92b8 >> 2),
462 (0x0e00 << 16) | (0x92bc >> 2),
464 (0x0e00 << 16) | (0x92c0 >> 2),
466 (0x0e00 << 16) | (0x92c4 >> 2),
468 (0x0e00 << 16) | (0x92c8 >> 2),
470 (0x0e00 << 16) | (0x92cc >> 2),
472 (0x0e00 << 16) | (0x92d0 >> 2),
474 (0x0e00 << 16) | (0x8c00 >> 2),
476 (0x0e00 << 16) | (0x8c04 >> 2),
478 (0x0e00 << 16) | (0x8c20 >> 2),
480 (0x0e00 << 16) | (0x8c38 >> 2),
482 (0x0e00 << 16) | (0x8c3c >> 2),
484 (0x0e00 << 16) | (0xae00 >> 2),
486 (0x0e00 << 16) | (0x9604 >> 2),
488 (0x0e00 << 16) | (0xac08 >> 2),
490 (0x0e00 << 16) | (0xac0c >> 2),
492 (0x0e00 << 16) | (0xac10 >> 2),
494 (0x0e00 << 16) | (0xac14 >> 2),
496 (0x0e00 << 16) | (0xac58 >> 2),
498 (0x0e00 << 16) | (0xac68 >> 2),
500 (0x0e00 << 16) | (0xac6c >> 2),
502 (0x0e00 << 16) | (0xac70 >> 2),
504 (0x0e00 << 16) | (0xac74 >> 2),
506 (0x0e00 << 16) | (0xac78 >> 2),
508 (0x0e00 << 16) | (0xac7c >> 2),
510 (0x0e00 << 16) | (0xac80 >> 2),
512 (0x0e00 << 16) | (0xac84 >> 2),
514 (0x0e00 << 16) | (0xac88 >> 2),
516 (0x0e00 << 16) | (0xac8c >> 2),
518 (0x0e00 << 16) | (0x970c >> 2),
520 (0x0e00 << 16) | (0x9714 >> 2),
522 (0x0e00 << 16) | (0x9718 >> 2),
524 (0x0e00 << 16) | (0x971c >> 2),
526 (0x0e00 << 16) | (0x31068 >> 2),
528 (0x4e00 << 16) | (0x31068 >> 2),
530 (0x5e00 << 16) | (0x31068 >> 2),
532 (0x6e00 << 16) | (0x31068 >> 2),
534 (0x7e00 << 16) | (0x31068 >> 2),
536 (0x8e00 << 16) | (0x31068 >> 2),
538 (0x9e00 << 16) | (0x31068 >> 2),
540 (0xae00 << 16) | (0x31068 >> 2),
542 (0xbe00 << 16) | (0x31068 >> 2),
544 (0x0e00 << 16) | (0xcd10 >> 2),
546 (0x0e00 << 16) | (0xcd14 >> 2),
548 (0x0e00 << 16) | (0x88b0 >> 2),
550 (0x0e00 << 16) | (0x88b4 >> 2),
552 (0x0e00 << 16) | (0x88b8 >> 2),
554 (0x0e00 << 16) | (0x88bc >> 2),
556 (0x0400 << 16) | (0x89c0 >> 2),
558 (0x0e00 << 16) | (0x88c4 >> 2),
560 (0x0e00 << 16) | (0x88c8 >> 2),
562 (0x0e00 << 16) | (0x88d0 >> 2),
564 (0x0e00 << 16) | (0x88d4 >> 2),
566 (0x0e00 << 16) | (0x88d8 >> 2),
568 (0x0e00 << 16) | (0x8980 >> 2),
570 (0x0e00 << 16) | (0x30938 >> 2),
572 (0x0e00 << 16) | (0x3093c >> 2),
574 (0x0e00 << 16) | (0x30940 >> 2),
576 (0x0e00 << 16) | (0x89a0 >> 2),
578 (0x0e00 << 16) | (0x30900 >> 2),
580 (0x0e00 << 16) | (0x30904 >> 2),
582 (0x0e00 << 16) | (0x89b4 >> 2),
584 (0x0e00 << 16) | (0x3c210 >> 2),
586 (0x0e00 << 16) | (0x3c214 >> 2),
588 (0x0e00 << 16) | (0x3c218 >> 2),
590 (0x0e00 << 16) | (0x8904 >> 2),
593 (0x0e00 << 16) | (0x8c28 >> 2),
594 (0x0e00 << 16) | (0x8c2c >> 2),
595 (0x0e00 << 16) | (0x8c30 >> 2),
596 (0x0e00 << 16) | (0x8c34 >> 2),
597 (0x0e00 << 16) | (0x9600 >> 2),
600 static const u32 kalindi_rlc_save_restore_register_list[] =
602 (0x0e00 << 16) | (0xc12c >> 2),
604 (0x0e00 << 16) | (0xc140 >> 2),
606 (0x0e00 << 16) | (0xc150 >> 2),
608 (0x0e00 << 16) | (0xc15c >> 2),
610 (0x0e00 << 16) | (0xc168 >> 2),
612 (0x0e00 << 16) | (0xc170 >> 2),
614 (0x0e00 << 16) | (0xc204 >> 2),
616 (0x0e00 << 16) | (0xc2b4 >> 2),
618 (0x0e00 << 16) | (0xc2b8 >> 2),
620 (0x0e00 << 16) | (0xc2bc >> 2),
622 (0x0e00 << 16) | (0xc2c0 >> 2),
624 (0x0e00 << 16) | (0x8228 >> 2),
626 (0x0e00 << 16) | (0x829c >> 2),
628 (0x0e00 << 16) | (0x869c >> 2),
630 (0x0600 << 16) | (0x98f4 >> 2),
632 (0x0e00 << 16) | (0x98f8 >> 2),
634 (0x0e00 << 16) | (0x9900 >> 2),
636 (0x0e00 << 16) | (0xc260 >> 2),
638 (0x0e00 << 16) | (0x90e8 >> 2),
640 (0x0e00 << 16) | (0x3c000 >> 2),
642 (0x0e00 << 16) | (0x3c00c >> 2),
644 (0x0e00 << 16) | (0x8c1c >> 2),
646 (0x0e00 << 16) | (0x9700 >> 2),
648 (0x0e00 << 16) | (0xcd20 >> 2),
650 (0x4e00 << 16) | (0xcd20 >> 2),
652 (0x5e00 << 16) | (0xcd20 >> 2),
654 (0x6e00 << 16) | (0xcd20 >> 2),
656 (0x7e00 << 16) | (0xcd20 >> 2),
658 (0x0e00 << 16) | (0x89bc >> 2),
660 (0x0e00 << 16) | (0x8900 >> 2),
663 (0x0e00 << 16) | (0xc130 >> 2),
665 (0x0e00 << 16) | (0xc134 >> 2),
667 (0x0e00 << 16) | (0xc1fc >> 2),
669 (0x0e00 << 16) | (0xc208 >> 2),
671 (0x0e00 << 16) | (0xc264 >> 2),
673 (0x0e00 << 16) | (0xc268 >> 2),
675 (0x0e00 << 16) | (0xc26c >> 2),
677 (0x0e00 << 16) | (0xc270 >> 2),
679 (0x0e00 << 16) | (0xc274 >> 2),
681 (0x0e00 << 16) | (0xc28c >> 2),
683 (0x0e00 << 16) | (0xc290 >> 2),
685 (0x0e00 << 16) | (0xc294 >> 2),
687 (0x0e00 << 16) | (0xc298 >> 2),
689 (0x0e00 << 16) | (0xc2a0 >> 2),
691 (0x0e00 << 16) | (0xc2a4 >> 2),
693 (0x0e00 << 16) | (0xc2a8 >> 2),
695 (0x0e00 << 16) | (0xc2ac >> 2),
697 (0x0e00 << 16) | (0x301d0 >> 2),
699 (0x0e00 << 16) | (0x30238 >> 2),
701 (0x0e00 << 16) | (0x30250 >> 2),
703 (0x0e00 << 16) | (0x30254 >> 2),
705 (0x0e00 << 16) | (0x30258 >> 2),
707 (0x0e00 << 16) | (0x3025c >> 2),
709 (0x4e00 << 16) | (0xc900 >> 2),
711 (0x5e00 << 16) | (0xc900 >> 2),
713 (0x6e00 << 16) | (0xc900 >> 2),
715 (0x7e00 << 16) | (0xc900 >> 2),
717 (0x4e00 << 16) | (0xc904 >> 2),
719 (0x5e00 << 16) | (0xc904 >> 2),
721 (0x6e00 << 16) | (0xc904 >> 2),
723 (0x7e00 << 16) | (0xc904 >> 2),
725 (0x4e00 << 16) | (0xc908 >> 2),
727 (0x5e00 << 16) | (0xc908 >> 2),
729 (0x6e00 << 16) | (0xc908 >> 2),
731 (0x7e00 << 16) | (0xc908 >> 2),
733 (0x4e00 << 16) | (0xc90c >> 2),
735 (0x5e00 << 16) | (0xc90c >> 2),
737 (0x6e00 << 16) | (0xc90c >> 2),
739 (0x7e00 << 16) | (0xc90c >> 2),
741 (0x4e00 << 16) | (0xc910 >> 2),
743 (0x5e00 << 16) | (0xc910 >> 2),
745 (0x6e00 << 16) | (0xc910 >> 2),
747 (0x7e00 << 16) | (0xc910 >> 2),
749 (0x0e00 << 16) | (0xc99c >> 2),
751 (0x0e00 << 16) | (0x9834 >> 2),
753 (0x0000 << 16) | (0x30f00 >> 2),
755 (0x0000 << 16) | (0x30f04 >> 2),
757 (0x0000 << 16) | (0x30f08 >> 2),
759 (0x0000 << 16) | (0x30f0c >> 2),
761 (0x0600 << 16) | (0x9b7c >> 2),
763 (0x0e00 << 16) | (0x8a14 >> 2),
765 (0x0e00 << 16) | (0x8a18 >> 2),
767 (0x0600 << 16) | (0x30a00 >> 2),
769 (0x0e00 << 16) | (0x8bf0 >> 2),
771 (0x0e00 << 16) | (0x8bcc >> 2),
773 (0x0e00 << 16) | (0x8b24 >> 2),
775 (0x0e00 << 16) | (0x30a04 >> 2),
777 (0x0600 << 16) | (0x30a10 >> 2),
779 (0x0600 << 16) | (0x30a14 >> 2),
781 (0x0600 << 16) | (0x30a18 >> 2),
783 (0x0600 << 16) | (0x30a2c >> 2),
785 (0x0e00 << 16) | (0xc700 >> 2),
787 (0x0e00 << 16) | (0xc704 >> 2),
789 (0x0e00 << 16) | (0xc708 >> 2),
791 (0x0e00 << 16) | (0xc768 >> 2),
793 (0x0400 << 16) | (0xc770 >> 2),
795 (0x0400 << 16) | (0xc774 >> 2),
797 (0x0400 << 16) | (0xc798 >> 2),
799 (0x0400 << 16) | (0xc79c >> 2),
801 (0x0e00 << 16) | (0x9100 >> 2),
803 (0x0e00 << 16) | (0x3c010 >> 2),
805 (0x0e00 << 16) | (0x8c00 >> 2),
807 (0x0e00 << 16) | (0x8c04 >> 2),
809 (0x0e00 << 16) | (0x8c20 >> 2),
811 (0x0e00 << 16) | (0x8c38 >> 2),
813 (0x0e00 << 16) | (0x8c3c >> 2),
815 (0x0e00 << 16) | (0xae00 >> 2),
817 (0x0e00 << 16) | (0x9604 >> 2),
819 (0x0e00 << 16) | (0xac08 >> 2),
821 (0x0e00 << 16) | (0xac0c >> 2),
823 (0x0e00 << 16) | (0xac10 >> 2),
825 (0x0e00 << 16) | (0xac14 >> 2),
827 (0x0e00 << 16) | (0xac58 >> 2),
829 (0x0e00 << 16) | (0xac68 >> 2),
831 (0x0e00 << 16) | (0xac6c >> 2),
833 (0x0e00 << 16) | (0xac70 >> 2),
835 (0x0e00 << 16) | (0xac74 >> 2),
837 (0x0e00 << 16) | (0xac78 >> 2),
839 (0x0e00 << 16) | (0xac7c >> 2),
841 (0x0e00 << 16) | (0xac80 >> 2),
843 (0x0e00 << 16) | (0xac84 >> 2),
845 (0x0e00 << 16) | (0xac88 >> 2),
847 (0x0e00 << 16) | (0xac8c >> 2),
849 (0x0e00 << 16) | (0x970c >> 2),
851 (0x0e00 << 16) | (0x9714 >> 2),
853 (0x0e00 << 16) | (0x9718 >> 2),
855 (0x0e00 << 16) | (0x971c >> 2),
857 (0x0e00 << 16) | (0x31068 >> 2),
859 (0x4e00 << 16) | (0x31068 >> 2),
861 (0x5e00 << 16) | (0x31068 >> 2),
863 (0x6e00 << 16) | (0x31068 >> 2),
865 (0x7e00 << 16) | (0x31068 >> 2),
867 (0x0e00 << 16) | (0xcd10 >> 2),
869 (0x0e00 << 16) | (0xcd14 >> 2),
871 (0x0e00 << 16) | (0x88b0 >> 2),
873 (0x0e00 << 16) | (0x88b4 >> 2),
875 (0x0e00 << 16) | (0x88b8 >> 2),
877 (0x0e00 << 16) | (0x88bc >> 2),
879 (0x0400 << 16) | (0x89c0 >> 2),
881 (0x0e00 << 16) | (0x88c4 >> 2),
883 (0x0e00 << 16) | (0x88c8 >> 2),
885 (0x0e00 << 16) | (0x88d0 >> 2),
887 (0x0e00 << 16) | (0x88d4 >> 2),
889 (0x0e00 << 16) | (0x88d8 >> 2),
891 (0x0e00 << 16) | (0x8980 >> 2),
893 (0x0e00 << 16) | (0x30938 >> 2),
895 (0x0e00 << 16) | (0x3093c >> 2),
897 (0x0e00 << 16) | (0x30940 >> 2),
899 (0x0e00 << 16) | (0x89a0 >> 2),
901 (0x0e00 << 16) | (0x30900 >> 2),
903 (0x0e00 << 16) | (0x30904 >> 2),
905 (0x0e00 << 16) | (0x89b4 >> 2),
907 (0x0e00 << 16) | (0x3e1fc >> 2),
909 (0x0e00 << 16) | (0x3c210 >> 2),
911 (0x0e00 << 16) | (0x3c214 >> 2),
913 (0x0e00 << 16) | (0x3c218 >> 2),
915 (0x0e00 << 16) | (0x8904 >> 2),
918 (0x0e00 << 16) | (0x8c28 >> 2),
919 (0x0e00 << 16) | (0x8c2c >> 2),
920 (0x0e00 << 16) | (0x8c30 >> 2),
921 (0x0e00 << 16) | (0x8c34 >> 2),
922 (0x0e00 << 16) | (0x9600 >> 2),
925 static const u32 bonaire_golden_spm_registers[] =
927 0x30800, 0xe0ffffff, 0xe0000000
930 static const u32 bonaire_golden_common_registers[] =
932 0xc770, 0xffffffff, 0x00000800,
933 0xc774, 0xffffffff, 0x00000800,
934 0xc798, 0xffffffff, 0x00007fbf,
935 0xc79c, 0xffffffff, 0x00007faf
938 static const u32 bonaire_golden_registers[] =
940 0x3354, 0x00000333, 0x00000333,
941 0x3350, 0x000c0fc0, 0x00040200,
942 0x9a10, 0x00010000, 0x00058208,
943 0x3c000, 0xffff1fff, 0x00140000,
944 0x3c200, 0xfdfc0fff, 0x00000100,
945 0x3c234, 0x40000000, 0x40000200,
946 0x9830, 0xffffffff, 0x00000000,
947 0x9834, 0xf00fffff, 0x00000400,
948 0x9838, 0x0002021c, 0x00020200,
949 0xc78, 0x00000080, 0x00000000,
950 0x5bb0, 0x000000f0, 0x00000070,
951 0x5bc0, 0xf0311fff, 0x80300000,
952 0x98f8, 0x73773777, 0x12010001,
953 0x350c, 0x00810000, 0x408af000,
954 0x7030, 0x31000111, 0x00000011,
955 0x2f48, 0x73773777, 0x12010001,
956 0x220c, 0x00007fb6, 0x0021a1b1,
957 0x2210, 0x00007fb6, 0x002021b1,
958 0x2180, 0x00007fb6, 0x00002191,
959 0x2218, 0x00007fb6, 0x002121b1,
960 0x221c, 0x00007fb6, 0x002021b1,
961 0x21dc, 0x00007fb6, 0x00002191,
962 0x21e0, 0x00007fb6, 0x00002191,
963 0x3628, 0x0000003f, 0x0000000a,
964 0x362c, 0x0000003f, 0x0000000a,
965 0x2ae4, 0x00073ffe, 0x000022a2,
966 0x240c, 0x000007ff, 0x00000000,
967 0x8a14, 0xf000003f, 0x00000007,
968 0x8bf0, 0x00002001, 0x00000001,
969 0x8b24, 0xffffffff, 0x00ffffff,
970 0x30a04, 0x0000ff0f, 0x00000000,
971 0x28a4c, 0x07ffffff, 0x06000000,
972 0x4d8, 0x00000fff, 0x00000100,
973 0x3e78, 0x00000001, 0x00000002,
974 0x9100, 0x03000000, 0x0362c688,
975 0x8c00, 0x000000ff, 0x00000001,
976 0xe40, 0x00001fff, 0x00001fff,
977 0x9060, 0x0000007f, 0x00000020,
978 0x9508, 0x00010000, 0x00010000,
979 0xac14, 0x000003ff, 0x000000f3,
980 0xac0c, 0xffffffff, 0x00001032
983 static const u32 bonaire_mgcg_cgcg_init[] =
985 0xc420, 0xffffffff, 0xfffffffc,
986 0x30800, 0xffffffff, 0xe0000000,
987 0x3c2a0, 0xffffffff, 0x00000100,
988 0x3c208, 0xffffffff, 0x00000100,
989 0x3c2c0, 0xffffffff, 0xc0000100,
990 0x3c2c8, 0xffffffff, 0xc0000100,
991 0x3c2c4, 0xffffffff, 0xc0000100,
992 0x55e4, 0xffffffff, 0x00600100,
993 0x3c280, 0xffffffff, 0x00000100,
994 0x3c214, 0xffffffff, 0x06000100,
995 0x3c220, 0xffffffff, 0x00000100,
996 0x3c218, 0xffffffff, 0x06000100,
997 0x3c204, 0xffffffff, 0x00000100,
998 0x3c2e0, 0xffffffff, 0x00000100,
999 0x3c224, 0xffffffff, 0x00000100,
1000 0x3c200, 0xffffffff, 0x00000100,
1001 0x3c230, 0xffffffff, 0x00000100,
1002 0x3c234, 0xffffffff, 0x00000100,
1003 0x3c250, 0xffffffff, 0x00000100,
1004 0x3c254, 0xffffffff, 0x00000100,
1005 0x3c258, 0xffffffff, 0x00000100,
1006 0x3c25c, 0xffffffff, 0x00000100,
1007 0x3c260, 0xffffffff, 0x00000100,
1008 0x3c27c, 0xffffffff, 0x00000100,
1009 0x3c278, 0xffffffff, 0x00000100,
1010 0x3c210, 0xffffffff, 0x06000100,
1011 0x3c290, 0xffffffff, 0x00000100,
1012 0x3c274, 0xffffffff, 0x00000100,
1013 0x3c2b4, 0xffffffff, 0x00000100,
1014 0x3c2b0, 0xffffffff, 0x00000100,
1015 0x3c270, 0xffffffff, 0x00000100,
1016 0x30800, 0xffffffff, 0xe0000000,
1017 0x3c020, 0xffffffff, 0x00010000,
1018 0x3c024, 0xffffffff, 0x00030002,
1019 0x3c028, 0xffffffff, 0x00040007,
1020 0x3c02c, 0xffffffff, 0x00060005,
1021 0x3c030, 0xffffffff, 0x00090008,
1022 0x3c034, 0xffffffff, 0x00010000,
1023 0x3c038, 0xffffffff, 0x00030002,
1024 0x3c03c, 0xffffffff, 0x00040007,
1025 0x3c040, 0xffffffff, 0x00060005,
1026 0x3c044, 0xffffffff, 0x00090008,
1027 0x3c048, 0xffffffff, 0x00010000,
1028 0x3c04c, 0xffffffff, 0x00030002,
1029 0x3c050, 0xffffffff, 0x00040007,
1030 0x3c054, 0xffffffff, 0x00060005,
1031 0x3c058, 0xffffffff, 0x00090008,
1032 0x3c05c, 0xffffffff, 0x00010000,
1033 0x3c060, 0xffffffff, 0x00030002,
1034 0x3c064, 0xffffffff, 0x00040007,
1035 0x3c068, 0xffffffff, 0x00060005,
1036 0x3c06c, 0xffffffff, 0x00090008,
1037 0x3c070, 0xffffffff, 0x00010000,
1038 0x3c074, 0xffffffff, 0x00030002,
1039 0x3c078, 0xffffffff, 0x00040007,
1040 0x3c07c, 0xffffffff, 0x00060005,
1041 0x3c080, 0xffffffff, 0x00090008,
1042 0x3c084, 0xffffffff, 0x00010000,
1043 0x3c088, 0xffffffff, 0x00030002,
1044 0x3c08c, 0xffffffff, 0x00040007,
1045 0x3c090, 0xffffffff, 0x00060005,
1046 0x3c094, 0xffffffff, 0x00090008,
1047 0x3c098, 0xffffffff, 0x00010000,
1048 0x3c09c, 0xffffffff, 0x00030002,
1049 0x3c0a0, 0xffffffff, 0x00040007,
1050 0x3c0a4, 0xffffffff, 0x00060005,
1051 0x3c0a8, 0xffffffff, 0x00090008,
1052 0x3c000, 0xffffffff, 0x96e00200,
1053 0x8708, 0xffffffff, 0x00900100,
1054 0xc424, 0xffffffff, 0x0020003f,
1055 0x38, 0xffffffff, 0x0140001c,
1056 0x3c, 0x000f0000, 0x000f0000,
1057 0x220, 0xffffffff, 0xC060000C,
1058 0x224, 0xc0000fff, 0x00000100,
1059 0xf90, 0xffffffff, 0x00000100,
1060 0xf98, 0x00000101, 0x00000000,
1061 0x20a8, 0xffffffff, 0x00000104,
1062 0x55e4, 0xff000fff, 0x00000100,
1063 0x30cc, 0xc0000fff, 0x00000104,
1064 0xc1e4, 0x00000001, 0x00000001,
1065 0xd00c, 0xff000ff0, 0x00000100,
1066 0xd80c, 0xff000ff0, 0x00000100
1069 static const u32 spectre_golden_spm_registers[] =
1071 0x30800, 0xe0ffffff, 0xe0000000
1074 static const u32 spectre_golden_common_registers[] =
1076 0xc770, 0xffffffff, 0x00000800,
1077 0xc774, 0xffffffff, 0x00000800,
1078 0xc798, 0xffffffff, 0x00007fbf,
1079 0xc79c, 0xffffffff, 0x00007faf
1082 static const u32 spectre_golden_registers[] =
1084 0x3c000, 0xffff1fff, 0x96940200,
1085 0x3c00c, 0xffff0001, 0xff000000,
1086 0x3c200, 0xfffc0fff, 0x00000100,
1087 0x6ed8, 0x00010101, 0x00010000,
1088 0x9834, 0xf00fffff, 0x00000400,
1089 0x9838, 0xfffffffc, 0x00020200,
1090 0x5bb0, 0x000000f0, 0x00000070,
1091 0x5bc0, 0xf0311fff, 0x80300000,
1092 0x98f8, 0x73773777, 0x12010001,
1093 0x9b7c, 0x00ff0000, 0x00fc0000,
1094 0x2f48, 0x73773777, 0x12010001,
1095 0x8a14, 0xf000003f, 0x00000007,
1096 0x8b24, 0xffffffff, 0x00ffffff,
1097 0x28350, 0x3f3f3fff, 0x00000082,
1098 0x28355, 0x0000003f, 0x00000000,
1099 0x3e78, 0x00000001, 0x00000002,
1100 0x913c, 0xffff03df, 0x00000004,
1101 0xc768, 0x00000008, 0x00000008,
1102 0x8c00, 0x000008ff, 0x00000800,
1103 0x9508, 0x00010000, 0x00010000,
1104 0xac0c, 0xffffffff, 0x54763210,
1105 0x214f8, 0x01ff01ff, 0x00000002,
1106 0x21498, 0x007ff800, 0x00200000,
1107 0x2015c, 0xffffffff, 0x00000f40,
1108 0x30934, 0xffffffff, 0x00000001
1111 static const u32 spectre_mgcg_cgcg_init[] =
1113 0xc420, 0xffffffff, 0xfffffffc,
1114 0x30800, 0xffffffff, 0xe0000000,
1115 0x3c2a0, 0xffffffff, 0x00000100,
1116 0x3c208, 0xffffffff, 0x00000100,
1117 0x3c2c0, 0xffffffff, 0x00000100,
1118 0x3c2c8, 0xffffffff, 0x00000100,
1119 0x3c2c4, 0xffffffff, 0x00000100,
1120 0x55e4, 0xffffffff, 0x00600100,
1121 0x3c280, 0xffffffff, 0x00000100,
1122 0x3c214, 0xffffffff, 0x06000100,
1123 0x3c220, 0xffffffff, 0x00000100,
1124 0x3c218, 0xffffffff, 0x06000100,
1125 0x3c204, 0xffffffff, 0x00000100,
1126 0x3c2e0, 0xffffffff, 0x00000100,
1127 0x3c224, 0xffffffff, 0x00000100,
1128 0x3c200, 0xffffffff, 0x00000100,
1129 0x3c230, 0xffffffff, 0x00000100,
1130 0x3c234, 0xffffffff, 0x00000100,
1131 0x3c250, 0xffffffff, 0x00000100,
1132 0x3c254, 0xffffffff, 0x00000100,
1133 0x3c258, 0xffffffff, 0x00000100,
1134 0x3c25c, 0xffffffff, 0x00000100,
1135 0x3c260, 0xffffffff, 0x00000100,
1136 0x3c27c, 0xffffffff, 0x00000100,
1137 0x3c278, 0xffffffff, 0x00000100,
1138 0x3c210, 0xffffffff, 0x06000100,
1139 0x3c290, 0xffffffff, 0x00000100,
1140 0x3c274, 0xffffffff, 0x00000100,
1141 0x3c2b4, 0xffffffff, 0x00000100,
1142 0x3c2b0, 0xffffffff, 0x00000100,
1143 0x3c270, 0xffffffff, 0x00000100,
1144 0x30800, 0xffffffff, 0xe0000000,
1145 0x3c020, 0xffffffff, 0x00010000,
1146 0x3c024, 0xffffffff, 0x00030002,
1147 0x3c028, 0xffffffff, 0x00040007,
1148 0x3c02c, 0xffffffff, 0x00060005,
1149 0x3c030, 0xffffffff, 0x00090008,
1150 0x3c034, 0xffffffff, 0x00010000,
1151 0x3c038, 0xffffffff, 0x00030002,
1152 0x3c03c, 0xffffffff, 0x00040007,
1153 0x3c040, 0xffffffff, 0x00060005,
1154 0x3c044, 0xffffffff, 0x00090008,
1155 0x3c048, 0xffffffff, 0x00010000,
1156 0x3c04c, 0xffffffff, 0x00030002,
1157 0x3c050, 0xffffffff, 0x00040007,
1158 0x3c054, 0xffffffff, 0x00060005,
1159 0x3c058, 0xffffffff, 0x00090008,
1160 0x3c05c, 0xffffffff, 0x00010000,
1161 0x3c060, 0xffffffff, 0x00030002,
1162 0x3c064, 0xffffffff, 0x00040007,
1163 0x3c068, 0xffffffff, 0x00060005,
1164 0x3c06c, 0xffffffff, 0x00090008,
1165 0x3c070, 0xffffffff, 0x00010000,
1166 0x3c074, 0xffffffff, 0x00030002,
1167 0x3c078, 0xffffffff, 0x00040007,
1168 0x3c07c, 0xffffffff, 0x00060005,
1169 0x3c080, 0xffffffff, 0x00090008,
1170 0x3c084, 0xffffffff, 0x00010000,
1171 0x3c088, 0xffffffff, 0x00030002,
1172 0x3c08c, 0xffffffff, 0x00040007,
1173 0x3c090, 0xffffffff, 0x00060005,
1174 0x3c094, 0xffffffff, 0x00090008,
1175 0x3c098, 0xffffffff, 0x00010000,
1176 0x3c09c, 0xffffffff, 0x00030002,
1177 0x3c0a0, 0xffffffff, 0x00040007,
1178 0x3c0a4, 0xffffffff, 0x00060005,
1179 0x3c0a8, 0xffffffff, 0x00090008,
1180 0x3c0ac, 0xffffffff, 0x00010000,
1181 0x3c0b0, 0xffffffff, 0x00030002,
1182 0x3c0b4, 0xffffffff, 0x00040007,
1183 0x3c0b8, 0xffffffff, 0x00060005,
1184 0x3c0bc, 0xffffffff, 0x00090008,
1185 0x3c000, 0xffffffff, 0x96e00200,
1186 0x8708, 0xffffffff, 0x00900100,
1187 0xc424, 0xffffffff, 0x0020003f,
1188 0x38, 0xffffffff, 0x0140001c,
1189 0x3c, 0x000f0000, 0x000f0000,
1190 0x220, 0xffffffff, 0xC060000C,
1191 0x224, 0xc0000fff, 0x00000100,
1192 0xf90, 0xffffffff, 0x00000100,
1193 0xf98, 0x00000101, 0x00000000,
1194 0x20a8, 0xffffffff, 0x00000104,
1195 0x55e4, 0xff000fff, 0x00000100,
1196 0x30cc, 0xc0000fff, 0x00000104,
1197 0xc1e4, 0x00000001, 0x00000001,
1198 0xd00c, 0xff000ff0, 0x00000100,
1199 0xd80c, 0xff000ff0, 0x00000100
1202 static const u32 kalindi_golden_spm_registers[] =
1204 0x30800, 0xe0ffffff, 0xe0000000
1207 static const u32 kalindi_golden_common_registers[] =
1209 0xc770, 0xffffffff, 0x00000800,
1210 0xc774, 0xffffffff, 0x00000800,
1211 0xc798, 0xffffffff, 0x00007fbf,
1212 0xc79c, 0xffffffff, 0x00007faf
1215 static const u32 kalindi_golden_registers[] =
1217 0x3c000, 0xffffdfff, 0x6e944040,
1218 0x55e4, 0xff607fff, 0xfc000100,
1219 0x3c220, 0xff000fff, 0x00000100,
1220 0x3c224, 0xff000fff, 0x00000100,
1221 0x3c200, 0xfffc0fff, 0x00000100,
1222 0x6ed8, 0x00010101, 0x00010000,
1223 0x9830, 0xffffffff, 0x00000000,
1224 0x9834, 0xf00fffff, 0x00000400,
1225 0x5bb0, 0x000000f0, 0x00000070,
1226 0x5bc0, 0xf0311fff, 0x80300000,
1227 0x98f8, 0x73773777, 0x12010001,
1228 0x98fc, 0xffffffff, 0x00000010,
1229 0x9b7c, 0x00ff0000, 0x00fc0000,
1230 0x8030, 0x00001f0f, 0x0000100a,
1231 0x2f48, 0x73773777, 0x12010001,
1232 0x2408, 0x000fffff, 0x000c007f,
1233 0x8a14, 0xf000003f, 0x00000007,
1234 0x8b24, 0x3fff3fff, 0x00ffcfff,
1235 0x30a04, 0x0000ff0f, 0x00000000,
1236 0x28a4c, 0x07ffffff, 0x06000000,
1237 0x4d8, 0x00000fff, 0x00000100,
1238 0x3e78, 0x00000001, 0x00000002,
1239 0xc768, 0x00000008, 0x00000008,
1240 0x8c00, 0x000000ff, 0x00000003,
1241 0x214f8, 0x01ff01ff, 0x00000002,
1242 0x21498, 0x007ff800, 0x00200000,
1243 0x2015c, 0xffffffff, 0x00000f40,
1244 0x88c4, 0x001f3ae3, 0x00000082,
1245 0x88d4, 0x0000001f, 0x00000010,
1246 0x30934, 0xffffffff, 0x00000000
1249 static const u32 kalindi_mgcg_cgcg_init[] =
1251 0xc420, 0xffffffff, 0xfffffffc,
1252 0x30800, 0xffffffff, 0xe0000000,
1253 0x3c2a0, 0xffffffff, 0x00000100,
1254 0x3c208, 0xffffffff, 0x00000100,
1255 0x3c2c0, 0xffffffff, 0x00000100,
1256 0x3c2c8, 0xffffffff, 0x00000100,
1257 0x3c2c4, 0xffffffff, 0x00000100,
1258 0x55e4, 0xffffffff, 0x00600100,
1259 0x3c280, 0xffffffff, 0x00000100,
1260 0x3c214, 0xffffffff, 0x06000100,
1261 0x3c220, 0xffffffff, 0x00000100,
1262 0x3c218, 0xffffffff, 0x06000100,
1263 0x3c204, 0xffffffff, 0x00000100,
1264 0x3c2e0, 0xffffffff, 0x00000100,
1265 0x3c224, 0xffffffff, 0x00000100,
1266 0x3c200, 0xffffffff, 0x00000100,
1267 0x3c230, 0xffffffff, 0x00000100,
1268 0x3c234, 0xffffffff, 0x00000100,
1269 0x3c250, 0xffffffff, 0x00000100,
1270 0x3c254, 0xffffffff, 0x00000100,
1271 0x3c258, 0xffffffff, 0x00000100,
1272 0x3c25c, 0xffffffff, 0x00000100,
1273 0x3c260, 0xffffffff, 0x00000100,
1274 0x3c27c, 0xffffffff, 0x00000100,
1275 0x3c278, 0xffffffff, 0x00000100,
1276 0x3c210, 0xffffffff, 0x06000100,
1277 0x3c290, 0xffffffff, 0x00000100,
1278 0x3c274, 0xffffffff, 0x00000100,
1279 0x3c2b4, 0xffffffff, 0x00000100,
1280 0x3c2b0, 0xffffffff, 0x00000100,
1281 0x3c270, 0xffffffff, 0x00000100,
1282 0x30800, 0xffffffff, 0xe0000000,
1283 0x3c020, 0xffffffff, 0x00010000,
1284 0x3c024, 0xffffffff, 0x00030002,
1285 0x3c028, 0xffffffff, 0x00040007,
1286 0x3c02c, 0xffffffff, 0x00060005,
1287 0x3c030, 0xffffffff, 0x00090008,
1288 0x3c034, 0xffffffff, 0x00010000,
1289 0x3c038, 0xffffffff, 0x00030002,
1290 0x3c03c, 0xffffffff, 0x00040007,
1291 0x3c040, 0xffffffff, 0x00060005,
1292 0x3c044, 0xffffffff, 0x00090008,
1293 0x3c000, 0xffffffff, 0x96e00200,
1294 0x8708, 0xffffffff, 0x00900100,
1295 0xc424, 0xffffffff, 0x0020003f,
1296 0x38, 0xffffffff, 0x0140001c,
1297 0x3c, 0x000f0000, 0x000f0000,
1298 0x220, 0xffffffff, 0xC060000C,
1299 0x224, 0xc0000fff, 0x00000100,
1300 0x20a8, 0xffffffff, 0x00000104,
1301 0x55e4, 0xff000fff, 0x00000100,
1302 0x30cc, 0xc0000fff, 0x00000104,
1303 0xc1e4, 0x00000001, 0x00000001,
1304 0xd00c, 0xff000ff0, 0x00000100,
1305 0xd80c, 0xff000ff0, 0x00000100
1308 static const u32 hawaii_golden_spm_registers[] =
1310 0x30800, 0xe0ffffff, 0xe0000000
1313 static const u32 hawaii_golden_common_registers[] =
1315 0x30800, 0xffffffff, 0xe0000000,
1316 0x28350, 0xffffffff, 0x3a00161a,
1317 0x28354, 0xffffffff, 0x0000002e,
1318 0x9a10, 0xffffffff, 0x00018208,
1319 0x98f8, 0xffffffff, 0x12011003
1322 static const u32 hawaii_golden_registers[] =
1324 0x3354, 0x00000333, 0x00000333,
1325 0x9a10, 0x00010000, 0x00058208,
1326 0x9830, 0xffffffff, 0x00000000,
1327 0x9834, 0xf00fffff, 0x00000400,
1328 0x9838, 0x0002021c, 0x00020200,
1329 0xc78, 0x00000080, 0x00000000,
1330 0x5bb0, 0x000000f0, 0x00000070,
1331 0x5bc0, 0xf0311fff, 0x80300000,
1332 0x350c, 0x00810000, 0x408af000,
1333 0x7030, 0x31000111, 0x00000011,
1334 0x2f48, 0x73773777, 0x12010001,
1335 0x2120, 0x0000007f, 0x0000001b,
1336 0x21dc, 0x00007fb6, 0x00002191,
1337 0x3628, 0x0000003f, 0x0000000a,
1338 0x362c, 0x0000003f, 0x0000000a,
1339 0x2ae4, 0x00073ffe, 0x000022a2,
1340 0x240c, 0x000007ff, 0x00000000,
1341 0x8bf0, 0x00002001, 0x00000001,
1342 0x8b24, 0xffffffff, 0x00ffffff,
1343 0x30a04, 0x0000ff0f, 0x00000000,
1344 0x28a4c, 0x07ffffff, 0x06000000,
1345 0x3e78, 0x00000001, 0x00000002,
1346 0xc768, 0x00000008, 0x00000008,
1347 0xc770, 0x00000f00, 0x00000800,
1348 0xc774, 0x00000f00, 0x00000800,
1349 0xc798, 0x00ffffff, 0x00ff7fbf,
1350 0xc79c, 0x00ffffff, 0x00ff7faf,
1351 0x8c00, 0x000000ff, 0x00000800,
1352 0xe40, 0x00001fff, 0x00001fff,
1353 0x9060, 0x0000007f, 0x00000020,
1354 0x9508, 0x00010000, 0x00010000,
1355 0xae00, 0x00100000, 0x000ff07c,
1356 0xac14, 0x000003ff, 0x0000000f,
1357 0xac10, 0xffffffff, 0x7564fdec,
1358 0xac0c, 0xffffffff, 0x3120b9a8,
1359 0xac08, 0x20000000, 0x0f9c0000
1362 static const u32 hawaii_mgcg_cgcg_init[] =
1364 0xc420, 0xffffffff, 0xfffffffd,
1365 0x30800, 0xffffffff, 0xe0000000,
1366 0x3c2a0, 0xffffffff, 0x00000100,
1367 0x3c208, 0xffffffff, 0x00000100,
1368 0x3c2c0, 0xffffffff, 0x00000100,
1369 0x3c2c8, 0xffffffff, 0x00000100,
1370 0x3c2c4, 0xffffffff, 0x00000100,
1371 0x55e4, 0xffffffff, 0x00200100,
1372 0x3c280, 0xffffffff, 0x00000100,
1373 0x3c214, 0xffffffff, 0x06000100,
1374 0x3c220, 0xffffffff, 0x00000100,
1375 0x3c218, 0xffffffff, 0x06000100,
1376 0x3c204, 0xffffffff, 0x00000100,
1377 0x3c2e0, 0xffffffff, 0x00000100,
1378 0x3c224, 0xffffffff, 0x00000100,
1379 0x3c200, 0xffffffff, 0x00000100,
1380 0x3c230, 0xffffffff, 0x00000100,
1381 0x3c234, 0xffffffff, 0x00000100,
1382 0x3c250, 0xffffffff, 0x00000100,
1383 0x3c254, 0xffffffff, 0x00000100,
1384 0x3c258, 0xffffffff, 0x00000100,
1385 0x3c25c, 0xffffffff, 0x00000100,
1386 0x3c260, 0xffffffff, 0x00000100,
1387 0x3c27c, 0xffffffff, 0x00000100,
1388 0x3c278, 0xffffffff, 0x00000100,
1389 0x3c210, 0xffffffff, 0x06000100,
1390 0x3c290, 0xffffffff, 0x00000100,
1391 0x3c274, 0xffffffff, 0x00000100,
1392 0x3c2b4, 0xffffffff, 0x00000100,
1393 0x3c2b0, 0xffffffff, 0x00000100,
1394 0x3c270, 0xffffffff, 0x00000100,
1395 0x30800, 0xffffffff, 0xe0000000,
1396 0x3c020, 0xffffffff, 0x00010000,
1397 0x3c024, 0xffffffff, 0x00030002,
1398 0x3c028, 0xffffffff, 0x00040007,
1399 0x3c02c, 0xffffffff, 0x00060005,
1400 0x3c030, 0xffffffff, 0x00090008,
1401 0x3c034, 0xffffffff, 0x00010000,
1402 0x3c038, 0xffffffff, 0x00030002,
1403 0x3c03c, 0xffffffff, 0x00040007,
1404 0x3c040, 0xffffffff, 0x00060005,
1405 0x3c044, 0xffffffff, 0x00090008,
1406 0x3c048, 0xffffffff, 0x00010000,
1407 0x3c04c, 0xffffffff, 0x00030002,
1408 0x3c050, 0xffffffff, 0x00040007,
1409 0x3c054, 0xffffffff, 0x00060005,
1410 0x3c058, 0xffffffff, 0x00090008,
1411 0x3c05c, 0xffffffff, 0x00010000,
1412 0x3c060, 0xffffffff, 0x00030002,
1413 0x3c064, 0xffffffff, 0x00040007,
1414 0x3c068, 0xffffffff, 0x00060005,
1415 0x3c06c, 0xffffffff, 0x00090008,
1416 0x3c070, 0xffffffff, 0x00010000,
1417 0x3c074, 0xffffffff, 0x00030002,
1418 0x3c078, 0xffffffff, 0x00040007,
1419 0x3c07c, 0xffffffff, 0x00060005,
1420 0x3c080, 0xffffffff, 0x00090008,
1421 0x3c084, 0xffffffff, 0x00010000,
1422 0x3c088, 0xffffffff, 0x00030002,
1423 0x3c08c, 0xffffffff, 0x00040007,
1424 0x3c090, 0xffffffff, 0x00060005,
1425 0x3c094, 0xffffffff, 0x00090008,
1426 0x3c098, 0xffffffff, 0x00010000,
1427 0x3c09c, 0xffffffff, 0x00030002,
1428 0x3c0a0, 0xffffffff, 0x00040007,
1429 0x3c0a4, 0xffffffff, 0x00060005,
1430 0x3c0a8, 0xffffffff, 0x00090008,
1431 0x3c0ac, 0xffffffff, 0x00010000,
1432 0x3c0b0, 0xffffffff, 0x00030002,
1433 0x3c0b4, 0xffffffff, 0x00040007,
1434 0x3c0b8, 0xffffffff, 0x00060005,
1435 0x3c0bc, 0xffffffff, 0x00090008,
1436 0x3c0c0, 0xffffffff, 0x00010000,
1437 0x3c0c4, 0xffffffff, 0x00030002,
1438 0x3c0c8, 0xffffffff, 0x00040007,
1439 0x3c0cc, 0xffffffff, 0x00060005,
1440 0x3c0d0, 0xffffffff, 0x00090008,
1441 0x3c0d4, 0xffffffff, 0x00010000,
1442 0x3c0d8, 0xffffffff, 0x00030002,
1443 0x3c0dc, 0xffffffff, 0x00040007,
1444 0x3c0e0, 0xffffffff, 0x00060005,
1445 0x3c0e4, 0xffffffff, 0x00090008,
1446 0x3c0e8, 0xffffffff, 0x00010000,
1447 0x3c0ec, 0xffffffff, 0x00030002,
1448 0x3c0f0, 0xffffffff, 0x00040007,
1449 0x3c0f4, 0xffffffff, 0x00060005,
1450 0x3c0f8, 0xffffffff, 0x00090008,
1451 0xc318, 0xffffffff, 0x00020200,
1452 0x3350, 0xffffffff, 0x00000200,
1453 0x15c0, 0xffffffff, 0x00000400,
1454 0x55e8, 0xffffffff, 0x00000000,
1455 0x2f50, 0xffffffff, 0x00000902,
1456 0x3c000, 0xffffffff, 0x96940200,
1457 0x8708, 0xffffffff, 0x00900100,
1458 0xc424, 0xffffffff, 0x0020003f,
1459 0x38, 0xffffffff, 0x0140001c,
1460 0x3c, 0x000f0000, 0x000f0000,
1461 0x220, 0xffffffff, 0xc060000c,
1462 0x224, 0xc0000fff, 0x00000100,
1463 0xf90, 0xffffffff, 0x00000100,
1464 0xf98, 0x00000101, 0x00000000,
1465 0x20a8, 0xffffffff, 0x00000104,
1466 0x55e4, 0xff000fff, 0x00000100,
1467 0x30cc, 0xc0000fff, 0x00000104,
1468 0xc1e4, 0x00000001, 0x00000001,
1469 0xd00c, 0xff000ff0, 0x00000100,
1470 0xd80c, 0xff000ff0, 0x00000100
1473 static void cik_init_golden_registers(struct radeon_device *rdev)
1475 switch (rdev->family) {
1477 radeon_program_register_sequence(rdev,
1478 bonaire_mgcg_cgcg_init,
1479 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1480 radeon_program_register_sequence(rdev,
1481 bonaire_golden_registers,
1482 (const u32)ARRAY_SIZE(bonaire_golden_registers));
1483 radeon_program_register_sequence(rdev,
1484 bonaire_golden_common_registers,
1485 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1486 radeon_program_register_sequence(rdev,
1487 bonaire_golden_spm_registers,
1488 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1491 radeon_program_register_sequence(rdev,
1492 kalindi_mgcg_cgcg_init,
1493 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1494 radeon_program_register_sequence(rdev,
1495 kalindi_golden_registers,
1496 (const u32)ARRAY_SIZE(kalindi_golden_registers));
1497 radeon_program_register_sequence(rdev,
1498 kalindi_golden_common_registers,
1499 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1500 radeon_program_register_sequence(rdev,
1501 kalindi_golden_spm_registers,
1502 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1505 radeon_program_register_sequence(rdev,
1506 spectre_mgcg_cgcg_init,
1507 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1508 radeon_program_register_sequence(rdev,
1509 spectre_golden_registers,
1510 (const u32)ARRAY_SIZE(spectre_golden_registers));
1511 radeon_program_register_sequence(rdev,
1512 spectre_golden_common_registers,
1513 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1514 radeon_program_register_sequence(rdev,
1515 spectre_golden_spm_registers,
1516 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1519 radeon_program_register_sequence(rdev,
1520 hawaii_mgcg_cgcg_init,
1521 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1522 radeon_program_register_sequence(rdev,
1523 hawaii_golden_registers,
1524 (const u32)ARRAY_SIZE(hawaii_golden_registers));
1525 radeon_program_register_sequence(rdev,
1526 hawaii_golden_common_registers,
1527 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1528 radeon_program_register_sequence(rdev,
1529 hawaii_golden_spm_registers,
1530 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1538 * cik_get_xclk - get the xclk
1540 * @rdev: radeon_device pointer
1542 * Returns the reference clock used by the gfx engine
1545 u32 cik_get_xclk(struct radeon_device *rdev)
1547 u32 reference_clock = rdev->clock.spll.reference_freq;
1549 if (rdev->flags & RADEON_IS_IGP) {
1550 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1551 return reference_clock / 2;
1553 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1554 return reference_clock / 4;
1556 return reference_clock;
1560 * cik_mm_rdoorbell - read a doorbell dword
1562 * @rdev: radeon_device pointer
1563 * @index: doorbell index
1565 * Returns the value in the doorbell aperture at the
1566 * requested doorbell index (CIK).
1568 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1570 if (index < rdev->doorbell.num_doorbells) {
1571 return readl(rdev->doorbell.ptr + index);
1573 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1579 * cik_mm_wdoorbell - write a doorbell dword
1581 * @rdev: radeon_device pointer
1582 * @index: doorbell index
1583 * @v: value to write
1585 * Writes @v to the doorbell aperture at the
1586 * requested doorbell index (CIK).
1588 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1590 if (index < rdev->doorbell.num_doorbells) {
1591 writel(v, rdev->doorbell.ptr + index);
1593 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1597 #define BONAIRE_IO_MC_REGS_SIZE 36
1599 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1601 {0x00000070, 0x04400000},
1602 {0x00000071, 0x80c01803},
1603 {0x00000072, 0x00004004},
1604 {0x00000073, 0x00000100},
1605 {0x00000074, 0x00ff0000},
1606 {0x00000075, 0x34000000},
1607 {0x00000076, 0x08000014},
1608 {0x00000077, 0x00cc08ec},
1609 {0x00000078, 0x00000400},
1610 {0x00000079, 0x00000000},
1611 {0x0000007a, 0x04090000},
1612 {0x0000007c, 0x00000000},
1613 {0x0000007e, 0x4408a8e8},
1614 {0x0000007f, 0x00000304},
1615 {0x00000080, 0x00000000},
1616 {0x00000082, 0x00000001},
1617 {0x00000083, 0x00000002},
1618 {0x00000084, 0xf3e4f400},
1619 {0x00000085, 0x052024e3},
1620 {0x00000087, 0x00000000},
1621 {0x00000088, 0x01000000},
1622 {0x0000008a, 0x1c0a0000},
1623 {0x0000008b, 0xff010000},
1624 {0x0000008d, 0xffffefff},
1625 {0x0000008e, 0xfff3efff},
1626 {0x0000008f, 0xfff3efbf},
1627 {0x00000092, 0xf7ffffff},
1628 {0x00000093, 0xffffff7f},
1629 {0x00000095, 0x00101101},
1630 {0x00000096, 0x00000fff},
1631 {0x00000097, 0x00116fff},
1632 {0x00000098, 0x60010000},
1633 {0x00000099, 0x10010000},
1634 {0x0000009a, 0x00006000},
1635 {0x0000009b, 0x00001000},
1636 {0x0000009f, 0x00b48000}
1639 #define HAWAII_IO_MC_REGS_SIZE 22
1641 static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1643 {0x0000007d, 0x40000000},
1644 {0x0000007e, 0x40180304},
1645 {0x0000007f, 0x0000ff00},
1646 {0x00000081, 0x00000000},
1647 {0x00000083, 0x00000800},
1648 {0x00000086, 0x00000000},
1649 {0x00000087, 0x00000100},
1650 {0x00000088, 0x00020100},
1651 {0x00000089, 0x00000000},
1652 {0x0000008b, 0x00040000},
1653 {0x0000008c, 0x00000100},
1654 {0x0000008e, 0xff010000},
1655 {0x00000090, 0xffffefff},
1656 {0x00000091, 0xfff3efff},
1657 {0x00000092, 0xfff3efbf},
1658 {0x00000093, 0xf7ffffff},
1659 {0x00000094, 0xffffff7f},
1660 {0x00000095, 0x00000fff},
1661 {0x00000096, 0x00116fff},
1662 {0x00000097, 0x60010000},
1663 {0x00000098, 0x10010000},
1664 {0x0000009f, 0x00c79000}
1669 * cik_srbm_select - select specific register instances
1671 * @rdev: radeon_device pointer
1672 * @me: selected ME (micro engine)
1677 * Switches the currently active registers instances. Some
1678 * registers are instanced per VMID, others are instanced per
1679 * me/pipe/queue combination.
1681 static void cik_srbm_select(struct radeon_device *rdev,
1682 u32 me, u32 pipe, u32 queue, u32 vmid)
1684 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1687 QUEUEID(queue & 0x7));
1688 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1693 * ci_mc_load_microcode - load MC ucode into the hw
1695 * @rdev: radeon_device pointer
1697 * Load the GDDR MC ucode into the hw (CIK).
1698 * Returns 0 on success, error on failure.
1700 int ci_mc_load_microcode(struct radeon_device *rdev)
1702 const __be32 *fw_data;
1703 u32 running, blackout = 0;
1705 int i, ucode_size, regs_size;
1710 switch (rdev->family) {
1712 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1713 ucode_size = CIK_MC_UCODE_SIZE;
1714 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1717 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1718 ucode_size = HAWAII_MC_UCODE_SIZE;
1719 regs_size = HAWAII_IO_MC_REGS_SIZE;
1725 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1729 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1730 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1733 /* reset the engine and set to writable */
1734 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1735 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1737 /* load mc io regs */
1738 for (i = 0; i < regs_size; i++) {
1739 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1740 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1742 /* load the MC ucode */
1743 fw_data = (const __be32 *)rdev->mc_fw->data;
1744 for (i = 0; i < ucode_size; i++)
1745 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1747 /* put the engine back into the active state */
1748 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1749 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1750 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1752 /* wait for training to complete */
1753 for (i = 0; i < rdev->usec_timeout; i++) {
1754 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1758 for (i = 0; i < rdev->usec_timeout; i++) {
1759 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1765 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1772 * cik_init_microcode - load ucode images from disk
1774 * @rdev: radeon_device pointer
1776 * Use the firmware interface to load the ucode images into
1777 * the driver (not loaded into hw).
1778 * Returns 0 on success, error on failure.
1780 static int cik_init_microcode(struct radeon_device *rdev)
1782 const char *chip_name;
1783 size_t pfp_req_size, me_req_size, ce_req_size,
1784 mec_req_size, rlc_req_size, mc_req_size = 0,
1785 sdma_req_size, smc_req_size = 0;
1791 switch (rdev->family) {
1793 chip_name = "BONAIRE";
1794 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1795 me_req_size = CIK_ME_UCODE_SIZE * 4;
1796 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1797 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1798 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1799 mc_req_size = CIK_MC_UCODE_SIZE * 4;
1800 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1801 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
1804 chip_name = "HAWAII";
1805 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1806 me_req_size = CIK_ME_UCODE_SIZE * 4;
1807 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1808 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1809 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1810 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
1811 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1812 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
1815 chip_name = "KAVERI";
1816 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1817 me_req_size = CIK_ME_UCODE_SIZE * 4;
1818 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1819 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1820 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
1821 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1824 chip_name = "KABINI";
1825 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1826 me_req_size = CIK_ME_UCODE_SIZE * 4;
1827 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1828 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1829 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
1830 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1835 DRM_INFO("Loading %s Microcode\n", chip_name);
1837 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1838 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1841 if (rdev->pfp_fw->size != pfp_req_size) {
1843 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1844 rdev->pfp_fw->size, fw_name);
1849 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1850 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1853 if (rdev->me_fw->size != me_req_size) {
1855 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1856 rdev->me_fw->size, fw_name);
1860 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1861 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1864 if (rdev->ce_fw->size != ce_req_size) {
1866 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1867 rdev->ce_fw->size, fw_name);
1871 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
1872 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
1875 if (rdev->mec_fw->size != mec_req_size) {
1877 "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1878 rdev->mec_fw->size, fw_name);
1882 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1883 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1886 if (rdev->rlc_fw->size != rlc_req_size) {
1888 "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
1889 rdev->rlc_fw->size, fw_name);
1893 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
1894 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
1897 if (rdev->sdma_fw->size != sdma_req_size) {
1899 "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
1900 rdev->sdma_fw->size, fw_name);
1904 /* No SMC, MC ucode on APUs */
1905 if (!(rdev->flags & RADEON_IS_IGP)) {
1906 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1907 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1910 if (rdev->mc_fw->size != mc_req_size) {
1912 "cik_mc: Bogus length %zu in firmware \"%s\"\n",
1913 rdev->mc_fw->size, fw_name);
1917 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1918 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1921 "smc: error loading firmware \"%s\"\n",
1923 release_firmware(rdev->smc_fw);
1924 rdev->smc_fw = NULL;
1926 } else if (rdev->smc_fw->size != smc_req_size) {
1928 "cik_smc: Bogus length %zu in firmware \"%s\"\n",
1929 rdev->smc_fw->size, fw_name);
1938 "cik_cp: Failed to load firmware \"%s\"\n",
1940 release_firmware(rdev->pfp_fw);
1941 rdev->pfp_fw = NULL;
1942 release_firmware(rdev->me_fw);
1944 release_firmware(rdev->ce_fw);
1946 release_firmware(rdev->rlc_fw);
1947 rdev->rlc_fw = NULL;
1948 release_firmware(rdev->mc_fw);
1950 release_firmware(rdev->smc_fw);
1951 rdev->smc_fw = NULL;
1960 * cik_tiling_mode_table_init - init the hw tiling table
1962 * @rdev: radeon_device pointer
1964 * Starting with SI, the tiling setup is done globally in a
1965 * set of 32 tiling modes. Rather than selecting each set of
1966 * parameters per surface as on older asics, we just select
1967 * which index in the tiling table we want to use, and the
1968 * surface uses those parameters (CIK).
1970 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
1972 const u32 num_tile_mode_states = 32;
1973 const u32 num_secondary_tile_mode_states = 16;
1974 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1975 u32 num_pipe_configs;
1976 u32 num_rbs = rdev->config.cik.max_backends_per_se *
1977 rdev->config.cik.max_shader_engines;
1979 switch (rdev->config.cik.mem_row_size_in_kb) {
1981 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1985 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1988 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1992 num_pipe_configs = rdev->config.cik.max_tile_pipes;
1993 if (num_pipe_configs > 8)
1994 num_pipe_configs = 16;
1996 if (num_pipe_configs == 16) {
1997 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1998 switch (reg_offset) {
2000 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2001 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2002 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2006 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2007 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2008 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2012 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2013 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2014 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2015 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2018 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2019 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2020 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2024 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2025 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2026 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2027 TILE_SPLIT(split_equal_to_row_size));
2030 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2031 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2034 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2035 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2036 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2040 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2041 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2042 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2043 TILE_SPLIT(split_equal_to_row_size));
2046 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2047 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2050 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2051 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2054 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2055 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2056 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2060 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2061 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2062 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2063 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2066 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2067 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2068 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2069 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2072 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2073 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2076 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2077 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2078 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2079 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2082 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2083 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2084 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2088 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2089 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2090 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2094 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2095 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2098 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2100 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2104 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2105 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2106 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2110 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2111 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2112 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2119 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2120 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2122 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2123 switch (reg_offset) {
2125 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2128 NUM_BANKS(ADDR_SURF_16_BANK));
2131 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2133 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2134 NUM_BANKS(ADDR_SURF_16_BANK));
2137 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2140 NUM_BANKS(ADDR_SURF_16_BANK));
2143 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2145 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2146 NUM_BANKS(ADDR_SURF_16_BANK));
2149 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2152 NUM_BANKS(ADDR_SURF_8_BANK));
2155 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2158 NUM_BANKS(ADDR_SURF_4_BANK));
2161 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2164 NUM_BANKS(ADDR_SURF_2_BANK));
2167 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2170 NUM_BANKS(ADDR_SURF_16_BANK));
2173 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2176 NUM_BANKS(ADDR_SURF_16_BANK));
2179 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2182 NUM_BANKS(ADDR_SURF_16_BANK));
2185 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2186 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2187 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2188 NUM_BANKS(ADDR_SURF_8_BANK));
2191 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2194 NUM_BANKS(ADDR_SURF_4_BANK));
2197 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2200 NUM_BANKS(ADDR_SURF_2_BANK));
2203 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2206 NUM_BANKS(ADDR_SURF_2_BANK));
2212 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2214 } else if (num_pipe_configs == 8) {
2215 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2216 switch (reg_offset) {
2218 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2220 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2224 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2225 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2226 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2230 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2232 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2236 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2238 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2242 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2243 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2244 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2245 TILE_SPLIT(split_equal_to_row_size));
2248 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2249 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2252 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2253 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2254 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2258 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2259 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2260 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2261 TILE_SPLIT(split_equal_to_row_size));
2264 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2265 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2268 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2269 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2272 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2273 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2274 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2278 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2279 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2280 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2284 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2285 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2286 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2290 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2291 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2294 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2295 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2296 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2300 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2301 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2302 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2303 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2306 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2307 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2308 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2312 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2313 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2316 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2317 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2318 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2322 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2323 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2324 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2328 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2330 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2337 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2338 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2340 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2341 switch (reg_offset) {
2343 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2346 NUM_BANKS(ADDR_SURF_16_BANK));
2349 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2352 NUM_BANKS(ADDR_SURF_16_BANK));
2355 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2358 NUM_BANKS(ADDR_SURF_16_BANK));
2361 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2364 NUM_BANKS(ADDR_SURF_16_BANK));
2367 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2370 NUM_BANKS(ADDR_SURF_8_BANK));
2373 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2376 NUM_BANKS(ADDR_SURF_4_BANK));
2379 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2382 NUM_BANKS(ADDR_SURF_2_BANK));
2385 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2388 NUM_BANKS(ADDR_SURF_16_BANK));
2391 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2394 NUM_BANKS(ADDR_SURF_16_BANK));
2397 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2400 NUM_BANKS(ADDR_SURF_16_BANK));
2403 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2406 NUM_BANKS(ADDR_SURF_16_BANK));
2409 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2412 NUM_BANKS(ADDR_SURF_8_BANK));
2415 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2418 NUM_BANKS(ADDR_SURF_4_BANK));
2421 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2424 NUM_BANKS(ADDR_SURF_2_BANK));
2430 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2431 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2433 } else if (num_pipe_configs == 4) {
2435 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2436 switch (reg_offset) {
2438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2439 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2440 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2444 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2445 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2446 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2447 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2450 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2451 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2452 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2453 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2456 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2457 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2458 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2462 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2463 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2464 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2465 TILE_SPLIT(split_equal_to_row_size));
2468 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2469 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2472 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2473 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2474 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2475 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2478 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2479 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2480 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2481 TILE_SPLIT(split_equal_to_row_size));
2484 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2485 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2488 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2489 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2492 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2493 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2494 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2498 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2499 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2500 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2501 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2504 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2505 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2506 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2507 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2510 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2511 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2514 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2515 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2516 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2517 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2520 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2521 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2522 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2523 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2526 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2527 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2528 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2529 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2532 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2533 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2536 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2537 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2538 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2539 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2542 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2544 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2545 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2548 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2549 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2550 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2551 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2558 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2560 } else if (num_rbs < 4) {
2561 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2562 switch (reg_offset) {
2564 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2565 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2566 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2567 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2570 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2572 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2576 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2577 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2578 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2579 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2582 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2584 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2589 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2590 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2591 TILE_SPLIT(split_equal_to_row_size));
2594 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2598 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2600 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2604 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2605 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2606 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2607 TILE_SPLIT(split_equal_to_row_size));
2610 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2611 PIPE_CONFIG(ADDR_SURF_P4_8x16));
2614 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2619 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2620 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2621 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2624 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2625 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2626 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2627 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2630 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2631 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2632 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2633 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2636 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2637 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2641 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2642 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2643 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2646 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2647 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2648 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2649 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2652 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2653 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2654 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2655 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2658 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2659 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2662 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2663 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2664 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2665 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2668 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2669 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2670 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2671 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2674 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2675 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2676 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2677 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2683 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2684 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2687 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2688 switch (reg_offset) {
2690 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2693 NUM_BANKS(ADDR_SURF_16_BANK));
2696 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2698 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2699 NUM_BANKS(ADDR_SURF_16_BANK));
2702 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2705 NUM_BANKS(ADDR_SURF_16_BANK));
2708 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2711 NUM_BANKS(ADDR_SURF_16_BANK));
2714 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2716 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2717 NUM_BANKS(ADDR_SURF_16_BANK));
2720 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2723 NUM_BANKS(ADDR_SURF_8_BANK));
2726 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2729 NUM_BANKS(ADDR_SURF_4_BANK));
2732 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2733 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2734 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2735 NUM_BANKS(ADDR_SURF_16_BANK));
2738 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2741 NUM_BANKS(ADDR_SURF_16_BANK));
2744 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2747 NUM_BANKS(ADDR_SURF_16_BANK));
2750 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2753 NUM_BANKS(ADDR_SURF_16_BANK));
2756 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2757 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2758 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2759 NUM_BANKS(ADDR_SURF_16_BANK));
2762 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2765 NUM_BANKS(ADDR_SURF_8_BANK));
2768 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2771 NUM_BANKS(ADDR_SURF_4_BANK));
2777 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2778 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2780 } else if (num_pipe_configs == 2) {
2781 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2782 switch (reg_offset) {
2784 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2786 PIPE_CONFIG(ADDR_SURF_P2) |
2787 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2790 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2791 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2792 PIPE_CONFIG(ADDR_SURF_P2) |
2793 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2796 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2798 PIPE_CONFIG(ADDR_SURF_P2) |
2799 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2802 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2803 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2804 PIPE_CONFIG(ADDR_SURF_P2) |
2805 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2808 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2809 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2810 PIPE_CONFIG(ADDR_SURF_P2) |
2811 TILE_SPLIT(split_equal_to_row_size));
2814 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2815 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2818 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2819 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2820 PIPE_CONFIG(ADDR_SURF_P2) |
2821 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2824 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2825 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2826 PIPE_CONFIG(ADDR_SURF_P2) |
2827 TILE_SPLIT(split_equal_to_row_size));
2830 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
2833 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2834 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2837 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2838 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2839 PIPE_CONFIG(ADDR_SURF_P2) |
2840 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2843 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2844 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2845 PIPE_CONFIG(ADDR_SURF_P2) |
2846 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2849 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2850 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2851 PIPE_CONFIG(ADDR_SURF_P2) |
2852 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2855 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2856 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2859 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2860 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2861 PIPE_CONFIG(ADDR_SURF_P2) |
2862 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2865 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2866 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2867 PIPE_CONFIG(ADDR_SURF_P2) |
2868 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2871 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2872 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2873 PIPE_CONFIG(ADDR_SURF_P2) |
2874 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2877 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2878 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2881 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2882 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2883 PIPE_CONFIG(ADDR_SURF_P2) |
2884 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2887 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2888 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2889 PIPE_CONFIG(ADDR_SURF_P2) |
2890 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2893 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2894 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2895 PIPE_CONFIG(ADDR_SURF_P2) |
2896 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2902 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2903 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2905 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2906 switch (reg_offset) {
2908 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2911 NUM_BANKS(ADDR_SURF_16_BANK));
2914 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2915 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2916 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2917 NUM_BANKS(ADDR_SURF_16_BANK));
2920 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2923 NUM_BANKS(ADDR_SURF_16_BANK));
2926 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2927 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2928 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2929 NUM_BANKS(ADDR_SURF_16_BANK));
2932 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2933 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2934 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2935 NUM_BANKS(ADDR_SURF_16_BANK));
2938 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2941 NUM_BANKS(ADDR_SURF_16_BANK));
2944 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2947 NUM_BANKS(ADDR_SURF_8_BANK));
2950 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2951 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2952 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2953 NUM_BANKS(ADDR_SURF_16_BANK));
2956 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2959 NUM_BANKS(ADDR_SURF_16_BANK));
2962 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2963 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2964 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2965 NUM_BANKS(ADDR_SURF_16_BANK));
2968 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971 NUM_BANKS(ADDR_SURF_16_BANK));
2974 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2977 NUM_BANKS(ADDR_SURF_16_BANK));
2980 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2983 NUM_BANKS(ADDR_SURF_16_BANK));
2986 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2987 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2988 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2989 NUM_BANKS(ADDR_SURF_8_BANK));
2995 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2996 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2999 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3003 * cik_select_se_sh - select which SE, SH to address
3005 * @rdev: radeon_device pointer
3006 * @se_num: shader engine to address
3007 * @sh_num: sh block to address
3009 * Select which SE, SH combinations to address. Certain
3010 * registers are instanced per SE or SH. 0xffffffff means
3011 * broadcast to all SEs or SHs (CIK).
3013 static void cik_select_se_sh(struct radeon_device *rdev,
3014 u32 se_num, u32 sh_num)
3016 u32 data = INSTANCE_BROADCAST_WRITES;
3018 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3019 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3020 else if (se_num == 0xffffffff)
3021 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3022 else if (sh_num == 0xffffffff)
3023 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3025 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3026 WREG32(GRBM_GFX_INDEX, data);
3030 * cik_create_bitmask - create a bitmask
3032 * @bit_width: length of the mask
3034 * create a variable length bit mask (CIK).
3035 * Returns the bitmask.
3037 static u32 cik_create_bitmask(u32 bit_width)
3041 for (i = 0; i < bit_width; i++) {
3049 * cik_select_se_sh - select which SE, SH to address
3051 * @rdev: radeon_device pointer
3052 * @max_rb_num: max RBs (render backends) for the asic
3053 * @se_num: number of SEs (shader engines) for the asic
3054 * @sh_per_se: number of SH blocks per SE for the asic
3056 * Calculates the bitmask of disabled RBs (CIK).
3057 * Returns the disabled RB bitmask.
3059 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3060 u32 max_rb_num_per_se,
3065 data = RREG32(CC_RB_BACKEND_DISABLE);
3067 data &= BACKEND_DISABLE_MASK;
3070 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3072 data >>= BACKEND_DISABLE_SHIFT;
3074 mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3080 * cik_setup_rb - setup the RBs on the asic
3082 * @rdev: radeon_device pointer
3083 * @se_num: number of SEs (shader engines) for the asic
3084 * @sh_per_se: number of SH blocks per SE for the asic
3085 * @max_rb_num: max RBs (render backends) for the asic
3087 * Configures per-SE/SH RB registers (CIK).
3089 static void cik_setup_rb(struct radeon_device *rdev,
3090 u32 se_num, u32 sh_per_se,
3091 u32 max_rb_num_per_se)
3095 u32 disabled_rbs = 0;
3096 u32 enabled_rbs = 0;
3098 for (i = 0; i < se_num; i++) {
3099 for (j = 0; j < sh_per_se; j++) {
3100 cik_select_se_sh(rdev, i, j);
3101 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3102 if (rdev->family == CHIP_HAWAII)
3103 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3105 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3108 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3111 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3112 if (!(disabled_rbs & mask))
3113 enabled_rbs |= mask;
3117 rdev->config.cik.backend_enable_mask = enabled_rbs;
3119 for (i = 0; i < se_num; i++) {
3120 cik_select_se_sh(rdev, i, 0xffffffff);
3122 for (j = 0; j < sh_per_se; j++) {
3123 switch (enabled_rbs & 3) {
3126 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3128 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3131 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3134 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3138 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3143 WREG32(PA_SC_RASTER_CONFIG, data);
3145 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3149 * cik_gpu_init - setup the 3D engine
3151 * @rdev: radeon_device pointer
3153 * Configures the 3D engine and tiling configuration
3154 * registers so that the 3D engine is usable.
3156 static void cik_gpu_init(struct radeon_device *rdev)
3158 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3159 u32 mc_shared_chmap, mc_arb_ramcfg;
3160 u32 hdp_host_path_cntl;
3164 switch (rdev->family) {
3166 rdev->config.cik.max_shader_engines = 2;
3167 rdev->config.cik.max_tile_pipes = 4;
3168 rdev->config.cik.max_cu_per_sh = 7;
3169 rdev->config.cik.max_sh_per_se = 1;
3170 rdev->config.cik.max_backends_per_se = 2;
3171 rdev->config.cik.max_texture_channel_caches = 4;
3172 rdev->config.cik.max_gprs = 256;
3173 rdev->config.cik.max_gs_threads = 32;
3174 rdev->config.cik.max_hw_contexts = 8;
3176 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3177 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3178 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3179 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3180 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3183 rdev->config.cik.max_shader_engines = 4;
3184 rdev->config.cik.max_tile_pipes = 16;
3185 rdev->config.cik.max_cu_per_sh = 11;
3186 rdev->config.cik.max_sh_per_se = 1;
3187 rdev->config.cik.max_backends_per_se = 4;
3188 rdev->config.cik.max_texture_channel_caches = 16;
3189 rdev->config.cik.max_gprs = 256;
3190 rdev->config.cik.max_gs_threads = 32;
3191 rdev->config.cik.max_hw_contexts = 8;
3193 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3194 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3195 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3196 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3197 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3200 rdev->config.cik.max_shader_engines = 1;
3201 rdev->config.cik.max_tile_pipes = 4;
3202 if ((rdev->pdev->device == 0x1304) ||
3203 (rdev->pdev->device == 0x1305) ||
3204 (rdev->pdev->device == 0x130C) ||
3205 (rdev->pdev->device == 0x130F) ||
3206 (rdev->pdev->device == 0x1310) ||
3207 (rdev->pdev->device == 0x1311) ||
3208 (rdev->pdev->device == 0x131C)) {
3209 rdev->config.cik.max_cu_per_sh = 8;
3210 rdev->config.cik.max_backends_per_se = 2;
3211 } else if ((rdev->pdev->device == 0x1309) ||
3212 (rdev->pdev->device == 0x130A) ||
3213 (rdev->pdev->device == 0x130D) ||
3214 (rdev->pdev->device == 0x1313) ||
3215 (rdev->pdev->device == 0x131D)) {
3216 rdev->config.cik.max_cu_per_sh = 6;
3217 rdev->config.cik.max_backends_per_se = 2;
3218 } else if ((rdev->pdev->device == 0x1306) ||
3219 (rdev->pdev->device == 0x1307) ||
3220 (rdev->pdev->device == 0x130B) ||
3221 (rdev->pdev->device == 0x130E) ||
3222 (rdev->pdev->device == 0x1315) ||
3223 (rdev->pdev->device == 0x131B)) {
3224 rdev->config.cik.max_cu_per_sh = 4;
3225 rdev->config.cik.max_backends_per_se = 1;
3227 rdev->config.cik.max_cu_per_sh = 3;
3228 rdev->config.cik.max_backends_per_se = 1;
3230 rdev->config.cik.max_sh_per_se = 1;
3231 rdev->config.cik.max_texture_channel_caches = 4;
3232 rdev->config.cik.max_gprs = 256;
3233 rdev->config.cik.max_gs_threads = 16;
3234 rdev->config.cik.max_hw_contexts = 8;
3236 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3237 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3238 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3239 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3240 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3244 rdev->config.cik.max_shader_engines = 1;
3245 rdev->config.cik.max_tile_pipes = 2;
3246 rdev->config.cik.max_cu_per_sh = 2;
3247 rdev->config.cik.max_sh_per_se = 1;
3248 rdev->config.cik.max_backends_per_se = 1;
3249 rdev->config.cik.max_texture_channel_caches = 2;
3250 rdev->config.cik.max_gprs = 256;
3251 rdev->config.cik.max_gs_threads = 16;
3252 rdev->config.cik.max_hw_contexts = 8;
3254 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3255 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3256 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3257 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3258 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3262 /* Initialize HDP */
3263 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3264 WREG32((0x2c14 + j), 0x00000000);
3265 WREG32((0x2c18 + j), 0x00000000);
3266 WREG32((0x2c1c + j), 0x00000000);
3267 WREG32((0x2c20 + j), 0x00000000);
3268 WREG32((0x2c24 + j), 0x00000000);
3271 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3273 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3275 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3276 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3278 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3279 rdev->config.cik.mem_max_burst_length_bytes = 256;
3280 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3281 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3282 if (rdev->config.cik.mem_row_size_in_kb > 4)
3283 rdev->config.cik.mem_row_size_in_kb = 4;
3284 /* XXX use MC settings? */
3285 rdev->config.cik.shader_engine_tile_size = 32;
3286 rdev->config.cik.num_gpus = 1;
3287 rdev->config.cik.multi_gpu_tile_size = 64;
3289 /* fix up row size */
3290 gb_addr_config &= ~ROW_SIZE_MASK;
3291 switch (rdev->config.cik.mem_row_size_in_kb) {
3294 gb_addr_config |= ROW_SIZE(0);
3297 gb_addr_config |= ROW_SIZE(1);
3300 gb_addr_config |= ROW_SIZE(2);
3304 /* setup tiling info dword. gb_addr_config is not adequate since it does
3305 * not have bank info, so create a custom tiling dword.
3306 * bits 3:0 num_pipes
3307 * bits 7:4 num_banks
3308 * bits 11:8 group_size
3309 * bits 15:12 row_size
3311 rdev->config.cik.tile_config = 0;
3312 switch (rdev->config.cik.num_tile_pipes) {
3314 rdev->config.cik.tile_config |= (0 << 0);
3317 rdev->config.cik.tile_config |= (1 << 0);
3320 rdev->config.cik.tile_config |= (2 << 0);
3324 /* XXX what about 12? */
3325 rdev->config.cik.tile_config |= (3 << 0);
3328 rdev->config.cik.tile_config |=
3329 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
3330 rdev->config.cik.tile_config |=
3331 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3332 rdev->config.cik.tile_config |=
3333 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3335 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3336 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3337 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3338 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3339 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3340 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3341 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3342 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3344 cik_tiling_mode_table_init(rdev);
3346 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3347 rdev->config.cik.max_sh_per_se,
3348 rdev->config.cik.max_backends_per_se);
3350 /* set HW defaults for 3D engine */
3351 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3353 WREG32(SX_DEBUG_1, 0x20);
3355 WREG32(TA_CNTL_AUX, 0x00010000);
3357 tmp = RREG32(SPI_CONFIG_CNTL);
3359 WREG32(SPI_CONFIG_CNTL, tmp);
3361 WREG32(SQ_CONFIG, 1);
3363 WREG32(DB_DEBUG, 0);
3365 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3367 WREG32(DB_DEBUG2, tmp);
3369 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3371 WREG32(DB_DEBUG3, tmp);
3373 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3375 WREG32(CB_HW_CONTROL, tmp);
3377 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3379 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3380 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3381 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3382 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3384 WREG32(VGT_NUM_INSTANCES, 1);
3386 WREG32(CP_PERFMON_CNTL, 0);
3388 WREG32(SQ_CONFIG, 0);
3390 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3391 FORCE_EOV_MAX_REZ_CNT(255)));
3393 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3394 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3396 WREG32(VGT_GS_VERTEX_REUSE, 16);
3397 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3399 tmp = RREG32(HDP_MISC_CNTL);
3400 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3401 WREG32(HDP_MISC_CNTL, tmp);
3403 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3404 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3406 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3407 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3413 * GPU scratch registers helpers function.
3416 * cik_scratch_init - setup driver info for CP scratch regs
3418 * @rdev: radeon_device pointer
3420 * Set up the number and offset of the CP scratch registers.
3421 * NOTE: use of CP scratch registers is a legacy inferface and
3422 * is not used by default on newer asics (r6xx+). On newer asics,
3423 * memory buffers are used for fences rather than scratch regs.
3425 static void cik_scratch_init(struct radeon_device *rdev)
3429 rdev->scratch.num_reg = 7;
3430 rdev->scratch.reg_base = SCRATCH_REG0;
3431 for (i = 0; i < rdev->scratch.num_reg; i++) {
3432 rdev->scratch.free[i] = true;
3433 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3438 * cik_ring_test - basic gfx ring test
3440 * @rdev: radeon_device pointer
3441 * @ring: radeon_ring structure holding ring information
3443 * Allocate a scratch register and write to it using the gfx ring (CIK).
3444 * Provides a basic gfx ring test to verify that the ring is working.
3445 * Used by cik_cp_gfx_resume();
3446 * Returns 0 on success, error on failure.
3448 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3455 r = radeon_scratch_get(rdev, &scratch);
3457 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3460 WREG32(scratch, 0xCAFEDEAD);
3461 r = radeon_ring_lock(rdev, ring, 3);
3463 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3464 radeon_scratch_free(rdev, scratch);
3467 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3468 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3469 radeon_ring_write(ring, 0xDEADBEEF);
3470 radeon_ring_unlock_commit(rdev, ring);
3472 for (i = 0; i < rdev->usec_timeout; i++) {
3473 tmp = RREG32(scratch);
3474 if (tmp == 0xDEADBEEF)
3478 if (i < rdev->usec_timeout) {
3479 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3481 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3482 ring->idx, scratch, tmp);
3485 radeon_scratch_free(rdev, scratch);
3490 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3492 * @rdev: radeon_device pointer
3493 * @ridx: radeon ring index
3495 * Emits an hdp flush on the cp.
3497 static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3500 struct radeon_ring *ring = &rdev->ring[ridx];
3503 switch (ring->idx) {
3504 case CAYMAN_RING_TYPE_CP1_INDEX:
3505 case CAYMAN_RING_TYPE_CP2_INDEX:
3509 ref_and_mask = CP2 << ring->pipe;
3512 ref_and_mask = CP6 << ring->pipe;
3518 case RADEON_RING_TYPE_GFX_INDEX:
3523 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3524 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3525 WAIT_REG_MEM_FUNCTION(3) | /* == */
3526 WAIT_REG_MEM_ENGINE(1))); /* pfp */
3527 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3528 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3529 radeon_ring_write(ring, ref_and_mask);
3530 radeon_ring_write(ring, ref_and_mask);
3531 radeon_ring_write(ring, 0x20); /* poll interval */
3535 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3537 * @rdev: radeon_device pointer
3538 * @fence: radeon fence object
3540 * Emits a fence sequnce number on the gfx ring and flushes
3543 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3544 struct radeon_fence *fence)
3546 struct radeon_ring *ring = &rdev->ring[fence->ring];
3547 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3549 /* EVENT_WRITE_EOP - flush caches, send int */
3550 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3551 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3553 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3555 radeon_ring_write(ring, addr & 0xfffffffc);
3556 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3557 radeon_ring_write(ring, fence->seq);
3558 radeon_ring_write(ring, 0);
3560 cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3564 * cik_fence_compute_ring_emit - emit a fence on the compute ring
3566 * @rdev: radeon_device pointer
3567 * @fence: radeon fence object
3569 * Emits a fence sequnce number on the compute ring and flushes
3572 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3573 struct radeon_fence *fence)
3575 struct radeon_ring *ring = &rdev->ring[fence->ring];
3576 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3578 /* RELEASE_MEM - flush caches, send int */
3579 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3580 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3582 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3584 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3585 radeon_ring_write(ring, addr & 0xfffffffc);
3586 radeon_ring_write(ring, upper_32_bits(addr));
3587 radeon_ring_write(ring, fence->seq);
3588 radeon_ring_write(ring, 0);
3590 cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3593 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3594 struct radeon_ring *ring,
3595 struct radeon_semaphore *semaphore,
3598 uint64_t addr = semaphore->gpu_addr;
3599 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3601 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3602 radeon_ring_write(ring, addr & 0xffffffff);
3603 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3609 * cik_copy_cpdma - copy pages using the CP DMA engine
3611 * @rdev: radeon_device pointer
3612 * @src_offset: src GPU address
3613 * @dst_offset: dst GPU address
3614 * @num_gpu_pages: number of GPU pages to xfer
3615 * @fence: radeon fence object
3617 * Copy GPU paging using the CP DMA engine (CIK+).
3618 * Used by the radeon ttm implementation to move pages if
3619 * registered as the asic copy callback.
3621 int cik_copy_cpdma(struct radeon_device *rdev,
3622 uint64_t src_offset, uint64_t dst_offset,
3623 unsigned num_gpu_pages,
3624 struct radeon_fence **fence)
3626 struct radeon_semaphore *sem = NULL;
3627 int ring_index = rdev->asic->copy.blit_ring_index;
3628 struct radeon_ring *ring = &rdev->ring[ring_index];
3629 u32 size_in_bytes, cur_size_in_bytes, control;
3633 r = radeon_semaphore_create(rdev, &sem);
3635 DRM_ERROR("radeon: moving bo (%d).\n", r);
3639 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3640 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3641 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3643 DRM_ERROR("radeon: moving bo (%d).\n", r);
3644 radeon_semaphore_free(rdev, &sem, NULL);
3648 radeon_semaphore_sync_to(sem, *fence);
3649 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
3651 for (i = 0; i < num_loops; i++) {
3652 cur_size_in_bytes = size_in_bytes;
3653 if (cur_size_in_bytes > 0x1fffff)
3654 cur_size_in_bytes = 0x1fffff;
3655 size_in_bytes -= cur_size_in_bytes;
3657 if (size_in_bytes == 0)
3658 control |= PACKET3_DMA_DATA_CP_SYNC;
3659 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
3660 radeon_ring_write(ring, control);
3661 radeon_ring_write(ring, lower_32_bits(src_offset));
3662 radeon_ring_write(ring, upper_32_bits(src_offset));
3663 radeon_ring_write(ring, lower_32_bits(dst_offset));
3664 radeon_ring_write(ring, upper_32_bits(dst_offset));
3665 radeon_ring_write(ring, cur_size_in_bytes);
3666 src_offset += cur_size_in_bytes;
3667 dst_offset += cur_size_in_bytes;
3670 r = radeon_fence_emit(rdev, fence, ring->idx);
3672 radeon_ring_unlock_undo(rdev, ring);
3676 radeon_ring_unlock_commit(rdev, ring);
3677 radeon_semaphore_free(rdev, &sem, *fence);
3686 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
3688 * @rdev: radeon_device pointer
3689 * @ib: radeon indirect buffer object
3691 * Emits an DE (drawing engine) or CE (constant engine) IB
3692 * on the gfx ring. IBs are usually generated by userspace
3693 * acceleration drivers and submitted to the kernel for
3694 * sheduling on the ring. This function schedules the IB
3695 * on the gfx ring for execution by the GPU.
3697 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3699 struct radeon_ring *ring = &rdev->ring[ib->ring];
3700 u32 header, control = INDIRECT_BUFFER_VALID;
3702 if (ib->is_const_ib) {
3703 /* set switch buffer packet before const IB */
3704 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3705 radeon_ring_write(ring, 0);
3707 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3710 if (ring->rptr_save_reg) {
3711 next_rptr = ring->wptr + 3 + 4;
3712 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3713 radeon_ring_write(ring, ((ring->rptr_save_reg -
3714 PACKET3_SET_UCONFIG_REG_START) >> 2));
3715 radeon_ring_write(ring, next_rptr);
3716 } else if (rdev->wb.enabled) {
3717 next_rptr = ring->wptr + 5 + 4;
3718 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3719 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
3720 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3721 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3722 radeon_ring_write(ring, next_rptr);
3725 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3728 control |= ib->length_dw |
3729 (ib->vm ? (ib->vm->id << 24) : 0);
3731 radeon_ring_write(ring, header);
3732 radeon_ring_write(ring,
3736 (ib->gpu_addr & 0xFFFFFFFC));
3737 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3738 radeon_ring_write(ring, control);
3742 * cik_ib_test - basic gfx ring IB test
3744 * @rdev: radeon_device pointer
3745 * @ring: radeon_ring structure holding ring information
3747 * Allocate an IB and execute it on the gfx ring (CIK).
3748 * Provides a basic gfx ring test to verify that IBs are working.
3749 * Returns 0 on success, error on failure.
3751 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3753 struct radeon_ib ib;
3759 r = radeon_scratch_get(rdev, &scratch);
3761 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3764 WREG32(scratch, 0xCAFEDEAD);
3765 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3767 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3768 radeon_scratch_free(rdev, scratch);
3771 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3772 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
3773 ib.ptr[2] = 0xDEADBEEF;
3775 r = radeon_ib_schedule(rdev, &ib, NULL);
3777 radeon_scratch_free(rdev, scratch);
3778 radeon_ib_free(rdev, &ib);
3779 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3782 r = radeon_fence_wait(ib.fence, false);
3784 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3785 radeon_scratch_free(rdev, scratch);
3786 radeon_ib_free(rdev, &ib);
3789 for (i = 0; i < rdev->usec_timeout; i++) {
3790 tmp = RREG32(scratch);
3791 if (tmp == 0xDEADBEEF)
3795 if (i < rdev->usec_timeout) {
3796 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3798 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3802 radeon_scratch_free(rdev, scratch);
3803 radeon_ib_free(rdev, &ib);
3809 * On CIK, gfx and compute now have independant command processors.
3812 * Gfx consists of a single ring and can process both gfx jobs and
3813 * compute jobs. The gfx CP consists of three microengines (ME):
3814 * PFP - Pre-Fetch Parser
3816 * CE - Constant Engine
3817 * The PFP and ME make up what is considered the Drawing Engine (DE).
3818 * The CE is an asynchronous engine used for updating buffer desciptors
3819 * used by the DE so that they can be loaded into cache in parallel
3820 * while the DE is processing state update packets.
3823 * The compute CP consists of two microengines (ME):
3824 * MEC1 - Compute MicroEngine 1
3825 * MEC2 - Compute MicroEngine 2
3826 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
3827 * The queues are exposed to userspace and are programmed directly
3828 * by the compute runtime.
3831 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
3833 * @rdev: radeon_device pointer
3834 * @enable: enable or disable the MEs
3836 * Halts or unhalts the gfx MEs.
3838 static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3841 WREG32(CP_ME_CNTL, 0);
3843 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3844 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3845 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3846 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3852 * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
3854 * @rdev: radeon_device pointer
3856 * Loads the gfx PFP, ME, and CE ucode.
3857 * Returns 0 for success, -EINVAL if the ucode is not available.
3859 static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3861 const __be32 *fw_data;
3864 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3867 cik_cp_gfx_enable(rdev, false);
3870 fw_data = (const __be32 *)rdev->pfp_fw->data;
3871 WREG32(CP_PFP_UCODE_ADDR, 0);
3872 for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
3873 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3874 WREG32(CP_PFP_UCODE_ADDR, 0);
3877 fw_data = (const __be32 *)rdev->ce_fw->data;
3878 WREG32(CP_CE_UCODE_ADDR, 0);
3879 for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
3880 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3881 WREG32(CP_CE_UCODE_ADDR, 0);
3884 fw_data = (const __be32 *)rdev->me_fw->data;
3885 WREG32(CP_ME_RAM_WADDR, 0);
3886 for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
3887 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3888 WREG32(CP_ME_RAM_WADDR, 0);
3890 WREG32(CP_PFP_UCODE_ADDR, 0);
3891 WREG32(CP_CE_UCODE_ADDR, 0);
3892 WREG32(CP_ME_RAM_WADDR, 0);
3893 WREG32(CP_ME_RAM_RADDR, 0);
3898 * cik_cp_gfx_start - start the gfx ring
3900 * @rdev: radeon_device pointer
3902 * Enables the ring and loads the clear state context and other
3903 * packets required to init the ring.
3904 * Returns 0 for success, error for failure.
3906 static int cik_cp_gfx_start(struct radeon_device *rdev)
3908 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3912 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
3913 WREG32(CP_ENDIAN_SWAP, 0);
3914 WREG32(CP_DEVICE_ID, 1);
3916 cik_cp_gfx_enable(rdev, true);
3918 r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
3920 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3924 /* init the CE partitions. CE only used for gfx on CIK */
3925 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3926 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3927 radeon_ring_write(ring, 0xc000);
3928 radeon_ring_write(ring, 0xc000);
3930 /* setup clear context state */
3931 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3932 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3934 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3935 radeon_ring_write(ring, 0x80000000);
3936 radeon_ring_write(ring, 0x80000000);
3938 for (i = 0; i < cik_default_size; i++)
3939 radeon_ring_write(ring, cik_default_state[i]);
3941 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3942 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3944 /* set clear context state */
3945 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3946 radeon_ring_write(ring, 0);
3948 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3949 radeon_ring_write(ring, 0x00000316);
3950 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3951 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3953 radeon_ring_unlock_commit(rdev, ring);
3959 * cik_cp_gfx_fini - stop the gfx ring
3961 * @rdev: radeon_device pointer
3963 * Stop the gfx ring and tear down the driver ring
3966 static void cik_cp_gfx_fini(struct radeon_device *rdev)
3968 cik_cp_gfx_enable(rdev, false);
3969 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3973 * cik_cp_gfx_resume - setup the gfx ring buffer registers
3975 * @rdev: radeon_device pointer
3977 * Program the location and size of the gfx ring buffer
3978 * and test it to make sure it's working.
3979 * Returns 0 for success, error for failure.
3981 static int cik_cp_gfx_resume(struct radeon_device *rdev)
3983 struct radeon_ring *ring;
3989 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3990 if (rdev->family != CHIP_HAWAII)
3991 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3993 /* Set the write pointer delay */
3994 WREG32(CP_RB_WPTR_DELAY, 0);
3996 /* set the RB to use vmid 0 */
3997 WREG32(CP_RB_VMID, 0);
3999 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
4001 /* ring 0 - compute and gfx */
4002 /* Set ring buffer size */
4003 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4004 rb_bufsz = order_base_2(ring->ring_size / 8);
4005 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4007 tmp |= BUF_SWAP_32BIT;
4009 WREG32(CP_RB0_CNTL, tmp);
4011 /* Initialize the ring buffer's read and write pointers */
4012 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4014 WREG32(CP_RB0_WPTR, ring->wptr);
4016 /* set the wb address wether it's enabled or not */
4017 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
4018 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
4020 /* scratch register shadowing is no longer supported */
4021 WREG32(SCRATCH_UMSK, 0);
4023 if (!rdev->wb.enabled)
4024 tmp |= RB_NO_UPDATE;
4027 WREG32(CP_RB0_CNTL, tmp);
4029 rb_addr = ring->gpu_addr >> 8;
4030 WREG32(CP_RB0_BASE, rb_addr);
4031 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4033 ring->rptr = RREG32(CP_RB0_RPTR);
4035 /* start the ring */
4036 cik_cp_gfx_start(rdev);
4037 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4038 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4040 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4044 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4045 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
4050 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4051 struct radeon_ring *ring)
4055 if (rdev->wb.enabled)
4056 rptr = rdev->wb.wb[ring->rptr_offs/4];
4058 rptr = RREG32(CP_RB0_RPTR);
4063 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4064 struct radeon_ring *ring)
4068 wptr = RREG32(CP_RB0_WPTR);
4073 void cik_gfx_set_wptr(struct radeon_device *rdev,
4074 struct radeon_ring *ring)
4076 WREG32(CP_RB0_WPTR, ring->wptr);
4077 (void)RREG32(CP_RB0_WPTR);
4080 u32 cik_compute_get_rptr(struct radeon_device *rdev,
4081 struct radeon_ring *ring)
4085 if (rdev->wb.enabled) {
4086 rptr = rdev->wb.wb[ring->rptr_offs/4];
4088 mutex_lock(&rdev->srbm_mutex);
4089 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4090 rptr = RREG32(CP_HQD_PQ_RPTR);
4091 cik_srbm_select(rdev, 0, 0, 0, 0);
4092 mutex_unlock(&rdev->srbm_mutex);
4098 u32 cik_compute_get_wptr(struct radeon_device *rdev,
4099 struct radeon_ring *ring)
4103 if (rdev->wb.enabled) {
4104 /* XXX check if swapping is necessary on BE */
4105 wptr = rdev->wb.wb[ring->wptr_offs/4];
4107 mutex_lock(&rdev->srbm_mutex);
4108 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4109 wptr = RREG32(CP_HQD_PQ_WPTR);
4110 cik_srbm_select(rdev, 0, 0, 0, 0);
4111 mutex_unlock(&rdev->srbm_mutex);
4117 void cik_compute_set_wptr(struct radeon_device *rdev,
4118 struct radeon_ring *ring)
4120 /* XXX check if swapping is necessary on BE */
4121 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4122 WDOORBELL32(ring->doorbell_index, ring->wptr);
4126 * cik_cp_compute_enable - enable/disable the compute CP MEs
4128 * @rdev: radeon_device pointer
4129 * @enable: enable or disable the MEs
4131 * Halts or unhalts the compute MEs.
4133 static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4136 WREG32(CP_MEC_CNTL, 0);
4138 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4143 * cik_cp_compute_load_microcode - load the compute CP ME ucode
4145 * @rdev: radeon_device pointer
4147 * Loads the compute MEC1&2 ucode.
4148 * Returns 0 for success, -EINVAL if the ucode is not available.
4150 static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4152 const __be32 *fw_data;
4158 cik_cp_compute_enable(rdev, false);
4161 fw_data = (const __be32 *)rdev->mec_fw->data;
4162 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4163 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4164 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4165 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4167 if (rdev->family == CHIP_KAVERI) {
4169 fw_data = (const __be32 *)rdev->mec_fw->data;
4170 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4171 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4172 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4173 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4180 * cik_cp_compute_start - start the compute queues
4182 * @rdev: radeon_device pointer
4184 * Enable the compute queues.
4185 * Returns 0 for success, error for failure.
4187 static int cik_cp_compute_start(struct radeon_device *rdev)
4189 cik_cp_compute_enable(rdev, true);
4195 * cik_cp_compute_fini - stop the compute queues
4197 * @rdev: radeon_device pointer
4199 * Stop the compute queues and tear down the driver queue
4202 static void cik_cp_compute_fini(struct radeon_device *rdev)
4206 cik_cp_compute_enable(rdev, false);
4208 for (i = 0; i < 2; i++) {
4210 idx = CAYMAN_RING_TYPE_CP1_INDEX;
4212 idx = CAYMAN_RING_TYPE_CP2_INDEX;
4214 if (rdev->ring[idx].mqd_obj) {
4215 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4216 if (unlikely(r != 0))
4217 dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
4219 radeon_bo_unpin(rdev->ring[idx].mqd_obj);
4220 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4222 radeon_bo_unref(&rdev->ring[idx].mqd_obj);
4223 rdev->ring[idx].mqd_obj = NULL;
4228 static void cik_mec_fini(struct radeon_device *rdev)
4232 if (rdev->mec.hpd_eop_obj) {
4233 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4234 if (unlikely(r != 0))
4235 dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n", r);
4236 radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4237 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4239 radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4240 rdev->mec.hpd_eop_obj = NULL;
4244 #define MEC_HPD_SIZE 2048
4246 static int cik_mec_init(struct radeon_device *rdev)
4252 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4253 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
4255 if (rdev->family == CHIP_KAVERI)
4256 rdev->mec.num_mec = 2;
4258 rdev->mec.num_mec = 1;
4259 rdev->mec.num_pipe = 4;
4260 rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
4262 if (rdev->mec.hpd_eop_obj == NULL) {
4263 r = radeon_bo_create(rdev,
4264 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4266 RADEON_GEM_DOMAIN_GTT, NULL,
4267 &rdev->mec.hpd_eop_obj);
4269 dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
4274 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4275 if (unlikely(r != 0)) {
4279 r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
4280 &rdev->mec.hpd_eop_gpu_addr);
4282 dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r);
4286 r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
4288 dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r);
4293 /* clear memory. Not sure if this is required or not */
4294 memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
4296 radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
4297 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4302 struct hqd_registers
4304 u32 cp_mqd_base_addr;
4305 u32 cp_mqd_base_addr_hi;
4308 u32 cp_hqd_persistent_state;
4309 u32 cp_hqd_pipe_priority;
4310 u32 cp_hqd_queue_priority;
4313 u32 cp_hqd_pq_base_hi;
4315 u32 cp_hqd_pq_rptr_report_addr;
4316 u32 cp_hqd_pq_rptr_report_addr_hi;
4317 u32 cp_hqd_pq_wptr_poll_addr;
4318 u32 cp_hqd_pq_wptr_poll_addr_hi;
4319 u32 cp_hqd_pq_doorbell_control;
4321 u32 cp_hqd_pq_control;
4322 u32 cp_hqd_ib_base_addr;
4323 u32 cp_hqd_ib_base_addr_hi;
4325 u32 cp_hqd_ib_control;
4326 u32 cp_hqd_iq_timer;
4328 u32 cp_hqd_dequeue_request;
4329 u32 cp_hqd_dma_offload;
4330 u32 cp_hqd_sema_cmd;
4331 u32 cp_hqd_msg_type;
4332 u32 cp_hqd_atomic0_preop_lo;
4333 u32 cp_hqd_atomic0_preop_hi;
4334 u32 cp_hqd_atomic1_preop_lo;
4335 u32 cp_hqd_atomic1_preop_hi;
4336 u32 cp_hqd_hq_scheduler0;
4337 u32 cp_hqd_hq_scheduler1;
4344 u32 dispatch_initiator;
4348 u32 pipeline_stat_enable;
4349 u32 perf_counter_enable;
4355 u32 resource_limits;
4356 u32 static_thread_mgmt01[2];
4358 u32 static_thread_mgmt23[2];
4360 u32 thread_trace_enable;
4363 u32 vgtcs_invoke_count[2];
4364 struct hqd_registers queue_state;
4366 u32 interrupt_queue[64];
4370 * cik_cp_compute_resume - setup the compute queue registers
4372 * @rdev: radeon_device pointer
4374 * Program the compute queues and test them to make sure they
4376 * Returns 0 for success, error for failure.
4378 static int cik_cp_compute_resume(struct radeon_device *rdev)
4382 bool use_doorbell = true;
4388 struct bonaire_mqd *mqd;
4390 r = cik_cp_compute_start(rdev);
4394 /* fix up chicken bits */
4395 tmp = RREG32(CP_CPF_DEBUG);
4397 WREG32(CP_CPF_DEBUG, tmp);
4399 /* init the pipes */
4400 mutex_lock(&rdev->srbm_mutex);
4401 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) {
4402 int me = (i < 4) ? 1 : 2;
4403 int pipe = (i < 4) ? i : (i - 4);
4405 eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
4407 cik_srbm_select(rdev, me, pipe, 0, 0);
4409 /* write the EOP addr */
4410 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
4411 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
4413 /* set the VMID assigned */
4414 WREG32(CP_HPD_EOP_VMID, 0);
4416 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4417 tmp = RREG32(CP_HPD_EOP_CONTROL);
4418 tmp &= ~EOP_SIZE_MASK;
4419 tmp |= order_base_2(MEC_HPD_SIZE / 8);
4420 WREG32(CP_HPD_EOP_CONTROL, tmp);
4422 cik_srbm_select(rdev, 0, 0, 0, 0);
4423 mutex_unlock(&rdev->srbm_mutex);
4425 /* init the queues. Just two for now. */
4426 for (i = 0; i < 2; i++) {
4428 idx = CAYMAN_RING_TYPE_CP1_INDEX;
4430 idx = CAYMAN_RING_TYPE_CP2_INDEX;
4432 if (rdev->ring[idx].mqd_obj == NULL) {
4433 r = radeon_bo_create(rdev,
4434 sizeof(struct bonaire_mqd),
4436 RADEON_GEM_DOMAIN_GTT, NULL,
4437 &rdev->ring[idx].mqd_obj);
4439 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4444 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4445 if (unlikely(r != 0)) {
4446 cik_cp_compute_fini(rdev);
4449 r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT,
4452 dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
4453 cik_cp_compute_fini(rdev);
4456 r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf);
4458 dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
4459 cik_cp_compute_fini(rdev);
4463 /* init the mqd struct */
4464 memset(buf, 0, sizeof(struct bonaire_mqd));
4466 mqd = (struct bonaire_mqd *)buf;
4467 mqd->header = 0xC0310800;
4468 mqd->static_thread_mgmt01[0] = 0xffffffff;
4469 mqd->static_thread_mgmt01[1] = 0xffffffff;
4470 mqd->static_thread_mgmt23[0] = 0xffffffff;
4471 mqd->static_thread_mgmt23[1] = 0xffffffff;
4473 mutex_lock(&rdev->srbm_mutex);
4474 cik_srbm_select(rdev, rdev->ring[idx].me,
4475 rdev->ring[idx].pipe,
4476 rdev->ring[idx].queue, 0);
4478 /* disable wptr polling */
4479 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4480 tmp &= ~WPTR_POLL_EN;
4481 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4483 /* enable doorbell? */
4484 mqd->queue_state.cp_hqd_pq_doorbell_control =
4485 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4487 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4489 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4490 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4491 mqd->queue_state.cp_hqd_pq_doorbell_control);
4493 /* disable the queue if it's active */
4494 mqd->queue_state.cp_hqd_dequeue_request = 0;
4495 mqd->queue_state.cp_hqd_pq_rptr = 0;
4496 mqd->queue_state.cp_hqd_pq_wptr= 0;
4497 if (RREG32(CP_HQD_ACTIVE) & 1) {
4498 WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4499 for (i = 0; i < rdev->usec_timeout; i++) {
4500 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4504 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4505 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4506 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4509 /* set the pointer to the MQD */
4510 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4511 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4512 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4513 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4514 /* set MQD vmid to 0 */
4515 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4516 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4517 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4519 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4520 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;
4521 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4522 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4523 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4524 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4526 /* set up the HQD, this is similar to CP_RB0_CNTL */
4527 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4528 mqd->queue_state.cp_hqd_pq_control &=
4529 ~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
4531 mqd->queue_state.cp_hqd_pq_control |=
4532 order_base_2(rdev->ring[idx].ring_size / 8);
4533 mqd->queue_state.cp_hqd_pq_control |=
4534 (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
4536 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4538 mqd->queue_state.cp_hqd_pq_control &=
4539 ~(UNORD_DISPATCH | ROQ_PQ_IB_FLIP | PQ_VOLATILE);
4540 mqd->queue_state.cp_hqd_pq_control |=
4541 PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
4542 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4544 /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
4546 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4548 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4549 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4550 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4551 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4552 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
4553 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4555 /* set the wb address wether it's enabled or not */
4557 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4559 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4560 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4561 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4562 upper_32_bits(wb_gpu_addr) & 0xffff;
4563 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
4564 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4565 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4566 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4568 /* enable the doorbell if requested */
4570 mqd->queue_state.cp_hqd_pq_doorbell_control =
4571 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4572 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4573 mqd->queue_state.cp_hqd_pq_doorbell_control |=
4574 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index);
4575 mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4576 mqd->queue_state.cp_hqd_pq_doorbell_control &=
4577 ~(DOORBELL_SOURCE | DOORBELL_HIT);
4580 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4582 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4583 mqd->queue_state.cp_hqd_pq_doorbell_control);
4585 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4586 rdev->ring[idx].wptr = 0;
4587 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4588 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4589 rdev->ring[idx].rptr = RREG32(CP_HQD_PQ_RPTR);
4590 mqd->queue_state.cp_hqd_pq_rptr = rdev->ring[idx].rptr;
4592 /* set the vmid for the queue */
4593 mqd->queue_state.cp_hqd_vmid = 0;
4594 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4596 /* activate the queue */
4597 mqd->queue_state.cp_hqd_active = 1;
4598 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
4600 cik_srbm_select(rdev, 0, 0, 0, 0);
4601 mutex_unlock(&rdev->srbm_mutex);
4603 radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
4604 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4606 rdev->ring[idx].ready = true;
4607 r = radeon_ring_test(rdev, idx, &rdev->ring[idx]);
4609 rdev->ring[idx].ready = false;
4615 static void cik_cp_enable(struct radeon_device *rdev, bool enable)
4617 cik_cp_gfx_enable(rdev, enable);
4618 cik_cp_compute_enable(rdev, enable);
4621 static int cik_cp_load_microcode(struct radeon_device *rdev)
4625 r = cik_cp_gfx_load_microcode(rdev);
4628 r = cik_cp_compute_load_microcode(rdev);
4635 static void cik_cp_fini(struct radeon_device *rdev)
4637 cik_cp_gfx_fini(rdev);
4638 cik_cp_compute_fini(rdev);
4641 static int cik_cp_resume(struct radeon_device *rdev)
4645 cik_enable_gui_idle_interrupt(rdev, false);
4647 r = cik_cp_load_microcode(rdev);
4651 r = cik_cp_gfx_resume(rdev);
4654 r = cik_cp_compute_resume(rdev);
4658 cik_enable_gui_idle_interrupt(rdev, true);
4663 static void cik_print_gpu_status_regs(struct radeon_device *rdev)
4665 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
4666 RREG32(GRBM_STATUS));
4667 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
4668 RREG32(GRBM_STATUS2));
4669 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4670 RREG32(GRBM_STATUS_SE0));
4671 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4672 RREG32(GRBM_STATUS_SE1));
4673 dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4674 RREG32(GRBM_STATUS_SE2));
4675 dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4676 RREG32(GRBM_STATUS_SE3));
4677 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
4678 RREG32(SRBM_STATUS));
4679 dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
4680 RREG32(SRBM_STATUS2));
4681 dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
4682 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
4683 dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
4684 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
4685 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
4686 dev_info(rdev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4687 RREG32(CP_STALLED_STAT1));
4688 dev_info(rdev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4689 RREG32(CP_STALLED_STAT2));
4690 dev_info(rdev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4691 RREG32(CP_STALLED_STAT3));
4692 dev_info(rdev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4693 RREG32(CP_CPF_BUSY_STAT));
4694 dev_info(rdev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4695 RREG32(CP_CPF_STALLED_STAT1));
4696 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
4697 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
4698 dev_info(rdev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4699 RREG32(CP_CPC_STALLED_STAT1));
4700 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
4704 * cik_gpu_check_soft_reset - check which blocks are busy
4706 * @rdev: radeon_device pointer
4708 * Check which blocks are busy and return the relevant reset
4709 * mask to be used by cik_gpu_soft_reset().
4710 * Returns a mask of the blocks to be reset.
4712 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
4718 tmp = RREG32(GRBM_STATUS);
4719 if (tmp & (PA_BUSY | SC_BUSY |
4720 BCI_BUSY | SX_BUSY |
4721 TA_BUSY | VGT_BUSY |
4723 GDS_BUSY | SPI_BUSY |
4724 IA_BUSY | IA_BUSY_NO_DMA))
4725 reset_mask |= RADEON_RESET_GFX;
4727 if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
4728 reset_mask |= RADEON_RESET_CP;
4731 tmp = RREG32(GRBM_STATUS2);
4733 reset_mask |= RADEON_RESET_RLC;
4735 /* SDMA0_STATUS_REG */
4736 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4737 if (!(tmp & SDMA_IDLE))
4738 reset_mask |= RADEON_RESET_DMA;
4740 /* SDMA1_STATUS_REG */
4741 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4742 if (!(tmp & SDMA_IDLE))
4743 reset_mask |= RADEON_RESET_DMA1;
4746 tmp = RREG32(SRBM_STATUS2);
4747 if (tmp & SDMA_BUSY)
4748 reset_mask |= RADEON_RESET_DMA;
4750 if (tmp & SDMA1_BUSY)
4751 reset_mask |= RADEON_RESET_DMA1;
4754 tmp = RREG32(SRBM_STATUS);
4757 reset_mask |= RADEON_RESET_IH;
4760 reset_mask |= RADEON_RESET_SEM;
4762 if (tmp & GRBM_RQ_PENDING)
4763 reset_mask |= RADEON_RESET_GRBM;
4766 reset_mask |= RADEON_RESET_VMC;
4768 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
4769 MCC_BUSY | MCD_BUSY))
4770 reset_mask |= RADEON_RESET_MC;
4772 if (evergreen_is_display_hung(rdev))
4773 reset_mask |= RADEON_RESET_DISPLAY;
4775 /* Skip MC reset as it's mostly likely not hung, just busy */
4776 if (reset_mask & RADEON_RESET_MC) {
4777 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
4778 reset_mask &= ~RADEON_RESET_MC;
4785 * cik_gpu_soft_reset - soft reset GPU
4787 * @rdev: radeon_device pointer
4788 * @reset_mask: mask of which blocks to reset
4790 * Soft reset the blocks specified in @reset_mask.
4792 static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4794 struct evergreen_mc_save save;
4795 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4798 if (reset_mask == 0)
4801 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
4803 cik_print_gpu_status_regs(rdev);
4804 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4805 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4806 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4807 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4816 /* Disable GFX parsing/prefetching */
4817 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4819 /* Disable MEC parsing/prefetching */
4820 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
4822 if (reset_mask & RADEON_RESET_DMA) {
4824 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4826 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
4828 if (reset_mask & RADEON_RESET_DMA1) {
4830 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
4832 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
4835 evergreen_mc_stop(rdev, &save);
4836 if (evergreen_mc_wait_for_idle(rdev)) {
4837 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4840 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
4841 grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
4843 if (reset_mask & RADEON_RESET_CP) {
4844 grbm_soft_reset |= SOFT_RESET_CP;
4846 srbm_soft_reset |= SOFT_RESET_GRBM;
4849 if (reset_mask & RADEON_RESET_DMA)
4850 srbm_soft_reset |= SOFT_RESET_SDMA;
4852 if (reset_mask & RADEON_RESET_DMA1)
4853 srbm_soft_reset |= SOFT_RESET_SDMA1;
4855 if (reset_mask & RADEON_RESET_DISPLAY)
4856 srbm_soft_reset |= SOFT_RESET_DC;
4858 if (reset_mask & RADEON_RESET_RLC)
4859 grbm_soft_reset |= SOFT_RESET_RLC;
4861 if (reset_mask & RADEON_RESET_SEM)
4862 srbm_soft_reset |= SOFT_RESET_SEM;
4864 if (reset_mask & RADEON_RESET_IH)
4865 srbm_soft_reset |= SOFT_RESET_IH;
4867 if (reset_mask & RADEON_RESET_GRBM)
4868 srbm_soft_reset |= SOFT_RESET_GRBM;
4870 if (reset_mask & RADEON_RESET_VMC)
4871 srbm_soft_reset |= SOFT_RESET_VMC;
4873 if (!(rdev->flags & RADEON_IS_IGP)) {
4874 if (reset_mask & RADEON_RESET_MC)
4875 srbm_soft_reset |= SOFT_RESET_MC;
4878 if (grbm_soft_reset) {
4879 tmp = RREG32(GRBM_SOFT_RESET);
4880 tmp |= grbm_soft_reset;
4881 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4882 WREG32(GRBM_SOFT_RESET, tmp);
4883 tmp = RREG32(GRBM_SOFT_RESET);
4887 tmp &= ~grbm_soft_reset;
4888 WREG32(GRBM_SOFT_RESET, tmp);
4889 tmp = RREG32(GRBM_SOFT_RESET);
4892 if (srbm_soft_reset) {
4893 tmp = RREG32(SRBM_SOFT_RESET);
4894 tmp |= srbm_soft_reset;
4895 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4896 WREG32(SRBM_SOFT_RESET, tmp);
4897 tmp = RREG32(SRBM_SOFT_RESET);
4901 tmp &= ~srbm_soft_reset;
4902 WREG32(SRBM_SOFT_RESET, tmp);
4903 tmp = RREG32(SRBM_SOFT_RESET);
4906 /* Wait a little for things to settle down */
4909 evergreen_mc_resume(rdev, &save);
4912 cik_print_gpu_status_regs(rdev);
4915 struct kv_reset_save_regs {
4916 u32 gmcon_reng_execute;
4921 static void kv_save_regs_for_reset(struct radeon_device *rdev,
4922 struct kv_reset_save_regs *save)
4924 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
4925 save->gmcon_misc = RREG32(GMCON_MISC);
4926 save->gmcon_misc3 = RREG32(GMCON_MISC3);
4928 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
4929 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
4930 STCTRL_STUTTER_EN));
4933 static void kv_restore_regs_for_reset(struct radeon_device *rdev,
4934 struct kv_reset_save_regs *save)
4938 WREG32(GMCON_PGFSM_WRITE, 0);
4939 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
4941 for (i = 0; i < 5; i++)
4942 WREG32(GMCON_PGFSM_WRITE, 0);
4944 WREG32(GMCON_PGFSM_WRITE, 0);
4945 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
4947 for (i = 0; i < 5; i++)
4948 WREG32(GMCON_PGFSM_WRITE, 0);
4950 WREG32(GMCON_PGFSM_WRITE, 0x210000);
4951 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
4953 for (i = 0; i < 5; i++)
4954 WREG32(GMCON_PGFSM_WRITE, 0);
4956 WREG32(GMCON_PGFSM_WRITE, 0x21003);
4957 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
4959 for (i = 0; i < 5; i++)
4960 WREG32(GMCON_PGFSM_WRITE, 0);
4962 WREG32(GMCON_PGFSM_WRITE, 0x2b00);
4963 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
4965 for (i = 0; i < 5; i++)
4966 WREG32(GMCON_PGFSM_WRITE, 0);
4968 WREG32(GMCON_PGFSM_WRITE, 0);
4969 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
4971 for (i = 0; i < 5; i++)
4972 WREG32(GMCON_PGFSM_WRITE, 0);
4974 WREG32(GMCON_PGFSM_WRITE, 0x420000);
4975 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
4977 for (i = 0; i < 5; i++)
4978 WREG32(GMCON_PGFSM_WRITE, 0);
4980 WREG32(GMCON_PGFSM_WRITE, 0x120202);
4981 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
4983 for (i = 0; i < 5; i++)
4984 WREG32(GMCON_PGFSM_WRITE, 0);
4986 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
4987 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
4989 for (i = 0; i < 5; i++)
4990 WREG32(GMCON_PGFSM_WRITE, 0);
4992 WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
4993 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
4995 for (i = 0; i < 5; i++)
4996 WREG32(GMCON_PGFSM_WRITE, 0);
4998 WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
4999 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
5001 WREG32(GMCON_MISC3, save->gmcon_misc3);
5002 WREG32(GMCON_MISC, save->gmcon_misc);
5003 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
5006 static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
5008 struct evergreen_mc_save save;
5009 struct kv_reset_save_regs kv_save = { 0 };
5012 dev_info(rdev->dev, "GPU pci config reset\n");
5020 /* Disable GFX parsing/prefetching */
5021 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5023 /* Disable MEC parsing/prefetching */
5024 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5027 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5029 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5031 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5033 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5034 /* XXX other engines? */
5036 /* halt the rlc, disable cp internal ints */
5041 /* disable mem access */
5042 evergreen_mc_stop(rdev, &save);
5043 if (evergreen_mc_wait_for_idle(rdev)) {
5044 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
5047 if (rdev->flags & RADEON_IS_IGP)
5048 kv_save_regs_for_reset(rdev, &kv_save);
5051 pci_clear_master(rdev->pdev);
5053 radeon_pci_config_reset(rdev);
5057 /* wait for asic to come out of reset */
5058 for (i = 0; i < rdev->usec_timeout; i++) {
5059 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5064 /* does asic init need to be run first??? */
5065 if (rdev->flags & RADEON_IS_IGP)
5066 kv_restore_regs_for_reset(rdev, &kv_save);
5070 * cik_asic_reset - soft reset GPU
5072 * @rdev: radeon_device pointer
5074 * Look up which blocks are hung and attempt
5076 * Returns 0 for success.
5078 int cik_asic_reset(struct radeon_device *rdev)
5082 reset_mask = cik_gpu_check_soft_reset(rdev);
5085 r600_set_bios_scratch_engine_hung(rdev, true);
5087 /* try soft reset */
5088 cik_gpu_soft_reset(rdev, reset_mask);
5090 reset_mask = cik_gpu_check_soft_reset(rdev);
5092 /* try pci config reset */
5093 if (reset_mask && radeon_hard_reset)
5094 cik_gpu_pci_config_reset(rdev);
5096 reset_mask = cik_gpu_check_soft_reset(rdev);
5099 r600_set_bios_scratch_engine_hung(rdev, false);
5105 * cik_gfx_is_lockup - check if the 3D engine is locked up
5107 * @rdev: radeon_device pointer
5108 * @ring: radeon_ring structure holding ring information
5110 * Check if the 3D engine is locked up (CIK).
5111 * Returns true if the engine is locked, false if not.
5113 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5115 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5117 if (!(reset_mask & (RADEON_RESET_GFX |
5118 RADEON_RESET_COMPUTE |
5119 RADEON_RESET_CP))) {
5120 radeon_ring_lockup_update(ring);
5123 /* force CP activities */
5124 radeon_ring_force_activity(rdev, ring);
5125 return radeon_ring_test_lockup(rdev, ring);
5130 * cik_mc_program - program the GPU memory controller
5132 * @rdev: radeon_device pointer
5134 * Set the location of vram, gart, and AGP in the GPU's
5135 * physical address space (CIK).
5137 static void cik_mc_program(struct radeon_device *rdev)
5139 struct evergreen_mc_save save;
5143 /* Initialize HDP */
5144 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
5145 WREG32((0x2c14 + j), 0x00000000);
5146 WREG32((0x2c18 + j), 0x00000000);
5147 WREG32((0x2c1c + j), 0x00000000);
5148 WREG32((0x2c20 + j), 0x00000000);
5149 WREG32((0x2c24 + j), 0x00000000);
5151 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
5153 evergreen_mc_stop(rdev, &save);
5154 if (radeon_mc_wait_for_idle(rdev)) {
5155 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5157 /* Lockout access through VGA aperture*/
5158 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
5159 /* Update configuration */
5160 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
5161 rdev->mc.vram_start >> 12);
5162 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5163 rdev->mc.vram_end >> 12);
5164 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
5165 rdev->vram_scratch.gpu_addr >> 12);
5166 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5167 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5168 WREG32(MC_VM_FB_LOCATION, tmp);
5169 /* XXX double check these! */
5170 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
5171 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
5172 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
5173 WREG32(MC_VM_AGP_BASE, 0);
5174 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
5175 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
5176 if (radeon_mc_wait_for_idle(rdev)) {
5177 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5179 evergreen_mc_resume(rdev, &save);
5180 /* we need to own VRAM, so turn off the VGA renderer here
5181 * to stop it overwriting our objects */
5182 rv515_vga_render_disable(rdev);
5186 * cik_mc_init - initialize the memory controller driver params
5188 * @rdev: radeon_device pointer
5190 * Look up the amount of vram, vram width, and decide how to place
5191 * vram and gart within the GPU's physical address space (CIK).
5192 * Returns 0 for success.
5194 static int cik_mc_init(struct radeon_device *rdev)
5197 int chansize, numchan;
5199 /* Get VRAM informations */
5200 rdev->mc.vram_is_ddr = true;
5201 tmp = RREG32(MC_ARB_RAMCFG);
5202 if (tmp & CHANSIZE_MASK) {
5207 tmp = RREG32(MC_SHARED_CHMAP);
5208 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5238 rdev->mc.vram_width = numchan * chansize;
5239 /* Could aper size report 0 ? */
5240 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
5241 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
5242 /* size in MB on si */
5243 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5244 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5245 rdev->mc.visible_vram_size = rdev->mc.aper_size;
5246 si_vram_gtt_location(rdev, &rdev->mc);
5247 radeon_update_bandwidth_info(rdev);
5254 * VMID 0 is the physical GPU addresses as used by the kernel.
5255 * VMIDs 1-15 are used for userspace clients and are handled
5256 * by the radeon vm/hsa code.
5259 * cik_pcie_gart_tlb_flush - gart tlb flush callback
5261 * @rdev: radeon_device pointer
5263 * Flush the TLB for the VMID 0 page table (CIK).
5265 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
5267 /* flush hdp cache */
5268 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
5270 /* bits 0-15 are the VM contexts0-15 */
5271 WREG32(VM_INVALIDATE_REQUEST, 0x1);
5275 * cik_pcie_gart_enable - gart enable
5277 * @rdev: radeon_device pointer
5279 * This sets up the TLBs, programs the page tables for VMID0,
5280 * sets up the hw for VMIDs 1-15 which are allocated on
5281 * demand, and sets up the global locations for the LDS, GDS,
5282 * and GPUVM for FSA64 clients (CIK).
5283 * Returns 0 for success, errors for failure.
5285 static int cik_pcie_gart_enable(struct radeon_device *rdev)
5289 if (rdev->gart.robj == NULL) {
5290 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
5293 r = radeon_gart_table_vram_pin(rdev);
5296 radeon_gart_restore(rdev);
5297 /* Setup TLB control */
5298 WREG32(MC_VM_MX_L1_TLB_CNTL,
5301 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5302 ENABLE_ADVANCED_DRIVER_MODEL |
5303 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5304 /* Setup L2 cache */
5305 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
5306 ENABLE_L2_FRAGMENT_PROCESSING |
5307 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5308 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5309 EFFECTIVE_L2_QUEUE_SIZE(7) |
5310 CONTEXT1_IDENTITY_ACCESS_MODE(1));
5311 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
5312 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5313 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5314 /* setup context0 */
5315 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
5316 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
5317 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
5318 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
5319 (u32)(rdev->dummy_page.addr >> 12));
5320 WREG32(VM_CONTEXT0_CNTL2, 0);
5321 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
5322 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
5328 /* empty context1-15 */
5329 /* FIXME start with 4G, once using 2 level pt switch to full
5332 /* set vm size, must be a multiple of 4 */
5333 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
5334 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
5335 for (i = 1; i < 16; i++) {
5337 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
5338 rdev->gart.table_addr >> 12);
5340 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
5341 rdev->gart.table_addr >> 12);
5344 /* enable context1-15 */
5345 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
5346 (u32)(rdev->dummy_page.addr >> 12));
5347 WREG32(VM_CONTEXT1_CNTL2, 4);
5348 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
5349 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5350 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5351 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5352 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5353 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
5354 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
5355 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
5356 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
5357 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
5358 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
5359 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5360 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
5362 if (rdev->family == CHIP_KAVERI) {
5363 u32 tmp = RREG32(CHUB_CONTROL);
5365 WREG32(CHUB_CONTROL, tmp);
5368 /* XXX SH_MEM regs */
5369 /* where to put LDS, scratch, GPUVM in FSA64 space */
5370 mutex_lock(&rdev->srbm_mutex);
5371 for (i = 0; i < 16; i++) {
5372 cik_srbm_select(rdev, 0, 0, 0, i);
5373 /* CP and shaders */
5374 WREG32(SH_MEM_CONFIG, 0);
5375 WREG32(SH_MEM_APE1_BASE, 1);
5376 WREG32(SH_MEM_APE1_LIMIT, 0);
5377 WREG32(SH_MEM_BASES, 0);
5379 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
5380 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
5381 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
5382 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
5383 /* XXX SDMA RLC - todo */
5385 cik_srbm_select(rdev, 0, 0, 0, 0);
5386 mutex_unlock(&rdev->srbm_mutex);
5388 cik_pcie_gart_tlb_flush(rdev);
5389 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
5390 (unsigned)(rdev->mc.gtt_size >> 20),
5391 (unsigned long long)rdev->gart.table_addr);
5392 rdev->gart.ready = true;
5397 * cik_pcie_gart_disable - gart disable
5399 * @rdev: radeon_device pointer
5401 * This disables all VM page table (CIK).
5403 static void cik_pcie_gart_disable(struct radeon_device *rdev)
5405 /* Disable all tables */
5406 WREG32(VM_CONTEXT0_CNTL, 0);
5407 WREG32(VM_CONTEXT1_CNTL, 0);
5408 /* Setup TLB control */
5409 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5410 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5411 /* Setup L2 cache */
5413 ENABLE_L2_FRAGMENT_PROCESSING |
5414 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5415 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5416 EFFECTIVE_L2_QUEUE_SIZE(7) |
5417 CONTEXT1_IDENTITY_ACCESS_MODE(1));
5418 WREG32(VM_L2_CNTL2, 0);
5419 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5420 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5421 radeon_gart_table_vram_unpin(rdev);
5425 * cik_pcie_gart_fini - vm fini callback
5427 * @rdev: radeon_device pointer
5429 * Tears down the driver GART/VM setup (CIK).
5431 static void cik_pcie_gart_fini(struct radeon_device *rdev)
5433 cik_pcie_gart_disable(rdev);
5434 radeon_gart_table_vram_free(rdev);
5435 radeon_gart_fini(rdev);
5440 * cik_ib_parse - vm ib_parse callback
5442 * @rdev: radeon_device pointer
5443 * @ib: indirect buffer pointer
5445 * CIK uses hw IB checking so this is a nop (CIK).
5447 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
5454 * VMID 0 is the physical GPU addresses as used by the kernel.
5455 * VMIDs 1-15 are used for userspace clients and are handled
5456 * by the radeon vm/hsa code.
5459 * cik_vm_init - cik vm init callback
5461 * @rdev: radeon_device pointer
5463 * Inits cik specific vm parameters (number of VMs, base of vram for
5464 * VMIDs 1-15) (CIK).
5465 * Returns 0 for success.
5467 int cik_vm_init(struct radeon_device *rdev)
5470 rdev->vm_manager.nvm = 16;
5471 /* base offset of vram pages */
5472 if (rdev->flags & RADEON_IS_IGP) {
5473 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5475 rdev->vm_manager.vram_base_offset = tmp;
5477 rdev->vm_manager.vram_base_offset = 0;
5483 * cik_vm_fini - cik vm fini callback
5485 * @rdev: radeon_device pointer
5487 * Tear down any asic specific VM setup (CIK).
5489 void cik_vm_fini(struct radeon_device *rdev)
5494 * cik_vm_decode_fault - print human readable fault info
5496 * @rdev: radeon_device pointer
5497 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
5498 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
5500 * Print human readable fault information (CIK).
5502 static void cik_vm_decode_fault(struct radeon_device *rdev,
5503 u32 status, u32 addr, u32 mc_client)
5506 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
5507 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
5508 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
5509 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
5511 if (rdev->family == CHIP_HAWAII)
5512 mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5514 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5516 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
5517 protections, vmid, addr,
5518 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5519 block, mc_client, mc_id);
5523 * cik_vm_flush - cik vm flush using the CP
5525 * @rdev: radeon_device pointer
5527 * Update the page table base and flush the VM TLB
5528 * using the CP (CIK).
5530 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
5532 struct radeon_ring *ring = &rdev->ring[ridx];
5537 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5538 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5539 WRITE_DATA_DST_SEL(0)));
5541 radeon_ring_write(ring,
5542 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
5544 radeon_ring_write(ring,
5545 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
5547 radeon_ring_write(ring, 0);
5548 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
5550 /* update SH_MEM_* regs */
5551 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5552 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5553 WRITE_DATA_DST_SEL(0)));
5554 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5555 radeon_ring_write(ring, 0);
5556 radeon_ring_write(ring, VMID(vm->id));
5558 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
5559 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5560 WRITE_DATA_DST_SEL(0)));
5561 radeon_ring_write(ring, SH_MEM_BASES >> 2);
5562 radeon_ring_write(ring, 0);
5564 radeon_ring_write(ring, 0); /* SH_MEM_BASES */
5565 radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
5566 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
5567 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
5569 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5570 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5571 WRITE_DATA_DST_SEL(0)));
5572 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5573 radeon_ring_write(ring, 0);
5574 radeon_ring_write(ring, VMID(0));
5577 cik_hdp_flush_cp_ring_emit(rdev, ridx);
5579 /* bits 0-15 are the VM contexts0-15 */
5580 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5581 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5582 WRITE_DATA_DST_SEL(0)));
5583 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5584 radeon_ring_write(ring, 0);
5585 radeon_ring_write(ring, 1 << vm->id);
5587 /* compute doesn't have PFP */
5588 if (ridx == RADEON_RING_TYPE_GFX_INDEX) {
5589 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5590 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5591 radeon_ring_write(ring, 0x0);
5597 * The RLC is a multi-purpose microengine that handles a
5598 * variety of functions, the most important of which is
5599 * the interrupt controller.
5601 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
5604 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5607 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5609 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5610 WREG32(CP_INT_CNTL_RING0, tmp);
5613 static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
5617 tmp = RREG32(RLC_LB_CNTL);
5619 tmp |= LOAD_BALANCE_ENABLE;
5621 tmp &= ~LOAD_BALANCE_ENABLE;
5622 WREG32(RLC_LB_CNTL, tmp);
5625 static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
5630 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5631 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5632 cik_select_se_sh(rdev, i, j);
5633 for (k = 0; k < rdev->usec_timeout; k++) {
5634 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5640 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5642 mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
5643 for (k = 0; k < rdev->usec_timeout; k++) {
5644 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5650 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
5654 tmp = RREG32(RLC_CNTL);
5656 WREG32(RLC_CNTL, rlc);
5659 static u32 cik_halt_rlc(struct radeon_device *rdev)
5663 orig = data = RREG32(RLC_CNTL);
5665 if (data & RLC_ENABLE) {
5668 data &= ~RLC_ENABLE;
5669 WREG32(RLC_CNTL, data);
5671 for (i = 0; i < rdev->usec_timeout; i++) {
5672 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
5677 cik_wait_for_rlc_serdes(rdev);
5683 void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
5687 tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5688 WREG32(RLC_GPR_REG2, tmp);
5690 mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
5691 for (i = 0; i < rdev->usec_timeout; i++) {
5692 if ((RREG32(RLC_GPM_STAT) & mask) == mask)
5697 for (i = 0; i < rdev->usec_timeout; i++) {
5698 if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
5704 void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
5708 tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5709 WREG32(RLC_GPR_REG2, tmp);
5713 * cik_rlc_stop - stop the RLC ME
5715 * @rdev: radeon_device pointer
5717 * Halt the RLC ME (MicroEngine) (CIK).
5719 static void cik_rlc_stop(struct radeon_device *rdev)
5721 WREG32(RLC_CNTL, 0);
5723 cik_enable_gui_idle_interrupt(rdev, false);
5725 cik_wait_for_rlc_serdes(rdev);
5729 * cik_rlc_start - start the RLC ME
5731 * @rdev: radeon_device pointer
5733 * Unhalt the RLC ME (MicroEngine) (CIK).
5735 static void cik_rlc_start(struct radeon_device *rdev)
5737 WREG32(RLC_CNTL, RLC_ENABLE);
5739 cik_enable_gui_idle_interrupt(rdev, true);
5745 * cik_rlc_resume - setup the RLC hw
5747 * @rdev: radeon_device pointer
5749 * Initialize the RLC registers, load the ucode,
5750 * and start the RLC (CIK).
5751 * Returns 0 for success, -EINVAL if the ucode is not available.
5753 static int cik_rlc_resume(struct radeon_device *rdev)
5756 const __be32 *fw_data;
5761 switch (rdev->family) {
5765 size = BONAIRE_RLC_UCODE_SIZE;
5768 size = KV_RLC_UCODE_SIZE;
5771 size = KB_RLC_UCODE_SIZE;
5778 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5779 WREG32(RLC_CGCG_CGLS_CTRL, tmp);
5787 WREG32(RLC_LB_CNTR_INIT, 0);
5788 WREG32(RLC_LB_CNTR_MAX, 0x00008000);
5790 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5791 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5792 WREG32(RLC_LB_PARAMS, 0x00600408);
5793 WREG32(RLC_LB_CNTL, 0x80000004);
5795 WREG32(RLC_MC_CNTL, 0);
5796 WREG32(RLC_UCODE_CNTL, 0);
5798 fw_data = (const __be32 *)rdev->rlc_fw->data;
5799 WREG32(RLC_GPM_UCODE_ADDR, 0);
5800 for (i = 0; i < size; i++)
5801 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
5802 WREG32(RLC_GPM_UCODE_ADDR, 0);
5804 /* XXX - find out what chips support lbpw */
5805 cik_enable_lbpw(rdev, false);
5807 if (rdev->family == CHIP_BONAIRE)
5808 WREG32(RLC_DRIVER_DMA_STATUS, 0);
5810 cik_rlc_start(rdev);
5815 static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
5817 u32 data, orig, tmp, tmp2;
5819 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5821 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5822 cik_enable_gui_idle_interrupt(rdev, true);
5824 tmp = cik_halt_rlc(rdev);
5826 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5827 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5828 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5829 tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
5830 WREG32(RLC_SERDES_WR_CTRL, tmp2);
5832 cik_update_rlc(rdev, tmp);
5834 data |= CGCG_EN | CGLS_EN;
5836 cik_enable_gui_idle_interrupt(rdev, false);
5838 RREG32(CB_CGTT_SCLK_CTRL);
5839 RREG32(CB_CGTT_SCLK_CTRL);
5840 RREG32(CB_CGTT_SCLK_CTRL);
5841 RREG32(CB_CGTT_SCLK_CTRL);
5843 data &= ~(CGCG_EN | CGLS_EN);
5847 WREG32(RLC_CGCG_CGLS_CTRL, data);
5851 static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
5853 u32 data, orig, tmp = 0;
5855 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5856 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) {
5857 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5858 orig = data = RREG32(CP_MEM_SLP_CNTL);
5859 data |= CP_MEM_LS_EN;
5861 WREG32(CP_MEM_SLP_CNTL, data);
5865 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5868 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5870 tmp = cik_halt_rlc(rdev);
5872 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5873 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5874 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5875 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
5876 WREG32(RLC_SERDES_WR_CTRL, data);
5878 cik_update_rlc(rdev, tmp);
5880 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
5881 orig = data = RREG32(CGTS_SM_CTRL_REG);
5882 data &= ~SM_MODE_MASK;
5883 data |= SM_MODE(0x2);
5884 data |= SM_MODE_ENABLE;
5885 data &= ~CGTS_OVERRIDE;
5886 if ((rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) &&
5887 (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS_LS))
5888 data &= ~CGTS_LS_OVERRIDE;
5889 data &= ~ON_MONITOR_ADD_MASK;
5890 data |= ON_MONITOR_ADD_EN;
5891 data |= ON_MONITOR_ADD(0x96);
5893 WREG32(CGTS_SM_CTRL_REG, data);
5896 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5899 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5901 data = RREG32(RLC_MEM_SLP_CNTL);
5902 if (data & RLC_MEM_LS_EN) {
5903 data &= ~RLC_MEM_LS_EN;
5904 WREG32(RLC_MEM_SLP_CNTL, data);
5907 data = RREG32(CP_MEM_SLP_CNTL);
5908 if (data & CP_MEM_LS_EN) {
5909 data &= ~CP_MEM_LS_EN;
5910 WREG32(CP_MEM_SLP_CNTL, data);
5913 orig = data = RREG32(CGTS_SM_CTRL_REG);
5914 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
5916 WREG32(CGTS_SM_CTRL_REG, data);
5918 tmp = cik_halt_rlc(rdev);
5920 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5921 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5922 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5923 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
5924 WREG32(RLC_SERDES_WR_CTRL, data);
5926 cik_update_rlc(rdev, tmp);
5930 static const u32 mc_cg_registers[] =
5943 static void cik_enable_mc_ls(struct radeon_device *rdev,
5949 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5950 orig = data = RREG32(mc_cg_registers[i]);
5951 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5952 data |= MC_LS_ENABLE;
5954 data &= ~MC_LS_ENABLE;
5956 WREG32(mc_cg_registers[i], data);
5960 static void cik_enable_mc_mgcg(struct radeon_device *rdev,
5966 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5967 orig = data = RREG32(mc_cg_registers[i]);
5968 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5969 data |= MC_CG_ENABLE;
5971 data &= ~MC_CG_ENABLE;
5973 WREG32(mc_cg_registers[i], data);
5977 static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
5982 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5983 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
5984 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
5986 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
5989 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
5991 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
5994 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
5998 static void cik_enable_sdma_mgls(struct radeon_device *rdev,
6003 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
6004 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6007 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6009 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6012 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6014 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6017 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6019 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6022 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6026 static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
6031 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
6032 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6034 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6036 orig = data = RREG32(UVD_CGC_CTRL);
6039 WREG32(UVD_CGC_CTRL, data);
6041 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6043 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6045 orig = data = RREG32(UVD_CGC_CTRL);
6048 WREG32(UVD_CGC_CTRL, data);
6052 static void cik_enable_bif_mgls(struct radeon_device *rdev,
6057 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
6059 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
6060 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
6061 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
6063 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
6064 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
6067 WREG32_PCIE_PORT(PCIE_CNTL2, data);
6070 static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
6075 orig = data = RREG32(HDP_HOST_PATH_CNTL);
6077 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
6078 data &= ~CLOCK_GATING_DIS;
6080 data |= CLOCK_GATING_DIS;
6083 WREG32(HDP_HOST_PATH_CNTL, data);
6086 static void cik_enable_hdp_ls(struct radeon_device *rdev,
6091 orig = data = RREG32(HDP_MEM_POWER_LS);
6093 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
6094 data |= HDP_LS_ENABLE;
6096 data &= ~HDP_LS_ENABLE;
6099 WREG32(HDP_MEM_POWER_LS, data);
6102 void cik_update_cg(struct radeon_device *rdev,
6103 u32 block, bool enable)
6106 if (block & RADEON_CG_BLOCK_GFX) {
6107 cik_enable_gui_idle_interrupt(rdev, false);
6108 /* order matters! */
6110 cik_enable_mgcg(rdev, true);
6111 cik_enable_cgcg(rdev, true);
6113 cik_enable_cgcg(rdev, false);
6114 cik_enable_mgcg(rdev, false);
6116 cik_enable_gui_idle_interrupt(rdev, true);
6119 if (block & RADEON_CG_BLOCK_MC) {
6120 if (!(rdev->flags & RADEON_IS_IGP)) {
6121 cik_enable_mc_mgcg(rdev, enable);
6122 cik_enable_mc_ls(rdev, enable);
6126 if (block & RADEON_CG_BLOCK_SDMA) {
6127 cik_enable_sdma_mgcg(rdev, enable);
6128 cik_enable_sdma_mgls(rdev, enable);
6131 if (block & RADEON_CG_BLOCK_BIF) {
6132 cik_enable_bif_mgls(rdev, enable);
6135 if (block & RADEON_CG_BLOCK_UVD) {
6137 cik_enable_uvd_mgcg(rdev, enable);
6140 if (block & RADEON_CG_BLOCK_HDP) {
6141 cik_enable_hdp_mgcg(rdev, enable);
6142 cik_enable_hdp_ls(rdev, enable);
6146 static void cik_init_cg(struct radeon_device *rdev)
6149 cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);
6152 si_init_uvd_internal_cg(rdev);
6154 cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6155 RADEON_CG_BLOCK_SDMA |
6156 RADEON_CG_BLOCK_BIF |
6157 RADEON_CG_BLOCK_UVD |
6158 RADEON_CG_BLOCK_HDP), true);
6161 static void cik_fini_cg(struct radeon_device *rdev)
6163 cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6164 RADEON_CG_BLOCK_SDMA |
6165 RADEON_CG_BLOCK_BIF |
6166 RADEON_CG_BLOCK_UVD |
6167 RADEON_CG_BLOCK_HDP), false);
6169 cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
6172 static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
6177 orig = data = RREG32(RLC_PG_CNTL);
6178 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6179 data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6181 data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6183 WREG32(RLC_PG_CNTL, data);
6186 static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
6191 orig = data = RREG32(RLC_PG_CNTL);
6192 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6193 data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6195 data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6197 WREG32(RLC_PG_CNTL, data);
6200 static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
6204 orig = data = RREG32(RLC_PG_CNTL);
6205 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
6206 data &= ~DISABLE_CP_PG;
6208 data |= DISABLE_CP_PG;
6210 WREG32(RLC_PG_CNTL, data);
6213 static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6217 orig = data = RREG32(RLC_PG_CNTL);
6218 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
6219 data &= ~DISABLE_GDS_PG;
6221 data |= DISABLE_GDS_PG;
6223 WREG32(RLC_PG_CNTL, data);
6226 #define CP_ME_TABLE_SIZE 96
6227 #define CP_ME_TABLE_OFFSET 2048
6228 #define CP_MEC_TABLE_OFFSET 4096
6230 void cik_init_cp_pg_table(struct radeon_device *rdev)
6232 const __be32 *fw_data;
6233 volatile u32 *dst_ptr;
6234 int me, i, max_me = 4;
6238 if (rdev->family == CHIP_KAVERI)
6241 if (rdev->rlc.cp_table_ptr == NULL)
6244 /* write the cp table buffer */
6245 dst_ptr = rdev->rlc.cp_table_ptr;
6246 for (me = 0; me < max_me; me++) {
6248 fw_data = (const __be32 *)rdev->ce_fw->data;
6249 table_offset = CP_ME_TABLE_OFFSET;
6250 } else if (me == 1) {
6251 fw_data = (const __be32 *)rdev->pfp_fw->data;
6252 table_offset = CP_ME_TABLE_OFFSET;
6253 } else if (me == 2) {
6254 fw_data = (const __be32 *)rdev->me_fw->data;
6255 table_offset = CP_ME_TABLE_OFFSET;
6257 fw_data = (const __be32 *)rdev->mec_fw->data;
6258 table_offset = CP_MEC_TABLE_OFFSET;
6261 for (i = 0; i < CP_ME_TABLE_SIZE; i ++) {
6262 dst_ptr[bo_offset + i] = cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
6264 bo_offset += CP_ME_TABLE_SIZE;
6268 static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
6273 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
6274 orig = data = RREG32(RLC_PG_CNTL);
6275 data |= GFX_PG_ENABLE;
6277 WREG32(RLC_PG_CNTL, data);
6279 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6282 WREG32(RLC_AUTO_PG_CTRL, data);
6284 orig = data = RREG32(RLC_PG_CNTL);
6285 data &= ~GFX_PG_ENABLE;
6287 WREG32(RLC_PG_CNTL, data);
6289 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6290 data &= ~AUTO_PG_EN;
6292 WREG32(RLC_AUTO_PG_CTRL, data);
6294 data = RREG32(DB_RENDER_CONTROL);
6298 static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6300 u32 mask = 0, tmp, tmp1;
6303 cik_select_se_sh(rdev, se, sh);
6304 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6305 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6306 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6313 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6318 return (~tmp) & mask;
6321 static void cik_init_ao_cu_mask(struct radeon_device *rdev)
6323 u32 i, j, k, active_cu_number = 0;
6324 u32 mask, counter, cu_bitmap;
6327 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6328 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6332 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
6333 if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
6341 active_cu_number += counter;
6342 tmp |= (cu_bitmap << (i * 16 + j * 8));
6346 WREG32(RLC_PG_AO_CU_MASK, tmp);
6348 tmp = RREG32(RLC_MAX_PG_CU);
6349 tmp &= ~MAX_PU_CU_MASK;
6350 tmp |= MAX_PU_CU(active_cu_number);
6351 WREG32(RLC_MAX_PG_CU, tmp);
6354 static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
6359 orig = data = RREG32(RLC_PG_CNTL);
6360 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
6361 data |= STATIC_PER_CU_PG_ENABLE;
6363 data &= ~STATIC_PER_CU_PG_ENABLE;
6365 WREG32(RLC_PG_CNTL, data);
6368 static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
6373 orig = data = RREG32(RLC_PG_CNTL);
6374 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
6375 data |= DYN_PER_CU_PG_ENABLE;
6377 data &= ~DYN_PER_CU_PG_ENABLE;
6379 WREG32(RLC_PG_CNTL, data);
6382 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
6383 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
6385 static void cik_init_gfx_cgpg(struct radeon_device *rdev)
6390 if (rdev->rlc.cs_data) {
6391 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6392 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
6393 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
6394 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
6396 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6397 for (i = 0; i < 3; i++)
6398 WREG32(RLC_GPM_SCRATCH_DATA, 0);
6400 if (rdev->rlc.reg_list) {
6401 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
6402 for (i = 0; i < rdev->rlc.reg_list_size; i++)
6403 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
6406 orig = data = RREG32(RLC_PG_CNTL);
6409 WREG32(RLC_PG_CNTL, data);
6411 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
6412 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
6414 data = RREG32(CP_RB_WPTR_POLL_CNTL);
6415 data &= ~IDLE_POLL_COUNT_MASK;
6416 data |= IDLE_POLL_COUNT(0x60);
6417 WREG32(CP_RB_WPTR_POLL_CNTL, data);
6420 WREG32(RLC_PG_DELAY, data);
6422 data = RREG32(RLC_PG_DELAY_2);
6425 WREG32(RLC_PG_DELAY_2, data);
6427 data = RREG32(RLC_AUTO_PG_CTRL);
6428 data &= ~GRBM_REG_SGIT_MASK;
6429 data |= GRBM_REG_SGIT(0x700);
6430 WREG32(RLC_AUTO_PG_CTRL, data);
6434 static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
6436 cik_enable_gfx_cgpg(rdev, enable);
6437 cik_enable_gfx_static_mgpg(rdev, enable);
6438 cik_enable_gfx_dynamic_mgpg(rdev, enable);
6441 u32 cik_get_csb_size(struct radeon_device *rdev)
6444 const struct cs_section_def *sect = NULL;
6445 const struct cs_extent_def *ext = NULL;
6447 if (rdev->rlc.cs_data == NULL)
6450 /* begin clear state */
6452 /* context control state */
6455 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6456 for (ext = sect->section; ext->extent != NULL; ++ext) {
6457 if (sect->id == SECT_CONTEXT)
6458 count += 2 + ext->reg_count;
6463 /* pa_sc_raster_config/pa_sc_raster_config1 */
6465 /* end clear state */
6473 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
6476 const struct cs_section_def *sect = NULL;
6477 const struct cs_extent_def *ext = NULL;
6479 if (rdev->rlc.cs_data == NULL)
6484 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6485 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6487 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6488 buffer[count++] = cpu_to_le32(0x80000000);
6489 buffer[count++] = cpu_to_le32(0x80000000);
6491 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6492 for (ext = sect->section; ext->extent != NULL; ++ext) {
6493 if (sect->id == SECT_CONTEXT) {
6495 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
6496 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
6497 for (i = 0; i < ext->reg_count; i++)
6498 buffer[count++] = cpu_to_le32(ext->extent[i]);
6505 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
6506 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
6507 switch (rdev->family) {
6509 buffer[count++] = cpu_to_le32(0x16000012);
6510 buffer[count++] = cpu_to_le32(0x00000000);
6513 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6514 buffer[count++] = cpu_to_le32(0x00000000);
6517 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6518 buffer[count++] = cpu_to_le32(0x00000000);
6521 buffer[count++] = 0x3a00161a;
6522 buffer[count++] = 0x0000002e;
6525 buffer[count++] = cpu_to_le32(0x00000000);
6526 buffer[count++] = cpu_to_le32(0x00000000);
6530 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6531 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
6533 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
6534 buffer[count++] = cpu_to_le32(0);
6537 static void cik_init_pg(struct radeon_device *rdev)
6539 if (rdev->pg_flags) {
6540 cik_enable_sck_slowdown_on_pu(rdev, true);
6541 cik_enable_sck_slowdown_on_pd(rdev, true);
6542 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6543 cik_init_gfx_cgpg(rdev);
6544 cik_enable_cp_pg(rdev, true);
6545 cik_enable_gds_pg(rdev, true);
6547 cik_init_ao_cu_mask(rdev);
6548 cik_update_gfx_pg(rdev, true);
6552 static void cik_fini_pg(struct radeon_device *rdev)
6554 if (rdev->pg_flags) {
6555 cik_update_gfx_pg(rdev, false);
6556 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6557 cik_enable_cp_pg(rdev, false);
6558 cik_enable_gds_pg(rdev, false);
6565 * Starting with r6xx, interrupts are handled via a ring buffer.
6566 * Ring buffers are areas of GPU accessible memory that the GPU
6567 * writes interrupt vectors into and the host reads vectors out of.
6568 * There is a rptr (read pointer) that determines where the
6569 * host is currently reading, and a wptr (write pointer)
6570 * which determines where the GPU has written. When the
6571 * pointers are equal, the ring is idle. When the GPU
6572 * writes vectors to the ring buffer, it increments the
6573 * wptr. When there is an interrupt, the host then starts
6574 * fetching commands and processing them until the pointers are
6575 * equal again at which point it updates the rptr.
6579 * cik_enable_interrupts - Enable the interrupt ring buffer
6581 * @rdev: radeon_device pointer
6583 * Enable the interrupt ring buffer (CIK).
6585 static void cik_enable_interrupts(struct radeon_device *rdev)
6587 u32 ih_cntl = RREG32(IH_CNTL);
6588 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6590 ih_cntl |= ENABLE_INTR;
6591 ih_rb_cntl |= IH_RB_ENABLE;
6592 WREG32(IH_CNTL, ih_cntl);
6593 WREG32(IH_RB_CNTL, ih_rb_cntl);
6594 rdev->ih.enabled = true;
6598 * cik_disable_interrupts - Disable the interrupt ring buffer
6600 * @rdev: radeon_device pointer
6602 * Disable the interrupt ring buffer (CIK).
6604 static void cik_disable_interrupts(struct radeon_device *rdev)
6606 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6607 u32 ih_cntl = RREG32(IH_CNTL);
6609 ih_rb_cntl &= ~IH_RB_ENABLE;
6610 ih_cntl &= ~ENABLE_INTR;
6611 WREG32(IH_RB_CNTL, ih_rb_cntl);
6612 WREG32(IH_CNTL, ih_cntl);
6613 /* set rptr, wptr to 0 */
6614 WREG32(IH_RB_RPTR, 0);
6615 WREG32(IH_RB_WPTR, 0);
6616 rdev->ih.enabled = false;
6621 * cik_disable_interrupt_state - Disable all interrupt sources
6623 * @rdev: radeon_device pointer
6625 * Clear all interrupt enable bits used by the driver (CIK).
6627 static void cik_disable_interrupt_state(struct radeon_device *rdev)
6632 tmp = RREG32(CP_INT_CNTL_RING0) &
6633 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6634 WREG32(CP_INT_CNTL_RING0, tmp);
6636 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6637 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6638 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6639 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
6640 /* compute queues */
6641 WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
6642 WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
6643 WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
6644 WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
6645 WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
6646 WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
6647 WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
6648 WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
6650 WREG32(GRBM_INT_CNTL, 0);
6651 /* vline/vblank, etc. */
6652 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6653 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6654 if (rdev->num_crtc >= 4) {
6655 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6656 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6658 if (rdev->num_crtc >= 6) {
6659 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6660 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6664 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
6666 /* digital hotplug */
6667 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6668 WREG32(DC_HPD1_INT_CONTROL, tmp);
6669 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6670 WREG32(DC_HPD2_INT_CONTROL, tmp);
6671 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6672 WREG32(DC_HPD3_INT_CONTROL, tmp);
6673 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6674 WREG32(DC_HPD4_INT_CONTROL, tmp);
6675 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6676 WREG32(DC_HPD5_INT_CONTROL, tmp);
6677 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6678 WREG32(DC_HPD6_INT_CONTROL, tmp);
6683 * cik_irq_init - init and enable the interrupt ring
6685 * @rdev: radeon_device pointer
6687 * Allocate a ring buffer for the interrupt controller,
6688 * enable the RLC, disable interrupts, enable the IH
6689 * ring buffer and enable it (CIK).
6690 * Called at device load and reume.
6691 * Returns 0 for success, errors for failure.
6693 static int cik_irq_init(struct radeon_device *rdev)
6697 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
6700 ret = r600_ih_ring_alloc(rdev);
6705 cik_disable_interrupts(rdev);
6708 ret = cik_rlc_resume(rdev);
6710 r600_ih_ring_fini(rdev);
6714 /* setup interrupt control */
6715 /* XXX this should actually be a bus address, not an MC address. same on older asics */
6716 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
6717 interrupt_cntl = RREG32(INTERRUPT_CNTL);
6718 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
6719 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
6721 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
6722 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6723 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6724 WREG32(INTERRUPT_CNTL, interrupt_cntl);
6726 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6727 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6729 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6730 IH_WPTR_OVERFLOW_CLEAR |
6733 if (rdev->wb.enabled)
6734 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6736 /* set the writeback address whether it's enabled or not */
6737 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6738 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6740 WREG32(IH_RB_CNTL, ih_rb_cntl);
6742 /* set rptr, wptr to 0 */
6743 WREG32(IH_RB_RPTR, 0);
6744 WREG32(IH_RB_WPTR, 0);
6746 /* Default settings for IH_CNTL (disabled at first) */
6747 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6748 /* RPTR_REARM only works if msi's are enabled */
6749 if (rdev->msi_enabled)
6750 ih_cntl |= RPTR_REARM;
6751 WREG32(IH_CNTL, ih_cntl);
6753 /* force the active interrupt state to all disabled */
6754 cik_disable_interrupt_state(rdev);
6756 pci_set_master(rdev->pdev);
6759 cik_enable_interrupts(rdev);
6765 * cik_irq_set - enable/disable interrupt sources
6767 * @rdev: radeon_device pointer
6769 * Enable interrupt sources on the GPU (vblanks, hpd,
6771 * Returns 0 for success, errors for failure.
6773 int cik_irq_set(struct radeon_device *rdev)
6776 u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
6777 u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
6778 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
6779 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
6780 u32 grbm_int_cntl = 0;
6781 u32 dma_cntl, dma_cntl1;
6784 if (!rdev->irq.installed) {
6785 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6788 /* don't enable anything if the ih is disabled */
6789 if (!rdev->ih.enabled) {
6790 cik_disable_interrupts(rdev);
6791 /* force the active interrupt state to all disabled */
6792 cik_disable_interrupt_state(rdev);
6796 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6797 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6798 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
6800 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
6801 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
6802 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
6803 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
6804 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
6805 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
6807 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6808 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6810 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6811 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6812 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6813 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6814 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6815 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6816 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6817 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6819 if (rdev->flags & RADEON_IS_IGP)
6820 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &
6821 ~(THERM_INTH_MASK | THERM_INTL_MASK);
6823 thermal_int = RREG32_SMC(CG_THERMAL_INT) &
6824 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6826 /* enable CP interrupts on all rings */
6827 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6828 DRM_DEBUG("cik_irq_set: sw int gfx\n");
6829 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6831 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6832 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6833 DRM_DEBUG("si_irq_set: sw int cp1\n");
6834 if (ring->me == 1) {
6835 switch (ring->pipe) {
6837 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
6840 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
6843 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6846 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6849 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
6852 } else if (ring->me == 2) {
6853 switch (ring->pipe) {
6855 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
6858 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
6861 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6864 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6867 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
6871 DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me);
6874 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6875 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6876 DRM_DEBUG("si_irq_set: sw int cp2\n");
6877 if (ring->me == 1) {
6878 switch (ring->pipe) {
6880 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
6883 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
6886 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6889 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6892 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
6895 } else if (ring->me == 2) {
6896 switch (ring->pipe) {
6898 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
6901 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
6904 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6907 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6910 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
6914 DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me);
6918 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6919 DRM_DEBUG("cik_irq_set: sw int dma\n");
6920 dma_cntl |= TRAP_ENABLE;
6923 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6924 DRM_DEBUG("cik_irq_set: sw int dma1\n");
6925 dma_cntl1 |= TRAP_ENABLE;
6928 if (rdev->irq.crtc_vblank_int[0] ||
6929 atomic_read(&rdev->irq.pflip[0])) {
6930 DRM_DEBUG("cik_irq_set: vblank 0\n");
6931 crtc1 |= VBLANK_INTERRUPT_MASK;
6933 if (rdev->irq.crtc_vblank_int[1] ||
6934 atomic_read(&rdev->irq.pflip[1])) {
6935 DRM_DEBUG("cik_irq_set: vblank 1\n");
6936 crtc2 |= VBLANK_INTERRUPT_MASK;
6938 if (rdev->irq.crtc_vblank_int[2] ||
6939 atomic_read(&rdev->irq.pflip[2])) {
6940 DRM_DEBUG("cik_irq_set: vblank 2\n");
6941 crtc3 |= VBLANK_INTERRUPT_MASK;
6943 if (rdev->irq.crtc_vblank_int[3] ||
6944 atomic_read(&rdev->irq.pflip[3])) {
6945 DRM_DEBUG("cik_irq_set: vblank 3\n");
6946 crtc4 |= VBLANK_INTERRUPT_MASK;
6948 if (rdev->irq.crtc_vblank_int[4] ||
6949 atomic_read(&rdev->irq.pflip[4])) {
6950 DRM_DEBUG("cik_irq_set: vblank 4\n");
6951 crtc5 |= VBLANK_INTERRUPT_MASK;
6953 if (rdev->irq.crtc_vblank_int[5] ||
6954 atomic_read(&rdev->irq.pflip[5])) {
6955 DRM_DEBUG("cik_irq_set: vblank 5\n");
6956 crtc6 |= VBLANK_INTERRUPT_MASK;
6958 if (rdev->irq.hpd[0]) {
6959 DRM_DEBUG("cik_irq_set: hpd 1\n");
6960 hpd1 |= DC_HPDx_INT_EN;
6962 if (rdev->irq.hpd[1]) {
6963 DRM_DEBUG("cik_irq_set: hpd 2\n");
6964 hpd2 |= DC_HPDx_INT_EN;
6966 if (rdev->irq.hpd[2]) {
6967 DRM_DEBUG("cik_irq_set: hpd 3\n");
6968 hpd3 |= DC_HPDx_INT_EN;
6970 if (rdev->irq.hpd[3]) {
6971 DRM_DEBUG("cik_irq_set: hpd 4\n");
6972 hpd4 |= DC_HPDx_INT_EN;
6974 if (rdev->irq.hpd[4]) {
6975 DRM_DEBUG("cik_irq_set: hpd 5\n");
6976 hpd5 |= DC_HPDx_INT_EN;
6978 if (rdev->irq.hpd[5]) {
6979 DRM_DEBUG("cik_irq_set: hpd 6\n");
6980 hpd6 |= DC_HPDx_INT_EN;
6983 if (rdev->irq.dpm_thermal) {
6984 DRM_DEBUG("dpm thermal\n");
6985 if (rdev->flags & RADEON_IS_IGP)
6986 thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
6988 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6991 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6993 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
6994 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
6996 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
6997 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
6998 WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
6999 WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
7000 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
7001 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
7002 WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
7003 WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
7005 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
7007 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
7008 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
7009 if (rdev->num_crtc >= 4) {
7010 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
7011 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
7013 if (rdev->num_crtc >= 6) {
7014 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
7015 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7018 WREG32(DC_HPD1_INT_CONTROL, hpd1);
7019 WREG32(DC_HPD2_INT_CONTROL, hpd2);
7020 WREG32(DC_HPD3_INT_CONTROL, hpd3);
7021 WREG32(DC_HPD4_INT_CONTROL, hpd4);
7022 WREG32(DC_HPD5_INT_CONTROL, hpd5);
7023 WREG32(DC_HPD6_INT_CONTROL, hpd6);
7025 if (rdev->flags & RADEON_IS_IGP)
7026 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
7028 WREG32_SMC(CG_THERMAL_INT, thermal_int);
7034 * cik_irq_ack - ack interrupt sources
7036 * @rdev: radeon_device pointer
7038 * Ack interrupt sources on the GPU (vblanks, hpd,
7039 * etc.) (CIK). Certain interrupts sources are sw
7040 * generated and do not require an explicit ack.
7042 static inline void cik_irq_ack(struct radeon_device *rdev)
7046 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7047 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7048 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7049 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7050 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7051 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7052 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7054 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7055 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7056 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7057 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
7058 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
7059 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
7060 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
7061 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7063 if (rdev->num_crtc >= 4) {
7064 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7065 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7066 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
7067 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
7068 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
7069 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
7070 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
7071 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
7074 if (rdev->num_crtc >= 6) {
7075 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7076 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7077 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
7078 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
7079 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
7080 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
7081 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
7082 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
7085 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7086 tmp = RREG32(DC_HPD1_INT_CONTROL);
7087 tmp |= DC_HPDx_INT_ACK;
7088 WREG32(DC_HPD1_INT_CONTROL, tmp);
7090 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7091 tmp = RREG32(DC_HPD2_INT_CONTROL);
7092 tmp |= DC_HPDx_INT_ACK;
7093 WREG32(DC_HPD2_INT_CONTROL, tmp);
7095 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7096 tmp = RREG32(DC_HPD3_INT_CONTROL);
7097 tmp |= DC_HPDx_INT_ACK;
7098 WREG32(DC_HPD3_INT_CONTROL, tmp);
7100 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7101 tmp = RREG32(DC_HPD4_INT_CONTROL);
7102 tmp |= DC_HPDx_INT_ACK;
7103 WREG32(DC_HPD4_INT_CONTROL, tmp);
7105 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7106 tmp = RREG32(DC_HPD5_INT_CONTROL);
7107 tmp |= DC_HPDx_INT_ACK;
7108 WREG32(DC_HPD5_INT_CONTROL, tmp);
7110 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7111 tmp = RREG32(DC_HPD5_INT_CONTROL);
7112 tmp |= DC_HPDx_INT_ACK;
7113 WREG32(DC_HPD6_INT_CONTROL, tmp);
7118 * cik_irq_disable - disable interrupts
7120 * @rdev: radeon_device pointer
7122 * Disable interrupts on the hw (CIK).
7124 static void cik_irq_disable(struct radeon_device *rdev)
7126 cik_disable_interrupts(rdev);
7127 /* Wait and acknowledge irq */
7130 cik_disable_interrupt_state(rdev);
7134 * cik_irq_disable - disable interrupts for suspend
7136 * @rdev: radeon_device pointer
7138 * Disable interrupts and stop the RLC (CIK).
7141 static void cik_irq_suspend(struct radeon_device *rdev)
7143 cik_irq_disable(rdev);
7148 * cik_irq_fini - tear down interrupt support
7150 * @rdev: radeon_device pointer
7152 * Disable interrupts on the hw and free the IH ring
7154 * Used for driver unload.
7156 static void cik_irq_fini(struct radeon_device *rdev)
7158 cik_irq_suspend(rdev);
7159 r600_ih_ring_fini(rdev);
7163 * cik_get_ih_wptr - get the IH ring buffer wptr
7165 * @rdev: radeon_device pointer
7167 * Get the IH ring buffer wptr from either the register
7168 * or the writeback memory buffer (CIK). Also check for
7169 * ring buffer overflow and deal with it.
7170 * Used by cik_irq_process().
7171 * Returns the value of the wptr.
7173 static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
7177 if (rdev->wb.enabled)
7178 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
7180 wptr = RREG32(IH_RB_WPTR);
7182 if (wptr & RB_OVERFLOW) {
7183 /* When a ring buffer overflow happen start parsing interrupt
7184 * from the last not overwritten vector (wptr + 16). Hopefully
7185 * this should allow us to catchup.
7187 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
7188 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
7189 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
7190 tmp = RREG32(IH_RB_CNTL);
7191 tmp |= IH_WPTR_OVERFLOW_CLEAR;
7192 WREG32(IH_RB_CNTL, tmp);
7194 return (wptr & rdev->ih.ptr_mask);
7198 * Each IV ring entry is 128 bits:
7199 * [7:0] - interrupt source id
7201 * [59:32] - interrupt source data
7202 * [63:60] - reserved
7205 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
7206 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
7207 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
7208 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
7209 * PIPE_ID - ME0 0=3D
7210 * - ME1&2 compute dispatcher (4 pipes each)
7212 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
7213 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
7214 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
7217 * [127:96] - reserved
7220 * cik_irq_process - interrupt handler
7222 * @rdev: radeon_device pointer
7224 * Interrupt hander (CIK). Walk the IH ring,
7225 * ack interrupts and schedule work to handle
7227 * Returns irq process return code.
7229 int cik_irq_process(struct radeon_device *rdev)
7231 struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7232 struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7235 u32 src_id, src_data, ring_id;
7236 u8 me_id, pipe_id, queue_id;
7238 bool queue_hotplug = false;
7239 bool queue_reset = false;
7240 u32 addr, status, mc_client;
7241 bool queue_thermal = false;
7243 if (!rdev->ih.enabled || rdev->shutdown)
7246 wptr = cik_get_ih_wptr(rdev);
7249 /* is somebody else already processing irqs? */
7250 if (atomic_xchg(&rdev->ih.lock, 1))
7253 rptr = rdev->ih.rptr;
7254 DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
7256 /* Order reading of wptr vs. reading of IH ring data */
7259 /* display interrupts */
7262 while (rptr != wptr) {
7263 /* wptr/rptr are in bytes! */
7264 ring_index = rptr / 4;
7265 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
7266 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
7267 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
7270 case 1: /* D1 vblank/vline */
7272 case 0: /* D1 vblank */
7273 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) {
7274 if (rdev->irq.crtc_vblank_int[0]) {
7275 drm_handle_vblank(rdev->ddev, 0);
7276 rdev->pm.vblank_sync = true;
7277 wake_up(&rdev->irq.vblank_queue);
7279 if (atomic_read(&rdev->irq.pflip[0]))
7280 radeon_crtc_handle_flip(rdev, 0);
7281 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7282 DRM_DEBUG("IH: D1 vblank\n");
7285 case 1: /* D1 vline */
7286 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) {
7287 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7288 DRM_DEBUG("IH: D1 vline\n");
7292 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7296 case 2: /* D2 vblank/vline */
7298 case 0: /* D2 vblank */
7299 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
7300 if (rdev->irq.crtc_vblank_int[1]) {
7301 drm_handle_vblank(rdev->ddev, 1);
7302 rdev->pm.vblank_sync = true;
7303 wake_up(&rdev->irq.vblank_queue);
7305 if (atomic_read(&rdev->irq.pflip[1]))
7306 radeon_crtc_handle_flip(rdev, 1);
7307 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
7308 DRM_DEBUG("IH: D2 vblank\n");
7311 case 1: /* D2 vline */
7312 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
7313 rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
7314 DRM_DEBUG("IH: D2 vline\n");
7318 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7322 case 3: /* D3 vblank/vline */
7324 case 0: /* D3 vblank */
7325 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
7326 if (rdev->irq.crtc_vblank_int[2]) {
7327 drm_handle_vblank(rdev->ddev, 2);
7328 rdev->pm.vblank_sync = true;
7329 wake_up(&rdev->irq.vblank_queue);
7331 if (atomic_read(&rdev->irq.pflip[2]))
7332 radeon_crtc_handle_flip(rdev, 2);
7333 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
7334 DRM_DEBUG("IH: D3 vblank\n");
7337 case 1: /* D3 vline */
7338 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
7339 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
7340 DRM_DEBUG("IH: D3 vline\n");
7344 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7348 case 4: /* D4 vblank/vline */
7350 case 0: /* D4 vblank */
7351 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
7352 if (rdev->irq.crtc_vblank_int[3]) {
7353 drm_handle_vblank(rdev->ddev, 3);
7354 rdev->pm.vblank_sync = true;
7355 wake_up(&rdev->irq.vblank_queue);
7357 if (atomic_read(&rdev->irq.pflip[3]))
7358 radeon_crtc_handle_flip(rdev, 3);
7359 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
7360 DRM_DEBUG("IH: D4 vblank\n");
7363 case 1: /* D4 vline */
7364 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
7365 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
7366 DRM_DEBUG("IH: D4 vline\n");
7370 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7374 case 5: /* D5 vblank/vline */
7376 case 0: /* D5 vblank */
7377 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
7378 if (rdev->irq.crtc_vblank_int[4]) {
7379 drm_handle_vblank(rdev->ddev, 4);
7380 rdev->pm.vblank_sync = true;
7381 wake_up(&rdev->irq.vblank_queue);
7383 if (atomic_read(&rdev->irq.pflip[4]))
7384 radeon_crtc_handle_flip(rdev, 4);
7385 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
7386 DRM_DEBUG("IH: D5 vblank\n");
7389 case 1: /* D5 vline */
7390 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
7391 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
7392 DRM_DEBUG("IH: D5 vline\n");
7396 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7400 case 6: /* D6 vblank/vline */
7402 case 0: /* D6 vblank */
7403 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
7404 if (rdev->irq.crtc_vblank_int[5]) {
7405 drm_handle_vblank(rdev->ddev, 5);
7406 rdev->pm.vblank_sync = true;
7407 wake_up(&rdev->irq.vblank_queue);
7409 if (atomic_read(&rdev->irq.pflip[5]))
7410 radeon_crtc_handle_flip(rdev, 5);
7411 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
7412 DRM_DEBUG("IH: D6 vblank\n");
7415 case 1: /* D6 vline */
7416 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
7417 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
7418 DRM_DEBUG("IH: D6 vline\n");
7422 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7426 case 42: /* HPD hotplug */
7429 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7430 rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
7431 queue_hotplug = true;
7432 DRM_DEBUG("IH: HPD1\n");
7436 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7437 rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
7438 queue_hotplug = true;
7439 DRM_DEBUG("IH: HPD2\n");
7443 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7444 rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
7445 queue_hotplug = true;
7446 DRM_DEBUG("IH: HPD3\n");
7450 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7451 rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
7452 queue_hotplug = true;
7453 DRM_DEBUG("IH: HPD4\n");
7457 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7458 rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
7459 queue_hotplug = true;
7460 DRM_DEBUG("IH: HPD5\n");
7464 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7465 rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
7466 queue_hotplug = true;
7467 DRM_DEBUG("IH: HPD6\n");
7471 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7476 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
7477 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
7481 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
7482 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
7483 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
7484 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
7485 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
7487 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
7489 cik_vm_decode_fault(rdev, status, addr, mc_client);
7490 /* reset addr and status */
7491 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
7493 case 176: /* GFX RB CP_INT */
7494 case 177: /* GFX IB CP_INT */
7495 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7497 case 181: /* CP EOP event */
7498 DRM_DEBUG("IH: CP EOP\n");
7499 /* XXX check the bitfield order! */
7500 me_id = (ring_id & 0x60) >> 5;
7501 pipe_id = (ring_id & 0x18) >> 3;
7502 queue_id = (ring_id & 0x7) >> 0;
7505 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7509 if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
7510 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7511 if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
7512 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7516 case 184: /* CP Privileged reg access */
7517 DRM_ERROR("Illegal register access in command stream\n");
7518 /* XXX check the bitfield order! */
7519 me_id = (ring_id & 0x60) >> 5;
7520 pipe_id = (ring_id & 0x18) >> 3;
7521 queue_id = (ring_id & 0x7) >> 0;
7524 /* This results in a full GPU reset, but all we need to do is soft
7525 * reset the CP for gfx
7539 case 185: /* CP Privileged inst */
7540 DRM_ERROR("Illegal instruction in command stream\n");
7541 /* XXX check the bitfield order! */
7542 me_id = (ring_id & 0x60) >> 5;
7543 pipe_id = (ring_id & 0x18) >> 3;
7544 queue_id = (ring_id & 0x7) >> 0;
7547 /* This results in a full GPU reset, but all we need to do is soft
7548 * reset the CP for gfx
7562 case 224: /* SDMA trap event */
7563 /* XXX check the bitfield order! */
7564 me_id = (ring_id & 0x3) >> 0;
7565 queue_id = (ring_id & 0xc) >> 2;
7566 DRM_DEBUG("IH: SDMA trap\n");
7571 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
7584 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7596 case 230: /* thermal low to high */
7597 DRM_DEBUG("IH: thermal low to high\n");
7598 rdev->pm.dpm.thermal.high_to_low = false;
7599 queue_thermal = true;
7601 case 231: /* thermal high to low */
7602 DRM_DEBUG("IH: thermal high to low\n");
7603 rdev->pm.dpm.thermal.high_to_low = true;
7604 queue_thermal = true;
7606 case 233: /* GUI IDLE */
7607 DRM_DEBUG("IH: GUI idle\n");
7609 case 241: /* SDMA Privileged inst */
7610 case 247: /* SDMA Privileged inst */
7611 DRM_ERROR("Illegal instruction in SDMA command stream\n");
7612 /* XXX check the bitfield order! */
7613 me_id = (ring_id & 0x3) >> 0;
7614 queue_id = (ring_id & 0xc) >> 2;
7649 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7653 /* wptr/rptr are in bytes! */
7655 rptr &= rdev->ih.ptr_mask;
7658 schedule_work(&rdev->hotplug_work);
7660 schedule_work(&rdev->reset_work);
7662 schedule_work(&rdev->pm.dpm.thermal.work);
7663 rdev->ih.rptr = rptr;
7664 WREG32(IH_RB_RPTR, rdev->ih.rptr);
7665 atomic_set(&rdev->ih.lock, 0);
7667 /* make sure wptr hasn't changed while processing */
7668 wptr = cik_get_ih_wptr(rdev);
7676 * startup/shutdown callbacks
7679 * cik_startup - program the asic to a functional state
7681 * @rdev: radeon_device pointer
7683 * Programs the asic to a functional state (CIK).
7684 * Called by cik_init() and cik_resume().
7685 * Returns 0 for success, error for failure.
7687 static int cik_startup(struct radeon_device *rdev)
7689 struct radeon_ring *ring;
7692 /* enable pcie gen2/3 link */
7693 cik_pcie_gen3_enable(rdev);
7695 cik_program_aspm(rdev);
7697 /* scratch needs to be initialized before MC */
7698 r = r600_vram_scratch_init(rdev);
7702 cik_mc_program(rdev);
7704 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
7705 r = ci_mc_load_microcode(rdev);
7707 DRM_ERROR("Failed to load MC firmware!\n");
7712 r = cik_pcie_gart_enable(rdev);
7717 /* allocate rlc buffers */
7718 if (rdev->flags & RADEON_IS_IGP) {
7719 if (rdev->family == CHIP_KAVERI) {
7720 rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
7721 rdev->rlc.reg_list_size =
7722 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
7724 rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
7725 rdev->rlc.reg_list_size =
7726 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
7729 rdev->rlc.cs_data = ci_cs_data;
7730 rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
7731 r = sumo_rlc_init(rdev);
7733 DRM_ERROR("Failed to init rlc BOs!\n");
7737 /* allocate wb buffer */
7738 r = radeon_wb_init(rdev);
7742 /* allocate mec buffers */
7743 r = cik_mec_init(rdev);
7745 DRM_ERROR("Failed to init MEC BOs!\n");
7749 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
7751 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7755 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7757 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7761 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7763 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7767 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
7769 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7773 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7775 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7779 r = radeon_uvd_resume(rdev);
7781 r = uvd_v4_2_resume(rdev);
7783 r = radeon_fence_driver_start_ring(rdev,
7784 R600_RING_TYPE_UVD_INDEX);
7786 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
7790 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
7793 if (!rdev->irq.installed) {
7794 r = radeon_irq_kms_init(rdev);
7799 r = cik_irq_init(rdev);
7801 DRM_ERROR("radeon: IH init failed (%d).\n", r);
7802 radeon_irq_kms_fini(rdev);
7807 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7808 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
7809 PACKET3(PACKET3_NOP, 0x3FFF));
7813 /* set up the compute queues */
7814 /* type-2 packets are deprecated on MEC, use type-3 instead */
7815 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7816 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
7817 PACKET3(PACKET3_NOP, 0x3FFF));
7820 ring->me = 1; /* first MEC */
7821 ring->pipe = 0; /* first pipe */
7822 ring->queue = 0; /* first queue */
7823 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
7825 /* type-2 packets are deprecated on MEC, use type-3 instead */
7826 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7827 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
7828 PACKET3(PACKET3_NOP, 0x3FFF));
7831 /* dGPU only have 1 MEC */
7832 ring->me = 1; /* first MEC */
7833 ring->pipe = 0; /* first pipe */
7834 ring->queue = 1; /* second queue */
7835 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
7837 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7838 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
7839 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7843 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7844 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
7845 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7849 r = cik_cp_resume(rdev);
7853 r = cik_sdma_resume(rdev);
7857 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
7858 if (ring->ring_size) {
7859 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
7862 r = uvd_v1_0_init(rdev);
7864 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
7867 r = radeon_ib_pool_init(rdev);
7869 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7873 r = radeon_vm_manager_init(rdev);
7875 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7879 r = dce6_audio_init(rdev);
7887 * cik_resume - resume the asic to a functional state
7889 * @rdev: radeon_device pointer
7891 * Programs the asic to a functional state (CIK).
7893 * Returns 0 for success, error for failure.
7895 int cik_resume(struct radeon_device *rdev)
7900 atom_asic_init(rdev->mode_info.atom_context);
7902 /* init golden registers */
7903 cik_init_golden_registers(rdev);
7905 radeon_pm_resume(rdev);
7907 rdev->accel_working = true;
7908 r = cik_startup(rdev);
7910 DRM_ERROR("cik startup failed on resume\n");
7911 rdev->accel_working = false;
7920 * cik_suspend - suspend the asic
7922 * @rdev: radeon_device pointer
7924 * Bring the chip into a state suitable for suspend (CIK).
7925 * Called at suspend.
7926 * Returns 0 for success.
7928 int cik_suspend(struct radeon_device *rdev)
7930 radeon_pm_suspend(rdev);
7931 dce6_audio_fini(rdev);
7932 radeon_vm_manager_fini(rdev);
7933 cik_cp_enable(rdev, false);
7934 cik_sdma_enable(rdev, false);
7935 uvd_v1_0_fini(rdev);
7936 radeon_uvd_suspend(rdev);
7939 cik_irq_suspend(rdev);
7940 radeon_wb_disable(rdev);
7941 cik_pcie_gart_disable(rdev);
7945 /* Plan is to move initialization in that function and use
7946 * helper function so that radeon_device_init pretty much
7947 * do nothing more than calling asic specific function. This
7948 * should also allow to remove a bunch of callback function
7952 * cik_init - asic specific driver and hw init
7954 * @rdev: radeon_device pointer
7956 * Setup asic specific driver variables and program the hw
7957 * to a functional state (CIK).
7958 * Called at driver startup.
7959 * Returns 0 for success, errors for failure.
7961 int cik_init(struct radeon_device *rdev)
7963 struct radeon_ring *ring;
7967 if (!radeon_get_bios(rdev)) {
7968 if (ASIC_IS_AVIVO(rdev))
7971 /* Must be an ATOMBIOS */
7972 if (!rdev->is_atom_bios) {
7973 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7976 r = radeon_atombios_init(rdev);
7980 /* Post card if necessary */
7981 if (!radeon_card_posted(rdev)) {
7983 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7986 DRM_INFO("GPU not posted. posting now...\n");
7987 atom_asic_init(rdev->mode_info.atom_context);
7989 /* init golden registers */
7990 cik_init_golden_registers(rdev);
7991 /* Initialize scratch registers */
7992 cik_scratch_init(rdev);
7993 /* Initialize surface registers */
7994 radeon_surface_init(rdev);
7995 /* Initialize clocks */
7996 radeon_get_clock_info(rdev->ddev);
7999 r = radeon_fence_driver_init(rdev);
8003 /* initialize memory controller */
8004 r = cik_mc_init(rdev);
8007 /* Memory manager */
8008 r = radeon_bo_init(rdev);
8012 if (rdev->flags & RADEON_IS_IGP) {
8013 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8014 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
8015 r = cik_init_microcode(rdev);
8017 DRM_ERROR("Failed to load firmware!\n");
8022 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8023 !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
8025 r = cik_init_microcode(rdev);
8027 DRM_ERROR("Failed to load firmware!\n");
8033 /* Initialize power management */
8034 radeon_pm_init(rdev);
8036 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8037 ring->ring_obj = NULL;
8038 r600_ring_init(rdev, ring, 1024 * 1024);
8040 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8041 ring->ring_obj = NULL;
8042 r600_ring_init(rdev, ring, 1024 * 1024);
8043 r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8047 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8048 ring->ring_obj = NULL;
8049 r600_ring_init(rdev, ring, 1024 * 1024);
8050 r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8054 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8055 ring->ring_obj = NULL;
8056 r600_ring_init(rdev, ring, 256 * 1024);
8058 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8059 ring->ring_obj = NULL;
8060 r600_ring_init(rdev, ring, 256 * 1024);
8062 r = radeon_uvd_init(rdev);
8064 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
8065 ring->ring_obj = NULL;
8066 r600_ring_init(rdev, ring, 4096);
8069 rdev->ih.ring_obj = NULL;
8070 r600_ih_ring_init(rdev, 64 * 1024);
8072 r = r600_pcie_gart_init(rdev);
8076 rdev->accel_working = true;
8077 r = cik_startup(rdev);
8079 dev_err(rdev->dev, "disabling GPU acceleration\n");
8081 cik_sdma_fini(rdev);
8083 sumo_rlc_fini(rdev);
8085 radeon_wb_fini(rdev);
8086 radeon_ib_pool_fini(rdev);
8087 radeon_vm_manager_fini(rdev);
8088 radeon_irq_kms_fini(rdev);
8089 cik_pcie_gart_fini(rdev);
8090 rdev->accel_working = false;
8093 /* Don't start up if the MC ucode is missing.
8094 * The default clocks and voltages before the MC ucode
8095 * is loaded are not suffient for advanced operations.
8097 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
8098 DRM_ERROR("radeon: MC ucode required for NI+.\n");
8106 * cik_fini - asic specific driver and hw fini
8108 * @rdev: radeon_device pointer
8110 * Tear down the asic specific driver variables and program the hw
8111 * to an idle state (CIK).
8112 * Called at driver unload.
8114 void cik_fini(struct radeon_device *rdev)
8116 radeon_pm_fini(rdev);
8118 cik_sdma_fini(rdev);
8122 sumo_rlc_fini(rdev);
8124 radeon_wb_fini(rdev);
8125 radeon_vm_manager_fini(rdev);
8126 radeon_ib_pool_fini(rdev);
8127 radeon_irq_kms_fini(rdev);
8128 uvd_v1_0_fini(rdev);
8129 radeon_uvd_fini(rdev);
8130 cik_pcie_gart_fini(rdev);
8131 r600_vram_scratch_fini(rdev);
8132 radeon_gem_fini(rdev);
8133 radeon_fence_driver_fini(rdev);
8134 radeon_bo_fini(rdev);
8135 radeon_atombios_fini(rdev);
8140 void dce8_program_fmt(struct drm_encoder *encoder)
8142 struct drm_device *dev = encoder->dev;
8143 struct radeon_device *rdev = dev->dev_private;
8144 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
8146 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
8149 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
8152 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
8153 bpc = radeon_get_monitor_bpc(connector);
8154 dither = radeon_connector->dither;
8157 /* LVDS/eDP FMT is set up by atom */
8158 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
8161 /* not needed for analog */
8162 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
8163 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
8171 if (dither == RADEON_FMT_DITHER_ENABLE)
8172 /* XXX sort out optimal dither settings */
8173 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8174 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
8176 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
8179 if (dither == RADEON_FMT_DITHER_ENABLE)
8180 /* XXX sort out optimal dither settings */
8181 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8182 FMT_RGB_RANDOM_ENABLE |
8183 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
8185 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
8188 if (dither == RADEON_FMT_DITHER_ENABLE)
8189 /* XXX sort out optimal dither settings */
8190 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8191 FMT_RGB_RANDOM_ENABLE |
8192 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
8194 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
8201 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8204 /* display watermark setup */
8206 * dce8_line_buffer_adjust - Set up the line buffer
8208 * @rdev: radeon_device pointer
8209 * @radeon_crtc: the selected display controller
8210 * @mode: the current display mode on the selected display
8213 * Setup up the line buffer allocation for
8214 * the selected display controller (CIK).
8215 * Returns the line buffer size in pixels.
8217 static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
8218 struct radeon_crtc *radeon_crtc,
8219 struct drm_display_mode *mode)
8221 u32 tmp, buffer_alloc, i;
8222 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
8225 * There are 6 line buffers, one for each display controllers.
8226 * There are 3 partitions per LB. Select the number of partitions
8227 * to enable based on the display width. For display widths larger
8228 * than 4096, you need use to use 2 display controllers and combine
8229 * them using the stereo blender.
8231 if (radeon_crtc->base.enabled && mode) {
8232 if (mode->crtc_hdisplay < 1920) {
8235 } else if (mode->crtc_hdisplay < 2560) {
8238 } else if (mode->crtc_hdisplay < 4096) {
8240 buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8242 DRM_DEBUG_KMS("Mode too big for LB!\n");
8244 buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8251 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
8252 LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
8254 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8255 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
8256 for (i = 0; i < rdev->usec_timeout; i++) {
8257 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
8258 DMIF_BUFFERS_ALLOCATED_COMPLETED)
8263 if (radeon_crtc->base.enabled && mode) {
8275 /* controller not enabled, so no lb used */
8280 * cik_get_number_of_dram_channels - get the number of dram channels
8282 * @rdev: radeon_device pointer
8284 * Look up the number of video ram channels (CIK).
8285 * Used for display watermark bandwidth calculations
8286 * Returns the number of dram channels
8288 static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
8290 u32 tmp = RREG32(MC_SHARED_CHMAP);
8292 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
8315 struct dce8_wm_params {
8316 u32 dram_channels; /* number of dram channels */
8317 u32 yclk; /* bandwidth per dram data pin in kHz */
8318 u32 sclk; /* engine clock in kHz */
8319 u32 disp_clk; /* display clock in kHz */
8320 u32 src_width; /* viewport width */
8321 u32 active_time; /* active display time in ns */
8322 u32 blank_time; /* blank time in ns */
8323 bool interlaced; /* mode is interlaced */
8324 fixed20_12 vsc; /* vertical scale ratio */
8325 u32 num_heads; /* number of active crtcs */
8326 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
8327 u32 lb_size; /* line buffer allocated to pipe */
8328 u32 vtaps; /* vertical scaler taps */
8332 * dce8_dram_bandwidth - get the dram bandwidth
8334 * @wm: watermark calculation data
8336 * Calculate the raw dram bandwidth (CIK).
8337 * Used for display watermark bandwidth calculations
8338 * Returns the dram bandwidth in MBytes/s
8340 static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
8342 /* Calculate raw DRAM Bandwidth */
8343 fixed20_12 dram_efficiency; /* 0.7 */
8344 fixed20_12 yclk, dram_channels, bandwidth;
8347 a.full = dfixed_const(1000);
8348 yclk.full = dfixed_const(wm->yclk);
8349 yclk.full = dfixed_div(yclk, a);
8350 dram_channels.full = dfixed_const(wm->dram_channels * 4);
8351 a.full = dfixed_const(10);
8352 dram_efficiency.full = dfixed_const(7);
8353 dram_efficiency.full = dfixed_div(dram_efficiency, a);
8354 bandwidth.full = dfixed_mul(dram_channels, yclk);
8355 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
8357 return dfixed_trunc(bandwidth);
8361 * dce8_dram_bandwidth_for_display - get the dram bandwidth for display
8363 * @wm: watermark calculation data
8365 * Calculate the dram bandwidth used for display (CIK).
8366 * Used for display watermark bandwidth calculations
8367 * Returns the dram bandwidth for display in MBytes/s
8369 static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
8371 /* Calculate DRAM Bandwidth and the part allocated to display. */
8372 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
8373 fixed20_12 yclk, dram_channels, bandwidth;
8376 a.full = dfixed_const(1000);
8377 yclk.full = dfixed_const(wm->yclk);
8378 yclk.full = dfixed_div(yclk, a);
8379 dram_channels.full = dfixed_const(wm->dram_channels * 4);
8380 a.full = dfixed_const(10);
8381 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
8382 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
8383 bandwidth.full = dfixed_mul(dram_channels, yclk);
8384 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
8386 return dfixed_trunc(bandwidth);
8390 * dce8_data_return_bandwidth - get the data return bandwidth
8392 * @wm: watermark calculation data
8394 * Calculate the data return bandwidth used for display (CIK).
8395 * Used for display watermark bandwidth calculations
8396 * Returns the data return bandwidth in MBytes/s
8398 static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
8400 /* Calculate the display Data return Bandwidth */
8401 fixed20_12 return_efficiency; /* 0.8 */
8402 fixed20_12 sclk, bandwidth;
8405 a.full = dfixed_const(1000);
8406 sclk.full = dfixed_const(wm->sclk);
8407 sclk.full = dfixed_div(sclk, a);
8408 a.full = dfixed_const(10);
8409 return_efficiency.full = dfixed_const(8);
8410 return_efficiency.full = dfixed_div(return_efficiency, a);
8411 a.full = dfixed_const(32);
8412 bandwidth.full = dfixed_mul(a, sclk);
8413 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
8415 return dfixed_trunc(bandwidth);
8419 * dce8_dmif_request_bandwidth - get the dmif bandwidth
8421 * @wm: watermark calculation data
8423 * Calculate the dmif bandwidth used for display (CIK).
8424 * Used for display watermark bandwidth calculations
8425 * Returns the dmif bandwidth in MBytes/s
8427 static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
8429 /* Calculate the DMIF Request Bandwidth */
8430 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
8431 fixed20_12 disp_clk, bandwidth;
8434 a.full = dfixed_const(1000);
8435 disp_clk.full = dfixed_const(wm->disp_clk);
8436 disp_clk.full = dfixed_div(disp_clk, a);
8437 a.full = dfixed_const(32);
8438 b.full = dfixed_mul(a, disp_clk);
8440 a.full = dfixed_const(10);
8441 disp_clk_request_efficiency.full = dfixed_const(8);
8442 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
8444 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
8446 return dfixed_trunc(bandwidth);
8450 * dce8_available_bandwidth - get the min available bandwidth
8452 * @wm: watermark calculation data
8454 * Calculate the min available bandwidth used for display (CIK).
8455 * Used for display watermark bandwidth calculations
8456 * Returns the min available bandwidth in MBytes/s
8458 static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
8460 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
8461 u32 dram_bandwidth = dce8_dram_bandwidth(wm);
8462 u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
8463 u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
8465 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
8469 * dce8_average_bandwidth - get the average available bandwidth
8471 * @wm: watermark calculation data
8473 * Calculate the average available bandwidth used for display (CIK).
8474 * Used for display watermark bandwidth calculations
8475 * Returns the average available bandwidth in MBytes/s
8477 static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
8479 /* Calculate the display mode Average Bandwidth
8480 * DisplayMode should contain the source and destination dimensions,
8484 fixed20_12 line_time;
8485 fixed20_12 src_width;
8486 fixed20_12 bandwidth;
8489 a.full = dfixed_const(1000);
8490 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
8491 line_time.full = dfixed_div(line_time, a);
8492 bpp.full = dfixed_const(wm->bytes_per_pixel);
8493 src_width.full = dfixed_const(wm->src_width);
8494 bandwidth.full = dfixed_mul(src_width, bpp);
8495 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
8496 bandwidth.full = dfixed_div(bandwidth, line_time);
8498 return dfixed_trunc(bandwidth);
8502 * dce8_latency_watermark - get the latency watermark
8504 * @wm: watermark calculation data
8506 * Calculate the latency watermark (CIK).
8507 * Used for display watermark bandwidth calculations
8508 * Returns the latency watermark in ns
8510 static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
8512 /* First calculate the latency in ns */
8513 u32 mc_latency = 2000; /* 2000 ns. */
8514 u32 available_bandwidth = dce8_available_bandwidth(wm);
8515 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
8516 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
8517 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
8518 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
8519 (wm->num_heads * cursor_line_pair_return_time);
8520 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
8521 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
8522 u32 tmp, dmif_size = 12288;
8525 if (wm->num_heads == 0)
8528 a.full = dfixed_const(2);
8529 b.full = dfixed_const(1);
8530 if ((wm->vsc.full > a.full) ||
8531 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
8533 ((wm->vsc.full >= a.full) && wm->interlaced))
8534 max_src_lines_per_dst_line = 4;
8536 max_src_lines_per_dst_line = 2;
8538 a.full = dfixed_const(available_bandwidth);
8539 b.full = dfixed_const(wm->num_heads);
8540 a.full = dfixed_div(a, b);
8542 b.full = dfixed_const(mc_latency + 512);
8543 c.full = dfixed_const(wm->disp_clk);
8544 b.full = dfixed_div(b, c);
8546 c.full = dfixed_const(dmif_size);
8547 b.full = dfixed_div(c, b);
8549 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
8551 b.full = dfixed_const(1000);
8552 c.full = dfixed_const(wm->disp_clk);
8553 b.full = dfixed_div(c, b);
8554 c.full = dfixed_const(wm->bytes_per_pixel);
8555 b.full = dfixed_mul(b, c);
8557 lb_fill_bw = min(tmp, dfixed_trunc(b));
8559 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
8560 b.full = dfixed_const(1000);
8561 c.full = dfixed_const(lb_fill_bw);
8562 b.full = dfixed_div(c, b);
8563 a.full = dfixed_div(a, b);
8564 line_fill_time = dfixed_trunc(a);
8566 if (line_fill_time < wm->active_time)
8569 return latency + (line_fill_time - wm->active_time);
8574 * dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
8575 * average and available dram bandwidth
8577 * @wm: watermark calculation data
8579 * Check if the display average bandwidth fits in the display
8580 * dram bandwidth (CIK).
8581 * Used for display watermark bandwidth calculations
8582 * Returns true if the display fits, false if not.
8584 static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
8586 if (dce8_average_bandwidth(wm) <=
8587 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
8594 * dce8_average_bandwidth_vs_available_bandwidth - check
8595 * average and available bandwidth
8597 * @wm: watermark calculation data
8599 * Check if the display average bandwidth fits in the display
8600 * available bandwidth (CIK).
8601 * Used for display watermark bandwidth calculations
8602 * Returns true if the display fits, false if not.
8604 static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
8606 if (dce8_average_bandwidth(wm) <=
8607 (dce8_available_bandwidth(wm) / wm->num_heads))
8614 * dce8_check_latency_hiding - check latency hiding
8616 * @wm: watermark calculation data
8618 * Check latency hiding (CIK).
8619 * Used for display watermark bandwidth calculations
8620 * Returns true if the display fits, false if not.
8622 static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
8624 u32 lb_partitions = wm->lb_size / wm->src_width;
8625 u32 line_time = wm->active_time + wm->blank_time;
8626 u32 latency_tolerant_lines;
8630 a.full = dfixed_const(1);
8631 if (wm->vsc.full > a.full)
8632 latency_tolerant_lines = 1;
8634 if (lb_partitions <= (wm->vtaps + 1))
8635 latency_tolerant_lines = 1;
8637 latency_tolerant_lines = 2;
8640 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
8642 if (dce8_latency_watermark(wm) <= latency_hiding)
8649 * dce8_program_watermarks - program display watermarks
8651 * @rdev: radeon_device pointer
8652 * @radeon_crtc: the selected display controller
8653 * @lb_size: line buffer size
8654 * @num_heads: number of display controllers in use
8656 * Calculate and program the display watermarks for the
8657 * selected display controller (CIK).
8659 static void dce8_program_watermarks(struct radeon_device *rdev,
8660 struct radeon_crtc *radeon_crtc,
8661 u32 lb_size, u32 num_heads)
8663 struct drm_display_mode *mode = &radeon_crtc->base.mode;
8664 struct dce8_wm_params wm_low, wm_high;
8667 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8670 if (radeon_crtc->base.enabled && num_heads && mode) {
8671 pixel_period = 1000000 / (u32)mode->clock;
8672 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
8674 /* watermark for high clocks */
8675 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
8676 rdev->pm.dpm_enabled) {
8678 radeon_dpm_get_mclk(rdev, false) * 10;
8680 radeon_dpm_get_sclk(rdev, false) * 10;
8682 wm_high.yclk = rdev->pm.current_mclk * 10;
8683 wm_high.sclk = rdev->pm.current_sclk * 10;
8686 wm_high.disp_clk = mode->clock;
8687 wm_high.src_width = mode->crtc_hdisplay;
8688 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
8689 wm_high.blank_time = line_time - wm_high.active_time;
8690 wm_high.interlaced = false;
8691 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
8692 wm_high.interlaced = true;
8693 wm_high.vsc = radeon_crtc->vsc;
8695 if (radeon_crtc->rmx_type != RMX_OFF)
8697 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
8698 wm_high.lb_size = lb_size;
8699 wm_high.dram_channels = cik_get_number_of_dram_channels(rdev);
8700 wm_high.num_heads = num_heads;
8702 /* set for high clocks */
8703 latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);
8705 /* possibly force display priority to high */
8706 /* should really do this at mode validation time... */
8707 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
8708 !dce8_average_bandwidth_vs_available_bandwidth(&wm_high) ||
8709 !dce8_check_latency_hiding(&wm_high) ||
8710 (rdev->disp_priority == 2)) {
8711 DRM_DEBUG_KMS("force priority to high\n");
8714 /* watermark for low clocks */
8715 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
8716 rdev->pm.dpm_enabled) {
8718 radeon_dpm_get_mclk(rdev, true) * 10;
8720 radeon_dpm_get_sclk(rdev, true) * 10;
8722 wm_low.yclk = rdev->pm.current_mclk * 10;
8723 wm_low.sclk = rdev->pm.current_sclk * 10;
8726 wm_low.disp_clk = mode->clock;
8727 wm_low.src_width = mode->crtc_hdisplay;
8728 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
8729 wm_low.blank_time = line_time - wm_low.active_time;
8730 wm_low.interlaced = false;
8731 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
8732 wm_low.interlaced = true;
8733 wm_low.vsc = radeon_crtc->vsc;
8735 if (radeon_crtc->rmx_type != RMX_OFF)
8737 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
8738 wm_low.lb_size = lb_size;
8739 wm_low.dram_channels = cik_get_number_of_dram_channels(rdev);
8740 wm_low.num_heads = num_heads;
8742 /* set for low clocks */
8743 latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);
8745 /* possibly force display priority to high */
8746 /* should really do this at mode validation time... */
8747 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
8748 !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) ||
8749 !dce8_check_latency_hiding(&wm_low) ||
8750 (rdev->disp_priority == 2)) {
8751 DRM_DEBUG_KMS("force priority to high\n");
8756 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
8758 tmp &= ~LATENCY_WATERMARK_MASK(3);
8759 tmp |= LATENCY_WATERMARK_MASK(1);
8760 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
8761 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
8762 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
8763 LATENCY_HIGH_WATERMARK(line_time)));
8765 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
8766 tmp &= ~LATENCY_WATERMARK_MASK(3);
8767 tmp |= LATENCY_WATERMARK_MASK(2);
8768 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
8769 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
8770 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
8771 LATENCY_HIGH_WATERMARK(line_time)));
8772 /* restore original selection */
8773 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
8775 /* save values for DPM */
8776 radeon_crtc->line_time = line_time;
8777 radeon_crtc->wm_high = latency_watermark_a;
8778 radeon_crtc->wm_low = latency_watermark_b;
8782 * dce8_bandwidth_update - program display watermarks
8784 * @rdev: radeon_device pointer
8786 * Calculate and program the display watermarks and line
8787 * buffer allocation (CIK).
8789 void dce8_bandwidth_update(struct radeon_device *rdev)
8791 struct drm_display_mode *mode = NULL;
8792 u32 num_heads = 0, lb_size;
8795 radeon_update_display_priority(rdev);
8797 for (i = 0; i < rdev->num_crtc; i++) {
8798 if (rdev->mode_info.crtcs[i]->base.enabled)
8801 for (i = 0; i < rdev->num_crtc; i++) {
8802 mode = &rdev->mode_info.crtcs[i]->base.mode;
8803 lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
8804 dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
8809 * cik_get_gpu_clock_counter - return GPU clock counter snapshot
8811 * @rdev: radeon_device pointer
8813 * Fetches a GPU clock counter snapshot (SI).
8814 * Returns the 64 bit clock counter snapshot.
8816 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
8820 mutex_lock(&rdev->gpu_clock_mutex);
8821 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
8822 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
8823 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
8824 mutex_unlock(&rdev->gpu_clock_mutex);
8828 static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
8829 u32 cntl_reg, u32 status_reg)
8832 struct atom_clock_dividers dividers;
8835 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
8836 clock, false, ÷rs);
8840 tmp = RREG32_SMC(cntl_reg);
8841 tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
8842 tmp |= dividers.post_divider;
8843 WREG32_SMC(cntl_reg, tmp);
8845 for (i = 0; i < 100; i++) {
8846 if (RREG32_SMC(status_reg) & DCLK_STATUS)
8856 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
8860 r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
8864 r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
8868 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
8870 struct pci_dev *root = rdev->pdev->bus->self;
8871 int bridge_pos, gpu_pos;
8872 u32 speed_cntl, mask, current_data_rate;
8876 if (radeon_pcie_gen2 == 0)
8879 if (rdev->flags & RADEON_IS_IGP)
8882 if (!(rdev->flags & RADEON_IS_PCIE))
8885 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
8889 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
8892 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
8893 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
8894 LC_CURRENT_DATA_RATE_SHIFT;
8895 if (mask & DRM_PCIE_SPEED_80) {
8896 if (current_data_rate == 2) {
8897 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
8900 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
8901 } else if (mask & DRM_PCIE_SPEED_50) {
8902 if (current_data_rate == 1) {
8903 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
8906 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
8909 bridge_pos = pci_pcie_cap(root);
8913 gpu_pos = pci_pcie_cap(rdev->pdev);
8917 if (mask & DRM_PCIE_SPEED_80) {
8918 /* re-try equalization if gen3 is not already enabled */
8919 if (current_data_rate != 2) {
8920 u16 bridge_cfg, gpu_cfg;
8921 u16 bridge_cfg2, gpu_cfg2;
8922 u32 max_lw, current_lw, tmp;
8924 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
8925 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
8927 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
8928 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
8930 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
8931 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
8933 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
8934 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
8935 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
8937 if (current_lw < max_lw) {
8938 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
8939 if (tmp & LC_RENEGOTIATION_SUPPORT) {
8940 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
8941 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
8942 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
8943 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
8947 for (i = 0; i < 10; i++) {
8949 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
8950 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
8953 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
8954 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
8956 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
8957 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
8959 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8960 tmp |= LC_SET_QUIESCE;
8961 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8963 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8965 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8970 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
8971 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
8972 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
8973 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
8975 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
8976 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
8977 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
8978 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
8981 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
8982 tmp16 &= ~((1 << 4) | (7 << 9));
8983 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
8984 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
8986 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
8987 tmp16 &= ~((1 << 4) | (7 << 9));
8988 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
8989 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
8991 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8992 tmp &= ~LC_SET_QUIESCE;
8993 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8998 /* set the link speed */
8999 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
9000 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
9001 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9003 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9005 if (mask & DRM_PCIE_SPEED_80)
9006 tmp16 |= 3; /* gen3 */
9007 else if (mask & DRM_PCIE_SPEED_50)
9008 tmp16 |= 2; /* gen2 */
9010 tmp16 |= 1; /* gen1 */
9011 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9013 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9014 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
9015 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9017 for (i = 0; i < rdev->usec_timeout; i++) {
9018 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9019 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
9025 static void cik_program_aspm(struct radeon_device *rdev)
9028 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
9029 bool disable_clkreq = false;
9031 if (radeon_aspm == 0)
9034 /* XXX double check IGPs */
9035 if (rdev->flags & RADEON_IS_IGP)
9038 if (!(rdev->flags & RADEON_IS_PCIE))
9041 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9042 data &= ~LC_XMIT_N_FTS_MASK;
9043 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
9045 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
9047 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
9048 data |= LC_GO_TO_RECOVERY;
9050 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
9052 orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
9053 data |= P_IGNORE_EDB_ERR;
9055 WREG32_PCIE_PORT(PCIE_P_CNTL, data);
9057 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9058 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
9059 data |= LC_PMI_TO_L1_DIS;
9061 data |= LC_L0S_INACTIVITY(7);
9064 data |= LC_L1_INACTIVITY(7);
9065 data &= ~LC_PMI_TO_L1_DIS;
9067 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9069 if (!disable_plloff_in_l1) {
9070 bool clk_req_support;
9072 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
9073 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9074 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9076 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
9078 orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
9079 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9080 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9082 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
9084 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
9085 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9086 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9088 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
9090 orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
9091 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9092 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9094 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
9096 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9097 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
9098 data |= LC_DYN_LANES_PWR_STATE(3);
9100 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
9102 if (!disable_clkreq) {
9103 struct pci_dev *root = rdev->pdev->bus->self;
9106 clk_req_support = false;
9107 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
9108 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
9109 clk_req_support = true;
9111 clk_req_support = false;
9114 if (clk_req_support) {
9115 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
9116 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
9118 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
9120 orig = data = RREG32_SMC(THM_CLK_CNTL);
9121 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
9122 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
9124 WREG32_SMC(THM_CLK_CNTL, data);
9126 orig = data = RREG32_SMC(MISC_CLK_CTRL);
9127 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
9128 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
9130 WREG32_SMC(MISC_CLK_CTRL, data);
9132 orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
9133 data &= ~BCLK_AS_XCLK;
9135 WREG32_SMC(CG_CLKPIN_CNTL, data);
9137 orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
9138 data &= ~FORCE_BIF_REFCLK_EN;
9140 WREG32_SMC(CG_CLKPIN_CNTL_2, data);
9142 orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
9143 data &= ~MPLL_CLKOUT_SEL_MASK;
9144 data |= MPLL_CLKOUT_SEL(4);
9146 WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
9151 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9154 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
9155 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
9157 WREG32_PCIE_PORT(PCIE_CNTL2, data);
9160 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9161 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
9162 data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9163 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
9164 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9165 data &= ~LC_L0S_INACTIVITY_MASK;
9167 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);