2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
43 /* get temperature in millidegrees */
44 u32 evergreen_get_temp(struct radeon_device *rdev)
46 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
52 else if ((temp >> 9) & 1)
55 actual_temp = (temp >> 1) & 0xff;
57 return actual_temp * 1000;
60 void evergreen_pm_misc(struct radeon_device *rdev)
62 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
76 void evergreen_pm_prepare(struct radeon_device *rdev)
78 struct drm_device *ddev = rdev->ddev;
79 struct drm_crtc *crtc;
80 struct radeon_crtc *radeon_crtc;
83 /* disable any active CRTCs */
84 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
85 radeon_crtc = to_radeon_crtc(crtc);
86 if (radeon_crtc->enabled) {
87 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
88 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
89 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
94 void evergreen_pm_finish(struct radeon_device *rdev)
96 struct drm_device *ddev = rdev->ddev;
97 struct drm_crtc *crtc;
98 struct radeon_crtc *radeon_crtc;
101 /* enable any active CRTCs */
102 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
103 radeon_crtc = to_radeon_crtc(crtc);
104 if (radeon_crtc->enabled) {
105 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
106 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
107 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
112 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
114 bool connected = false;
118 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
122 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
126 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
130 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
134 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
138 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
148 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
149 enum radeon_hpd_id hpd)
152 bool connected = evergreen_hpd_sense(rdev, hpd);
156 tmp = RREG32(DC_HPD1_INT_CONTROL);
158 tmp &= ~DC_HPDx_INT_POLARITY;
160 tmp |= DC_HPDx_INT_POLARITY;
161 WREG32(DC_HPD1_INT_CONTROL, tmp);
164 tmp = RREG32(DC_HPD2_INT_CONTROL);
166 tmp &= ~DC_HPDx_INT_POLARITY;
168 tmp |= DC_HPDx_INT_POLARITY;
169 WREG32(DC_HPD2_INT_CONTROL, tmp);
172 tmp = RREG32(DC_HPD3_INT_CONTROL);
174 tmp &= ~DC_HPDx_INT_POLARITY;
176 tmp |= DC_HPDx_INT_POLARITY;
177 WREG32(DC_HPD3_INT_CONTROL, tmp);
180 tmp = RREG32(DC_HPD4_INT_CONTROL);
182 tmp &= ~DC_HPDx_INT_POLARITY;
184 tmp |= DC_HPDx_INT_POLARITY;
185 WREG32(DC_HPD4_INT_CONTROL, tmp);
188 tmp = RREG32(DC_HPD5_INT_CONTROL);
190 tmp &= ~DC_HPDx_INT_POLARITY;
192 tmp |= DC_HPDx_INT_POLARITY;
193 WREG32(DC_HPD5_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HPD6_INT_CONTROL);
198 tmp &= ~DC_HPDx_INT_POLARITY;
200 tmp |= DC_HPDx_INT_POLARITY;
201 WREG32(DC_HPD6_INT_CONTROL, tmp);
208 void evergreen_hpd_init(struct radeon_device *rdev)
210 struct drm_device *dev = rdev->ddev;
211 struct drm_connector *connector;
212 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
213 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
215 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
216 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
217 switch (radeon_connector->hpd.hpd) {
219 WREG32(DC_HPD1_CONTROL, tmp);
220 rdev->irq.hpd[0] = true;
223 WREG32(DC_HPD2_CONTROL, tmp);
224 rdev->irq.hpd[1] = true;
227 WREG32(DC_HPD3_CONTROL, tmp);
228 rdev->irq.hpd[2] = true;
231 WREG32(DC_HPD4_CONTROL, tmp);
232 rdev->irq.hpd[3] = true;
235 WREG32(DC_HPD5_CONTROL, tmp);
236 rdev->irq.hpd[4] = true;
239 WREG32(DC_HPD6_CONTROL, tmp);
240 rdev->irq.hpd[5] = true;
246 if (rdev->irq.installed)
247 evergreen_irq_set(rdev);
250 void evergreen_hpd_fini(struct radeon_device *rdev)
252 struct drm_device *dev = rdev->ddev;
253 struct drm_connector *connector;
255 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
256 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
257 switch (radeon_connector->hpd.hpd) {
259 WREG32(DC_HPD1_CONTROL, 0);
260 rdev->irq.hpd[0] = false;
263 WREG32(DC_HPD2_CONTROL, 0);
264 rdev->irq.hpd[1] = false;
267 WREG32(DC_HPD3_CONTROL, 0);
268 rdev->irq.hpd[2] = false;
271 WREG32(DC_HPD4_CONTROL, 0);
272 rdev->irq.hpd[3] = false;
275 WREG32(DC_HPD5_CONTROL, 0);
276 rdev->irq.hpd[4] = false;
279 WREG32(DC_HPD6_CONTROL, 0);
280 rdev->irq.hpd[5] = false;
288 /* watermark setup */
290 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
291 struct radeon_crtc *radeon_crtc,
292 struct drm_display_mode *mode,
293 struct drm_display_mode *other_mode)
298 * There are 3 line buffers, each one shared by 2 display controllers.
299 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
300 * the display controllers. The paritioning is done via one of four
301 * preset allocations specified in bits 2:0:
302 * first display controller
303 * 0 - first half of lb (3840 * 2)
304 * 1 - first 3/4 of lb (5760 * 2)
305 * 2 - whole lb (7680 * 2)
306 * 3 - first 1/4 of lb (1920 * 2)
307 * second display controller
308 * 4 - second half of lb (3840 * 2)
309 * 5 - second 3/4 of lb (5760 * 2)
310 * 6 - whole lb (7680 * 2)
311 * 7 - last 1/4 of lb (1920 * 2)
313 if (mode && other_mode) {
314 if (mode->hdisplay > other_mode->hdisplay) {
315 if (mode->hdisplay > 2560)
319 } else if (other_mode->hdisplay > mode->hdisplay) {
320 if (other_mode->hdisplay > 2560)
331 /* second controller of the pair uses second half of the lb */
332 if (radeon_crtc->crtc_id % 2)
334 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
353 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
355 u32 tmp = RREG32(MC_SHARED_CHMAP);
357 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
370 struct evergreen_wm_params {
371 u32 dram_channels; /* number of dram channels */
372 u32 yclk; /* bandwidth per dram data pin in kHz */
373 u32 sclk; /* engine clock in kHz */
374 u32 disp_clk; /* display clock in kHz */
375 u32 src_width; /* viewport width */
376 u32 active_time; /* active display time in ns */
377 u32 blank_time; /* blank time in ns */
378 bool interlaced; /* mode is interlaced */
379 fixed20_12 vsc; /* vertical scale ratio */
380 u32 num_heads; /* number of active crtcs */
381 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
382 u32 lb_size; /* line buffer allocated to pipe */
383 u32 vtaps; /* vertical scaler taps */
386 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
388 /* Calculate DRAM Bandwidth and the part allocated to display. */
389 fixed20_12 dram_efficiency; /* 0.7 */
390 fixed20_12 yclk, dram_channels, bandwidth;
393 a.full = dfixed_const(1000);
394 yclk.full = dfixed_const(wm->yclk);
395 yclk.full = dfixed_div(yclk, a);
396 dram_channels.full = dfixed_const(wm->dram_channels * 4);
397 a.full = dfixed_const(10);
398 dram_efficiency.full = dfixed_const(7);
399 dram_efficiency.full = dfixed_div(dram_efficiency, a);
400 bandwidth.full = dfixed_mul(dram_channels, yclk);
401 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
403 return dfixed_trunc(bandwidth);
406 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
408 /* Calculate DRAM Bandwidth and the part allocated to display. */
409 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
410 fixed20_12 yclk, dram_channels, bandwidth;
413 a.full = dfixed_const(1000);
414 yclk.full = dfixed_const(wm->yclk);
415 yclk.full = dfixed_div(yclk, a);
416 dram_channels.full = dfixed_const(wm->dram_channels * 4);
417 a.full = dfixed_const(10);
418 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
419 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
420 bandwidth.full = dfixed_mul(dram_channels, yclk);
421 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
423 return dfixed_trunc(bandwidth);
426 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
428 /* Calculate the display Data return Bandwidth */
429 fixed20_12 return_efficiency; /* 0.8 */
430 fixed20_12 sclk, bandwidth;
433 a.full = dfixed_const(1000);
434 sclk.full = dfixed_const(wm->sclk);
435 sclk.full = dfixed_div(sclk, a);
436 a.full = dfixed_const(10);
437 return_efficiency.full = dfixed_const(8);
438 return_efficiency.full = dfixed_div(return_efficiency, a);
439 a.full = dfixed_const(32);
440 bandwidth.full = dfixed_mul(a, sclk);
441 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
443 return dfixed_trunc(bandwidth);
446 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
448 /* Calculate the DMIF Request Bandwidth */
449 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
450 fixed20_12 disp_clk, bandwidth;
453 a.full = dfixed_const(1000);
454 disp_clk.full = dfixed_const(wm->disp_clk);
455 disp_clk.full = dfixed_div(disp_clk, a);
456 a.full = dfixed_const(10);
457 disp_clk_request_efficiency.full = dfixed_const(8);
458 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
459 a.full = dfixed_const(32);
460 bandwidth.full = dfixed_mul(a, disp_clk);
461 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
463 return dfixed_trunc(bandwidth);
466 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
468 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
469 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
470 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
471 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
473 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
476 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
478 /* Calculate the display mode Average Bandwidth
479 * DisplayMode should contain the source and destination dimensions,
483 fixed20_12 line_time;
484 fixed20_12 src_width;
485 fixed20_12 bandwidth;
488 a.full = dfixed_const(1000);
489 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
490 line_time.full = dfixed_div(line_time, a);
491 bpp.full = dfixed_const(wm->bytes_per_pixel);
492 src_width.full = dfixed_const(wm->src_width);
493 bandwidth.full = dfixed_mul(src_width, bpp);
494 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
495 bandwidth.full = dfixed_div(bandwidth, line_time);
497 return dfixed_trunc(bandwidth);
500 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
502 /* First calcualte the latency in ns */
503 u32 mc_latency = 2000; /* 2000 ns. */
504 u32 available_bandwidth = evergreen_available_bandwidth(wm);
505 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
506 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
507 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
508 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
509 (wm->num_heads * cursor_line_pair_return_time);
510 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
511 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
514 if (wm->num_heads == 0)
517 a.full = dfixed_const(2);
518 b.full = dfixed_const(1);
519 if ((wm->vsc.full > a.full) ||
520 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
522 ((wm->vsc.full >= a.full) && wm->interlaced))
523 max_src_lines_per_dst_line = 4;
525 max_src_lines_per_dst_line = 2;
527 a.full = dfixed_const(available_bandwidth);
528 b.full = dfixed_const(wm->num_heads);
529 a.full = dfixed_div(a, b);
531 b.full = dfixed_const(1000);
532 c.full = dfixed_const(wm->disp_clk);
533 b.full = dfixed_div(c, b);
534 c.full = dfixed_const(wm->bytes_per_pixel);
535 b.full = dfixed_mul(b, c);
537 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
539 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
540 b.full = dfixed_const(1000);
541 c.full = dfixed_const(lb_fill_bw);
542 b.full = dfixed_div(c, b);
543 a.full = dfixed_div(a, b);
544 line_fill_time = dfixed_trunc(a);
546 if (line_fill_time < wm->active_time)
549 return latency + (line_fill_time - wm->active_time);
553 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
555 if (evergreen_average_bandwidth(wm) <=
556 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
562 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
564 if (evergreen_average_bandwidth(wm) <=
565 (evergreen_available_bandwidth(wm) / wm->num_heads))
571 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
573 u32 lb_partitions = wm->lb_size / wm->src_width;
574 u32 line_time = wm->active_time + wm->blank_time;
575 u32 latency_tolerant_lines;
579 a.full = dfixed_const(1);
580 if (wm->vsc.full > a.full)
581 latency_tolerant_lines = 1;
583 if (lb_partitions <= (wm->vtaps + 1))
584 latency_tolerant_lines = 1;
586 latency_tolerant_lines = 2;
589 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
591 if (evergreen_latency_watermark(wm) <= latency_hiding)
597 static void evergreen_program_watermarks(struct radeon_device *rdev,
598 struct radeon_crtc *radeon_crtc,
599 u32 lb_size, u32 num_heads)
601 struct drm_display_mode *mode = &radeon_crtc->base.mode;
602 struct evergreen_wm_params wm;
605 u32 latency_watermark_a = 0, latency_watermark_b = 0;
606 u32 priority_a_mark = 0, priority_b_mark = 0;
607 u32 priority_a_cnt = PRIORITY_OFF;
608 u32 priority_b_cnt = PRIORITY_OFF;
609 u32 pipe_offset = radeon_crtc->crtc_id * 16;
610 u32 tmp, arb_control3;
613 if (radeon_crtc->base.enabled && num_heads && mode) {
614 pixel_period = 1000000 / (u32)mode->clock;
615 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
619 wm.yclk = rdev->pm.current_mclk * 10;
620 wm.sclk = rdev->pm.current_sclk * 10;
621 wm.disp_clk = mode->clock;
622 wm.src_width = mode->crtc_hdisplay;
623 wm.active_time = mode->crtc_hdisplay * pixel_period;
624 wm.blank_time = line_time - wm.active_time;
625 wm.interlaced = false;
626 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
627 wm.interlaced = true;
628 wm.vsc = radeon_crtc->vsc;
630 if (radeon_crtc->rmx_type != RMX_OFF)
632 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
633 wm.lb_size = lb_size;
634 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
635 wm.num_heads = num_heads;
637 /* set for high clocks */
638 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
639 /* set for low clocks */
640 /* wm.yclk = low clk; wm.sclk = low clk */
641 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
643 /* possibly force display priority to high */
644 /* should really do this at mode validation time... */
645 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
646 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
647 !evergreen_check_latency_hiding(&wm) ||
648 (rdev->disp_priority == 2)) {
649 DRM_INFO("force priority to high\n");
650 priority_a_cnt |= PRIORITY_ALWAYS_ON;
651 priority_b_cnt |= PRIORITY_ALWAYS_ON;
654 a.full = dfixed_const(1000);
655 b.full = dfixed_const(mode->clock);
656 b.full = dfixed_div(b, a);
657 c.full = dfixed_const(latency_watermark_a);
658 c.full = dfixed_mul(c, b);
659 c.full = dfixed_mul(c, radeon_crtc->hsc);
660 c.full = dfixed_div(c, a);
661 a.full = dfixed_const(16);
662 c.full = dfixed_div(c, a);
663 priority_a_mark = dfixed_trunc(c);
664 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
666 a.full = dfixed_const(1000);
667 b.full = dfixed_const(mode->clock);
668 b.full = dfixed_div(b, a);
669 c.full = dfixed_const(latency_watermark_b);
670 c.full = dfixed_mul(c, b);
671 c.full = dfixed_mul(c, radeon_crtc->hsc);
672 c.full = dfixed_div(c, a);
673 a.full = dfixed_const(16);
674 c.full = dfixed_div(c, a);
675 priority_b_mark = dfixed_trunc(c);
676 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
680 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
682 tmp &= ~LATENCY_WATERMARK_MASK(3);
683 tmp |= LATENCY_WATERMARK_MASK(1);
684 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
685 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
686 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
687 LATENCY_HIGH_WATERMARK(line_time)));
689 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
690 tmp &= ~LATENCY_WATERMARK_MASK(3);
691 tmp |= LATENCY_WATERMARK_MASK(2);
692 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
693 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
694 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
695 LATENCY_HIGH_WATERMARK(line_time)));
696 /* restore original selection */
697 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
699 /* write the priority marks */
700 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
701 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
705 void evergreen_bandwidth_update(struct radeon_device *rdev)
707 struct drm_display_mode *mode0 = NULL;
708 struct drm_display_mode *mode1 = NULL;
709 u32 num_heads = 0, lb_size;
712 radeon_update_display_priority(rdev);
714 for (i = 0; i < rdev->num_crtc; i++) {
715 if (rdev->mode_info.crtcs[i]->base.enabled)
718 for (i = 0; i < rdev->num_crtc; i += 2) {
719 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
720 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
721 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
722 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
723 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
724 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
728 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
733 for (i = 0; i < rdev->usec_timeout; i++) {
735 tmp = RREG32(SRBM_STATUS) & 0x1F00;
746 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
751 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
753 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
754 for (i = 0; i < rdev->usec_timeout; i++) {
756 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
757 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
759 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
769 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
774 if (rdev->gart.table.vram.robj == NULL) {
775 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
778 r = radeon_gart_table_vram_pin(rdev);
781 radeon_gart_restore(rdev);
783 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
784 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
785 EFFECTIVE_L2_QUEUE_SIZE(7));
786 WREG32(VM_L2_CNTL2, 0);
787 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
788 /* Setup TLB control */
789 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
790 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
791 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
792 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
793 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
794 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
795 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
796 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
797 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
798 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
799 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
800 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
801 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
802 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
803 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
804 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
805 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
806 (u32)(rdev->dummy_page.addr >> 12));
807 WREG32(VM_CONTEXT1_CNTL, 0);
809 evergreen_pcie_gart_tlb_flush(rdev);
810 rdev->gart.ready = true;
814 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
819 /* Disable all tables */
820 WREG32(VM_CONTEXT0_CNTL, 0);
821 WREG32(VM_CONTEXT1_CNTL, 0);
824 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
825 EFFECTIVE_L2_QUEUE_SIZE(7));
826 WREG32(VM_L2_CNTL2, 0);
827 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
828 /* Setup TLB control */
829 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
830 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
831 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
832 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
833 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
834 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
835 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
836 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
837 if (rdev->gart.table.vram.robj) {
838 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
839 if (likely(r == 0)) {
840 radeon_bo_kunmap(rdev->gart.table.vram.robj);
841 radeon_bo_unpin(rdev->gart.table.vram.robj);
842 radeon_bo_unreserve(rdev->gart.table.vram.robj);
847 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
849 evergreen_pcie_gart_disable(rdev);
850 radeon_gart_table_vram_free(rdev);
851 radeon_gart_fini(rdev);
855 void evergreen_agp_enable(struct radeon_device *rdev)
860 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
861 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
862 EFFECTIVE_L2_QUEUE_SIZE(7));
863 WREG32(VM_L2_CNTL2, 0);
864 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
865 /* Setup TLB control */
866 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
867 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
868 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
869 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
870 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
871 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
872 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
873 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
874 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
875 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
876 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
877 WREG32(VM_CONTEXT0_CNTL, 0);
878 WREG32(VM_CONTEXT1_CNTL, 0);
881 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
883 save->vga_control[0] = RREG32(D1VGA_CONTROL);
884 save->vga_control[1] = RREG32(D2VGA_CONTROL);
885 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
886 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
887 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
888 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
889 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
890 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
891 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
892 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
893 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
894 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
895 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
896 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
899 WREG32(VGA_RENDER_CONTROL, 0);
900 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
901 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
902 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
903 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
904 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
905 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
906 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
907 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
908 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
909 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
910 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
911 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
912 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
913 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
914 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
915 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
916 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
917 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
919 WREG32(D1VGA_CONTROL, 0);
920 WREG32(D2VGA_CONTROL, 0);
921 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
922 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
923 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
924 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
927 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
929 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
930 upper_32_bits(rdev->mc.vram_start));
931 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
932 upper_32_bits(rdev->mc.vram_start));
933 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
934 (u32)rdev->mc.vram_start);
935 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
936 (u32)rdev->mc.vram_start);
938 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
939 upper_32_bits(rdev->mc.vram_start));
940 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
941 upper_32_bits(rdev->mc.vram_start));
942 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
943 (u32)rdev->mc.vram_start);
944 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
945 (u32)rdev->mc.vram_start);
947 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
948 upper_32_bits(rdev->mc.vram_start));
949 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
950 upper_32_bits(rdev->mc.vram_start));
951 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
952 (u32)rdev->mc.vram_start);
953 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
954 (u32)rdev->mc.vram_start);
956 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
957 upper_32_bits(rdev->mc.vram_start));
958 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
959 upper_32_bits(rdev->mc.vram_start));
960 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
961 (u32)rdev->mc.vram_start);
962 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
963 (u32)rdev->mc.vram_start);
965 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
966 upper_32_bits(rdev->mc.vram_start));
967 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
968 upper_32_bits(rdev->mc.vram_start));
969 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
970 (u32)rdev->mc.vram_start);
971 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
972 (u32)rdev->mc.vram_start);
974 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
975 upper_32_bits(rdev->mc.vram_start));
976 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
977 upper_32_bits(rdev->mc.vram_start));
978 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
979 (u32)rdev->mc.vram_start);
980 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
981 (u32)rdev->mc.vram_start);
983 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
984 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
985 /* Unlock host access */
986 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
988 /* Restore video state */
989 WREG32(D1VGA_CONTROL, save->vga_control[0]);
990 WREG32(D2VGA_CONTROL, save->vga_control[1]);
991 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
992 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
993 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
994 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
995 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
996 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
997 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1000 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1001 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1002 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1003 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1004 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1005 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1016 static void evergreen_mc_program(struct radeon_device *rdev)
1018 struct evergreen_mc_save save;
1022 /* Initialize HDP */
1023 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1024 WREG32((0x2c14 + j), 0x00000000);
1025 WREG32((0x2c18 + j), 0x00000000);
1026 WREG32((0x2c1c + j), 0x00000000);
1027 WREG32((0x2c20 + j), 0x00000000);
1028 WREG32((0x2c24 + j), 0x00000000);
1030 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1032 evergreen_mc_stop(rdev, &save);
1033 if (evergreen_mc_wait_for_idle(rdev)) {
1034 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1036 /* Lockout access through VGA aperture*/
1037 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1038 /* Update configuration */
1039 if (rdev->flags & RADEON_IS_AGP) {
1040 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1041 /* VRAM before AGP */
1042 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1043 rdev->mc.vram_start >> 12);
1044 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1045 rdev->mc.gtt_end >> 12);
1047 /* VRAM after AGP */
1048 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1049 rdev->mc.gtt_start >> 12);
1050 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1051 rdev->mc.vram_end >> 12);
1054 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1055 rdev->mc.vram_start >> 12);
1056 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1057 rdev->mc.vram_end >> 12);
1059 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1060 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1061 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1062 WREG32(MC_VM_FB_LOCATION, tmp);
1063 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1064 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1065 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1066 if (rdev->flags & RADEON_IS_AGP) {
1067 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1068 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1069 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1071 WREG32(MC_VM_AGP_BASE, 0);
1072 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1073 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1075 if (evergreen_mc_wait_for_idle(rdev)) {
1076 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1078 evergreen_mc_resume(rdev, &save);
1079 /* we need to own VRAM, so turn off the VGA renderer here
1080 * to stop it overwriting our objects */
1081 rv515_vga_render_disable(rdev);
1088 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1090 const __be32 *fw_data;
1093 if (!rdev->me_fw || !rdev->pfp_fw)
1097 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1099 fw_data = (const __be32 *)rdev->pfp_fw->data;
1100 WREG32(CP_PFP_UCODE_ADDR, 0);
1101 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1102 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1103 WREG32(CP_PFP_UCODE_ADDR, 0);
1105 fw_data = (const __be32 *)rdev->me_fw->data;
1106 WREG32(CP_ME_RAM_WADDR, 0);
1107 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1108 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1110 WREG32(CP_PFP_UCODE_ADDR, 0);
1111 WREG32(CP_ME_RAM_WADDR, 0);
1112 WREG32(CP_ME_RAM_RADDR, 0);
1116 static int evergreen_cp_start(struct radeon_device *rdev)
1121 r = radeon_ring_lock(rdev, 7);
1123 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1126 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1127 radeon_ring_write(rdev, 0x1);
1128 radeon_ring_write(rdev, 0x0);
1129 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1130 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1131 radeon_ring_write(rdev, 0);
1132 radeon_ring_write(rdev, 0);
1133 radeon_ring_unlock_commit(rdev);
1136 WREG32(CP_ME_CNTL, cp_me);
1138 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1140 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1144 /* setup clear context state */
1145 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1146 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1148 for (i = 0; i < evergreen_default_size; i++)
1149 radeon_ring_write(rdev, evergreen_default_state[i]);
1151 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1152 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1154 /* set clear context state */
1155 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1156 radeon_ring_write(rdev, 0);
1158 /* SQ_VTX_BASE_VTX_LOC */
1159 radeon_ring_write(rdev, 0xc0026f00);
1160 radeon_ring_write(rdev, 0x00000000);
1161 radeon_ring_write(rdev, 0x00000000);
1162 radeon_ring_write(rdev, 0x00000000);
1165 radeon_ring_write(rdev, 0xc0036f00);
1166 radeon_ring_write(rdev, 0x00000bc4);
1167 radeon_ring_write(rdev, 0xffffffff);
1168 radeon_ring_write(rdev, 0xffffffff);
1169 radeon_ring_write(rdev, 0xffffffff);
1171 radeon_ring_write(rdev, 0xc0026900);
1172 radeon_ring_write(rdev, 0x00000316);
1173 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1174 radeon_ring_write(rdev, 0x00000010); /* */
1176 radeon_ring_unlock_commit(rdev);
1181 int evergreen_cp_resume(struct radeon_device *rdev)
1187 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1188 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1193 RREG32(GRBM_SOFT_RESET);
1195 WREG32(GRBM_SOFT_RESET, 0);
1196 RREG32(GRBM_SOFT_RESET);
1198 /* Set ring buffer size */
1199 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1200 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1202 tmp |= BUF_SWAP_32BIT;
1204 WREG32(CP_RB_CNTL, tmp);
1205 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1207 /* Set the write pointer delay */
1208 WREG32(CP_RB_WPTR_DELAY, 0);
1210 /* Initialize the ring buffer's read and write pointers */
1211 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1212 WREG32(CP_RB_RPTR_WR, 0);
1213 WREG32(CP_RB_WPTR, 0);
1215 /* set the wb address wether it's enabled or not */
1216 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1217 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1218 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1220 if (rdev->wb.enabled)
1221 WREG32(SCRATCH_UMSK, 0xff);
1223 tmp |= RB_NO_UPDATE;
1224 WREG32(SCRATCH_UMSK, 0);
1228 WREG32(CP_RB_CNTL, tmp);
1230 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1231 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1233 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1234 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1236 evergreen_cp_start(rdev);
1237 rdev->cp.ready = true;
1238 r = radeon_ring_test(rdev);
1240 rdev->cp.ready = false;
1249 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1252 u32 backend_disable_mask)
1254 u32 backend_map = 0;
1255 u32 enabled_backends_mask = 0;
1256 u32 enabled_backends_count = 0;
1258 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1259 u32 cur_backend = 0;
1261 bool force_no_swizzle;
1263 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1264 num_tile_pipes = EVERGREEN_MAX_PIPES;
1265 if (num_tile_pipes < 1)
1267 if (num_backends > EVERGREEN_MAX_BACKENDS)
1268 num_backends = EVERGREEN_MAX_BACKENDS;
1269 if (num_backends < 1)
1272 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1273 if (((backend_disable_mask >> i) & 1) == 0) {
1274 enabled_backends_mask |= (1 << i);
1275 ++enabled_backends_count;
1277 if (enabled_backends_count == num_backends)
1281 if (enabled_backends_count == 0) {
1282 enabled_backends_mask = 1;
1283 enabled_backends_count = 1;
1286 if (enabled_backends_count != num_backends)
1287 num_backends = enabled_backends_count;
1289 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1290 switch (rdev->family) {
1293 force_no_swizzle = false;
1299 force_no_swizzle = true;
1302 if (force_no_swizzle) {
1303 bool last_backend_enabled = false;
1305 force_no_swizzle = false;
1306 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1307 if (((enabled_backends_mask >> i) & 1) == 1) {
1308 if (last_backend_enabled)
1309 force_no_swizzle = true;
1310 last_backend_enabled = true;
1312 last_backend_enabled = false;
1316 switch (num_tile_pipes) {
1321 DRM_ERROR("odd number of pipes!\n");
1324 swizzle_pipe[0] = 0;
1325 swizzle_pipe[1] = 1;
1328 if (force_no_swizzle) {
1329 swizzle_pipe[0] = 0;
1330 swizzle_pipe[1] = 1;
1331 swizzle_pipe[2] = 2;
1332 swizzle_pipe[3] = 3;
1334 swizzle_pipe[0] = 0;
1335 swizzle_pipe[1] = 2;
1336 swizzle_pipe[2] = 1;
1337 swizzle_pipe[3] = 3;
1341 if (force_no_swizzle) {
1342 swizzle_pipe[0] = 0;
1343 swizzle_pipe[1] = 1;
1344 swizzle_pipe[2] = 2;
1345 swizzle_pipe[3] = 3;
1346 swizzle_pipe[4] = 4;
1347 swizzle_pipe[5] = 5;
1349 swizzle_pipe[0] = 0;
1350 swizzle_pipe[1] = 2;
1351 swizzle_pipe[2] = 4;
1352 swizzle_pipe[3] = 1;
1353 swizzle_pipe[4] = 3;
1354 swizzle_pipe[5] = 5;
1358 if (force_no_swizzle) {
1359 swizzle_pipe[0] = 0;
1360 swizzle_pipe[1] = 1;
1361 swizzle_pipe[2] = 2;
1362 swizzle_pipe[3] = 3;
1363 swizzle_pipe[4] = 4;
1364 swizzle_pipe[5] = 5;
1365 swizzle_pipe[6] = 6;
1366 swizzle_pipe[7] = 7;
1368 swizzle_pipe[0] = 0;
1369 swizzle_pipe[1] = 2;
1370 swizzle_pipe[2] = 4;
1371 swizzle_pipe[3] = 6;
1372 swizzle_pipe[4] = 1;
1373 swizzle_pipe[5] = 3;
1374 swizzle_pipe[6] = 5;
1375 swizzle_pipe[7] = 7;
1380 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1381 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1382 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1384 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1386 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1392 static void evergreen_gpu_init(struct radeon_device *rdev)
1394 u32 cc_rb_backend_disable = 0;
1395 u32 cc_gc_shader_pipe_config;
1396 u32 gb_addr_config = 0;
1397 u32 mc_shared_chmap, mc_arb_ramcfg;
1403 u32 sq_lds_resource_mgmt;
1404 u32 sq_gpr_resource_mgmt_1;
1405 u32 sq_gpr_resource_mgmt_2;
1406 u32 sq_gpr_resource_mgmt_3;
1407 u32 sq_thread_resource_mgmt;
1408 u32 sq_thread_resource_mgmt_2;
1409 u32 sq_stack_resource_mgmt_1;
1410 u32 sq_stack_resource_mgmt_2;
1411 u32 sq_stack_resource_mgmt_3;
1412 u32 vgt_cache_invalidation;
1413 u32 hdp_host_path_cntl;
1414 int i, j, num_shader_engines, ps_thread_count;
1416 switch (rdev->family) {
1419 rdev->config.evergreen.num_ses = 2;
1420 rdev->config.evergreen.max_pipes = 4;
1421 rdev->config.evergreen.max_tile_pipes = 8;
1422 rdev->config.evergreen.max_simds = 10;
1423 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1424 rdev->config.evergreen.max_gprs = 256;
1425 rdev->config.evergreen.max_threads = 248;
1426 rdev->config.evergreen.max_gs_threads = 32;
1427 rdev->config.evergreen.max_stack_entries = 512;
1428 rdev->config.evergreen.sx_num_of_sets = 4;
1429 rdev->config.evergreen.sx_max_export_size = 256;
1430 rdev->config.evergreen.sx_max_export_pos_size = 64;
1431 rdev->config.evergreen.sx_max_export_smx_size = 192;
1432 rdev->config.evergreen.max_hw_contexts = 8;
1433 rdev->config.evergreen.sq_num_cf_insts = 2;
1435 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1436 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1437 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1440 rdev->config.evergreen.num_ses = 1;
1441 rdev->config.evergreen.max_pipes = 4;
1442 rdev->config.evergreen.max_tile_pipes = 4;
1443 rdev->config.evergreen.max_simds = 10;
1444 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1445 rdev->config.evergreen.max_gprs = 256;
1446 rdev->config.evergreen.max_threads = 248;
1447 rdev->config.evergreen.max_gs_threads = 32;
1448 rdev->config.evergreen.max_stack_entries = 512;
1449 rdev->config.evergreen.sx_num_of_sets = 4;
1450 rdev->config.evergreen.sx_max_export_size = 256;
1451 rdev->config.evergreen.sx_max_export_pos_size = 64;
1452 rdev->config.evergreen.sx_max_export_smx_size = 192;
1453 rdev->config.evergreen.max_hw_contexts = 8;
1454 rdev->config.evergreen.sq_num_cf_insts = 2;
1456 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1457 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1458 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1461 rdev->config.evergreen.num_ses = 1;
1462 rdev->config.evergreen.max_pipes = 4;
1463 rdev->config.evergreen.max_tile_pipes = 4;
1464 rdev->config.evergreen.max_simds = 5;
1465 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1466 rdev->config.evergreen.max_gprs = 256;
1467 rdev->config.evergreen.max_threads = 248;
1468 rdev->config.evergreen.max_gs_threads = 32;
1469 rdev->config.evergreen.max_stack_entries = 256;
1470 rdev->config.evergreen.sx_num_of_sets = 4;
1471 rdev->config.evergreen.sx_max_export_size = 256;
1472 rdev->config.evergreen.sx_max_export_pos_size = 64;
1473 rdev->config.evergreen.sx_max_export_smx_size = 192;
1474 rdev->config.evergreen.max_hw_contexts = 8;
1475 rdev->config.evergreen.sq_num_cf_insts = 2;
1477 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1478 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1479 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1483 rdev->config.evergreen.num_ses = 1;
1484 rdev->config.evergreen.max_pipes = 2;
1485 rdev->config.evergreen.max_tile_pipes = 2;
1486 rdev->config.evergreen.max_simds = 2;
1487 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1488 rdev->config.evergreen.max_gprs = 256;
1489 rdev->config.evergreen.max_threads = 192;
1490 rdev->config.evergreen.max_gs_threads = 16;
1491 rdev->config.evergreen.max_stack_entries = 256;
1492 rdev->config.evergreen.sx_num_of_sets = 4;
1493 rdev->config.evergreen.sx_max_export_size = 128;
1494 rdev->config.evergreen.sx_max_export_pos_size = 32;
1495 rdev->config.evergreen.sx_max_export_smx_size = 96;
1496 rdev->config.evergreen.max_hw_contexts = 4;
1497 rdev->config.evergreen.sq_num_cf_insts = 1;
1499 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1500 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1501 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1505 /* Initialize HDP */
1506 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1507 WREG32((0x2c14 + j), 0x00000000);
1508 WREG32((0x2c18 + j), 0x00000000);
1509 WREG32((0x2c1c + j), 0x00000000);
1510 WREG32((0x2c20 + j), 0x00000000);
1511 WREG32((0x2c24 + j), 0x00000000);
1514 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1516 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1518 cc_gc_shader_pipe_config |=
1519 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1520 & EVERGREEN_MAX_PIPES_MASK);
1521 cc_gc_shader_pipe_config |=
1522 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1523 & EVERGREEN_MAX_SIMDS_MASK);
1525 cc_rb_backend_disable =
1526 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1527 & EVERGREEN_MAX_BACKENDS_MASK);
1530 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1531 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1533 switch (rdev->config.evergreen.max_tile_pipes) {
1536 gb_addr_config |= NUM_PIPES(0);
1539 gb_addr_config |= NUM_PIPES(1);
1542 gb_addr_config |= NUM_PIPES(2);
1545 gb_addr_config |= NUM_PIPES(3);
1549 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1550 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1551 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1552 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1553 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1554 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1556 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1557 gb_addr_config |= ROW_SIZE(2);
1559 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1561 if (rdev->ddev->pdev->device == 0x689e) {
1564 u8 efuse_box_bit_131_124;
1566 WREG32(RCU_IND_INDEX, 0x204);
1567 efuse_straps_4 = RREG32(RCU_IND_DATA);
1568 WREG32(RCU_IND_INDEX, 0x203);
1569 efuse_straps_3 = RREG32(RCU_IND_DATA);
1570 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1572 switch(efuse_box_bit_131_124) {
1574 gb_backend_map = 0x76543210;
1577 gb_backend_map = 0x77553311;
1580 gb_backend_map = 0x77553300;
1583 gb_backend_map = 0x77552211;
1586 gb_backend_map = 0x77443300;
1589 gb_backend_map = 0x66552211;
1592 gb_backend_map = 0x77552200;
1595 gb_backend_map = 0x66442200;
1598 gb_backend_map = 0x66553311;
1601 DRM_ERROR("bad backend map, using default\n");
1603 evergreen_get_tile_pipe_to_backend_map(rdev,
1604 rdev->config.evergreen.max_tile_pipes,
1605 rdev->config.evergreen.max_backends,
1606 ((EVERGREEN_MAX_BACKENDS_MASK <<
1607 rdev->config.evergreen.max_backends) &
1608 EVERGREEN_MAX_BACKENDS_MASK));
1611 } else if (rdev->ddev->pdev->device == 0x68b9) {
1613 u8 efuse_box_bit_127_124;
1615 WREG32(RCU_IND_INDEX, 0x203);
1616 efuse_straps_3 = RREG32(RCU_IND_DATA);
1617 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1619 switch(efuse_box_bit_127_124) {
1621 gb_backend_map = 0x00003210;
1627 gb_backend_map = 0x00003311;
1630 DRM_ERROR("bad backend map, using default\n");
1632 evergreen_get_tile_pipe_to_backend_map(rdev,
1633 rdev->config.evergreen.max_tile_pipes,
1634 rdev->config.evergreen.max_backends,
1635 ((EVERGREEN_MAX_BACKENDS_MASK <<
1636 rdev->config.evergreen.max_backends) &
1637 EVERGREEN_MAX_BACKENDS_MASK));
1641 switch (rdev->family) {
1644 gb_backend_map = 0x66442200;
1647 gb_backend_map = 0x00006420;
1651 evergreen_get_tile_pipe_to_backend_map(rdev,
1652 rdev->config.evergreen.max_tile_pipes,
1653 rdev->config.evergreen.max_backends,
1654 ((EVERGREEN_MAX_BACKENDS_MASK <<
1655 rdev->config.evergreen.max_backends) &
1656 EVERGREEN_MAX_BACKENDS_MASK));
1660 /* setup tiling info dword. gb_addr_config is not adequate since it does
1661 * not have bank info, so create a custom tiling dword.
1662 * bits 3:0 num_pipes
1663 * bits 7:4 num_banks
1664 * bits 11:8 group_size
1665 * bits 15:12 row_size
1667 rdev->config.evergreen.tile_config = 0;
1668 switch (rdev->config.evergreen.max_tile_pipes) {
1671 rdev->config.evergreen.tile_config |= (0 << 0);
1674 rdev->config.evergreen.tile_config |= (1 << 0);
1677 rdev->config.evergreen.tile_config |= (2 << 0);
1680 rdev->config.evergreen.tile_config |= (3 << 0);
1683 rdev->config.evergreen.tile_config |=
1684 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1685 rdev->config.evergreen.tile_config |=
1686 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1687 rdev->config.evergreen.tile_config |=
1688 ((gb_addr_config & 0x30000000) >> 28) << 12;
1690 WREG32(GB_BACKEND_MAP, gb_backend_map);
1691 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1692 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1693 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1695 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1696 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1698 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1699 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1700 u32 sp = cc_gc_shader_pipe_config;
1701 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1703 if (i == num_shader_engines) {
1704 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1705 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1708 WREG32(GRBM_GFX_INDEX, gfx);
1709 WREG32(RLC_GFX_INDEX, gfx);
1711 WREG32(CC_RB_BACKEND_DISABLE, rb);
1712 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1713 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1714 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1717 grbm_gfx_index |= SE_BROADCAST_WRITES;
1718 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1719 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1721 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1722 WREG32(CGTS_TCC_DISABLE, 0);
1723 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1724 WREG32(CGTS_USER_TCC_DISABLE, 0);
1726 /* set HW defaults for 3D engine */
1727 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1728 ROQ_IB2_START(0x2b)));
1730 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1732 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1737 sx_debug_1 = RREG32(SX_DEBUG_1);
1738 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1739 WREG32(SX_DEBUG_1, sx_debug_1);
1742 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1743 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1744 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1745 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1747 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1748 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1749 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1751 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1752 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1753 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1755 WREG32(VGT_NUM_INSTANCES, 1);
1756 WREG32(SPI_CONFIG_CNTL, 0);
1757 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1758 WREG32(CP_PERFMON_CNTL, 0);
1760 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1761 FETCH_FIFO_HIWATER(0x4) |
1762 DONE_FIFO_HIWATER(0xe0) |
1763 ALU_UPDATE_FIFO_HIWATER(0x8)));
1765 sq_config = RREG32(SQ_CONFIG);
1766 sq_config &= ~(PS_PRIO(3) |
1770 sq_config |= (VC_ENABLE |
1777 if (rdev->family == CHIP_CEDAR)
1778 /* no vertex cache */
1779 sq_config &= ~VC_ENABLE;
1781 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1783 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1784 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1785 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1786 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1787 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1788 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1789 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1791 if (rdev->family == CHIP_CEDAR)
1792 ps_thread_count = 96;
1794 ps_thread_count = 128;
1796 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1797 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1798 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1799 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1800 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1801 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1803 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1804 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1805 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1806 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1807 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1808 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1810 WREG32(SQ_CONFIG, sq_config);
1811 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1812 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1813 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1814 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1815 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1816 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1817 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1818 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1819 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1820 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1822 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1823 FORCE_EOV_MAX_REZ_CNT(255)));
1825 if (rdev->family == CHIP_CEDAR)
1826 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1828 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1829 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1830 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1832 WREG32(VGT_GS_VERTEX_REUSE, 16);
1833 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1835 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1836 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1838 WREG32(CB_PERF_CTR0_SEL_0, 0);
1839 WREG32(CB_PERF_CTR0_SEL_1, 0);
1840 WREG32(CB_PERF_CTR1_SEL_0, 0);
1841 WREG32(CB_PERF_CTR1_SEL_1, 0);
1842 WREG32(CB_PERF_CTR2_SEL_0, 0);
1843 WREG32(CB_PERF_CTR2_SEL_1, 0);
1844 WREG32(CB_PERF_CTR3_SEL_0, 0);
1845 WREG32(CB_PERF_CTR3_SEL_1, 0);
1847 /* clear render buffer base addresses */
1848 WREG32(CB_COLOR0_BASE, 0);
1849 WREG32(CB_COLOR1_BASE, 0);
1850 WREG32(CB_COLOR2_BASE, 0);
1851 WREG32(CB_COLOR3_BASE, 0);
1852 WREG32(CB_COLOR4_BASE, 0);
1853 WREG32(CB_COLOR5_BASE, 0);
1854 WREG32(CB_COLOR6_BASE, 0);
1855 WREG32(CB_COLOR7_BASE, 0);
1856 WREG32(CB_COLOR8_BASE, 0);
1857 WREG32(CB_COLOR9_BASE, 0);
1858 WREG32(CB_COLOR10_BASE, 0);
1859 WREG32(CB_COLOR11_BASE, 0);
1861 /* set the shader const cache sizes to 0 */
1862 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1864 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1867 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1868 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1870 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1876 int evergreen_mc_init(struct radeon_device *rdev)
1879 int chansize, numchan;
1881 /* Get VRAM informations */
1882 rdev->mc.vram_is_ddr = true;
1883 tmp = RREG32(MC_ARB_RAMCFG);
1884 if (tmp & CHANSIZE_OVERRIDE) {
1886 } else if (tmp & CHANSIZE_MASK) {
1891 tmp = RREG32(MC_SHARED_CHMAP);
1892 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1907 rdev->mc.vram_width = numchan * chansize;
1908 /* Could aper size report 0 ? */
1909 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1910 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1911 /* Setup GPU memory space */
1912 /* size in MB on evergreen */
1913 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1914 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1915 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1916 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1917 r600_vram_gtt_location(rdev, &rdev->mc);
1918 radeon_update_bandwidth_info(rdev);
1923 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1925 /* FIXME: implement for evergreen */
1929 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1931 struct evergreen_mc_save save;
1934 dev_info(rdev->dev, "GPU softreset \n");
1935 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1936 RREG32(GRBM_STATUS));
1937 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1938 RREG32(GRBM_STATUS_SE0));
1939 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1940 RREG32(GRBM_STATUS_SE1));
1941 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1942 RREG32(SRBM_STATUS));
1943 evergreen_mc_stop(rdev, &save);
1944 if (evergreen_mc_wait_for_idle(rdev)) {
1945 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1947 /* Disable CP parsing/prefetching */
1948 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1950 /* reset all the gfx blocks */
1951 grbm_reset = (SOFT_RESET_CP |
1964 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1965 WREG32(GRBM_SOFT_RESET, grbm_reset);
1966 (void)RREG32(GRBM_SOFT_RESET);
1968 WREG32(GRBM_SOFT_RESET, 0);
1969 (void)RREG32(GRBM_SOFT_RESET);
1970 /* Wait a little for things to settle down */
1972 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1973 RREG32(GRBM_STATUS));
1974 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1975 RREG32(GRBM_STATUS_SE0));
1976 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1977 RREG32(GRBM_STATUS_SE1));
1978 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1979 RREG32(SRBM_STATUS));
1980 evergreen_mc_resume(rdev, &save);
1984 int evergreen_asic_reset(struct radeon_device *rdev)
1986 return evergreen_gpu_soft_reset(rdev);
1991 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1995 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1997 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1999 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2001 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2003 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2005 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2011 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2015 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2016 WREG32(GRBM_INT_CNTL, 0);
2017 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2018 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2019 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2020 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2021 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2022 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2024 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2025 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2026 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2027 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2028 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2029 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2031 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2032 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2034 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2035 WREG32(DC_HPD1_INT_CONTROL, tmp);
2036 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2037 WREG32(DC_HPD2_INT_CONTROL, tmp);
2038 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2039 WREG32(DC_HPD3_INT_CONTROL, tmp);
2040 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2041 WREG32(DC_HPD4_INT_CONTROL, tmp);
2042 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2043 WREG32(DC_HPD5_INT_CONTROL, tmp);
2044 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2045 WREG32(DC_HPD6_INT_CONTROL, tmp);
2049 int evergreen_irq_set(struct radeon_device *rdev)
2051 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2052 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2053 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2054 u32 grbm_int_cntl = 0;
2056 if (!rdev->irq.installed) {
2057 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2060 /* don't enable anything if the ih is disabled */
2061 if (!rdev->ih.enabled) {
2062 r600_disable_interrupts(rdev);
2063 /* force the active interrupt state to all disabled */
2064 evergreen_disable_interrupt_state(rdev);
2068 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2069 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2070 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2071 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2072 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2073 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2075 if (rdev->irq.sw_int) {
2076 DRM_DEBUG("evergreen_irq_set: sw int\n");
2077 cp_int_cntl |= RB_INT_ENABLE;
2078 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2080 if (rdev->irq.crtc_vblank_int[0]) {
2081 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2082 crtc1 |= VBLANK_INT_MASK;
2084 if (rdev->irq.crtc_vblank_int[1]) {
2085 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2086 crtc2 |= VBLANK_INT_MASK;
2088 if (rdev->irq.crtc_vblank_int[2]) {
2089 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2090 crtc3 |= VBLANK_INT_MASK;
2092 if (rdev->irq.crtc_vblank_int[3]) {
2093 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2094 crtc4 |= VBLANK_INT_MASK;
2096 if (rdev->irq.crtc_vblank_int[4]) {
2097 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2098 crtc5 |= VBLANK_INT_MASK;
2100 if (rdev->irq.crtc_vblank_int[5]) {
2101 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2102 crtc6 |= VBLANK_INT_MASK;
2104 if (rdev->irq.hpd[0]) {
2105 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2106 hpd1 |= DC_HPDx_INT_EN;
2108 if (rdev->irq.hpd[1]) {
2109 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2110 hpd2 |= DC_HPDx_INT_EN;
2112 if (rdev->irq.hpd[2]) {
2113 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2114 hpd3 |= DC_HPDx_INT_EN;
2116 if (rdev->irq.hpd[3]) {
2117 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2118 hpd4 |= DC_HPDx_INT_EN;
2120 if (rdev->irq.hpd[4]) {
2121 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2122 hpd5 |= DC_HPDx_INT_EN;
2124 if (rdev->irq.hpd[5]) {
2125 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2126 hpd6 |= DC_HPDx_INT_EN;
2128 if (rdev->irq.gui_idle) {
2129 DRM_DEBUG("gui idle\n");
2130 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2133 WREG32(CP_INT_CNTL, cp_int_cntl);
2134 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2136 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2137 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2138 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2139 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2140 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2141 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2143 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2144 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2145 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2146 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2147 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2148 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2153 static inline void evergreen_irq_ack(struct radeon_device *rdev,
2156 u32 *disp_int_cont2,
2157 u32 *disp_int_cont3,
2158 u32 *disp_int_cont4,
2159 u32 *disp_int_cont5)
2163 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2164 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2165 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2166 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2167 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2168 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2170 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2171 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2172 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2173 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2175 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2176 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2177 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
2178 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2180 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2181 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2182 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2183 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2185 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2186 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2187 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2188 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2190 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2191 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2192 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2193 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2195 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2196 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2197 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2198 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2200 if (*disp_int & DC_HPD1_INTERRUPT) {
2201 tmp = RREG32(DC_HPD1_INT_CONTROL);
2202 tmp |= DC_HPDx_INT_ACK;
2203 WREG32(DC_HPD1_INT_CONTROL, tmp);
2205 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
2206 tmp = RREG32(DC_HPD2_INT_CONTROL);
2207 tmp |= DC_HPDx_INT_ACK;
2208 WREG32(DC_HPD2_INT_CONTROL, tmp);
2210 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
2211 tmp = RREG32(DC_HPD3_INT_CONTROL);
2212 tmp |= DC_HPDx_INT_ACK;
2213 WREG32(DC_HPD3_INT_CONTROL, tmp);
2215 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
2216 tmp = RREG32(DC_HPD4_INT_CONTROL);
2217 tmp |= DC_HPDx_INT_ACK;
2218 WREG32(DC_HPD4_INT_CONTROL, tmp);
2220 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
2221 tmp = RREG32(DC_HPD5_INT_CONTROL);
2222 tmp |= DC_HPDx_INT_ACK;
2223 WREG32(DC_HPD5_INT_CONTROL, tmp);
2225 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
2226 tmp = RREG32(DC_HPD5_INT_CONTROL);
2227 tmp |= DC_HPDx_INT_ACK;
2228 WREG32(DC_HPD6_INT_CONTROL, tmp);
2232 void evergreen_irq_disable(struct radeon_device *rdev)
2234 u32 disp_int, disp_int_cont, disp_int_cont2;
2235 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2237 r600_disable_interrupts(rdev);
2238 /* Wait and acknowledge irq */
2240 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2241 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2242 evergreen_disable_interrupt_state(rdev);
2245 static void evergreen_irq_suspend(struct radeon_device *rdev)
2247 evergreen_irq_disable(rdev);
2248 r600_rlc_stop(rdev);
2251 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2255 if (rdev->wb.enabled)
2256 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2258 wptr = RREG32(IH_RB_WPTR);
2260 if (wptr & RB_OVERFLOW) {
2261 /* When a ring buffer overflow happen start parsing interrupt
2262 * from the last not overwritten vector (wptr + 16). Hopefully
2263 * this should allow us to catchup.
2265 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2266 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2267 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2268 tmp = RREG32(IH_RB_CNTL);
2269 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2270 WREG32(IH_RB_CNTL, tmp);
2272 return (wptr & rdev->ih.ptr_mask);
2275 int evergreen_irq_process(struct radeon_device *rdev)
2277 u32 wptr = evergreen_get_ih_wptr(rdev);
2278 u32 rptr = rdev->ih.rptr;
2279 u32 src_id, src_data;
2281 u32 disp_int, disp_int_cont, disp_int_cont2;
2282 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2283 unsigned long flags;
2284 bool queue_hotplug = false;
2286 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2287 if (!rdev->ih.enabled)
2290 spin_lock_irqsave(&rdev->ih.lock, flags);
2293 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2296 if (rdev->shutdown) {
2297 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2302 /* display interrupts */
2303 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2304 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2306 rdev->ih.wptr = wptr;
2307 while (rptr != wptr) {
2308 /* wptr/rptr are in bytes! */
2309 ring_index = rptr / 4;
2310 src_id = rdev->ih.ring[ring_index] & 0xff;
2311 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2314 case 1: /* D1 vblank/vline */
2316 case 0: /* D1 vblank */
2317 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2318 drm_handle_vblank(rdev->ddev, 0);
2319 rdev->pm.vblank_sync = true;
2320 wake_up(&rdev->irq.vblank_queue);
2321 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2322 DRM_DEBUG("IH: D1 vblank\n");
2325 case 1: /* D1 vline */
2326 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2327 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2328 DRM_DEBUG("IH: D1 vline\n");
2332 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2336 case 2: /* D2 vblank/vline */
2338 case 0: /* D2 vblank */
2339 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2340 drm_handle_vblank(rdev->ddev, 1);
2341 rdev->pm.vblank_sync = true;
2342 wake_up(&rdev->irq.vblank_queue);
2343 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2344 DRM_DEBUG("IH: D2 vblank\n");
2347 case 1: /* D2 vline */
2348 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2349 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2350 DRM_DEBUG("IH: D2 vline\n");
2354 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2358 case 3: /* D3 vblank/vline */
2360 case 0: /* D3 vblank */
2361 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2362 drm_handle_vblank(rdev->ddev, 2);
2363 rdev->pm.vblank_sync = true;
2364 wake_up(&rdev->irq.vblank_queue);
2365 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2366 DRM_DEBUG("IH: D3 vblank\n");
2369 case 1: /* D3 vline */
2370 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2371 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2372 DRM_DEBUG("IH: D3 vline\n");
2376 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2380 case 4: /* D4 vblank/vline */
2382 case 0: /* D4 vblank */
2383 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2384 drm_handle_vblank(rdev->ddev, 3);
2385 rdev->pm.vblank_sync = true;
2386 wake_up(&rdev->irq.vblank_queue);
2387 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2388 DRM_DEBUG("IH: D4 vblank\n");
2391 case 1: /* D4 vline */
2392 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2393 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2394 DRM_DEBUG("IH: D4 vline\n");
2398 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2402 case 5: /* D5 vblank/vline */
2404 case 0: /* D5 vblank */
2405 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2406 drm_handle_vblank(rdev->ddev, 4);
2407 rdev->pm.vblank_sync = true;
2408 wake_up(&rdev->irq.vblank_queue);
2409 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2410 DRM_DEBUG("IH: D5 vblank\n");
2413 case 1: /* D5 vline */
2414 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2415 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2416 DRM_DEBUG("IH: D5 vline\n");
2420 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2424 case 6: /* D6 vblank/vline */
2426 case 0: /* D6 vblank */
2427 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2428 drm_handle_vblank(rdev->ddev, 5);
2429 rdev->pm.vblank_sync = true;
2430 wake_up(&rdev->irq.vblank_queue);
2431 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2432 DRM_DEBUG("IH: D6 vblank\n");
2435 case 1: /* D6 vline */
2436 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2437 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2438 DRM_DEBUG("IH: D6 vline\n");
2442 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2446 case 42: /* HPD hotplug */
2449 if (disp_int & DC_HPD1_INTERRUPT) {
2450 disp_int &= ~DC_HPD1_INTERRUPT;
2451 queue_hotplug = true;
2452 DRM_DEBUG("IH: HPD1\n");
2456 if (disp_int_cont & DC_HPD2_INTERRUPT) {
2457 disp_int_cont &= ~DC_HPD2_INTERRUPT;
2458 queue_hotplug = true;
2459 DRM_DEBUG("IH: HPD2\n");
2463 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
2464 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2465 queue_hotplug = true;
2466 DRM_DEBUG("IH: HPD3\n");
2470 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
2471 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2472 queue_hotplug = true;
2473 DRM_DEBUG("IH: HPD4\n");
2477 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
2478 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2479 queue_hotplug = true;
2480 DRM_DEBUG("IH: HPD5\n");
2484 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
2485 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2486 queue_hotplug = true;
2487 DRM_DEBUG("IH: HPD6\n");
2491 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2495 case 176: /* CP_INT in ring buffer */
2496 case 177: /* CP_INT in IB1 */
2497 case 178: /* CP_INT in IB2 */
2498 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2499 radeon_fence_process(rdev);
2501 case 181: /* CP EOP event */
2502 DRM_DEBUG("IH: CP EOP\n");
2503 radeon_fence_process(rdev);
2505 case 233: /* GUI IDLE */
2506 DRM_DEBUG("IH: CP EOP\n");
2507 rdev->pm.gui_idle = true;
2508 wake_up(&rdev->irq.idle_queue);
2511 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2515 /* wptr/rptr are in bytes! */
2517 rptr &= rdev->ih.ptr_mask;
2519 /* make sure wptr hasn't changed while processing */
2520 wptr = evergreen_get_ih_wptr(rdev);
2521 if (wptr != rdev->ih.wptr)
2524 queue_work(rdev->wq, &rdev->hotplug_work);
2525 rdev->ih.rptr = rptr;
2526 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2527 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2531 static int evergreen_startup(struct radeon_device *rdev)
2535 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2536 r = r600_init_microcode(rdev);
2538 DRM_ERROR("Failed to load firmware!\n");
2543 evergreen_mc_program(rdev);
2544 if (rdev->flags & RADEON_IS_AGP) {
2545 evergreen_agp_enable(rdev);
2547 r = evergreen_pcie_gart_enable(rdev);
2551 evergreen_gpu_init(rdev);
2553 r = evergreen_blit_init(rdev);
2555 evergreen_blit_fini(rdev);
2556 rdev->asic->copy = NULL;
2557 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2560 /* allocate wb buffer */
2561 r = radeon_wb_init(rdev);
2566 r = r600_irq_init(rdev);
2568 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2569 radeon_irq_kms_fini(rdev);
2572 evergreen_irq_set(rdev);
2574 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2577 r = evergreen_cp_load_microcode(rdev);
2580 r = evergreen_cp_resume(rdev);
2587 int evergreen_resume(struct radeon_device *rdev)
2591 /* reset the asic, the gfx blocks are often in a bad state
2592 * after the driver is unloaded or after a resume
2594 if (radeon_asic_reset(rdev))
2595 dev_warn(rdev->dev, "GPU reset failed !\n");
2596 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2597 * posting will perform necessary task to bring back GPU into good
2601 atom_asic_init(rdev->mode_info.atom_context);
2603 r = evergreen_startup(rdev);
2605 DRM_ERROR("r600 startup failed on resume\n");
2609 r = r600_ib_test(rdev);
2611 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2619 int evergreen_suspend(struct radeon_device *rdev)
2623 /* FIXME: we should wait for ring to be empty */
2625 rdev->cp.ready = false;
2626 evergreen_irq_suspend(rdev);
2627 radeon_wb_disable(rdev);
2628 evergreen_pcie_gart_disable(rdev);
2630 /* unpin shaders bo */
2631 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2632 if (likely(r == 0)) {
2633 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2634 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2640 int evergreen_copy_blit(struct radeon_device *rdev,
2641 uint64_t src_offset, uint64_t dst_offset,
2642 unsigned num_pages, struct radeon_fence *fence)
2646 mutex_lock(&rdev->r600_blit.mutex);
2647 rdev->r600_blit.vb_ib = NULL;
2648 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2650 if (rdev->r600_blit.vb_ib)
2651 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2652 mutex_unlock(&rdev->r600_blit.mutex);
2655 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2656 evergreen_blit_done_copy(rdev, fence);
2657 mutex_unlock(&rdev->r600_blit.mutex);
2661 static bool evergreen_card_posted(struct radeon_device *rdev)
2665 /* first check CRTCs */
2666 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2667 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2668 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2669 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2670 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2671 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2672 if (reg & EVERGREEN_CRTC_MASTER_EN)
2675 /* then check MEM_SIZE, in case the crtcs are off */
2676 if (RREG32(CONFIG_MEMSIZE))
2682 /* Plan is to move initialization in that function and use
2683 * helper function so that radeon_device_init pretty much
2684 * do nothing more than calling asic specific function. This
2685 * should also allow to remove a bunch of callback function
2688 int evergreen_init(struct radeon_device *rdev)
2692 r = radeon_dummy_page_init(rdev);
2695 /* This don't do much */
2696 r = radeon_gem_init(rdev);
2700 if (!radeon_get_bios(rdev)) {
2701 if (ASIC_IS_AVIVO(rdev))
2704 /* Must be an ATOMBIOS */
2705 if (!rdev->is_atom_bios) {
2706 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2709 r = radeon_atombios_init(rdev);
2712 /* reset the asic, the gfx blocks are often in a bad state
2713 * after the driver is unloaded or after a resume
2715 if (radeon_asic_reset(rdev))
2716 dev_warn(rdev->dev, "GPU reset failed !\n");
2717 /* Post card if necessary */
2718 if (!evergreen_card_posted(rdev)) {
2720 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2723 DRM_INFO("GPU not posted. posting now...\n");
2724 atom_asic_init(rdev->mode_info.atom_context);
2726 /* Initialize scratch registers */
2727 r600_scratch_init(rdev);
2728 /* Initialize surface registers */
2729 radeon_surface_init(rdev);
2730 /* Initialize clocks */
2731 radeon_get_clock_info(rdev->ddev);
2733 r = radeon_fence_driver_init(rdev);
2736 /* initialize AGP */
2737 if (rdev->flags & RADEON_IS_AGP) {
2738 r = radeon_agp_init(rdev);
2740 radeon_agp_disable(rdev);
2742 /* initialize memory controller */
2743 r = evergreen_mc_init(rdev);
2746 /* Memory manager */
2747 r = radeon_bo_init(rdev);
2751 r = radeon_irq_kms_init(rdev);
2755 rdev->cp.ring_obj = NULL;
2756 r600_ring_init(rdev, 1024 * 1024);
2758 rdev->ih.ring_obj = NULL;
2759 r600_ih_ring_init(rdev, 64 * 1024);
2761 r = r600_pcie_gart_init(rdev);
2765 rdev->accel_working = true;
2766 r = evergreen_startup(rdev);
2768 dev_err(rdev->dev, "disabling GPU acceleration\n");
2770 r600_irq_fini(rdev);
2771 radeon_wb_fini(rdev);
2772 radeon_irq_kms_fini(rdev);
2773 evergreen_pcie_gart_fini(rdev);
2774 rdev->accel_working = false;
2776 if (rdev->accel_working) {
2777 r = radeon_ib_pool_init(rdev);
2779 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2780 rdev->accel_working = false;
2782 r = r600_ib_test(rdev);
2784 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2785 rdev->accel_working = false;
2791 void evergreen_fini(struct radeon_device *rdev)
2793 evergreen_blit_fini(rdev);
2795 r600_irq_fini(rdev);
2796 radeon_wb_fini(rdev);
2797 radeon_irq_kms_fini(rdev);
2798 evergreen_pcie_gart_fini(rdev);
2799 radeon_gem_fini(rdev);
2800 radeon_fence_driver_fini(rdev);
2801 radeon_agp_fini(rdev);
2802 radeon_bo_fini(rdev);
2803 radeon_atombios_fini(rdev);
2806 radeon_dummy_page_fini(rdev);