2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "evergreend.h"
31 #include "evergreen_reg_safe.h"
32 #include "cayman_reg_safe.h"
34 #define MAX(a,b) (((a)>(b))?(a):(b))
35 #define MIN(a,b) (((a)<(b))?(a):(b))
37 #define REG_SAFE_BM_SIZE ARRAY_SIZE(evergreen_reg_safe_bm)
39 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
40 struct radeon_bo_list **cs_reloc);
41 struct evergreen_cs_track {
47 u32 nsamples; /* unused */
48 struct radeon_bo *cb_color_bo[12];
49 u32 cb_color_bo_offset[12];
50 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */
51 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */
52 u32 cb_color_info[12];
53 u32 cb_color_view[12];
54 u32 cb_color_pitch[12];
55 u32 cb_color_slice[12];
56 u32 cb_color_slice_idx[12];
57 u32 cb_color_attrib[12];
58 u32 cb_color_cmask_slice[8];/* unused */
59 u32 cb_color_fmask_slice[8];/* unused */
61 u32 cb_shader_mask; /* unused */
62 u32 vgt_strmout_config;
63 u32 vgt_strmout_buffer_config;
64 struct radeon_bo *vgt_strmout_bo[4];
65 u32 vgt_strmout_bo_offset[4];
66 u32 vgt_strmout_size[4];
73 u32 db_z_write_offset;
74 struct radeon_bo *db_z_read_bo;
75 struct radeon_bo *db_z_write_bo;
78 u32 db_s_write_offset;
79 struct radeon_bo *db_s_read_bo;
80 struct radeon_bo *db_s_write_bo;
81 bool sx_misc_kill_all_prims;
87 struct radeon_bo *htile_bo;
88 unsigned long indirect_draw_buffer_size;
89 const unsigned *reg_safe_bm;
92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
94 if (tiling_flags & RADEON_TILING_MACRO)
95 return ARRAY_2D_TILED_THIN1;
96 else if (tiling_flags & RADEON_TILING_MICRO)
97 return ARRAY_1D_TILED_THIN1;
99 return ARRAY_LINEAR_GENERAL;
102 static u32 evergreen_cs_get_num_banks(u32 nbanks)
106 return ADDR_SURF_2_BANK;
108 return ADDR_SURF_4_BANK;
111 return ADDR_SURF_8_BANK;
113 return ADDR_SURF_16_BANK;
117 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
121 for (i = 0; i < 8; i++) {
122 track->cb_color_fmask_bo[i] = NULL;
123 track->cb_color_cmask_bo[i] = NULL;
124 track->cb_color_cmask_slice[i] = 0;
125 track->cb_color_fmask_slice[i] = 0;
128 for (i = 0; i < 12; i++) {
129 track->cb_color_bo[i] = NULL;
130 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
131 track->cb_color_info[i] = 0;
132 track->cb_color_view[i] = 0xFFFFFFFF;
133 track->cb_color_pitch[i] = 0;
134 track->cb_color_slice[i] = 0xfffffff;
135 track->cb_color_slice_idx[i] = 0;
137 track->cb_target_mask = 0xFFFFFFFF;
138 track->cb_shader_mask = 0xFFFFFFFF;
139 track->cb_dirty = true;
141 track->db_depth_slice = 0xffffffff;
142 track->db_depth_view = 0xFFFFC000;
143 track->db_depth_size = 0xFFFFFFFF;
144 track->db_depth_control = 0xFFFFFFFF;
145 track->db_z_info = 0xFFFFFFFF;
146 track->db_z_read_offset = 0xFFFFFFFF;
147 track->db_z_write_offset = 0xFFFFFFFF;
148 track->db_z_read_bo = NULL;
149 track->db_z_write_bo = NULL;
150 track->db_s_info = 0xFFFFFFFF;
151 track->db_s_read_offset = 0xFFFFFFFF;
152 track->db_s_write_offset = 0xFFFFFFFF;
153 track->db_s_read_bo = NULL;
154 track->db_s_write_bo = NULL;
155 track->db_dirty = true;
156 track->htile_bo = NULL;
157 track->htile_offset = 0xFFFFFFFF;
158 track->htile_surface = 0;
160 for (i = 0; i < 4; i++) {
161 track->vgt_strmout_size[i] = 0;
162 track->vgt_strmout_bo[i] = NULL;
163 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
165 track->streamout_dirty = true;
166 track->sx_misc_kill_all_prims = false;
170 /* value gathered from cs */
186 unsigned long base_align;
189 static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
190 struct eg_surface *surf,
193 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
194 surf->base_align = surf->bpe;
200 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
201 struct eg_surface *surf,
204 struct evergreen_cs_track *track = p->track;
207 palign = MAX(64, track->group_size / surf->bpe);
208 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
209 surf->base_align = track->group_size;
210 surf->palign = palign;
212 if (surf->nbx & (palign - 1)) {
214 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
215 __func__, __LINE__, prefix, surf->nbx, palign);
222 static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
223 struct eg_surface *surf,
226 struct evergreen_cs_track *track = p->track;
229 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
230 palign = MAX(8, palign);
231 surf->layer_size = surf->nbx * surf->nby * surf->bpe;
232 surf->base_align = track->group_size;
233 surf->palign = palign;
235 if ((surf->nbx & (palign - 1))) {
237 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
238 __func__, __LINE__, prefix, surf->nbx, palign,
239 track->group_size, surf->bpe, surf->nsamples);
243 if ((surf->nby & (8 - 1))) {
245 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
246 __func__, __LINE__, prefix, surf->nby);
253 static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
254 struct eg_surface *surf,
257 struct evergreen_cs_track *track = p->track;
258 unsigned palign, halign, tileb, slice_pt;
259 unsigned mtile_pr, mtile_ps, mtileb;
261 tileb = 64 * surf->bpe * surf->nsamples;
263 if (tileb > surf->tsplit) {
264 slice_pt = tileb / surf->tsplit;
266 tileb = tileb / slice_pt;
267 /* macro tile width & height */
268 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
269 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
270 mtileb = (palign / 8) * (halign / 8) * tileb;
271 mtile_pr = surf->nbx / palign;
272 mtile_ps = (mtile_pr * surf->nby) / halign;
273 surf->layer_size = mtile_ps * mtileb * slice_pt;
274 surf->base_align = (palign / 8) * (halign / 8) * tileb;
275 surf->palign = palign;
276 surf->halign = halign;
278 if ((surf->nbx & (palign - 1))) {
280 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
281 __func__, __LINE__, prefix, surf->nbx, palign);
285 if ((surf->nby & (halign - 1))) {
287 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
288 __func__, __LINE__, prefix, surf->nby, halign);
296 static int evergreen_surface_check(struct radeon_cs_parser *p,
297 struct eg_surface *surf,
300 /* some common value computed here */
301 surf->bpe = r600_fmt_get_blocksize(surf->format);
303 switch (surf->mode) {
304 case ARRAY_LINEAR_GENERAL:
305 return evergreen_surface_check_linear(p, surf, prefix);
306 case ARRAY_LINEAR_ALIGNED:
307 return evergreen_surface_check_linear_aligned(p, surf, prefix);
308 case ARRAY_1D_TILED_THIN1:
309 return evergreen_surface_check_1d(p, surf, prefix);
310 case ARRAY_2D_TILED_THIN1:
311 return evergreen_surface_check_2d(p, surf, prefix);
313 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
314 __func__, __LINE__, prefix, surf->mode);
320 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
321 struct eg_surface *surf,
324 switch (surf->mode) {
325 case ARRAY_2D_TILED_THIN1:
327 case ARRAY_LINEAR_GENERAL:
328 case ARRAY_LINEAR_ALIGNED:
329 case ARRAY_1D_TILED_THIN1:
332 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
333 __func__, __LINE__, prefix, surf->mode);
337 switch (surf->nbanks) {
338 case 0: surf->nbanks = 2; break;
339 case 1: surf->nbanks = 4; break;
340 case 2: surf->nbanks = 8; break;
341 case 3: surf->nbanks = 16; break;
343 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
344 __func__, __LINE__, prefix, surf->nbanks);
347 switch (surf->bankw) {
348 case 0: surf->bankw = 1; break;
349 case 1: surf->bankw = 2; break;
350 case 2: surf->bankw = 4; break;
351 case 3: surf->bankw = 8; break;
353 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
354 __func__, __LINE__, prefix, surf->bankw);
357 switch (surf->bankh) {
358 case 0: surf->bankh = 1; break;
359 case 1: surf->bankh = 2; break;
360 case 2: surf->bankh = 4; break;
361 case 3: surf->bankh = 8; break;
363 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
364 __func__, __LINE__, prefix, surf->bankh);
367 switch (surf->mtilea) {
368 case 0: surf->mtilea = 1; break;
369 case 1: surf->mtilea = 2; break;
370 case 2: surf->mtilea = 4; break;
371 case 3: surf->mtilea = 8; break;
373 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
374 __func__, __LINE__, prefix, surf->mtilea);
377 switch (surf->tsplit) {
378 case 0: surf->tsplit = 64; break;
379 case 1: surf->tsplit = 128; break;
380 case 2: surf->tsplit = 256; break;
381 case 3: surf->tsplit = 512; break;
382 case 4: surf->tsplit = 1024; break;
383 case 5: surf->tsplit = 2048; break;
384 case 6: surf->tsplit = 4096; break;
386 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
387 __func__, __LINE__, prefix, surf->tsplit);
393 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
395 struct evergreen_cs_track *track = p->track;
396 struct eg_surface surf;
397 unsigned pitch, slice, mslice;
398 unsigned long offset;
401 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
402 pitch = track->cb_color_pitch[id];
403 slice = track->cb_color_slice[id];
404 surf.nbx = (pitch + 1) * 8;
405 surf.nby = ((slice + 1) * 64) / surf.nbx;
406 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
407 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
408 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
409 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
410 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
411 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
412 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
415 if (!r600_fmt_is_valid_color(surf.format)) {
416 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
417 __func__, __LINE__, surf.format,
418 id, track->cb_color_info[id]);
422 r = evergreen_surface_value_conv_check(p, &surf, "cb");
427 r = evergreen_surface_check(p, &surf, "cb");
429 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
430 __func__, __LINE__, id, track->cb_color_pitch[id],
431 track->cb_color_slice[id], track->cb_color_attrib[id],
432 track->cb_color_info[id]);
436 offset = track->cb_color_bo_offset[id] << 8;
437 if (offset & (surf.base_align - 1)) {
438 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
439 __func__, __LINE__, id, offset, surf.base_align);
443 offset += surf.layer_size * mslice;
444 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
445 /* old ddx are broken they allocate bo with w*h*bpp but
446 * program slice with ALIGN(h, 8), catch this and patch
450 uint32_t *ib = p->ib.ptr;
451 unsigned long tmp, nby, bsize, size, min = 0;
453 /* find the height the ddx wants */
457 bsize = radeon_bo_size(track->cb_color_bo[id]);
458 tmp = track->cb_color_bo_offset[id] << 8;
459 for (nby = surf.nby; nby > min; nby--) {
460 size = nby * surf.nbx * surf.bpe * surf.nsamples;
461 if ((tmp + size * mslice) <= bsize) {
467 slice = ((nby * surf.nbx) / 64) - 1;
468 if (!evergreen_surface_check(p, &surf, "cb")) {
469 /* check if this one works */
470 tmp += surf.layer_size * mslice;
472 ib[track->cb_color_slice_idx[id]] = slice;
478 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
479 "offset %d, max layer %d, bo size %ld, slice %d)\n",
480 __func__, __LINE__, id, surf.layer_size,
481 track->cb_color_bo_offset[id] << 8, mslice,
482 radeon_bo_size(track->cb_color_bo[id]), slice);
483 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
484 __func__, __LINE__, surf.nbx, surf.nby,
485 surf.mode, surf.bpe, surf.nsamples,
486 surf.bankw, surf.bankh,
487 surf.tsplit, surf.mtilea);
495 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
496 unsigned nbx, unsigned nby)
498 struct evergreen_cs_track *track = p->track;
501 if (track->htile_bo == NULL) {
502 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
503 __func__, __LINE__, track->db_z_info);
507 if (G_028ABC_LINEAR(track->htile_surface)) {
508 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
509 nbx = round_up(nbx, 16 * 8);
510 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
511 nby = round_up(nby, track->npipes * 8);
513 /* always assume 8x8 htile */
514 /* align is htile align * 8, htile align vary according to
515 * number of pipe and tile width and nby
517 switch (track->npipes) {
519 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
520 nbx = round_up(nbx, 64 * 8);
521 nby = round_up(nby, 64 * 8);
524 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
525 nbx = round_up(nbx, 64 * 8);
526 nby = round_up(nby, 32 * 8);
529 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
530 nbx = round_up(nbx, 32 * 8);
531 nby = round_up(nby, 32 * 8);
534 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
535 nbx = round_up(nbx, 32 * 8);
536 nby = round_up(nby, 16 * 8);
539 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
540 __func__, __LINE__, track->npipes);
544 /* compute number of htile */
547 /* size must be aligned on npipes * 2K boundary */
548 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
549 size += track->htile_offset;
551 if (size > radeon_bo_size(track->htile_bo)) {
552 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
553 __func__, __LINE__, radeon_bo_size(track->htile_bo),
560 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
562 struct evergreen_cs_track *track = p->track;
563 struct eg_surface surf;
564 unsigned pitch, slice, mslice;
565 unsigned long offset;
568 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
569 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
570 slice = track->db_depth_slice;
571 surf.nbx = (pitch + 1) * 8;
572 surf.nby = ((slice + 1) * 64) / surf.nbx;
573 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
574 surf.format = G_028044_FORMAT(track->db_s_info);
575 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
576 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
577 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
578 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
579 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
582 if (surf.format != 1) {
583 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
584 __func__, __LINE__, surf.format);
587 /* replace by color format so we can use same code */
588 surf.format = V_028C70_COLOR_8;
590 r = evergreen_surface_value_conv_check(p, &surf, "stencil");
595 r = evergreen_surface_check(p, &surf, NULL);
597 /* old userspace doesn't compute proper depth/stencil alignment
598 * check that alignment against a bigger byte per elements and
599 * only report if that alignment is wrong too.
601 surf.format = V_028C70_COLOR_8_8_8_8;
602 r = evergreen_surface_check(p, &surf, "stencil");
604 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
605 __func__, __LINE__, track->db_depth_size,
606 track->db_depth_slice, track->db_s_info, track->db_z_info);
611 offset = track->db_s_read_offset << 8;
612 if (offset & (surf.base_align - 1)) {
613 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
614 __func__, __LINE__, offset, surf.base_align);
617 offset += surf.layer_size * mslice;
618 if (offset > radeon_bo_size(track->db_s_read_bo)) {
619 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
620 "offset %ld, max layer %d, bo size %ld)\n",
621 __func__, __LINE__, surf.layer_size,
622 (unsigned long)track->db_s_read_offset << 8, mslice,
623 radeon_bo_size(track->db_s_read_bo));
624 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
625 __func__, __LINE__, track->db_depth_size,
626 track->db_depth_slice, track->db_s_info, track->db_z_info);
630 offset = track->db_s_write_offset << 8;
631 if (offset & (surf.base_align - 1)) {
632 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
633 __func__, __LINE__, offset, surf.base_align);
636 offset += surf.layer_size * mslice;
637 if (offset > radeon_bo_size(track->db_s_write_bo)) {
638 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
639 "offset %ld, max layer %d, bo size %ld)\n",
640 __func__, __LINE__, surf.layer_size,
641 (unsigned long)track->db_s_write_offset << 8, mslice,
642 radeon_bo_size(track->db_s_write_bo));
647 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
648 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
657 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
659 struct evergreen_cs_track *track = p->track;
660 struct eg_surface surf;
661 unsigned pitch, slice, mslice;
662 unsigned long offset;
665 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
666 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
667 slice = track->db_depth_slice;
668 surf.nbx = (pitch + 1) * 8;
669 surf.nby = ((slice + 1) * 64) / surf.nbx;
670 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
671 surf.format = G_028040_FORMAT(track->db_z_info);
672 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
673 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
674 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
675 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
676 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
679 switch (surf.format) {
681 surf.format = V_028C70_COLOR_16;
684 case V_028040_Z_32_FLOAT:
685 surf.format = V_028C70_COLOR_8_8_8_8;
688 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
689 __func__, __LINE__, surf.format);
693 r = evergreen_surface_value_conv_check(p, &surf, "depth");
695 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
696 __func__, __LINE__, track->db_depth_size,
697 track->db_depth_slice, track->db_z_info);
701 r = evergreen_surface_check(p, &surf, "depth");
703 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
704 __func__, __LINE__, track->db_depth_size,
705 track->db_depth_slice, track->db_z_info);
709 offset = track->db_z_read_offset << 8;
710 if (offset & (surf.base_align - 1)) {
711 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
712 __func__, __LINE__, offset, surf.base_align);
715 offset += surf.layer_size * mslice;
716 if (offset > radeon_bo_size(track->db_z_read_bo)) {
717 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
718 "offset %ld, max layer %d, bo size %ld)\n",
719 __func__, __LINE__, surf.layer_size,
720 (unsigned long)track->db_z_read_offset << 8, mslice,
721 radeon_bo_size(track->db_z_read_bo));
725 offset = track->db_z_write_offset << 8;
726 if (offset & (surf.base_align - 1)) {
727 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
728 __func__, __LINE__, offset, surf.base_align);
731 offset += surf.layer_size * mslice;
732 if (offset > radeon_bo_size(track->db_z_write_bo)) {
733 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
734 "offset %ld, max layer %d, bo size %ld)\n",
735 __func__, __LINE__, surf.layer_size,
736 (unsigned long)track->db_z_write_offset << 8, mslice,
737 radeon_bo_size(track->db_z_write_bo));
742 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
743 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
752 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
753 struct radeon_bo *texture,
754 struct radeon_bo *mipmap,
757 struct eg_surface surf;
758 unsigned long toffset, moffset;
759 unsigned dim, llevel, mslice, width, height, depth, i;
763 texdw[0] = radeon_get_ib_value(p, idx + 0);
764 texdw[1] = radeon_get_ib_value(p, idx + 1);
765 texdw[2] = radeon_get_ib_value(p, idx + 2);
766 texdw[3] = radeon_get_ib_value(p, idx + 3);
767 texdw[4] = radeon_get_ib_value(p, idx + 4);
768 texdw[5] = radeon_get_ib_value(p, idx + 5);
769 texdw[6] = radeon_get_ib_value(p, idx + 6);
770 texdw[7] = radeon_get_ib_value(p, idx + 7);
771 dim = G_030000_DIM(texdw[0]);
772 llevel = G_030014_LAST_LEVEL(texdw[5]);
773 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
774 width = G_030000_TEX_WIDTH(texdw[0]) + 1;
775 height = G_030004_TEX_HEIGHT(texdw[1]) + 1;
776 depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
777 surf.format = G_03001C_DATA_FORMAT(texdw[7]);
778 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
779 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
780 surf.nby = r600_fmt_get_nblocksy(surf.format, height);
781 surf.mode = G_030004_ARRAY_MODE(texdw[1]);
782 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
783 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
784 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
785 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
786 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
788 toffset = texdw[2] << 8;
789 moffset = texdw[3] << 8;
791 if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
792 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
793 __func__, __LINE__, surf.format);
797 case V_030000_SQ_TEX_DIM_1D:
798 case V_030000_SQ_TEX_DIM_2D:
799 case V_030000_SQ_TEX_DIM_CUBEMAP:
800 case V_030000_SQ_TEX_DIM_1D_ARRAY:
801 case V_030000_SQ_TEX_DIM_2D_ARRAY:
804 case V_030000_SQ_TEX_DIM_2D_MSAA:
805 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
806 surf.nsamples = 1 << llevel;
810 case V_030000_SQ_TEX_DIM_3D:
813 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
814 __func__, __LINE__, dim);
818 r = evergreen_surface_value_conv_check(p, &surf, "texture");
824 evergreen_surface_check(p, &surf, NULL);
825 surf.nby = ALIGN(surf.nby, surf.halign);
827 r = evergreen_surface_check(p, &surf, "texture");
829 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
830 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
831 texdw[5], texdw[6], texdw[7]);
835 /* check texture size */
836 if (toffset & (surf.base_align - 1)) {
837 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
838 __func__, __LINE__, toffset, surf.base_align);
841 if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) {
842 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
843 __func__, __LINE__, moffset, surf.base_align);
846 if (dim == SQ_TEX_DIM_3D) {
847 toffset += surf.layer_size * depth;
849 toffset += surf.layer_size * mslice;
851 if (toffset > radeon_bo_size(texture)) {
852 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
853 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
854 __func__, __LINE__, surf.layer_size,
855 (unsigned long)texdw[2] << 8, mslice,
856 depth, radeon_bo_size(texture),
863 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
867 return 0; /* everything's ok */
871 /* check mipmap size */
872 for (i = 1; i <= llevel; i++) {
875 w = r600_mip_minify(width, i);
876 h = r600_mip_minify(height, i);
877 d = r600_mip_minify(depth, i);
878 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
879 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
882 case ARRAY_2D_TILED_THIN1:
883 if (surf.nbx < surf.palign || surf.nby < surf.halign) {
884 surf.mode = ARRAY_1D_TILED_THIN1;
886 /* recompute alignment */
887 evergreen_surface_check(p, &surf, NULL);
889 case ARRAY_LINEAR_GENERAL:
890 case ARRAY_LINEAR_ALIGNED:
891 case ARRAY_1D_TILED_THIN1:
894 dev_warn(p->dev, "%s:%d invalid array mode %d\n",
895 __func__, __LINE__, surf.mode);
898 surf.nbx = ALIGN(surf.nbx, surf.palign);
899 surf.nby = ALIGN(surf.nby, surf.halign);
901 r = evergreen_surface_check(p, &surf, "mipmap");
906 if (dim == SQ_TEX_DIM_3D) {
907 moffset += surf.layer_size * d;
909 moffset += surf.layer_size * mslice;
911 if (moffset > radeon_bo_size(mipmap)) {
912 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
913 "offset %ld, coffset %ld, max layer %d, depth %d, "
914 "bo size %ld) level0 (%d %d %d)\n",
915 __func__, __LINE__, i, surf.layer_size,
916 (unsigned long)texdw[3] << 8, moffset, mslice,
917 d, radeon_bo_size(mipmap),
918 width, height, depth);
919 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
920 __func__, __LINE__, surf.nbx, surf.nby,
921 surf.mode, surf.bpe, surf.nsamples,
922 surf.bankw, surf.bankh,
923 surf.tsplit, surf.mtilea);
931 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
933 struct evergreen_cs_track *track = p->track;
936 unsigned buffer_mask = 0;
938 /* check streamout */
939 if (track->streamout_dirty && track->vgt_strmout_config) {
940 for (i = 0; i < 4; i++) {
941 if (track->vgt_strmout_config & (1 << i)) {
942 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
946 for (i = 0; i < 4; i++) {
947 if (buffer_mask & (1 << i)) {
948 if (track->vgt_strmout_bo[i]) {
949 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
950 (u64)track->vgt_strmout_size[i];
951 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
952 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
954 radeon_bo_size(track->vgt_strmout_bo[i]));
958 dev_warn(p->dev, "No buffer for streamout %d\n", i);
963 track->streamout_dirty = false;
966 if (track->sx_misc_kill_all_prims)
969 /* check that we have a cb for each enabled target
971 if (track->cb_dirty) {
972 tmp = track->cb_target_mask;
973 for (i = 0; i < 8; i++) {
974 u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
976 if (format != V_028C70_COLOR_INVALID &&
977 (tmp >> (i * 4)) & 0xF) {
978 /* at least one component is enabled */
979 if (track->cb_color_bo[i] == NULL) {
980 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
981 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
985 r = evergreen_cs_track_validate_cb(p, i);
991 track->cb_dirty = false;
994 if (track->db_dirty) {
995 /* Check stencil buffer */
996 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
997 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
998 r = evergreen_cs_track_validate_stencil(p);
1002 /* Check depth buffer */
1003 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
1004 G_028800_Z_ENABLE(track->db_depth_control)) {
1005 r = evergreen_cs_track_validate_depth(p);
1009 track->db_dirty = false;
1016 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
1017 * @parser: parser structure holding parsing context.
1019 * This is an Evergreen(+)-specific function for parsing VLINE packets.
1020 * Real work is done by r600_cs_common_vline_parse function.
1021 * Here we just set up ASIC-specific register table and call
1022 * the common implementation function.
1024 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1027 static uint32_t vline_start_end[6] = {
1028 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
1029 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,
1030 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,
1031 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,
1032 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
1033 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
1035 static uint32_t vline_status[6] = {
1036 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1037 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1038 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1039 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1040 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1041 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
1044 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
1047 static int evergreen_packet0_check(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt,
1049 unsigned idx, unsigned reg)
1054 case EVERGREEN_VLINE_START_END:
1055 r = evergreen_cs_packet_parse_vline(p);
1057 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1063 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1070 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1071 struct radeon_cs_packet *pkt)
1079 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1080 r = evergreen_packet0_check(p, pkt, idx, reg);
1089 * evergreen_cs_handle_reg() - process registers that need special handling.
1090 * @parser: parser structure holding parsing context
1091 * @reg: register we are testing
1092 * @idx: index into the cs buffer
1094 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1096 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1097 struct radeon_bo_list *reloc;
1103 /* force following reg to 0 in an attempt to disable out buffer
1104 * which will need us to better understand how it works to perform
1105 * security check on it (Jerome)
1107 case SQ_ESGS_RING_SIZE:
1108 case SQ_GSVS_RING_SIZE:
1109 case SQ_ESTMP_RING_SIZE:
1110 case SQ_GSTMP_RING_SIZE:
1111 case SQ_HSTMP_RING_SIZE:
1112 case SQ_LSTMP_RING_SIZE:
1113 case SQ_PSTMP_RING_SIZE:
1114 case SQ_VSTMP_RING_SIZE:
1115 case SQ_ESGS_RING_ITEMSIZE:
1116 case SQ_ESTMP_RING_ITEMSIZE:
1117 case SQ_GSTMP_RING_ITEMSIZE:
1118 case SQ_GSVS_RING_ITEMSIZE:
1119 case SQ_GS_VERT_ITEMSIZE:
1120 case SQ_GS_VERT_ITEMSIZE_1:
1121 case SQ_GS_VERT_ITEMSIZE_2:
1122 case SQ_GS_VERT_ITEMSIZE_3:
1123 case SQ_GSVS_RING_OFFSET_1:
1124 case SQ_GSVS_RING_OFFSET_2:
1125 case SQ_GSVS_RING_OFFSET_3:
1126 case SQ_HSTMP_RING_ITEMSIZE:
1127 case SQ_LSTMP_RING_ITEMSIZE:
1128 case SQ_PSTMP_RING_ITEMSIZE:
1129 case SQ_VSTMP_RING_ITEMSIZE:
1130 case VGT_TF_RING_SIZE:
1131 /* get value to populate the IB don't remove */
1132 /*tmp =radeon_get_ib_value(p, idx);
1135 case SQ_ESGS_RING_BASE:
1136 case SQ_GSVS_RING_BASE:
1137 case SQ_ESTMP_RING_BASE:
1138 case SQ_GSTMP_RING_BASE:
1139 case SQ_HSTMP_RING_BASE:
1140 case SQ_LSTMP_RING_BASE:
1141 case SQ_PSTMP_RING_BASE:
1142 case SQ_VSTMP_RING_BASE:
1143 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1145 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1151 case DB_DEPTH_CONTROL:
1152 track->db_depth_control = radeon_get_ib_value(p, idx);
1153 track->db_dirty = true;
1155 case CAYMAN_DB_EQAA:
1156 if (p->rdev->family < CHIP_CAYMAN) {
1157 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1162 case CAYMAN_DB_DEPTH_INFO:
1163 if (p->rdev->family < CHIP_CAYMAN) {
1164 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1170 track->db_z_info = radeon_get_ib_value(p, idx);
1171 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1172 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1174 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1178 ib[idx] &= ~Z_ARRAY_MODE(0xf);
1179 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1183 unsigned bankw, bankh, mtaspect, tile_split;
1185 evergreen_tiling_fields(reloc->tiling_flags,
1186 &bankw, &bankh, &mtaspect,
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1189 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1190 DB_BANK_WIDTH(bankw) |
1191 DB_BANK_HEIGHT(bankh) |
1192 DB_MACRO_TILE_ASPECT(mtaspect);
1195 track->db_dirty = true;
1197 case DB_STENCIL_INFO:
1198 track->db_s_info = radeon_get_ib_value(p, idx);
1199 track->db_dirty = true;
1202 track->db_depth_view = radeon_get_ib_value(p, idx);
1203 track->db_dirty = true;
1206 track->db_depth_size = radeon_get_ib_value(p, idx);
1207 track->db_dirty = true;
1209 case R_02805C_DB_DEPTH_SLICE:
1210 track->db_depth_slice = radeon_get_ib_value(p, idx);
1211 track->db_dirty = true;
1213 case DB_Z_READ_BASE:
1214 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1216 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1220 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1222 track->db_z_read_bo = reloc->robj;
1223 track->db_dirty = true;
1225 case DB_Z_WRITE_BASE:
1226 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1228 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1232 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1234 track->db_z_write_bo = reloc->robj;
1235 track->db_dirty = true;
1237 case DB_STENCIL_READ_BASE:
1238 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1240 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1244 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1246 track->db_s_read_bo = reloc->robj;
1247 track->db_dirty = true;
1249 case DB_STENCIL_WRITE_BASE:
1250 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1252 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1256 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1258 track->db_s_write_bo = reloc->robj;
1259 track->db_dirty = true;
1261 case VGT_STRMOUT_CONFIG:
1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1263 track->streamout_dirty = true;
1265 case VGT_STRMOUT_BUFFER_CONFIG:
1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1267 track->streamout_dirty = true;
1269 case VGT_STRMOUT_BUFFER_BASE_0:
1270 case VGT_STRMOUT_BUFFER_BASE_1:
1271 case VGT_STRMOUT_BUFFER_BASE_2:
1272 case VGT_STRMOUT_BUFFER_BASE_3:
1273 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1275 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1279 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1282 track->vgt_strmout_bo[tmp] = reloc->robj;
1283 track->streamout_dirty = true;
1285 case VGT_STRMOUT_BUFFER_SIZE_0:
1286 case VGT_STRMOUT_BUFFER_SIZE_1:
1287 case VGT_STRMOUT_BUFFER_SIZE_2:
1288 case VGT_STRMOUT_BUFFER_SIZE_3:
1289 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1290 /* size in register is DWs, convert to bytes */
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1292 track->streamout_dirty = true;
1295 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1297 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1302 case CB_TARGET_MASK:
1303 track->cb_target_mask = radeon_get_ib_value(p, idx);
1304 track->cb_dirty = true;
1306 case CB_SHADER_MASK:
1307 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1308 track->cb_dirty = true;
1310 case PA_SC_AA_CONFIG:
1311 if (p->rdev->family >= CHIP_CAYMAN) {
1312 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1316 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1317 track->nsamples = 1 << tmp;
1319 case CAYMAN_PA_SC_AA_CONFIG:
1320 if (p->rdev->family < CHIP_CAYMAN) {
1321 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1325 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1326 track->nsamples = 1 << tmp;
1328 case CB_COLOR0_VIEW:
1329 case CB_COLOR1_VIEW:
1330 case CB_COLOR2_VIEW:
1331 case CB_COLOR3_VIEW:
1332 case CB_COLOR4_VIEW:
1333 case CB_COLOR5_VIEW:
1334 case CB_COLOR6_VIEW:
1335 case CB_COLOR7_VIEW:
1336 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1338 track->cb_dirty = true;
1340 case CB_COLOR8_VIEW:
1341 case CB_COLOR9_VIEW:
1342 case CB_COLOR10_VIEW:
1343 case CB_COLOR11_VIEW:
1344 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1346 track->cb_dirty = true;
1348 case CB_COLOR0_INFO:
1349 case CB_COLOR1_INFO:
1350 case CB_COLOR2_INFO:
1351 case CB_COLOR3_INFO:
1352 case CB_COLOR4_INFO:
1353 case CB_COLOR5_INFO:
1354 case CB_COLOR6_INFO:
1355 case CB_COLOR7_INFO:
1356 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1358 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1359 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1361 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1368 track->cb_dirty = true;
1370 case CB_COLOR8_INFO:
1371 case CB_COLOR9_INFO:
1372 case CB_COLOR10_INFO:
1373 case CB_COLOR11_INFO:
1374 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1376 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1377 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1379 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1384 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
1386 track->cb_dirty = true;
1388 case CB_COLOR0_PITCH:
1389 case CB_COLOR1_PITCH:
1390 case CB_COLOR2_PITCH:
1391 case CB_COLOR3_PITCH:
1392 case CB_COLOR4_PITCH:
1393 case CB_COLOR5_PITCH:
1394 case CB_COLOR6_PITCH:
1395 case CB_COLOR7_PITCH:
1396 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1398 track->cb_dirty = true;
1400 case CB_COLOR8_PITCH:
1401 case CB_COLOR9_PITCH:
1402 case CB_COLOR10_PITCH:
1403 case CB_COLOR11_PITCH:
1404 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1406 track->cb_dirty = true;
1408 case CB_COLOR0_SLICE:
1409 case CB_COLOR1_SLICE:
1410 case CB_COLOR2_SLICE:
1411 case CB_COLOR3_SLICE:
1412 case CB_COLOR4_SLICE:
1413 case CB_COLOR5_SLICE:
1414 case CB_COLOR6_SLICE:
1415 case CB_COLOR7_SLICE:
1416 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1418 track->cb_color_slice_idx[tmp] = idx;
1419 track->cb_dirty = true;
1421 case CB_COLOR8_SLICE:
1422 case CB_COLOR9_SLICE:
1423 case CB_COLOR10_SLICE:
1424 case CB_COLOR11_SLICE:
1425 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1427 track->cb_color_slice_idx[tmp] = idx;
1428 track->cb_dirty = true;
1430 case CB_COLOR0_ATTRIB:
1431 case CB_COLOR1_ATTRIB:
1432 case CB_COLOR2_ATTRIB:
1433 case CB_COLOR3_ATTRIB:
1434 case CB_COLOR4_ATTRIB:
1435 case CB_COLOR5_ATTRIB:
1436 case CB_COLOR6_ATTRIB:
1437 case CB_COLOR7_ATTRIB:
1438 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1440 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1444 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1446 unsigned bankw, bankh, mtaspect, tile_split;
1448 evergreen_tiling_fields(reloc->tiling_flags,
1449 &bankw, &bankh, &mtaspect,
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1453 CB_BANK_WIDTH(bankw) |
1454 CB_BANK_HEIGHT(bankh) |
1455 CB_MACRO_TILE_ASPECT(mtaspect);
1458 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1459 track->cb_color_attrib[tmp] = ib[idx];
1460 track->cb_dirty = true;
1462 case CB_COLOR8_ATTRIB:
1463 case CB_COLOR9_ATTRIB:
1464 case CB_COLOR10_ATTRIB:
1465 case CB_COLOR11_ATTRIB:
1466 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1468 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1472 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1474 unsigned bankw, bankh, mtaspect, tile_split;
1476 evergreen_tiling_fields(reloc->tiling_flags,
1477 &bankw, &bankh, &mtaspect,
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1481 CB_BANK_WIDTH(bankw) |
1482 CB_BANK_HEIGHT(bankh) |
1483 CB_MACRO_TILE_ASPECT(mtaspect);
1486 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1487 track->cb_color_attrib[tmp] = ib[idx];
1488 track->cb_dirty = true;
1490 case CB_COLOR0_FMASK:
1491 case CB_COLOR1_FMASK:
1492 case CB_COLOR2_FMASK:
1493 case CB_COLOR3_FMASK:
1494 case CB_COLOR4_FMASK:
1495 case CB_COLOR5_FMASK:
1496 case CB_COLOR6_FMASK:
1497 case CB_COLOR7_FMASK:
1498 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1499 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1501 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1505 track->cb_color_fmask_bo[tmp] = reloc->robj;
1507 case CB_COLOR0_CMASK:
1508 case CB_COLOR1_CMASK:
1509 case CB_COLOR2_CMASK:
1510 case CB_COLOR3_CMASK:
1511 case CB_COLOR4_CMASK:
1512 case CB_COLOR5_CMASK:
1513 case CB_COLOR6_CMASK:
1514 case CB_COLOR7_CMASK:
1515 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1516 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1518 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1522 track->cb_color_cmask_bo[tmp] = reloc->robj;
1524 case CB_COLOR0_FMASK_SLICE:
1525 case CB_COLOR1_FMASK_SLICE:
1526 case CB_COLOR2_FMASK_SLICE:
1527 case CB_COLOR3_FMASK_SLICE:
1528 case CB_COLOR4_FMASK_SLICE:
1529 case CB_COLOR5_FMASK_SLICE:
1530 case CB_COLOR6_FMASK_SLICE:
1531 case CB_COLOR7_FMASK_SLICE:
1532 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1535 case CB_COLOR0_CMASK_SLICE:
1536 case CB_COLOR1_CMASK_SLICE:
1537 case CB_COLOR2_CMASK_SLICE:
1538 case CB_COLOR3_CMASK_SLICE:
1539 case CB_COLOR4_CMASK_SLICE:
1540 case CB_COLOR5_CMASK_SLICE:
1541 case CB_COLOR6_CMASK_SLICE:
1542 case CB_COLOR7_CMASK_SLICE:
1543 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1546 case CB_COLOR0_BASE:
1547 case CB_COLOR1_BASE:
1548 case CB_COLOR2_BASE:
1549 case CB_COLOR3_BASE:
1550 case CB_COLOR4_BASE:
1551 case CB_COLOR5_BASE:
1552 case CB_COLOR6_BASE:
1553 case CB_COLOR7_BASE:
1554 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1556 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1560 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1563 track->cb_color_bo[tmp] = reloc->robj;
1564 track->cb_dirty = true;
1566 case CB_COLOR8_BASE:
1567 case CB_COLOR9_BASE:
1568 case CB_COLOR10_BASE:
1569 case CB_COLOR11_BASE:
1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1572 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1576 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1579 track->cb_color_bo[tmp] = reloc->robj;
1580 track->cb_dirty = true;
1582 case DB_HTILE_DATA_BASE:
1583 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1585 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1589 track->htile_offset = radeon_get_ib_value(p, idx);
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1591 track->htile_bo = reloc->robj;
1592 track->db_dirty = true;
1594 case DB_HTILE_SURFACE:
1596 track->htile_surface = radeon_get_ib_value(p, idx);
1597 /* force 8x8 htile width and height */
1599 track->db_dirty = true;
1601 case CB_IMMED0_BASE:
1602 case CB_IMMED1_BASE:
1603 case CB_IMMED2_BASE:
1604 case CB_IMMED3_BASE:
1605 case CB_IMMED4_BASE:
1606 case CB_IMMED5_BASE:
1607 case CB_IMMED6_BASE:
1608 case CB_IMMED7_BASE:
1609 case CB_IMMED8_BASE:
1610 case CB_IMMED9_BASE:
1611 case CB_IMMED10_BASE:
1612 case CB_IMMED11_BASE:
1613 case SQ_PGM_START_FS:
1614 case SQ_PGM_START_ES:
1615 case SQ_PGM_START_VS:
1616 case SQ_PGM_START_GS:
1617 case SQ_PGM_START_PS:
1618 case SQ_PGM_START_HS:
1619 case SQ_PGM_START_LS:
1620 case SQ_CONST_MEM_BASE:
1621 case SQ_ALU_CONST_CACHE_GS_0:
1622 case SQ_ALU_CONST_CACHE_GS_1:
1623 case SQ_ALU_CONST_CACHE_GS_2:
1624 case SQ_ALU_CONST_CACHE_GS_3:
1625 case SQ_ALU_CONST_CACHE_GS_4:
1626 case SQ_ALU_CONST_CACHE_GS_5:
1627 case SQ_ALU_CONST_CACHE_GS_6:
1628 case SQ_ALU_CONST_CACHE_GS_7:
1629 case SQ_ALU_CONST_CACHE_GS_8:
1630 case SQ_ALU_CONST_CACHE_GS_9:
1631 case SQ_ALU_CONST_CACHE_GS_10:
1632 case SQ_ALU_CONST_CACHE_GS_11:
1633 case SQ_ALU_CONST_CACHE_GS_12:
1634 case SQ_ALU_CONST_CACHE_GS_13:
1635 case SQ_ALU_CONST_CACHE_GS_14:
1636 case SQ_ALU_CONST_CACHE_GS_15:
1637 case SQ_ALU_CONST_CACHE_PS_0:
1638 case SQ_ALU_CONST_CACHE_PS_1:
1639 case SQ_ALU_CONST_CACHE_PS_2:
1640 case SQ_ALU_CONST_CACHE_PS_3:
1641 case SQ_ALU_CONST_CACHE_PS_4:
1642 case SQ_ALU_CONST_CACHE_PS_5:
1643 case SQ_ALU_CONST_CACHE_PS_6:
1644 case SQ_ALU_CONST_CACHE_PS_7:
1645 case SQ_ALU_CONST_CACHE_PS_8:
1646 case SQ_ALU_CONST_CACHE_PS_9:
1647 case SQ_ALU_CONST_CACHE_PS_10:
1648 case SQ_ALU_CONST_CACHE_PS_11:
1649 case SQ_ALU_CONST_CACHE_PS_12:
1650 case SQ_ALU_CONST_CACHE_PS_13:
1651 case SQ_ALU_CONST_CACHE_PS_14:
1652 case SQ_ALU_CONST_CACHE_PS_15:
1653 case SQ_ALU_CONST_CACHE_VS_0:
1654 case SQ_ALU_CONST_CACHE_VS_1:
1655 case SQ_ALU_CONST_CACHE_VS_2:
1656 case SQ_ALU_CONST_CACHE_VS_3:
1657 case SQ_ALU_CONST_CACHE_VS_4:
1658 case SQ_ALU_CONST_CACHE_VS_5:
1659 case SQ_ALU_CONST_CACHE_VS_6:
1660 case SQ_ALU_CONST_CACHE_VS_7:
1661 case SQ_ALU_CONST_CACHE_VS_8:
1662 case SQ_ALU_CONST_CACHE_VS_9:
1663 case SQ_ALU_CONST_CACHE_VS_10:
1664 case SQ_ALU_CONST_CACHE_VS_11:
1665 case SQ_ALU_CONST_CACHE_VS_12:
1666 case SQ_ALU_CONST_CACHE_VS_13:
1667 case SQ_ALU_CONST_CACHE_VS_14:
1668 case SQ_ALU_CONST_CACHE_VS_15:
1669 case SQ_ALU_CONST_CACHE_HS_0:
1670 case SQ_ALU_CONST_CACHE_HS_1:
1671 case SQ_ALU_CONST_CACHE_HS_2:
1672 case SQ_ALU_CONST_CACHE_HS_3:
1673 case SQ_ALU_CONST_CACHE_HS_4:
1674 case SQ_ALU_CONST_CACHE_HS_5:
1675 case SQ_ALU_CONST_CACHE_HS_6:
1676 case SQ_ALU_CONST_CACHE_HS_7:
1677 case SQ_ALU_CONST_CACHE_HS_8:
1678 case SQ_ALU_CONST_CACHE_HS_9:
1679 case SQ_ALU_CONST_CACHE_HS_10:
1680 case SQ_ALU_CONST_CACHE_HS_11:
1681 case SQ_ALU_CONST_CACHE_HS_12:
1682 case SQ_ALU_CONST_CACHE_HS_13:
1683 case SQ_ALU_CONST_CACHE_HS_14:
1684 case SQ_ALU_CONST_CACHE_HS_15:
1685 case SQ_ALU_CONST_CACHE_LS_0:
1686 case SQ_ALU_CONST_CACHE_LS_1:
1687 case SQ_ALU_CONST_CACHE_LS_2:
1688 case SQ_ALU_CONST_CACHE_LS_3:
1689 case SQ_ALU_CONST_CACHE_LS_4:
1690 case SQ_ALU_CONST_CACHE_LS_5:
1691 case SQ_ALU_CONST_CACHE_LS_6:
1692 case SQ_ALU_CONST_CACHE_LS_7:
1693 case SQ_ALU_CONST_CACHE_LS_8:
1694 case SQ_ALU_CONST_CACHE_LS_9:
1695 case SQ_ALU_CONST_CACHE_LS_10:
1696 case SQ_ALU_CONST_CACHE_LS_11:
1697 case SQ_ALU_CONST_CACHE_LS_12:
1698 case SQ_ALU_CONST_CACHE_LS_13:
1699 case SQ_ALU_CONST_CACHE_LS_14:
1700 case SQ_ALU_CONST_CACHE_LS_15:
1701 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1703 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1709 case SX_MEMORY_EXPORT_BASE:
1710 if (p->rdev->family >= CHIP_CAYMAN) {
1711 dev_warn(p->dev, "bad SET_CONFIG_REG "
1715 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1717 dev_warn(p->dev, "bad SET_CONFIG_REG "
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1723 case CAYMAN_SX_SCATTER_EXPORT_BASE:
1724 if (p->rdev->family < CHIP_CAYMAN) {
1725 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1729 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1731 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1741 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1748 * evergreen_is_safe_reg() - check if register is authorized or not
1749 * @parser: parser structure holding parsing context
1750 * @reg: register we are testing
1752 * This function will test against reg_safe_bm and return true
1753 * if register is safe or false otherwise.
1755 static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)
1757 struct evergreen_cs_track *track = p->track;
1761 if (unlikely(i >= REG_SAFE_BM_SIZE)) {
1764 m = 1 << ((reg >> 2) & 31);
1765 if (!(track->reg_safe_bm[i] & m))
1771 static int evergreen_packet3_check(struct radeon_cs_parser *p,
1772 struct radeon_cs_packet *pkt)
1774 struct radeon_bo_list *reloc;
1775 struct evergreen_cs_track *track;
1779 unsigned start_reg, end_reg, reg;
1783 track = (struct evergreen_cs_track *)p->track;
1786 idx_value = radeon_get_ib_value(p, idx);
1788 switch (pkt->opcode) {
1789 case PACKET3_SET_PREDICATION:
1795 if (pkt->count != 1) {
1796 DRM_ERROR("bad SET PREDICATION\n");
1800 tmp = radeon_get_ib_value(p, idx + 1);
1801 pred_op = (tmp >> 16) & 0x7;
1803 /* for the clear predicate operation */
1808 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1812 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1814 DRM_ERROR("bad SET PREDICATION\n");
1818 offset = reloc->gpu_offset +
1819 (idx_value & 0xfffffff0) +
1820 ((u64)(tmp & 0xff) << 32);
1822 ib[idx + 0] = offset;
1823 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1826 case PACKET3_CONTEXT_CONTROL:
1827 if (pkt->count != 1) {
1828 DRM_ERROR("bad CONTEXT_CONTROL\n");
1832 case PACKET3_INDEX_TYPE:
1833 case PACKET3_NUM_INSTANCES:
1834 case PACKET3_CLEAR_STATE:
1836 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1840 case CAYMAN_PACKET3_DEALLOC_STATE:
1841 if (p->rdev->family < CHIP_CAYMAN) {
1842 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1846 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1850 case PACKET3_INDEX_BASE:
1854 if (pkt->count != 1) {
1855 DRM_ERROR("bad INDEX_BASE\n");
1858 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1860 DRM_ERROR("bad INDEX_BASE\n");
1864 offset = reloc->gpu_offset +
1866 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1869 ib[idx+1] = upper_32_bits(offset) & 0xff;
1871 r = evergreen_cs_track_check(p);
1873 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1878 case PACKET3_INDEX_BUFFER_SIZE:
1880 if (pkt->count != 0) {
1881 DRM_ERROR("bad INDEX_BUFFER_SIZE\n");
1886 case PACKET3_DRAW_INDEX:
1889 if (pkt->count != 3) {
1890 DRM_ERROR("bad DRAW_INDEX\n");
1893 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1895 DRM_ERROR("bad DRAW_INDEX\n");
1899 offset = reloc->gpu_offset +
1901 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1904 ib[idx+1] = upper_32_bits(offset) & 0xff;
1906 r = evergreen_cs_track_check(p);
1908 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1913 case PACKET3_DRAW_INDEX_2:
1917 if (pkt->count != 4) {
1918 DRM_ERROR("bad DRAW_INDEX_2\n");
1921 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1923 DRM_ERROR("bad DRAW_INDEX_2\n");
1927 offset = reloc->gpu_offset +
1928 radeon_get_ib_value(p, idx+1) +
1929 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1932 ib[idx+2] = upper_32_bits(offset) & 0xff;
1934 r = evergreen_cs_track_check(p);
1936 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1941 case PACKET3_DRAW_INDEX_AUTO:
1942 if (pkt->count != 1) {
1943 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1946 r = evergreen_cs_track_check(p);
1948 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1952 case PACKET3_DRAW_INDEX_MULTI_AUTO:
1953 if (pkt->count != 2) {
1954 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1957 r = evergreen_cs_track_check(p);
1959 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1963 case PACKET3_DRAW_INDEX_IMMD:
1964 if (pkt->count < 2) {
1965 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1968 r = evergreen_cs_track_check(p);
1970 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1974 case PACKET3_DRAW_INDEX_OFFSET:
1975 if (pkt->count != 2) {
1976 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1979 r = evergreen_cs_track_check(p);
1981 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1985 case PACKET3_DRAW_INDEX_OFFSET_2:
1986 if (pkt->count != 3) {
1987 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
1990 r = evergreen_cs_track_check(p);
1992 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1996 case PACKET3_SET_BASE:
1999 DW 1 HEADER Header of the packet. Shader_Type in bit 1 of the Header will correspond to the shader type of the Load, see Type-3 Packet.
2000 2 BASE_INDEX Bits [3:0] BASE_INDEX - Base Index specifies which base address is specified in the last two DWs.
2001 0001: DX11 Draw_Index_Indirect Patch Table Base: Base address for Draw_Index_Indirect data.
2002 3 ADDRESS_LO Bits [31:3] - Lower bits of QWORD-Aligned Address. Bits [2:0] - Reserved
2003 4 ADDRESS_HI Bits [31:8] - Reserved. Bits [7:0] - Upper bits of Address [47:32]
2005 if (pkt->count != 2) {
2006 DRM_ERROR("bad SET_BASE\n");
2010 /* currently only supporting setting indirect draw buffer base address */
2011 if (idx_value != 1) {
2012 DRM_ERROR("bad SET_BASE\n");
2016 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2018 DRM_ERROR("bad SET_BASE\n");
2022 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj);
2024 ib[idx+1] = reloc->gpu_offset;
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;
2029 case PACKET3_DRAW_INDIRECT:
2030 case PACKET3_DRAW_INDEX_INDIRECT:
2032 u64 size = pkt->opcode == PACKET3_DRAW_INDIRECT ? 16 : 20;
2036 2 DATA_OFFSET Bits [31:0] + byte aligned offset where the required data structure starts. Bits 1:0 are zero
2037 3 DRAW_INITIATOR Draw Initiator Register. Written to the VGT_DRAW_INITIATOR register for the assigned context
2039 if (pkt->count != 1) {
2040 DRM_ERROR("bad DRAW_INDIRECT\n");
2044 if (idx_value + size > track->indirect_draw_buffer_size) {
2045 dev_warn(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n",
2046 idx_value, size, track->indirect_draw_buffer_size);
2050 r = evergreen_cs_track_check(p);
2052 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2057 case PACKET3_DISPATCH_DIRECT:
2058 if (pkt->count != 3) {
2059 DRM_ERROR("bad DISPATCH_DIRECT\n");
2062 r = evergreen_cs_track_check(p);
2064 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2068 case PACKET3_DISPATCH_INDIRECT:
2069 if (pkt->count != 1) {
2070 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2073 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2075 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
2079 r = evergreen_cs_track_check(p);
2081 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2085 case PACKET3_WAIT_REG_MEM:
2086 if (pkt->count != 5) {
2087 DRM_ERROR("bad WAIT_REG_MEM\n");
2090 /* bit 4 is reg (0) or mem (1) */
2091 if (idx_value & 0x10) {
2094 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2096 DRM_ERROR("bad WAIT_REG_MEM\n");
2100 offset = reloc->gpu_offset +
2101 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2102 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2104 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2105 ib[idx+2] = upper_32_bits(offset) & 0xff;
2106 } else if (idx_value & 0x100) {
2107 DRM_ERROR("cannot use PFP on REG wait\n");
2111 case PACKET3_CP_DMA:
2113 u32 command, size, info;
2115 if (pkt->count != 4) {
2116 DRM_ERROR("bad CP DMA\n");
2119 command = radeon_get_ib_value(p, idx+4);
2120 size = command & 0x1fffff;
2121 info = radeon_get_ib_value(p, idx+1);
2122 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
2123 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
2124 ((((info & 0x00300000) >> 20) == 0) &&
2125 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
2126 ((((info & 0x60000000) >> 29) == 0) &&
2127 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
2128 /* non mem to mem copies requires dw aligned count */
2130 DRM_ERROR("CP DMA command requires dw count alignment\n");
2134 if (command & PACKET3_CP_DMA_CMD_SAS) {
2135 /* src address space is register */
2137 if (((info & 0x60000000) >> 29) != 1) {
2138 DRM_ERROR("CP DMA SAS not supported\n");
2142 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2143 DRM_ERROR("CP DMA SAIC only supported for registers\n");
2146 /* src address space is memory */
2147 if (((info & 0x60000000) >> 29) == 0) {
2148 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2150 DRM_ERROR("bad CP DMA SRC\n");
2154 tmp = radeon_get_ib_value(p, idx) +
2155 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2157 offset = reloc->gpu_offset + tmp;
2159 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2160 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
2161 tmp + size, radeon_bo_size(reloc->robj));
2166 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2167 } else if (((info & 0x60000000) >> 29) != 2) {
2168 DRM_ERROR("bad CP DMA SRC_SEL\n");
2172 if (command & PACKET3_CP_DMA_CMD_DAS) {
2173 /* dst address space is register */
2175 if (((info & 0x00300000) >> 20) != 1) {
2176 DRM_ERROR("CP DMA DAS not supported\n");
2180 /* dst address space is memory */
2181 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2182 DRM_ERROR("CP DMA DAIC only supported for registers\n");
2185 if (((info & 0x00300000) >> 20) == 0) {
2186 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2188 DRM_ERROR("bad CP DMA DST\n");
2192 tmp = radeon_get_ib_value(p, idx+2) +
2193 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
2195 offset = reloc->gpu_offset + tmp;
2197 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2198 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
2199 tmp + size, radeon_bo_size(reloc->robj));
2204 ib[idx+3] = upper_32_bits(offset) & 0xff;
2206 DRM_ERROR("bad CP DMA DST_SEL\n");
2212 case PACKET3_SURFACE_SYNC:
2213 if (pkt->count != 3) {
2214 DRM_ERROR("bad SURFACE_SYNC\n");
2217 /* 0xffffffff/0x0 is flush all cache flag */
2218 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2219 radeon_get_ib_value(p, idx + 2) != 0) {
2220 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2222 DRM_ERROR("bad SURFACE_SYNC\n");
2225 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2228 case PACKET3_EVENT_WRITE:
2229 if (pkt->count != 2 && pkt->count != 0) {
2230 DRM_ERROR("bad EVENT_WRITE\n");
2236 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2238 DRM_ERROR("bad EVENT_WRITE\n");
2241 offset = reloc->gpu_offset +
2242 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2243 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2245 ib[idx+1] = offset & 0xfffffff8;
2246 ib[idx+2] = upper_32_bits(offset) & 0xff;
2249 case PACKET3_EVENT_WRITE_EOP:
2253 if (pkt->count != 4) {
2254 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2257 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2259 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2263 offset = reloc->gpu_offset +
2264 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2265 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2267 ib[idx+1] = offset & 0xfffffffc;
2268 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2271 case PACKET3_EVENT_WRITE_EOS:
2275 if (pkt->count != 3) {
2276 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2279 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2281 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2285 offset = reloc->gpu_offset +
2286 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2287 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2289 ib[idx+1] = offset & 0xfffffffc;
2290 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2293 case PACKET3_SET_CONFIG_REG:
2294 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2295 end_reg = 4 * pkt->count + start_reg - 4;
2296 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2297 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2298 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2299 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2302 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
2303 if (evergreen_is_safe_reg(p, reg))
2305 r = evergreen_cs_handle_reg(p, reg, idx);
2310 case PACKET3_SET_CONTEXT_REG:
2311 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2312 end_reg = 4 * pkt->count + start_reg - 4;
2313 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2314 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2315 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2316 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2319 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
2320 if (evergreen_is_safe_reg(p, reg))
2322 r = evergreen_cs_handle_reg(p, reg, idx);
2327 case PACKET3_SET_RESOURCE:
2328 if (pkt->count % 8) {
2329 DRM_ERROR("bad SET_RESOURCE\n");
2332 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2333 end_reg = 4 * pkt->count + start_reg - 4;
2334 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2335 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2336 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2337 DRM_ERROR("bad SET_RESOURCE\n");
2340 for (i = 0; i < (pkt->count / 8); i++) {
2341 struct radeon_bo *texture, *mipmap;
2342 u32 toffset, moffset;
2343 u32 size, offset, mip_address, tex_dim;
2345 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2346 case SQ_TEX_VTX_VALID_TEXTURE:
2348 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2350 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2353 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2354 ib[idx+1+(i*8)+1] |=
2355 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags));
2356 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
2357 unsigned bankw, bankh, mtaspect, tile_split;
2359 evergreen_tiling_fields(reloc->tiling_flags,
2360 &bankw, &bankh, &mtaspect,
2362 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2363 ib[idx+1+(i*8)+7] |=
2364 TEX_BANK_WIDTH(bankw) |
2365 TEX_BANK_HEIGHT(bankh) |
2366 MACRO_TILE_ASPECT(mtaspect) |
2367 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2370 texture = reloc->robj;
2371 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2374 tex_dim = ib[idx+1+(i*8)+0] & 0x7;
2375 mip_address = ib[idx+1+(i*8)+3];
2377 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
2379 !radeon_cs_packet_next_is_pkt3_nop(p)) {
2380 /* MIP_ADDRESS should point to FMASK for an MSAA texture.
2381 * It should be 0 if FMASK is disabled. */
2385 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2387 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2390 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2391 mipmap = reloc->robj;
2394 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2397 ib[idx+1+(i*8)+2] += toffset;
2398 ib[idx+1+(i*8)+3] += moffset;
2400 case SQ_TEX_VTX_VALID_BUFFER:
2404 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2406 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2409 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2410 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2411 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2412 /* force size to size of the buffer */
2413 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2414 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2417 offset64 = reloc->gpu_offset + offset;
2418 ib[idx+1+(i*8)+0] = offset64;
2419 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2420 (upper_32_bits(offset64) & 0xff);
2423 case SQ_TEX_VTX_INVALID_TEXTURE:
2424 case SQ_TEX_VTX_INVALID_BUFFER:
2426 DRM_ERROR("bad SET_RESOURCE\n");
2431 case PACKET3_SET_ALU_CONST:
2432 /* XXX fix me ALU const buffers only */
2434 case PACKET3_SET_BOOL_CONST:
2435 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2436 end_reg = 4 * pkt->count + start_reg - 4;
2437 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2438 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2439 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2440 DRM_ERROR("bad SET_BOOL_CONST\n");
2444 case PACKET3_SET_LOOP_CONST:
2445 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2446 end_reg = 4 * pkt->count + start_reg - 4;
2447 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2448 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2449 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2450 DRM_ERROR("bad SET_LOOP_CONST\n");
2454 case PACKET3_SET_CTL_CONST:
2455 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2456 end_reg = 4 * pkt->count + start_reg - 4;
2457 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2458 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2459 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2460 DRM_ERROR("bad SET_CTL_CONST\n");
2464 case PACKET3_SET_SAMPLER:
2465 if (pkt->count % 3) {
2466 DRM_ERROR("bad SET_SAMPLER\n");
2469 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2470 end_reg = 4 * pkt->count + start_reg - 4;
2471 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2472 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2473 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2474 DRM_ERROR("bad SET_SAMPLER\n");
2478 case PACKET3_STRMOUT_BUFFER_UPDATE:
2479 if (pkt->count != 4) {
2480 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2483 /* Updating memory at DST_ADDRESS. */
2484 if (idx_value & 0x1) {
2486 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2488 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2491 offset = radeon_get_ib_value(p, idx+1);
2492 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2493 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2494 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2495 offset + 4, radeon_bo_size(reloc->robj));
2498 offset += reloc->gpu_offset;
2500 ib[idx+2] = upper_32_bits(offset) & 0xff;
2502 /* Reading data from SRC_ADDRESS. */
2503 if (((idx_value >> 1) & 0x3) == 2) {
2505 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2507 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2510 offset = radeon_get_ib_value(p, idx+3);
2511 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2512 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2513 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2514 offset + 4, radeon_bo_size(reloc->robj));
2517 offset += reloc->gpu_offset;
2519 ib[idx+4] = upper_32_bits(offset) & 0xff;
2522 case PACKET3_MEM_WRITE:
2526 if (pkt->count != 3) {
2527 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2530 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2532 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2535 offset = radeon_get_ib_value(p, idx+0);
2536 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2538 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2541 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2542 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2543 offset + 8, radeon_bo_size(reloc->robj));
2546 offset += reloc->gpu_offset;
2548 ib[idx+1] = upper_32_bits(offset) & 0xff;
2551 case PACKET3_COPY_DW:
2552 if (pkt->count != 4) {
2553 DRM_ERROR("bad COPY_DW (invalid count)\n");
2556 if (idx_value & 0x1) {
2558 /* SRC is memory. */
2559 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2561 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2564 offset = radeon_get_ib_value(p, idx+1);
2565 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2566 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2567 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2568 offset + 4, radeon_bo_size(reloc->robj));
2571 offset += reloc->gpu_offset;
2573 ib[idx+2] = upper_32_bits(offset) & 0xff;
2576 reg = radeon_get_ib_value(p, idx+1) << 2;
2577 if (!evergreen_is_safe_reg(p, reg)) {
2578 dev_warn(p->dev, "forbidden register 0x%08x at %d\n",
2583 if (idx_value & 0x2) {
2585 /* DST is memory. */
2586 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2588 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2591 offset = radeon_get_ib_value(p, idx+3);
2592 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2593 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2594 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2595 offset + 4, radeon_bo_size(reloc->robj));
2598 offset += reloc->gpu_offset;
2600 ib[idx+4] = upper_32_bits(offset) & 0xff;
2603 reg = radeon_get_ib_value(p, idx+3) << 2;
2604 if (!evergreen_is_safe_reg(p, reg)) {
2605 dev_warn(p->dev, "forbidden register 0x%08x at %d\n",
2614 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2620 int evergreen_cs_parse(struct radeon_cs_parser *p)
2622 struct radeon_cs_packet pkt;
2623 struct evergreen_cs_track *track;
2627 if (p->track == NULL) {
2628 /* initialize tracker, we are in kms */
2629 track = kzalloc(sizeof(*track), GFP_KERNEL);
2632 evergreen_cs_track_init(track);
2633 if (p->rdev->family >= CHIP_CAYMAN) {
2634 tmp = p->rdev->config.cayman.tile_config;
2635 track->reg_safe_bm = cayman_reg_safe_bm;
2637 tmp = p->rdev->config.evergreen.tile_config;
2638 track->reg_safe_bm = evergreen_reg_safe_bm;
2640 BUILD_BUG_ON(ARRAY_SIZE(cayman_reg_safe_bm) != REG_SAFE_BM_SIZE);
2641 BUILD_BUG_ON(ARRAY_SIZE(evergreen_reg_safe_bm) != REG_SAFE_BM_SIZE);
2642 switch (tmp & 0xf) {
2658 switch ((tmp & 0xf0) >> 4) {
2671 switch ((tmp & 0xf00) >> 8) {
2673 track->group_size = 256;
2677 track->group_size = 512;
2681 switch ((tmp & 0xf000) >> 12) {
2683 track->row_size = 1;
2687 track->row_size = 2;
2690 track->row_size = 4;
2697 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2703 p->idx += pkt.count + 2;
2705 case RADEON_PACKET_TYPE0:
2706 r = evergreen_cs_parse_packet0(p, &pkt);
2708 case RADEON_PACKET_TYPE2:
2710 case RADEON_PACKET_TYPE3:
2711 r = evergreen_packet3_check(p, &pkt);
2714 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2724 } while (p->idx < p->chunk_ib->length_dw);
2726 for (r = 0; r < p->ib.length_dw; r++) {
2727 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2737 * evergreen_dma_cs_parse() - parse the DMA IB
2738 * @p: parser structure holding parsing context.
2740 * Parses the DMA IB from the CS ioctl and updates
2741 * the GPU addresses based on the reloc information and
2742 * checks for errors. (Evergreen-Cayman)
2743 * Returns 0 for success and an error on failure.
2745 int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2747 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
2748 struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;
2749 u32 header, cmd, count, sub_cmd;
2750 uint32_t *ib = p->ib.ptr;
2752 u64 src_offset, dst_offset, dst2_offset;
2756 if (p->idx >= ib_chunk->length_dw) {
2757 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2758 p->idx, ib_chunk->length_dw);
2762 header = radeon_get_ib_value(p, idx);
2763 cmd = GET_DMA_CMD(header);
2764 count = GET_DMA_COUNT(header);
2765 sub_cmd = GET_DMA_SUB_CMD(header);
2768 case DMA_PACKET_WRITE:
2769 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2771 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2777 dst_offset = radeon_get_ib_value(p, idx+1);
2780 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2781 p->idx += count + 7;
2785 dst_offset = radeon_get_ib_value(p, idx+1);
2786 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2788 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2789 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2790 p->idx += count + 3;
2793 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header);
2796 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2797 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2798 dst_offset, radeon_bo_size(dst_reloc->robj));
2802 case DMA_PACKET_COPY:
2803 r = r600_dma_cs_next_reloc(p, &src_reloc);
2805 DRM_ERROR("bad DMA_PACKET_COPY\n");
2808 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2810 DRM_ERROR("bad DMA_PACKET_COPY\n");
2814 /* Copy L2L, DW aligned */
2817 src_offset = radeon_get_ib_value(p, idx+2);
2818 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2819 dst_offset = radeon_get_ib_value(p, idx+1);
2820 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2821 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2822 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
2823 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2826 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2827 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
2828 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2832 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2833 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2834 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2840 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
2841 /* tiled src, linear dst */
2842 src_offset = radeon_get_ib_value(p, idx+1);
2844 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
2846 dst_offset = radeon_get_ib_value(p, idx + 7);
2847 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
2848 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2849 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2851 /* linear src, tiled dst */
2852 src_offset = radeon_get_ib_value(p, idx+7);
2853 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
2854 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2855 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2857 dst_offset = radeon_get_ib_value(p, idx+1);
2859 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2861 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2862 dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n",
2863 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2866 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2867 dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n",
2868 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2873 /* Copy L2L, byte aligned */
2876 src_offset = radeon_get_ib_value(p, idx+2);
2877 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2878 dst_offset = radeon_get_ib_value(p, idx+1);
2879 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2880 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
2881 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
2882 src_offset + count, radeon_bo_size(src_reloc->robj));
2885 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
2886 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
2887 dst_offset + count, radeon_bo_size(dst_reloc->robj));
2890 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
2891 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);
2892 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2893 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2896 /* Copy L2L, partial */
2899 if (p->family < CHIP_CAYMAN) {
2900 DRM_ERROR("L2L Partial is cayman only !\n");
2903 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);
2904 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2905 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff);
2906 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2910 /* Copy L2L, DW aligned, broadcast */
2912 /* L2L, dw, broadcast */
2913 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2915 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
2918 dst_offset = radeon_get_ib_value(p, idx+1);
2919 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2920 dst2_offset = radeon_get_ib_value(p, idx+2);
2921 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;
2922 src_offset = radeon_get_ib_value(p, idx+3);
2923 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2924 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2925 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
2926 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2929 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2930 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
2931 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2934 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2935 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
2936 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2939 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2940 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);
2941 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2942 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2943 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;
2944 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2947 /* Copy L2T Frame to Field */
2949 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
2950 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2953 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2955 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2958 dst_offset = radeon_get_ib_value(p, idx+1);
2960 dst2_offset = radeon_get_ib_value(p, idx+2);
2962 src_offset = radeon_get_ib_value(p, idx+8);
2963 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
2964 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2965 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
2966 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2969 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2970 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2971 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2974 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2975 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2976 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2979 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2980 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
2981 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2982 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2985 /* Copy L2T/T2L, partial */
2987 /* L2T, T2L partial */
2988 if (p->family < CHIP_CAYMAN) {
2989 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2993 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
2994 /* tiled src, linear dst */
2995 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
2997 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2998 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
3000 /* linear src, tiled dst */
3001 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3002 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3004 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
3008 /* Copy L2T broadcast */
3010 /* L2T, broadcast */
3011 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3012 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3015 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3017 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3020 dst_offset = radeon_get_ib_value(p, idx+1);
3022 dst2_offset = radeon_get_ib_value(p, idx+2);
3024 src_offset = radeon_get_ib_value(p, idx+8);
3025 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3026 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3027 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3028 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3031 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3032 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3033 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3036 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3037 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3038 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3041 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
3042 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
3043 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3044 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3047 /* Copy L2T/T2L (tile units) */
3051 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3052 /* tiled src, linear dst */
3053 src_offset = radeon_get_ib_value(p, idx+1);
3055 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
3057 dst_offset = radeon_get_ib_value(p, idx+7);
3058 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3059 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
3060 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
3062 /* linear src, tiled dst */
3063 src_offset = radeon_get_ib_value(p, idx+7);
3064 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
3065 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3066 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3068 dst_offset = radeon_get_ib_value(p, idx+1);
3070 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
3072 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3073 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
3074 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3077 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3078 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
3079 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3084 /* Copy T2T, partial (tile units) */
3087 if (p->family < CHIP_CAYMAN) {
3088 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
3091 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
3092 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8);
3095 /* Copy L2T broadcast (tile units) */
3097 /* L2T, broadcast */
3098 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {
3099 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3102 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3104 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3107 dst_offset = radeon_get_ib_value(p, idx+1);
3109 dst2_offset = radeon_get_ib_value(p, idx+2);
3111 src_offset = radeon_get_ib_value(p, idx+8);
3112 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
3113 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3114 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3115 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3118 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3119 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3120 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3123 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3124 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3125 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3128 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
3129 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);
3130 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3131 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3135 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header);
3139 case DMA_PACKET_CONSTANT_FILL:
3140 r = r600_dma_cs_next_reloc(p, &dst_reloc);
3142 DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
3145 dst_offset = radeon_get_ib_value(p, idx+1);
3146 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
3147 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3148 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
3149 dst_offset, radeon_bo_size(dst_reloc->robj));
3152 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
3153 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
3156 case DMA_PACKET_NOP:
3160 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
3163 } while (p->idx < p->chunk_ib->length_dw);
3165 for (r = 0; r < p->ib->length_dw; r++) {
3166 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
3174 static bool evergreen_vm_reg_valid(u32 reg)
3176 /* context regs are fine */
3180 /* check config regs */
3183 case GRBM_GFX_INDEX:
3184 case CP_STRMOUT_CNTL:
3187 case VGT_VTX_VECT_EJECT_REG:
3188 case VGT_CACHE_INVALIDATION:
3189 case VGT_GS_VERTEX_REUSE:
3190 case VGT_PRIMITIVE_TYPE:
3191 case VGT_INDEX_TYPE:
3192 case VGT_NUM_INDICES:
3193 case VGT_NUM_INSTANCES:
3194 case VGT_COMPUTE_DIM_X:
3195 case VGT_COMPUTE_DIM_Y:
3196 case VGT_COMPUTE_DIM_Z:
3197 case VGT_COMPUTE_START_X:
3198 case VGT_COMPUTE_START_Y:
3199 case VGT_COMPUTE_START_Z:
3200 case VGT_COMPUTE_INDEX:
3201 case VGT_COMPUTE_THREAD_GROUP_SIZE:
3202 case VGT_HS_OFFCHIP_PARAM:
3204 case PA_SU_LINE_STIPPLE_VALUE:
3205 case PA_SC_LINE_STIPPLE_STATE:
3207 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
3208 case SQ_DYN_GPR_SIMD_LOCK_EN:
3210 case SQ_GPR_RESOURCE_MGMT_1:
3211 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
3212 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
3213 case SQ_CONST_MEM_BASE:
3214 case SQ_STATIC_THREAD_MGMT_1:
3215 case SQ_STATIC_THREAD_MGMT_2:
3216 case SQ_STATIC_THREAD_MGMT_3:
3217 case SPI_CONFIG_CNTL:
3218 case SPI_CONFIG_CNTL_1:
3225 case TD_PS_BORDER_COLOR_INDEX:
3226 case TD_PS_BORDER_COLOR_RED:
3227 case TD_PS_BORDER_COLOR_GREEN:
3228 case TD_PS_BORDER_COLOR_BLUE:
3229 case TD_PS_BORDER_COLOR_ALPHA:
3230 case TD_VS_BORDER_COLOR_INDEX:
3231 case TD_VS_BORDER_COLOR_RED:
3232 case TD_VS_BORDER_COLOR_GREEN:
3233 case TD_VS_BORDER_COLOR_BLUE:
3234 case TD_VS_BORDER_COLOR_ALPHA:
3235 case TD_GS_BORDER_COLOR_INDEX:
3236 case TD_GS_BORDER_COLOR_RED:
3237 case TD_GS_BORDER_COLOR_GREEN:
3238 case TD_GS_BORDER_COLOR_BLUE:
3239 case TD_GS_BORDER_COLOR_ALPHA:
3240 case TD_HS_BORDER_COLOR_INDEX:
3241 case TD_HS_BORDER_COLOR_RED:
3242 case TD_HS_BORDER_COLOR_GREEN:
3243 case TD_HS_BORDER_COLOR_BLUE:
3244 case TD_HS_BORDER_COLOR_ALPHA:
3245 case TD_LS_BORDER_COLOR_INDEX:
3246 case TD_LS_BORDER_COLOR_RED:
3247 case TD_LS_BORDER_COLOR_GREEN:
3248 case TD_LS_BORDER_COLOR_BLUE:
3249 case TD_LS_BORDER_COLOR_ALPHA:
3250 case TD_CS_BORDER_COLOR_INDEX:
3251 case TD_CS_BORDER_COLOR_RED:
3252 case TD_CS_BORDER_COLOR_GREEN:
3253 case TD_CS_BORDER_COLOR_BLUE:
3254 case TD_CS_BORDER_COLOR_ALPHA:
3255 case SQ_ESGS_RING_SIZE:
3256 case SQ_GSVS_RING_SIZE:
3257 case SQ_ESTMP_RING_SIZE:
3258 case SQ_GSTMP_RING_SIZE:
3259 case SQ_HSTMP_RING_SIZE:
3260 case SQ_LSTMP_RING_SIZE:
3261 case SQ_PSTMP_RING_SIZE:
3262 case SQ_VSTMP_RING_SIZE:
3263 case SQ_ESGS_RING_ITEMSIZE:
3264 case SQ_ESTMP_RING_ITEMSIZE:
3265 case SQ_GSTMP_RING_ITEMSIZE:
3266 case SQ_GSVS_RING_ITEMSIZE:
3267 case SQ_GS_VERT_ITEMSIZE:
3268 case SQ_GS_VERT_ITEMSIZE_1:
3269 case SQ_GS_VERT_ITEMSIZE_2:
3270 case SQ_GS_VERT_ITEMSIZE_3:
3271 case SQ_GSVS_RING_OFFSET_1:
3272 case SQ_GSVS_RING_OFFSET_2:
3273 case SQ_GSVS_RING_OFFSET_3:
3274 case SQ_HSTMP_RING_ITEMSIZE:
3275 case SQ_LSTMP_RING_ITEMSIZE:
3276 case SQ_PSTMP_RING_ITEMSIZE:
3277 case SQ_VSTMP_RING_ITEMSIZE:
3278 case VGT_TF_RING_SIZE:
3279 case SQ_ESGS_RING_BASE:
3280 case SQ_GSVS_RING_BASE:
3281 case SQ_ESTMP_RING_BASE:
3282 case SQ_GSTMP_RING_BASE:
3283 case SQ_HSTMP_RING_BASE:
3284 case SQ_LSTMP_RING_BASE:
3285 case SQ_PSTMP_RING_BASE:
3286 case SQ_VSTMP_RING_BASE:
3287 case CAYMAN_VGT_OFFCHIP_LDS_BASE:
3288 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
3291 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
3296 static int evergreen_vm_packet3_check(struct radeon_device *rdev,
3297 u32 *ib, struct radeon_cs_packet *pkt)
3299 u32 idx = pkt->idx + 1;
3300 u32 idx_value = ib[idx];
3301 u32 start_reg, end_reg, reg, i;
3304 switch (pkt->opcode) {
3307 case PACKET3_SET_BASE:
3308 if (idx_value != 1) {
3309 DRM_ERROR("bad SET_BASE");
3313 case PACKET3_CLEAR_STATE:
3314 case PACKET3_INDEX_BUFFER_SIZE:
3315 case PACKET3_DISPATCH_DIRECT:
3316 case PACKET3_DISPATCH_INDIRECT:
3317 case PACKET3_MODE_CONTROL:
3318 case PACKET3_SET_PREDICATION:
3319 case PACKET3_COND_EXEC:
3320 case PACKET3_PRED_EXEC:
3321 case PACKET3_DRAW_INDIRECT:
3322 case PACKET3_DRAW_INDEX_INDIRECT:
3323 case PACKET3_INDEX_BASE:
3324 case PACKET3_DRAW_INDEX_2:
3325 case PACKET3_CONTEXT_CONTROL:
3326 case PACKET3_DRAW_INDEX_OFFSET:
3327 case PACKET3_INDEX_TYPE:
3328 case PACKET3_DRAW_INDEX:
3329 case PACKET3_DRAW_INDEX_AUTO:
3330 case PACKET3_DRAW_INDEX_IMMD:
3331 case PACKET3_NUM_INSTANCES:
3332 case PACKET3_DRAW_INDEX_MULTI_AUTO:
3333 case PACKET3_STRMOUT_BUFFER_UPDATE:
3334 case PACKET3_DRAW_INDEX_OFFSET_2:
3335 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
3336 case PACKET3_MPEG_INDEX:
3337 case PACKET3_WAIT_REG_MEM:
3338 case PACKET3_MEM_WRITE:
3339 case PACKET3_SURFACE_SYNC:
3340 case PACKET3_EVENT_WRITE:
3341 case PACKET3_EVENT_WRITE_EOP:
3342 case PACKET3_EVENT_WRITE_EOS:
3343 case PACKET3_SET_CONTEXT_REG:
3344 case PACKET3_SET_BOOL_CONST:
3345 case PACKET3_SET_LOOP_CONST:
3346 case PACKET3_SET_RESOURCE:
3347 case PACKET3_SET_SAMPLER:
3348 case PACKET3_SET_CTL_CONST:
3349 case PACKET3_SET_RESOURCE_OFFSET:
3350 case PACKET3_SET_CONTEXT_REG_INDIRECT:
3351 case PACKET3_SET_RESOURCE_INDIRECT:
3352 case CAYMAN_PACKET3_DEALLOC_STATE:
3354 case PACKET3_COND_WRITE:
3355 if (idx_value & 0x100) {
3356 reg = ib[idx + 5] * 4;
3357 if (!evergreen_vm_reg_valid(reg))
3361 case PACKET3_COPY_DW:
3362 if (idx_value & 0x2) {
3363 reg = ib[idx + 3] * 4;
3364 if (!evergreen_vm_reg_valid(reg))
3368 case PACKET3_SET_CONFIG_REG:
3369 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3370 end_reg = 4 * pkt->count + start_reg - 4;
3371 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
3372 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
3373 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
3374 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
3377 for (i = 0; i < pkt->count; i++) {
3378 reg = start_reg + (4 * i);
3379 if (!evergreen_vm_reg_valid(reg))
3383 case PACKET3_CP_DMA:
3384 command = ib[idx + 4];
3386 if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
3387 (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
3388 ((((info & 0x00300000) >> 20) == 0) &&
3389 (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
3390 ((((info & 0x60000000) >> 29) == 0) &&
3391 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
3392 /* non mem to mem copies requires dw aligned count */
3393 if ((command & 0x1fffff) % 4) {
3394 DRM_ERROR("CP DMA command requires dw count alignment\n");
3398 if (command & PACKET3_CP_DMA_CMD_SAS) {
3399 /* src address space is register */
3400 if (((info & 0x60000000) >> 29) == 0) {
3401 start_reg = idx_value << 2;
3402 if (command & PACKET3_CP_DMA_CMD_SAIC) {
3404 if (!evergreen_vm_reg_valid(reg)) {
3405 DRM_ERROR("CP DMA Bad SRC register\n");
3409 for (i = 0; i < (command & 0x1fffff); i++) {
3410 reg = start_reg + (4 * i);
3411 if (!evergreen_vm_reg_valid(reg)) {
3412 DRM_ERROR("CP DMA Bad SRC register\n");
3419 if (command & PACKET3_CP_DMA_CMD_DAS) {
3420 /* dst address space is register */
3421 if (((info & 0x00300000) >> 20) == 0) {
3422 start_reg = ib[idx + 2];
3423 if (command & PACKET3_CP_DMA_CMD_DAIC) {
3425 if (!evergreen_vm_reg_valid(reg)) {
3426 DRM_ERROR("CP DMA Bad DST register\n");
3430 for (i = 0; i < (command & 0x1fffff); i++) {
3431 reg = start_reg + (4 * i);
3432 if (!evergreen_vm_reg_valid(reg)) {
3433 DRM_ERROR("CP DMA Bad DST register\n");
3447 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3451 struct radeon_cs_packet pkt;
3455 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
3456 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
3459 case RADEON_PACKET_TYPE0:
3460 dev_err(rdev->dev, "Packet0 not allowed!\n");
3463 case RADEON_PACKET_TYPE2:
3466 case RADEON_PACKET_TYPE3:
3467 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3468 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
3469 idx += pkt.count + 2;
3472 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3478 } while (idx < ib->length_dw);
3484 * evergreen_dma_ib_parse() - parse the DMA IB for VM
3485 * @rdev: radeon_device pointer
3486 * @ib: radeon_ib pointer
3488 * Parses the DMA IB from the VM CS ioctl
3489 * checks for errors. (Cayman-SI)
3490 * Returns 0 for success and an error on failure.
3492 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3495 u32 header, cmd, count, sub_cmd;
3498 header = ib->ptr[idx];
3499 cmd = GET_DMA_CMD(header);
3500 count = GET_DMA_COUNT(header);
3501 sub_cmd = GET_DMA_SUB_CMD(header);
3504 case DMA_PACKET_WRITE:
3515 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]);
3519 case DMA_PACKET_COPY:
3521 /* Copy L2L, DW aligned */
3529 /* Copy L2L, byte aligned */
3533 /* Copy L2L, partial */
3537 /* Copy L2L, DW aligned, broadcast */
3541 /* Copy L2T Frame to Field */
3545 /* Copy L2T/T2L, partial */
3549 /* Copy L2T broadcast */
3553 /* Copy L2T/T2L (tile units) */
3557 /* Copy T2T, partial (tile units) */
3561 /* Copy L2T broadcast (tile units) */
3566 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]);
3570 case DMA_PACKET_CONSTANT_FILL:
3573 case DMA_PACKET_NOP:
3577 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
3580 } while (idx < ib->length_dw);