drivers/gpu/drm/radeon/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "cikd.h"
  27 #include "r600_dpm.h"
  28 #include "kv_dpm.h"
  29 #include "radeon_asic.h"
  30 #include <linux/seq_file.h>
  31
  32 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  33 #define KV_MINIMUM_ENGINE_CLOCK         800
  34 #define SMC_RAM_END                     0x40000
  35
  36 static void kv_init_graphics_levels(struct radeon_device *rdev);
  37 static int kv_calculate_ds_divider(struct radeon_device *rdev);
  38 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
  39 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
  40 static void kv_enable_new_levels(struct radeon_device *rdev);
  41 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
  42                                            struct radeon_ps *new_rps);
  43 static int kv_set_enabled_levels(struct radeon_device *rdev);
  44 static int kv_force_dpm_highest(struct radeon_device *rdev);
  45 static int kv_force_dpm_lowest(struct radeon_device *rdev);
  46 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
  47                                         struct radeon_ps *new_rps,
  48                                         struct radeon_ps *old_rps);
  49 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
  50                                             int min_temp, int max_temp);
  51 static int kv_init_fps_limits(struct radeon_device *rdev);
  52
  53 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  54 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
  55 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
  56 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
  57
  58 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
  59 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
  60 extern void cik_update_cg(struct radeon_device *rdev,
  61                           u32 block, bool enable);
  62
  63 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
  64 {
  65         {  0,       4,        1    },
  66         {  1,       4,        1    },
  67         {  2,       5,        1    },
  68         {  3,       4,        2    },
  69         {  4,       1,        1    },
  70         {  5,       5,        2    },
  71         {  6,       6,        1    },
  72         {  7,       9,        2    },
  73         { 0xffffffff }
  74 };
  75
  76 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
  77 {
  78         {  0,       4,        1    },
  79         { 0xffffffff }
  80 };
  81
  82 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
  83 {
  84         {  0,       4,        1    },
  85         { 0xffffffff }
  86 };
  87
  88 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
  89 {
  90         {  0,       4,        1    },
  91         { 0xffffffff }
  92 };
  93
  94 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
  95 {
  96         {  0,       4,        1    },
  97         { 0xffffffff }
  98 };
  99
 100 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 101 {
 102         {  0,       4,        1    },
 103         {  1,       4,        1    },
 104         {  2,       5,        1    },
 105         {  3,       4,        1    },
 106         {  4,       1,        1    },
 107         {  5,       5,        1    },
 108         {  6,       6,        1    },
 109         {  7,       9,        1    },
 110         {  8,       4,        1    },
 111         {  9,       2,        1    },
 112         {  10,      3,        1    },
 113         {  11,      6,        1    },
 114         {  12,      8,        2    },
 115         {  13,      1,        1    },
 116         {  14,      2,        1    },
 117         {  15,      3,        1    },
 118         {  16,      1,        1    },
 119         {  17,      4,        1    },
 120         {  18,      3,        1    },
 121         {  19,      1,        1    },
 122         {  20,      8,        1    },
 123         {  21,      5,        1    },
 124         {  22,      1,        1    },
 125         {  23,      1,        1    },
 126         {  24,      4,        1    },
 127         {  27,      6,        1    },
 128         {  28,      1,        1    },
 129         { 0xffffffff }
 130 };
 131
 132 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 133 {
 134         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 135 };
 136
 137 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 138 {
 139         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 140 };
 141
 142 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 143 {
 144         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 145 };
 146
 147 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 148 {
 149         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 150 };
 151
 152 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 153 {
 154         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 155 };
 156
 157 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 158 {
 159         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 160 };
 161
 162 static const struct kv_pt_config_reg didt_config_kv[] =
 163 {
 164         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 165         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 166         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 167         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 168         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 169         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 170         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 171         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 172         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 173         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 174         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 175         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 176         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 177         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 178         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 179         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 180         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 181         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 182         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 183         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 184         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 185         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 186         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 187         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 188         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 189         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 190         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 191         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 192         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 193         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 194         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 195         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 196         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 197         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 198         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 199         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 200         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 201         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 202         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 203         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 204         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 205         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 206         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 207         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 208         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 209         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 210         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 211         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 212         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 213         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 214         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 215         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 216         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 217         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 218         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 219         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 220         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 221         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 222         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 223         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 224         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 225         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 226         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 227         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 228         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 229         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 230         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 231         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 232         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 233         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 234         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 235         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 236         { 0xFFFFFFFF }
 237 };
 238
 239 static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
 240 {
 241         struct kv_ps *ps = rps->ps_priv;
 242
 243         return ps;
 244 }
 245
 246 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
 247 {
 248         struct kv_power_info *pi = rdev->pm.dpm.priv;
 249
 250         return pi;
 251 }
 252
 253 #if 0
 254 static void kv_program_local_cac_table(struct radeon_device *rdev,
 255                                        const struct kv_lcac_config_values *local_cac_table,
 256                                        const struct kv_lcac_config_reg *local_cac_reg)
 257 {
 258         u32 i, count, data;
 259         const struct kv_lcac_config_values *values = local_cac_table;
 260
 261         while (values->block_id != 0xffffffff) {
 262                 count = values->signal_id;
 263                 for (i = 0; i < count; i++) {
 264                         data = ((values->block_id << local_cac_reg->block_shift) &
 265                                 local_cac_reg->block_mask);
 266                         data |= ((i << local_cac_reg->signal_shift) &
 267                                  local_cac_reg->signal_mask);
 268                         data |= ((values->t << local_cac_reg->t_shift) &
 269                                  local_cac_reg->t_mask);
 270                         data |= ((1 << local_cac_reg->enable_shift) &
 271                                  local_cac_reg->enable_mask);
 272                         WREG32_SMC(local_cac_reg->cntl, data);
 273                 }
 274                 values++;
 275         }
 276 }
 277 #endif
 278
 279 static int kv_program_pt_config_registers(struct radeon_device *rdev,
 280                                           const struct kv_pt_config_reg *cac_config_regs)
 281 {
 282         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 283         u32 data;
 284         u32 cache = 0;
 285
 286         if (config_regs == NULL)
 287                 return -EINVAL;
 288
 289         while (config_regs->offset != 0xFFFFFFFF) {
 290                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 291                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 292                 } else {
 293                         switch (config_regs->type) {
 294                         case KV_CONFIGREG_SMC_IND:
 295                                 data = RREG32_SMC(config_regs->offset);
 296                                 break;
 297                         case KV_CONFIGREG_DIDT_IND:
 298                                 data = RREG32_DIDT(config_regs->offset);
 299                                 break;
 300                         default:
 301                                 data = RREG32(config_regs->offset << 2);
 302                                 break;
 303                         }
 304
 305                         data &= ~config_regs->mask;
 306                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 307                         data |= cache;
 308                         cache = 0;
 309
 310                         switch (config_regs->type) {
 311                         case KV_CONFIGREG_SMC_IND:
 312                                 WREG32_SMC(config_regs->offset, data);
 313                                 break;
 314                         case KV_CONFIGREG_DIDT_IND:
 315                                 WREG32_DIDT(config_regs->offset, data);
 316                                 break;
 317                         default:
 318                                 WREG32(config_regs->offset << 2, data);
 319                                 break;
 320                         }
 321                 }
 322                 config_regs++;
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
 329 {
 330         struct kv_power_info *pi = kv_get_pi(rdev);
 331         u32 data;
 332
 333         if (pi->caps_sq_ramping) {
 334                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 335                 if (enable)
 336                         data |= DIDT_CTRL_EN;
 337                 else
 338                         data &= ~DIDT_CTRL_EN;
 339                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 340         }
 341
 342         if (pi->caps_db_ramping) {
 343                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 344                 if (enable)
 345                         data |= DIDT_CTRL_EN;
 346                 else
 347                         data &= ~DIDT_CTRL_EN;
 348                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 349         }
 350
 351         if (pi->caps_td_ramping) {
 352                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 353                 if (enable)
 354                         data |= DIDT_CTRL_EN;
 355                 else
 356                         data &= ~DIDT_CTRL_EN;
 357                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 358         }
 359
 360         if (pi->caps_tcp_ramping) {
 361                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 362                 if (enable)
 363                         data |= DIDT_CTRL_EN;
 364                 else
 365                         data &= ~DIDT_CTRL_EN;
 366                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 367         }
 368 }
 369
 370 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
 371 {
 372         struct kv_power_info *pi = kv_get_pi(rdev);
 373         int ret;
 374
 375         if (pi->caps_sq_ramping ||
 376             pi->caps_db_ramping ||
 377             pi->caps_td_ramping ||
 378             pi->caps_tcp_ramping) {
 379                 cik_enter_rlc_safe_mode(rdev);
 380
 381                 if (enable) {
 382                         ret = kv_program_pt_config_registers(rdev, didt_config_kv);
 383                         if (ret) {
 384                                 cik_exit_rlc_safe_mode(rdev);
 385                                 return ret;
 386                         }
 387                 }
 388
 389                 kv_do_enable_didt(rdev, enable);
 390
 391                 cik_exit_rlc_safe_mode(rdev);
 392         }
 393
 394         return 0;
 395 }
 396
 397 #if 0
 398 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
 399 {
 400         struct kv_power_info *pi = kv_get_pi(rdev);
 401
 402         if (pi->caps_cac) {
 403                 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
 404                 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
 405                 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 406
 407                 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
 408                 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
 409                 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 410
 411                 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
 412                 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
 413                 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 414
 415                 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
 416                 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
 417                 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 418
 419                 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
 420                 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
 421                 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 422
 423                 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
 424                 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
 425                 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 426         }
 427 }
 428 #endif
 429
 430 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
 431 {
 432         struct kv_power_info *pi = kv_get_pi(rdev);
 433         int ret = 0;
 434
 435         if (pi->caps_cac) {
 436                 if (enable) {
 437                         ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
 438                         if (ret)
 439                                 pi->cac_enabled = false;
 440                         else
 441                                 pi->cac_enabled = true;
 442                 } else if (pi->cac_enabled) {
 443                         kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
 444                         pi->cac_enabled = false;
 445                 }
 446         }
 447
 448         return ret;
 449 }
 450
 451 static int kv_process_firmware_header(struct radeon_device *rdev)
 452 {
 453         struct kv_power_info *pi = kv_get_pi(rdev);
 454         u32 tmp;
 455         int ret;
 456
 457         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 458                                      offsetof(SMU7_Firmware_Header, DpmTable),
 459                                      &tmp, pi->sram_end);
 460
 461         if (ret == 0)
 462                 pi->dpm_table_start = tmp;
 463
 464         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 465                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 466                                      &tmp, pi->sram_end);
 467
 468         if (ret == 0)
 469                 pi->soft_regs_start = tmp;
 470
 471         return ret;
 472 }
 473
 474 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
 475 {
 476         struct kv_power_info *pi = kv_get_pi(rdev);
 477         int ret;
 478
 479         pi->graphics_voltage_change_enable = 1;
 480
 481         ret = kv_copy_bytes_to_smc(rdev,
 482                                    pi->dpm_table_start +
 483                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 484                                    &pi->graphics_voltage_change_enable,
 485                                    sizeof(u8), pi->sram_end);
 486
 487         return ret;
 488 }
 489
 490 static int kv_set_dpm_interval(struct radeon_device *rdev)
 491 {
 492         struct kv_power_info *pi = kv_get_pi(rdev);
 493         int ret;
 494
 495         pi->graphics_interval = 1;
 496
 497         ret = kv_copy_bytes_to_smc(rdev,
 498                                    pi->dpm_table_start +
 499                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 500                                    &pi->graphics_interval,
 501                                    sizeof(u8), pi->sram_end);
 502
 503         return ret;
 504 }
 505
 506 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
 507 {
 508         struct kv_power_info *pi = kv_get_pi(rdev);
 509         int ret;
 510
 511         ret = kv_copy_bytes_to_smc(rdev,
 512                                    pi->dpm_table_start +
 513                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 514                                    &pi->graphics_boot_level,
 515                                    sizeof(u8), pi->sram_end);
 516
 517         return ret;
 518 }
 519
 520 static void kv_program_vc(struct radeon_device *rdev)
 521 {
 522         WREG32_SMC(CG_FTV_0, 0x3FFFC000);
 523 }
 524
 525 static void kv_clear_vc(struct radeon_device *rdev)
 526 {
 527         WREG32_SMC(CG_FTV_0, 0);
 528 }
 529
 530 static int kv_set_divider_value(struct radeon_device *rdev,
 531                                 u32 index, u32 sclk)
 532 {
 533         struct kv_power_info *pi = kv_get_pi(rdev);
 534         struct atom_clock_dividers dividers;
 535         int ret;
 536
 537         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 538                                              sclk, false, &dividers);
 539         if (ret)
 540                 return ret;
 541
 542         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 543         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 544
 545         return 0;
 546 }
 547
 548 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
 549                                             u16 voltage)
 550 {
 551         return 6200 - (voltage * 25);
 552 }
 553
 554 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
 555                                             u32 vid_2bit)
 556 {
 557         struct kv_power_info *pi = kv_get_pi(rdev);
 558         u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
 559                                                  &pi->sys_info.vid_mapping_table,
 560                                                  vid_2bit);
 561
 562         return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
 563 }
 564
 565
 566 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 567 {
 568         struct kv_power_info *pi = kv_get_pi(rdev);
 569
 570         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 571         pi->graphics_level[index].MinVddNb =
 572                 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
 573
 574         return 0;
 575 }
 576
 577 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
 578 {
 579         struct kv_power_info *pi = kv_get_pi(rdev);
 580
 581         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 582
 583         return 0;
 584 }
 585
 586 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
 587                                       u32 index, bool enable)
 588 {
 589         struct kv_power_info *pi = kv_get_pi(rdev);
 590
 591         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 592 }
 593
 594 static void kv_start_dpm(struct radeon_device *rdev)
 595 {
 596         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
 597
 598         tmp |= GLOBAL_PWRMGT_EN;
 599         WREG32_SMC(GENERAL_PWRMGT, tmp);
 600
 601         kv_smc_dpm_enable(rdev, true);
 602 }
 603
 604 static void kv_stop_dpm(struct radeon_device *rdev)
 605 {
 606         kv_smc_dpm_enable(rdev, false);
 607 }
 608
 609 static void kv_start_am(struct radeon_device *rdev)
 610 {
 611         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 612
 613         sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
 614         sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
 615
 616         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 617 }
 618
 619 static void kv_reset_am(struct radeon_device *rdev)
 620 {
 621         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 622
 623         sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
 624
 625         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 626 }
 627
 628 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
 629 {
 630         return kv_notify_message_to_smu(rdev, freeze ?
 631                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 632 }
 633
 634 static int kv_force_lowest_valid(struct radeon_device *rdev)
 635 {
 636         return kv_force_dpm_lowest(rdev);
 637 }
 638
 639 static int kv_unforce_levels(struct radeon_device *rdev)
 640 {
 641         return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
 642 }
 643
 644 static int kv_update_sclk_t(struct radeon_device *rdev)
 645 {
 646         struct kv_power_info *pi = kv_get_pi(rdev);
 647         u32 low_sclk_interrupt_t = 0;
 648         int ret = 0;
 649
 650         if (pi->caps_sclk_throttle_low_notification) {
 651                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 652
 653                 ret = kv_copy_bytes_to_smc(rdev,
 654                                            pi->dpm_table_start +
 655                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 656                                            (u8 *)&low_sclk_interrupt_t,
 657                                            sizeof(u32), pi->sram_end);
 658         }
 659         return ret;
 660 }
 661
 662 static int kv_program_bootup_state(struct radeon_device *rdev)
 663 {
 664         struct kv_power_info *pi = kv_get_pi(rdev);
 665         u32 i;
 666         struct radeon_clock_voltage_dependency_table *table =
 667                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 668
 669         if (table && table->count) {
 670                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
 671                         if ((table->entries[i].clk == pi->boot_pl.sclk) ||
 672                             (i == 0))
 673                                 break;
 674                 }
 675
 676                 pi->graphics_boot_level = (u8)i;
 677                 kv_dpm_power_level_enable(rdev, i, true);
 678         } else {
 679                 struct sumo_sclk_voltage_mapping_table *table =
 680                         &pi->sys_info.sclk_voltage_mapping_table;
 681
 682                 if (table->num_max_dpm_entries == 0)
 683                         return -EINVAL;
 684
 685                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
 686                         if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) ||
 687                             (i == 0))
 688                                 break;
 689                 }
 690
 691                 pi->graphics_boot_level = (u8)i;
 692                 kv_dpm_power_level_enable(rdev, i, true);
 693         }
 694         return 0;
 695 }
 696
 697 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
 698 {
 699         struct kv_power_info *pi = kv_get_pi(rdev);
 700         int ret;
 701
 702         pi->graphics_therm_throttle_enable = 1;
 703
 704         ret = kv_copy_bytes_to_smc(rdev,
 705                                    pi->dpm_table_start +
 706                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 707                                    &pi->graphics_therm_throttle_enable,
 708                                    sizeof(u8), pi->sram_end);
 709
 710         return ret;
 711 }
 712
 713 static int kv_upload_dpm_settings(struct radeon_device *rdev)
 714 {
 715         struct kv_power_info *pi = kv_get_pi(rdev);
 716         int ret;
 717
 718         ret = kv_copy_bytes_to_smc(rdev,
 719                                    pi->dpm_table_start +
 720                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 721                                    (u8 *)&pi->graphics_level,
 722                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 723                                    pi->sram_end);
 724
 725         if (ret)
 726                 return ret;
 727
 728         ret = kv_copy_bytes_to_smc(rdev,
 729                                    pi->dpm_table_start +
 730                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 731                                    &pi->graphics_dpm_level_count,
 732                                    sizeof(u8), pi->sram_end);
 733
 734         return ret;
 735 }
 736
 737 static u32 kv_get_clock_difference(u32 a, u32 b)
 738 {
 739         return (a >= b) ? a - b : b - a;
 740 }
 741
 742 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
 743 {
 744         struct kv_power_info *pi = kv_get_pi(rdev);
 745         u32 value;
 746
 747         if (pi->caps_enable_dfs_bypass) {
 748                 if (kv_get_clock_difference(clk, 40000) < 200)
 749                         value = 3;
 750                 else if (kv_get_clock_difference(clk, 30000) < 200)
 751                         value = 2;
 752                 else if (kv_get_clock_difference(clk, 20000) < 200)
 753                         value = 7;
 754                 else if (kv_get_clock_difference(clk, 15000) < 200)
 755                         value = 6;
 756                 else if (kv_get_clock_difference(clk, 10000) < 200)
 757                         value = 8;
 758                 else
 759                         value = 0;
 760         } else {
 761                 value = 0;
 762         }
 763
 764         return value;
 765 }
 766
 767 static int kv_populate_uvd_table(struct radeon_device *rdev)
 768 {
 769         struct kv_power_info *pi = kv_get_pi(rdev);
 770         struct radeon_uvd_clock_voltage_dependency_table *table =
 771                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 772         struct atom_clock_dividers dividers;
 773         int ret;
 774         u32 i;
 775
 776         if (table == NULL || table->count == 0)
 777                 return 0;
 778
 779         pi->uvd_level_count = 0;
 780         for (i = 0; i < table->count; i++) {
 781                 if (pi->high_voltage_t &&
 782                     (pi->high_voltage_t < table->entries[i].v))
 783                         break;
 784
 785                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 786                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 787                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 788
 789                 pi->uvd_level[i].VClkBypassCntl =
 790                         (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
 791                 pi->uvd_level[i].DClkBypassCntl =
 792                         (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
 793
 794                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 795                                                      table->entries[i].vclk, false, &dividers);
 796                 if (ret)
 797                         return ret;
 798                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 799
 800                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 801                                                      table->entries[i].dclk, false, &dividers);
 802                 if (ret)
 803                         return ret;
 804                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 805
 806                 pi->uvd_level_count++;
 807         }
 808
 809         ret = kv_copy_bytes_to_smc(rdev,
 810                                    pi->dpm_table_start +
 811                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 812                                    (u8 *)&pi->uvd_level_count,
 813                                    sizeof(u8), pi->sram_end);
 814         if (ret)
 815                 return ret;
 816
 817         pi->uvd_interval = 1;
 818
 819         ret = kv_copy_bytes_to_smc(rdev,
 820                                    pi->dpm_table_start +
 821                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 822                                    &pi->uvd_interval,
 823                                    sizeof(u8), pi->sram_end);
 824         if (ret)
 825                 return ret;
 826
 827         ret = kv_copy_bytes_to_smc(rdev,
 828                                    pi->dpm_table_start +
 829                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 830                                    (u8 *)&pi->uvd_level,
 831                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 832                                    pi->sram_end);
 833
 834         return ret;
 835
 836 }
 837
 838 static int kv_populate_vce_table(struct radeon_device *rdev)
 839 {
 840         struct kv_power_info *pi = kv_get_pi(rdev);
 841         int ret;
 842         u32 i;
 843         struct radeon_vce_clock_voltage_dependency_table *table =
 844                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 845         struct atom_clock_dividers dividers;
 846
 847         if (table == NULL || table->count == 0)
 848                 return 0;
 849
 850         pi->vce_level_count = 0;
 851         for (i = 0; i < table->count; i++) {
 852                 if (pi->high_voltage_t &&
 853                     pi->high_voltage_t < table->entries[i].v)
 854                         break;
 855
 856                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 857                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 858
 859                 pi->vce_level[i].ClkBypassCntl =
 860                         (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
 861
 862                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 863                                                      table->entries[i].evclk, false, &dividers);
 864                 if (ret)
 865                         return ret;
 866                 pi->vce_level[i].Divider = (u8)dividers.post_div;
 867
 868                 pi->vce_level_count++;
 869         }
 870
 871         ret = kv_copy_bytes_to_smc(rdev,
 872                                    pi->dpm_table_start +
 873                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
 874                                    (u8 *)&pi->vce_level_count,
 875                                    sizeof(u8),
 876                                    pi->sram_end);
 877         if (ret)
 878                 return ret;
 879
 880         pi->vce_interval = 1;
 881
 882         ret = kv_copy_bytes_to_smc(rdev,
 883                                    pi->dpm_table_start +
 884                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
 885                                    (u8 *)&pi->vce_interval,
 886                                    sizeof(u8),
 887                                    pi->sram_end);
 888         if (ret)
 889                 return ret;
 890
 891         ret = kv_copy_bytes_to_smc(rdev,
 892                                    pi->dpm_table_start +
 893                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
 894                                    (u8 *)&pi->vce_level,
 895                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
 896                                    pi->sram_end);
 897
 898         return ret;
 899 }
 900
 901 static int kv_populate_samu_table(struct radeon_device *rdev)
 902 {
 903         struct kv_power_info *pi = kv_get_pi(rdev);
 904         struct radeon_clock_voltage_dependency_table *table =
 905                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
 906         struct atom_clock_dividers dividers;
 907         int ret;
 908         u32 i;
 909
 910         if (table == NULL || table->count == 0)
 911                 return 0;
 912
 913         pi->samu_level_count = 0;
 914         for (i = 0; i < table->count; i++) {
 915                 if (pi->high_voltage_t &&
 916                     pi->high_voltage_t < table->entries[i].v)
 917                         break;
 918
 919                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 920                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 921
 922                 pi->samu_level[i].ClkBypassCntl =
 923                         (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
 924
 925                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 926                                                      table->entries[i].clk, false, &dividers);
 927                 if (ret)
 928                         return ret;
 929                 pi->samu_level[i].Divider = (u8)dividers.post_div;
 930
 931                 pi->samu_level_count++;
 932         }
 933
 934         ret = kv_copy_bytes_to_smc(rdev,
 935                                    pi->dpm_table_start +
 936                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
 937                                    (u8 *)&pi->samu_level_count,
 938                                    sizeof(u8),
 939                                    pi->sram_end);
 940         if (ret)
 941                 return ret;
 942
 943         pi->samu_interval = 1;
 944
 945         ret = kv_copy_bytes_to_smc(rdev,
 946                                    pi->dpm_table_start +
 947                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
 948                                    (u8 *)&pi->samu_interval,
 949                                    sizeof(u8),
 950                                    pi->sram_end);
 951         if (ret)
 952                 return ret;
 953
 954         ret = kv_copy_bytes_to_smc(rdev,
 955                                    pi->dpm_table_start +
 956                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
 957                                    (u8 *)&pi->samu_level,
 958                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
 959                                    pi->sram_end);
 960         if (ret)
 961                 return ret;
 962
 963         return ret;
 964 }
 965
 966
 967 static int kv_populate_acp_table(struct radeon_device *rdev)
 968 {
 969         struct kv_power_info *pi = kv_get_pi(rdev);
 970         struct radeon_clock_voltage_dependency_table *table =
 971                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 972         struct atom_clock_dividers dividers;
 973         int ret;
 974         u32 i;
 975
 976         if (table == NULL || table->count == 0)
 977                 return 0;
 978
 979         pi->acp_level_count = 0;
 980         for (i = 0; i < table->count; i++) {
 981                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 982                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 983
 984                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 985                                                      table->entries[i].clk, false, &dividers);
 986                 if (ret)
 987                         return ret;
 988                 pi->acp_level[i].Divider = (u8)dividers.post_div;
 989
 990                 pi->acp_level_count++;
 991         }
 992
 993         ret = kv_copy_bytes_to_smc(rdev,
 994                                    pi->dpm_table_start +
 995                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
 996                                    (u8 *)&pi->acp_level_count,
 997                                    sizeof(u8),
 998                                    pi->sram_end);
 999         if (ret)
1000                 return ret;
1001
1002         pi->acp_interval = 1;
1003
1004         ret = kv_copy_bytes_to_smc(rdev,
1005                                    pi->dpm_table_start +
1006                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1007                                    (u8 *)&pi->acp_interval,
1008                                    sizeof(u8),
1009                                    pi->sram_end);
1010         if (ret)
1011                 return ret;
1012
1013         ret = kv_copy_bytes_to_smc(rdev,
1014                                    pi->dpm_table_start +
1015                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1016                                    (u8 *)&pi->acp_level,
1017                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1018                                    pi->sram_end);
1019         if (ret)
1020                 return ret;
1021
1022         return ret;
1023 }
1024
1025 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1026 {
1027         struct kv_power_info *pi = kv_get_pi(rdev);
1028         u32 i;
1029         struct radeon_clock_voltage_dependency_table *table =
1030                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1031
1032         if (table && table->count) {
1033                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1034                         if (pi->caps_enable_dfs_bypass) {
1035                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1036                                         pi->graphics_level[i].ClkBypassCntl = 3;
1037                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1038                                         pi->graphics_level[i].ClkBypassCntl = 2;
1039                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1040                                         pi->graphics_level[i].ClkBypassCntl = 7;
1041                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1042                                         pi->graphics_level[i].ClkBypassCntl = 6;
1043                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1044                                         pi->graphics_level[i].ClkBypassCntl = 8;
1045                                 else
1046                                         pi->graphics_level[i].ClkBypassCntl = 0;
1047                         } else {
1048                                 pi->graphics_level[i].ClkBypassCntl = 0;
1049                         }
1050                 }
1051         } else {
1052                 struct sumo_sclk_voltage_mapping_table *table =
1053                         &pi->sys_info.sclk_voltage_mapping_table;
1054                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1055                         if (pi->caps_enable_dfs_bypass) {
1056                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1057                                         pi->graphics_level[i].ClkBypassCntl = 3;
1058                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1059                                         pi->graphics_level[i].ClkBypassCntl = 2;
1060                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1061                                         pi->graphics_level[i].ClkBypassCntl = 7;
1062                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1063                                         pi->graphics_level[i].ClkBypassCntl = 6;
1064                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1065                                         pi->graphics_level[i].ClkBypassCntl = 8;
1066                                 else
1067                                         pi->graphics_level[i].ClkBypassCntl = 0;
1068                         } else {
1069                                 pi->graphics_level[i].ClkBypassCntl = 0;
1070                         }
1071                 }
1072         }
1073 }
1074
1075 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1076 {
1077         return kv_notify_message_to_smu(rdev, enable ?
1078                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1079 }
1080
1081 static void kv_update_current_ps(struct radeon_device *rdev,
1082                                  struct radeon_ps *rps)
1083 {
1084         struct kv_ps *new_ps = kv_get_ps(rps);
1085         struct kv_power_info *pi = kv_get_pi(rdev);
1086
1087         pi->current_rps = *rps;
1088         pi->current_ps = *new_ps;
1089         pi->current_rps.ps_priv = &pi->current_ps;
1090 }
1091
1092 static void kv_update_requested_ps(struct radeon_device *rdev,
1093                                    struct radeon_ps *rps)
1094 {
1095         struct kv_ps *new_ps = kv_get_ps(rps);
1096         struct kv_power_info *pi = kv_get_pi(rdev);
1097
1098         pi->requested_rps = *rps;
1099         pi->requested_ps = *new_ps;
1100         pi->requested_rps.ps_priv = &pi->requested_ps;
1101 }
1102
1103 int kv_dpm_enable(struct radeon_device *rdev)
1104 {
1105         struct kv_power_info *pi = kv_get_pi(rdev);
1106         int ret;
1107
1108         ret = kv_process_firmware_header(rdev);
1109         if (ret) {
1110                 DRM_ERROR("kv_process_firmware_header failed\n");
1111                 return ret;
1112         }
1113         kv_init_fps_limits(rdev);
1114         kv_init_graphics_levels(rdev);
1115         ret = kv_program_bootup_state(rdev);
1116         if (ret) {
1117                 DRM_ERROR("kv_program_bootup_state failed\n");
1118                 return ret;
1119         }
1120         kv_calculate_dfs_bypass_settings(rdev);
1121         ret = kv_upload_dpm_settings(rdev);
1122         if (ret) {
1123                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1124                 return ret;
1125         }
1126         ret = kv_populate_uvd_table(rdev);
1127         if (ret) {
1128                 DRM_ERROR("kv_populate_uvd_table failed\n");
1129                 return ret;
1130         }
1131         ret = kv_populate_vce_table(rdev);
1132         if (ret) {
1133                 DRM_ERROR("kv_populate_vce_table failed\n");
1134                 return ret;
1135         }
1136         ret = kv_populate_samu_table(rdev);
1137         if (ret) {
1138                 DRM_ERROR("kv_populate_samu_table failed\n");
1139                 return ret;
1140         }
1141         ret = kv_populate_acp_table(rdev);
1142         if (ret) {
1143                 DRM_ERROR("kv_populate_acp_table failed\n");
1144                 return ret;
1145         }
1146         kv_program_vc(rdev);
1147 #if 0
1148         kv_initialize_hardware_cac_manager(rdev);
1149 #endif
1150         kv_start_am(rdev);
1151         if (pi->enable_auto_thermal_throttling) {
1152                 ret = kv_enable_auto_thermal_throttling(rdev);
1153                 if (ret) {
1154                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1155                         return ret;
1156                 }
1157         }
1158         ret = kv_enable_dpm_voltage_scaling(rdev);
1159         if (ret) {
1160                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1161                 return ret;
1162         }
1163         ret = kv_set_dpm_interval(rdev);
1164         if (ret) {
1165                 DRM_ERROR("kv_set_dpm_interval failed\n");
1166                 return ret;
1167         }
1168         ret = kv_set_dpm_boot_state(rdev);
1169         if (ret) {
1170                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1171                 return ret;
1172         }
1173         ret = kv_enable_ulv(rdev, true);
1174         if (ret) {
1175                 DRM_ERROR("kv_enable_ulv failed\n");
1176                 return ret;
1177         }
1178         kv_start_dpm(rdev);
1179         ret = kv_enable_didt(rdev, true);
1180         if (ret) {
1181                 DRM_ERROR("kv_enable_didt failed\n");
1182                 return ret;
1183         }
1184         ret = kv_enable_smc_cac(rdev, true);
1185         if (ret) {
1186                 DRM_ERROR("kv_enable_smc_cac failed\n");
1187                 return ret;
1188         }
1189
1190         if (rdev->irq.installed &&
1191             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1192                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1193                 if (ret) {
1194                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1195                         return ret;
1196                 }
1197                 rdev->irq.dpm_thermal = true;
1198                 radeon_irq_set(rdev);
1199         }
1200
1201         /* powerdown unused blocks for now */
1202         kv_dpm_powergate_acp(rdev, true);
1203         kv_dpm_powergate_samu(rdev, true);
1204         kv_dpm_powergate_vce(rdev, true);
1205         kv_dpm_powergate_uvd(rdev, true);
1206
1207         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1208
1209         return ret;
1210 }
1211
1212 void kv_dpm_disable(struct radeon_device *rdev)
1213 {
1214         kv_enable_smc_cac(rdev, false);
1215         kv_enable_didt(rdev, false);
1216         kv_clear_vc(rdev);
1217         kv_stop_dpm(rdev);
1218         kv_enable_ulv(rdev, false);
1219         kv_reset_am(rdev);
1220
1221         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1222 }
1223
1224 #if 0
1225 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1226                                       u16 reg_offset, u32 value)
1227 {
1228         struct kv_power_info *pi = kv_get_pi(rdev);
1229
1230         return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1231                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1232 }
1233
1234 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1235                                      u16 reg_offset, u32 *value)
1236 {
1237         struct kv_power_info *pi = kv_get_pi(rdev);
1238
1239         return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1240                                       value, pi->sram_end);
1241 }
1242 #endif
1243
1244 static void kv_init_sclk_t(struct radeon_device *rdev)
1245 {
1246         struct kv_power_info *pi = kv_get_pi(rdev);
1247
1248         pi->low_sclk_interrupt_t = 0;
1249 }
1250
1251 static int kv_init_fps_limits(struct radeon_device *rdev)
1252 {
1253         struct kv_power_info *pi = kv_get_pi(rdev);
1254         int ret = 0;
1255
1256         if (pi->caps_fps) {
1257                 u16 tmp;
1258
1259                 tmp = 45;
1260                 pi->fps_high_t = cpu_to_be16(tmp);
1261                 ret = kv_copy_bytes_to_smc(rdev,
1262                                            pi->dpm_table_start +
1263                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1264                                            (u8 *)&pi->fps_high_t,
1265                                            sizeof(u16), pi->sram_end);
1266
1267                 tmp = 30;
1268                 pi->fps_low_t = cpu_to_be16(tmp);
1269
1270                 ret = kv_copy_bytes_to_smc(rdev,
1271                                            pi->dpm_table_start +
1272                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1273                                            (u8 *)&pi->fps_low_t,
1274                                            sizeof(u16), pi->sram_end);
1275
1276         }
1277         return ret;
1278 }
1279
1280 static void kv_init_powergate_state(struct radeon_device *rdev)
1281 {
1282         struct kv_power_info *pi = kv_get_pi(rdev);
1283
1284         pi->uvd_power_gated = false;
1285         pi->vce_power_gated = false;
1286         pi->samu_power_gated = false;
1287         pi->acp_power_gated = false;
1288
1289 }
1290
1291 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1292 {
1293         return kv_notify_message_to_smu(rdev, enable ?
1294                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1295 }
1296
1297 #if 0
1298 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1299 {
1300         return kv_notify_message_to_smu(rdev, enable ?
1301                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1302 }
1303 #endif
1304
1305 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1306 {
1307         return kv_notify_message_to_smu(rdev, enable ?
1308                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1309 }
1310
1311 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1312 {
1313         return kv_notify_message_to_smu(rdev, enable ?
1314                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1315 }
1316
1317 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1318 {
1319         struct kv_power_info *pi = kv_get_pi(rdev);
1320         struct radeon_uvd_clock_voltage_dependency_table *table =
1321                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1322         int ret;
1323
1324         if (!gate) {
1325                 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1326                         pi->uvd_boot_level = table->count - 1;
1327                 else
1328                         pi->uvd_boot_level = 0;
1329
1330                 ret = kv_copy_bytes_to_smc(rdev,
1331                                            pi->dpm_table_start +
1332                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1333                                            (uint8_t *)&pi->uvd_boot_level,
1334                                            sizeof(u8), pi->sram_end);
1335                 if (ret)
1336                         return ret;
1337
1338                 if (!pi->caps_uvd_dpm ||
1339                     pi->caps_stable_p_state)
1340                         kv_send_msg_to_smc_with_parameter(rdev,
1341                                                           PPSMC_MSG_UVDDPM_SetEnabledMask,
1342                                                           (1 << pi->uvd_boot_level));
1343         }
1344
1345         return kv_enable_uvd_dpm(rdev, !gate);
1346 }
1347
1348 #if 0
1349 static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1350 {
1351         u8 i;
1352         struct radeon_vce_clock_voltage_dependency_table *table =
1353                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1354
1355         for (i = 0; i < table->count; i++) {
1356                 if (table->entries[i].evclk >= 0) /* XXX */
1357                         break;
1358         }
1359
1360         return i;
1361 }
1362
1363 static int kv_update_vce_dpm(struct radeon_device *rdev,
1364                              struct radeon_ps *radeon_new_state,
1365                              struct radeon_ps *radeon_current_state)
1366 {
1367         struct kv_power_info *pi = kv_get_pi(rdev);
1368         struct radeon_vce_clock_voltage_dependency_table *table =
1369                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1370         int ret;
1371
1372         if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1373                 if (pi->caps_stable_p_state)
1374                         pi->vce_boot_level = table->count - 1;
1375                 else
1376                         pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1377
1378                 ret = kv_copy_bytes_to_smc(rdev,
1379                                            pi->dpm_table_start +
1380                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1381                                            (u8 *)&pi->vce_boot_level,
1382                                            sizeof(u8),
1383                                            pi->sram_end);
1384                 if (ret)
1385                         return ret;
1386
1387                 if (pi->caps_stable_p_state)
1388                         kv_send_msg_to_smc_with_parameter(rdev,
1389                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1390                                                           (1 << pi->vce_boot_level));
1391
1392                 kv_enable_vce_dpm(rdev, true);
1393         } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1394                 kv_enable_vce_dpm(rdev, false);
1395         }
1396
1397         return 0;
1398 }
1399 #endif
1400
1401 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1402 {
1403         struct kv_power_info *pi = kv_get_pi(rdev);
1404         struct radeon_clock_voltage_dependency_table *table =
1405                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1406         int ret;
1407
1408         if (!gate) {
1409                 if (pi->caps_stable_p_state)
1410                         pi->samu_boot_level = table->count - 1;
1411                 else
1412                         pi->samu_boot_level = 0;
1413
1414                 ret = kv_copy_bytes_to_smc(rdev,
1415                                            pi->dpm_table_start +
1416                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1417                                            (u8 *)&pi->samu_boot_level,
1418                                            sizeof(u8),
1419                                            pi->sram_end);
1420                 if (ret)
1421                         return ret;
1422
1423                 if (pi->caps_stable_p_state)
1424                         kv_send_msg_to_smc_with_parameter(rdev,
1425                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1426                                                           (1 << pi->samu_boot_level));
1427         }
1428
1429         return kv_enable_samu_dpm(rdev, !gate);
1430 }
1431
1432 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1433 {
1434         struct kv_power_info *pi = kv_get_pi(rdev);
1435         struct radeon_clock_voltage_dependency_table *table =
1436                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1437         int ret;
1438
1439         if (!gate) {
1440                 if (pi->caps_stable_p_state)
1441                         pi->acp_boot_level = table->count - 1;
1442                 else
1443                         pi->acp_boot_level = 0;
1444
1445                 ret = kv_copy_bytes_to_smc(rdev,
1446                                            pi->dpm_table_start +
1447                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1448                                            (u8 *)&pi->acp_boot_level,
1449                                            sizeof(u8),
1450                                            pi->sram_end);
1451                 if (ret)
1452                         return ret;
1453
1454                 if (pi->caps_stable_p_state)
1455                         kv_send_msg_to_smc_with_parameter(rdev,
1456                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1457                                                           (1 << pi->acp_boot_level));
1458         }
1459
1460         return kv_enable_acp_dpm(rdev, !gate);
1461 }
1462
1463 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1464 {
1465         struct kv_power_info *pi = kv_get_pi(rdev);
1466
1467         if (pi->uvd_power_gated == gate)
1468                 return;
1469
1470         pi->uvd_power_gated = gate;
1471
1472         if (gate) {
1473                 uvd_v1_0_stop(rdev);
1474                 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1475                 kv_update_uvd_dpm(rdev, gate);
1476                 if (pi->caps_uvd_pg)
1477                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1478         } else {
1479                 if (pi->caps_uvd_pg)
1480                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1481                 uvd_v4_2_resume(rdev);
1482                 uvd_v1_0_start(rdev);
1483                 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1484                 kv_update_uvd_dpm(rdev, gate);
1485         }
1486 }
1487
1488 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1489 {
1490         struct kv_power_info *pi = kv_get_pi(rdev);
1491
1492         if (pi->vce_power_gated == gate)
1493                 return;
1494
1495         pi->vce_power_gated = gate;
1496
1497         if (gate) {
1498                 if (pi->caps_vce_pg)
1499                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1500         } else {
1501                 if (pi->caps_vce_pg)
1502                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1503         }
1504 }
1505
1506 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1507 {
1508         struct kv_power_info *pi = kv_get_pi(rdev);
1509
1510         if (pi->samu_power_gated == gate)
1511                 return;
1512
1513         pi->samu_power_gated = gate;
1514
1515         if (gate) {
1516                 kv_update_samu_dpm(rdev, true);
1517                 if (pi->caps_samu_pg)
1518                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1519         } else {
1520                 if (pi->caps_samu_pg)
1521                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1522                 kv_update_samu_dpm(rdev, false);
1523         }
1524 }
1525
1526 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1527 {
1528         struct kv_power_info *pi = kv_get_pi(rdev);
1529
1530         if (pi->acp_power_gated == gate)
1531                 return;
1532
1533         if (rdev->family == CHIP_KABINI)
1534                 return;
1535
1536         pi->acp_power_gated = gate;
1537
1538         if (gate) {
1539                 kv_update_acp_dpm(rdev, true);
1540                 if (pi->caps_acp_pg)
1541                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1542         } else {
1543                 if (pi->caps_acp_pg)
1544                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1545                 kv_update_acp_dpm(rdev, false);
1546         }
1547 }
1548
1549 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1550                                      struct radeon_ps *new_rps)
1551 {
1552         struct kv_ps *new_ps = kv_get_ps(new_rps);
1553         struct kv_power_info *pi = kv_get_pi(rdev);
1554         u32 i;
1555         struct radeon_clock_voltage_dependency_table *table =
1556                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1557
1558         if (table && table->count) {
1559                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1560                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1561                             (i == (pi->graphics_dpm_level_count - 1))) {
1562                                 pi->lowest_valid = i;
1563                                 break;
1564                         }
1565                 }
1566
1567                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1568                         if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) ||
1569                             (i == 0)) {
1570                                 pi->highest_valid = i;
1571                                 break;
1572                         }
1573                 }
1574
1575                 if (pi->lowest_valid > pi->highest_valid) {
1576                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1577                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1578                                 pi->highest_valid = pi->lowest_valid;
1579                         else
1580                                 pi->lowest_valid =  pi->highest_valid;
1581                 }
1582         } else {
1583                 struct sumo_sclk_voltage_mapping_table *table =
1584                         &pi->sys_info.sclk_voltage_mapping_table;
1585
1586                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1587                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1588                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1589                                 pi->lowest_valid = i;
1590                                 break;
1591                         }
1592                 }
1593
1594                 for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) {
1595                         if (table->entries[i].sclk_frequency <=
1596                             new_ps->levels[new_ps->num_levels - 1].sclk ||
1597                             i == 0) {
1598                                 pi->highest_valid = i;
1599                                 break;
1600                         }
1601                 }
1602
1603                 if (pi->lowest_valid > pi->highest_valid) {
1604                         if ((new_ps->levels[0].sclk -
1605                              table->entries[pi->highest_valid].sclk_frequency) >
1606                             (table->entries[pi->lowest_valid].sclk_frequency -
1607                              new_ps->levels[new_ps->num_levels -1].sclk))
1608                                 pi->highest_valid = pi->lowest_valid;
1609                         else
1610                                 pi->lowest_valid =  pi->highest_valid;
1611                 }
1612         }
1613 }
1614
1615 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1616                                          struct radeon_ps *new_rps)
1617 {
1618         struct kv_ps *new_ps = kv_get_ps(new_rps);
1619         struct kv_power_info *pi = kv_get_pi(rdev);
1620         int ret = 0;
1621         u8 clk_bypass_cntl;
1622
1623         if (pi->caps_enable_dfs_bypass) {
1624                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1625                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1626                 ret = kv_copy_bytes_to_smc(rdev,
1627                                            (pi->dpm_table_start +
1628                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1629                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1630                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1631                                            &clk_bypass_cntl,
1632                                            sizeof(u8), pi->sram_end);
1633         }
1634
1635         return ret;
1636 }
1637
1638 static int kv_enable_nb_dpm(struct radeon_device *rdev)
1639 {
1640         struct kv_power_info *pi = kv_get_pi(rdev);
1641         int ret = 0;
1642
1643         if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1644                 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1645                 if (ret == 0)
1646                         pi->nb_dpm_enabled = true;
1647         }
1648
1649         return ret;
1650 }
1651
1652 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1653                                    enum radeon_dpm_forced_level level)
1654 {
1655         int ret;
1656
1657         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1658                 ret = kv_force_dpm_highest(rdev);
1659                 if (ret)
1660                         return ret;
1661         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1662                 ret = kv_force_dpm_lowest(rdev);
1663                 if (ret)
1664                         return ret;
1665         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1666                 ret = kv_unforce_levels(rdev);
1667                 if (ret)
1668                         return ret;
1669         }
1670
1671         rdev->pm.dpm.forced_level = level;
1672
1673         return 0;
1674 }
1675
1676 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1677 {
1678         struct kv_power_info *pi = kv_get_pi(rdev);
1679         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1680         struct radeon_ps *new_ps = &requested_ps;
1681
1682         kv_update_requested_ps(rdev, new_ps);
1683
1684         kv_apply_state_adjust_rules(rdev,
1685                                     &pi->requested_rps,
1686                                     &pi->current_rps);
1687
1688         return 0;
1689 }
1690
1691 int kv_dpm_set_power_state(struct radeon_device *rdev)
1692 {
1693         struct kv_power_info *pi = kv_get_pi(rdev);
1694         struct radeon_ps *new_ps = &pi->requested_rps;
1695         /*struct radeon_ps *old_ps = &pi->current_rps;*/
1696         int ret;
1697
1698         if (rdev->family == CHIP_KABINI) {
1699                 if (pi->enable_dpm) {
1700                         kv_set_valid_clock_range(rdev, new_ps);
1701                         kv_update_dfs_bypass_settings(rdev, new_ps);
1702                         ret = kv_calculate_ds_divider(rdev);
1703                         if (ret) {
1704                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1705                                 return ret;
1706                         }
1707                         kv_calculate_nbps_level_settings(rdev);
1708                         kv_calculate_dpm_settings(rdev);
1709                         kv_force_lowest_valid(rdev);
1710                         kv_enable_new_levels(rdev);
1711                         kv_upload_dpm_settings(rdev);
1712                         kv_program_nbps_index_settings(rdev, new_ps);
1713                         kv_unforce_levels(rdev);
1714                         kv_set_enabled_levels(rdev);
1715                         kv_force_lowest_valid(rdev);
1716                         kv_unforce_levels(rdev);
1717 #if 0
1718                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1719                         if (ret) {
1720                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1721                                 return ret;
1722                         }
1723 #endif
1724                         kv_update_sclk_t(rdev);
1725                 }
1726         } else {
1727                 if (pi->enable_dpm) {
1728                         kv_set_valid_clock_range(rdev, new_ps);
1729                         kv_update_dfs_bypass_settings(rdev, new_ps);
1730                         ret = kv_calculate_ds_divider(rdev);
1731                         if (ret) {
1732                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1733                                 return ret;
1734                         }
1735                         kv_calculate_nbps_level_settings(rdev);
1736                         kv_calculate_dpm_settings(rdev);
1737                         kv_freeze_sclk_dpm(rdev, true);
1738                         kv_upload_dpm_settings(rdev);
1739                         kv_program_nbps_index_settings(rdev, new_ps);
1740                         kv_freeze_sclk_dpm(rdev, false);
1741                         kv_set_enabled_levels(rdev);
1742 #if 0
1743                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1744                         if (ret) {
1745                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1746                                 return ret;
1747                         }
1748 #endif
1749                         kv_update_sclk_t(rdev);
1750                         kv_enable_nb_dpm(rdev);
1751                 }
1752         }
1753         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1754         return 0;
1755 }
1756
1757 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1758 {
1759         struct kv_power_info *pi = kv_get_pi(rdev);
1760         struct radeon_ps *new_ps = &pi->requested_rps;
1761
1762         kv_update_current_ps(rdev, new_ps);
1763 }
1764
1765 void kv_dpm_setup_asic(struct radeon_device *rdev)
1766 {
1767         sumo_take_smu_control(rdev, true);
1768         kv_init_powergate_state(rdev);
1769         kv_init_sclk_t(rdev);
1770 }
1771
1772 void kv_dpm_reset_asic(struct radeon_device *rdev)
1773 {
1774         kv_force_lowest_valid(rdev);
1775         kv_init_graphics_levels(rdev);
1776         kv_program_bootup_state(rdev);
1777         kv_upload_dpm_settings(rdev);
1778         kv_force_lowest_valid(rdev);
1779         kv_unforce_levels(rdev);
1780 }
1781
1782 //XXX use sumo_dpm_display_configuration_changed
1783
1784 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1785                                                 struct radeon_clock_and_voltage_limits *table)
1786 {
1787         struct kv_power_info *pi = kv_get_pi(rdev);
1788
1789         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1790                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1791                 table->sclk =
1792                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1793                 table->vddc =
1794                         kv_convert_2bit_index_to_voltage(rdev,
1795                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1796         }
1797
1798         table->mclk = pi->sys_info.nbp_memory_clock[0];
1799 }
1800
1801 static void kv_patch_voltage_values(struct radeon_device *rdev)
1802 {
1803         int i;
1804         struct radeon_uvd_clock_voltage_dependency_table *table =
1805                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1806
1807         if (table->count) {
1808                 for (i = 0; i < table->count; i++)
1809                         table->entries[i].v =
1810                                 kv_convert_8bit_index_to_voltage(rdev,
1811                                                                  table->entries[i].v);
1812         }
1813
1814 }
1815
1816 static void kv_construct_boot_state(struct radeon_device *rdev)
1817 {
1818         struct kv_power_info *pi = kv_get_pi(rdev);
1819
1820         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1821         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1822         pi->boot_pl.ds_divider_index = 0;
1823         pi->boot_pl.ss_divider_index = 0;
1824         pi->boot_pl.allow_gnb_slow = 1;
1825         pi->boot_pl.force_nbp_state = 0;
1826         pi->boot_pl.display_wm = 0;
1827         pi->boot_pl.vce_wm = 0;
1828 }
1829
1830 static int kv_force_dpm_highest(struct radeon_device *rdev)
1831 {
1832         int ret;
1833         u32 enable_mask, i;
1834
1835         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1836         if (ret)
1837                 return ret;
1838
1839         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) {
1840                 if (enable_mask & (1 << i))
1841                         break;
1842         }
1843
1844         return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1845 }
1846
1847 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1848 {
1849         int ret;
1850         u32 enable_mask, i;
1851
1852         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1853         if (ret)
1854                 return ret;
1855
1856         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1857                 if (enable_mask & (1 << i))
1858                         break;
1859         }
1860
1861         return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1862 }
1863
1864 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1865                                              u32 sclk, u32 min_sclk_in_sr)
1866 {
1867         struct kv_power_info *pi = kv_get_pi(rdev);
1868         u32 i;
1869         u32 temp;
1870         u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1871                 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1872
1873         if (sclk < min)
1874                 return 0;
1875
1876         if (!pi->caps_sclk_ds)
1877                 return 0;
1878
1879         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) {
1880                 temp = sclk / sumo_get_sleep_divider_from_id(i);
1881                 if ((temp >= min) || (i == 0))
1882                         break;
1883         }
1884
1885         return (u8)i;
1886 }
1887
1888 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
1889 {
1890         struct kv_power_info *pi = kv_get_pi(rdev);
1891         struct radeon_clock_voltage_dependency_table *table =
1892                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1893         int i;
1894
1895         if (table && table->count) {
1896                 for (i = table->count - 1; i >= 0; i--) {
1897                         if (pi->high_voltage_t &&
1898                             (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
1899                              pi->high_voltage_t)) {
1900                                 *limit = i;
1901                                 return 0;
1902                         }
1903                 }
1904         } else {
1905                 struct sumo_sclk_voltage_mapping_table *table =
1906                         &pi->sys_info.sclk_voltage_mapping_table;
1907
1908                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
1909                         if (pi->high_voltage_t &&
1910                             (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
1911                              pi->high_voltage_t)) {
1912                                 *limit = i;
1913                                 return 0;
1914                         }
1915                 }
1916         }
1917
1918         *limit = 0;
1919         return 0;
1920 }
1921
1922 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
1923                                         struct radeon_ps *new_rps,
1924                                         struct radeon_ps *old_rps)
1925 {
1926         struct kv_ps *ps = kv_get_ps(new_rps);
1927         struct kv_power_info *pi = kv_get_pi(rdev);
1928         u32 min_sclk = 10000; /* ??? */
1929         u32 sclk, mclk = 0;
1930         int i, limit;
1931         bool force_high;
1932         struct radeon_clock_voltage_dependency_table *table =
1933                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1934         u32 stable_p_state_sclk = 0;
1935         struct radeon_clock_and_voltage_limits *max_limits =
1936                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1937
1938         mclk = max_limits->mclk;
1939         sclk = min_sclk;
1940
1941         if (pi->caps_stable_p_state) {
1942                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
1943
1944                 for (i = table->count - 1; i >= 0; i++) {
1945                         if (stable_p_state_sclk >= table->entries[i].clk) {
1946                                 stable_p_state_sclk = table->entries[i].clk;
1947                                 break;
1948                         }
1949                 }
1950
1951                 if (i > 0)
1952                         stable_p_state_sclk = table->entries[0].clk;
1953
1954                 sclk = stable_p_state_sclk;
1955         }
1956
1957         ps->need_dfs_bypass = true;
1958
1959         for (i = 0; i < ps->num_levels; i++) {
1960                 if (ps->levels[i].sclk < sclk)
1961                         ps->levels[i].sclk = sclk;
1962         }
1963
1964         if (table && table->count) {
1965                 for (i = 0; i < ps->num_levels; i++) {
1966                         if (pi->high_voltage_t &&
1967                             (pi->high_voltage_t <
1968                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
1969                                 kv_get_high_voltage_limit(rdev, &limit);
1970                                 ps->levels[i].sclk = table->entries[limit].clk;
1971                         }
1972                 }
1973         } else {
1974                 struct sumo_sclk_voltage_mapping_table *table =
1975                         &pi->sys_info.sclk_voltage_mapping_table;
1976
1977                 for (i = 0; i < ps->num_levels; i++) {
1978                         if (pi->high_voltage_t &&
1979                             (pi->high_voltage_t <
1980                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
1981                                 kv_get_high_voltage_limit(rdev, &limit);
1982                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
1983                         }
1984                 }
1985         }
1986
1987         if (pi->caps_stable_p_state) {
1988                 for (i = 0; i < ps->num_levels; i++) {
1989                         ps->levels[i].sclk = stable_p_state_sclk;
1990                 }
1991         }
1992
1993         pi->video_start = new_rps->dclk || new_rps->vclk;
1994
1995         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1996             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1997                 pi->battery_state = true;
1998         else
1999                 pi->battery_state = false;
2000
2001         if (rdev->family == CHIP_KABINI) {
2002                 ps->dpm0_pg_nb_ps_lo = 0x1;
2003                 ps->dpm0_pg_nb_ps_hi = 0x0;
2004                 ps->dpmx_nb_ps_lo = 0x1;
2005                 ps->dpmx_nb_ps_hi = 0x0;
2006         } else {
2007                 ps->dpm0_pg_nb_ps_lo = 0x1;
2008                 ps->dpm0_pg_nb_ps_hi = 0x0;
2009                 ps->dpmx_nb_ps_lo = 0x2;
2010                 ps->dpmx_nb_ps_hi = 0x1;
2011
2012                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2013                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2014                                 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2015                                 pi->disable_nb_ps3_in_battery;
2016                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2017                         ps->dpm0_pg_nb_ps_hi = 0x2;
2018                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2019                         ps->dpmx_nb_ps_hi = 0x2;
2020                 }
2021         }
2022 }
2023
2024 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2025                                                     u32 index, bool enable)
2026 {
2027         struct kv_power_info *pi = kv_get_pi(rdev);
2028
2029         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2030 }
2031
2032 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2033 {
2034         struct kv_power_info *pi = kv_get_pi(rdev);
2035         u32 sclk_in_sr = 10000; /* ??? */
2036         u32 i;
2037
2038         if (pi->lowest_valid > pi->highest_valid)
2039                 return -EINVAL;
2040
2041         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2042                 pi->graphics_level[i].DeepSleepDivId =
2043                         kv_get_sleep_divider_id_from_clock(rdev,
2044                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2045                                                            sclk_in_sr);
2046         }
2047         return 0;
2048 }
2049
2050 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2051 {
2052         struct kv_power_info *pi = kv_get_pi(rdev);
2053         u32 i;
2054         bool force_high;
2055         struct radeon_clock_and_voltage_limits *max_limits =
2056                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2057         u32 mclk = max_limits->mclk;
2058
2059         if (pi->lowest_valid > pi->highest_valid)
2060                 return -EINVAL;
2061
2062         if (rdev->family == CHIP_KABINI) {
2063                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2064                         pi->graphics_level[i].GnbSlow = 1;
2065                         pi->graphics_level[i].ForceNbPs1 = 0;
2066                         pi->graphics_level[i].UpH = 0;
2067                 }
2068
2069                 if (!pi->sys_info.nb_dpm_enable)
2070                         return 0;
2071
2072                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2073                               (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2074
2075                 if (force_high) {
2076                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2077                                 pi->graphics_level[i].GnbSlow = 0;
2078                 } else {
2079                         if (pi->battery_state)
2080                                 pi->graphics_level[0].ForceNbPs1 = 1;
2081
2082                         pi->graphics_level[1].GnbSlow = 0;
2083                         pi->graphics_level[2].GnbSlow = 0;
2084                         pi->graphics_level[3].GnbSlow = 0;
2085                         pi->graphics_level[4].GnbSlow = 0;
2086                 }
2087         } else {
2088                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2089                         pi->graphics_level[i].GnbSlow = 1;
2090                         pi->graphics_level[i].ForceNbPs1 = 0;
2091                         pi->graphics_level[i].UpH = 0;
2092                 }
2093
2094                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2095                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2096                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2097                         if (pi->lowest_valid != pi->highest_valid)
2098                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2099                 }
2100         }
2101         return 0;
2102 }
2103
2104 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2105 {
2106         struct kv_power_info *pi = kv_get_pi(rdev);
2107         u32 i;
2108
2109         if (pi->lowest_valid > pi->highest_valid)
2110                 return -EINVAL;
2111
2112         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2113                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2114
2115         return 0;
2116 }
2117
2118 static void kv_init_graphics_levels(struct radeon_device *rdev)
2119 {
2120         struct kv_power_info *pi = kv_get_pi(rdev);
2121         u32 i;
2122         struct radeon_clock_voltage_dependency_table *table =
2123                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2124
2125         if (table && table->count) {
2126                 u32 vid_2bit;
2127
2128                 pi->graphics_dpm_level_count = 0;
2129                 for (i = 0; i < table->count; i++) {
2130                         if (pi->high_voltage_t &&
2131                             (pi->high_voltage_t <
2132                              kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2133                                 break;
2134
2135                         kv_set_divider_value(rdev, i, table->entries[i].clk);
2136                         vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2137                                                              &pi->sys_info.vid_mapping_table,
2138                                                              table->entries[i].v);
2139                         kv_set_vid(rdev, i, vid_2bit);
2140                         kv_set_at(rdev, i, pi->at[i]);
2141                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2142                         pi->graphics_dpm_level_count++;
2143                 }
2144         } else {
2145                 struct sumo_sclk_voltage_mapping_table *table =
2146                         &pi->sys_info.sclk_voltage_mapping_table;
2147
2148                 pi->graphics_dpm_level_count = 0;
2149                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2150                         if (pi->high_voltage_t &&
2151                             pi->high_voltage_t <
2152                             kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2153                                 break;
2154
2155                         kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2156                         kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2157                         kv_set_at(rdev, i, pi->at[i]);
2158                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2159                         pi->graphics_dpm_level_count++;
2160                 }
2161         }
2162
2163         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2164                 kv_dpm_power_level_enable(rdev, i, false);
2165 }
2166
2167 static void kv_enable_new_levels(struct radeon_device *rdev)
2168 {
2169         struct kv_power_info *pi = kv_get_pi(rdev);
2170         u32 i;
2171
2172         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2173                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2174                         kv_dpm_power_level_enable(rdev, i, true);
2175         }
2176 }
2177
2178 static int kv_set_enabled_levels(struct radeon_device *rdev)
2179 {
2180         struct kv_power_info *pi = kv_get_pi(rdev);
2181         u32 i, new_mask = 0;
2182
2183         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2184                 new_mask |= (1 << i);
2185
2186         return kv_send_msg_to_smc_with_parameter(rdev,
2187                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2188                                                  new_mask);
2189 }
2190
2191 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2192                                            struct radeon_ps *new_rps)
2193 {
2194         struct kv_ps *new_ps = kv_get_ps(new_rps);
2195         struct kv_power_info *pi = kv_get_pi(rdev);
2196         u32 nbdpmconfig1;
2197
2198         if (rdev->family == CHIP_KABINI)
2199                 return;
2200
2201         if (pi->sys_info.nb_dpm_enable) {
2202                 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2203                 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2204                                   DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2205                 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2206                                  Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2207                                  DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2208                                  DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2209                 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2210         }
2211 }
2212
2213 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2214                                             int min_temp, int max_temp)
2215 {
2216         int low_temp = 0 * 1000;
2217         int high_temp = 255 * 1000;
2218         u32 tmp;
2219
2220         if (low_temp < min_temp)
2221                 low_temp = min_temp;
2222         if (high_temp > max_temp)
2223                 high_temp = max_temp;
2224         if (high_temp < low_temp) {
2225                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2226                 return -EINVAL;
2227         }
2228
2229         tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2230         tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2231         tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2232                 DIG_THERM_INTL(49 + (low_temp / 1000)));
2233         WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2234
2235         rdev->pm.dpm.thermal.min_temp = low_temp;
2236         rdev->pm.dpm.thermal.max_temp = high_temp;
2237
2238         return 0;
2239 }
2240
2241 union igp_info {
2242         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2243         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2244         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2245         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2246         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2247         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2248 };
2249
2250 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2251 {
2252         struct kv_power_info *pi = kv_get_pi(rdev);
2253         struct radeon_mode_info *mode_info = &rdev->mode_info;
2254         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2255         union igp_info *igp_info;
2256         u8 frev, crev;
2257         u16 data_offset;
2258         int i;
2259
2260         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2261                                    &frev, &crev, &data_offset)) {
2262                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2263                                               data_offset);
2264
2265                 if (crev != 8) {
2266                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2267                         return -EINVAL;
2268                 }
2269                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2270                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2271                 pi->sys_info.bootup_nb_voltage_index =
2272                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2273                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2274                         pi->sys_info.htc_tmp_lmt = 203;
2275                 else
2276                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2277                 if (igp_info->info_8.ucHtcHystLmt == 0)
2278                         pi->sys_info.htc_hyst_lmt = 5;
2279                 else
2280                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2281                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2282                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2283                 }
2284
2285                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2286                         pi->sys_info.nb_dpm_enable = true;
2287                 else
2288                         pi->sys_info.nb_dpm_enable = false;
2289
2290                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2291                         pi->sys_info.nbp_memory_clock[i] =
2292                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2293                         pi->sys_info.nbp_n_clock[i] =
2294                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2295                 }
2296                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2297                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2298                         pi->caps_enable_dfs_bypass = true;
2299
2300                 sumo_construct_sclk_voltage_mapping_table(rdev,
2301                                                           &pi->sys_info.sclk_voltage_mapping_table,
2302                                                           igp_info->info_8.sAvail_SCLK);
2303
2304                 sumo_construct_vid_mapping_table(rdev,
2305                                                  &pi->sys_info.vid_mapping_table,
2306                                                  igp_info->info_8.sAvail_SCLK);
2307
2308                 kv_construct_max_power_limits_table(rdev,
2309                                                     &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2310         }
2311         return 0;
2312 }
2313
2314 union power_info {
2315         struct _ATOM_POWERPLAY_INFO info;
2316         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2317         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2318         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2319         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2320         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2321 };
2322
2323 union pplib_clock_info {
2324         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2325         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2326         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2327         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2328 };
2329
2330 union pplib_power_state {
2331         struct _ATOM_PPLIB_STATE v1;
2332         struct _ATOM_PPLIB_STATE_V2 v2;
2333 };
2334
2335 static void kv_patch_boot_state(struct radeon_device *rdev,
2336                                 struct kv_ps *ps)
2337 {
2338         struct kv_power_info *pi = kv_get_pi(rdev);
2339
2340         ps->num_levels = 1;
2341         ps->levels[0] = pi->boot_pl;
2342 }
2343
2344 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2345                                           struct radeon_ps *rps,
2346                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2347                                           u8 table_rev)
2348 {
2349         struct kv_ps *ps = kv_get_ps(rps);
2350
2351         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2352         rps->class = le16_to_cpu(non_clock_info->usClassification);
2353         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2354
2355         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2356                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2357                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2358         } else {
2359                 rps->vclk = 0;
2360                 rps->dclk = 0;
2361         }
2362
2363         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2364                 rdev->pm.dpm.boot_ps = rps;
2365                 kv_patch_boot_state(rdev, ps);
2366         }
2367         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2368                 rdev->pm.dpm.uvd_ps = rps;
2369 }
2370
2371 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2372                                       struct radeon_ps *rps, int index,
2373                                         union pplib_clock_info *clock_info)
2374 {
2375         struct kv_power_info *pi = kv_get_pi(rdev);
2376         struct kv_ps *ps = kv_get_ps(rps);
2377         struct kv_pl *pl = &ps->levels[index];
2378         u32 sclk;
2379
2380         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2381         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2382         pl->sclk = sclk;
2383         pl->vddc_index = clock_info->sumo.vddcIndex;
2384
2385         ps->num_levels = index + 1;
2386
2387         if (pi->caps_sclk_ds) {
2388                 pl->ds_divider_index = 5;
2389                 pl->ss_divider_index = 5;
2390         }
2391 }
2392
2393 static int kv_parse_power_table(struct radeon_device *rdev)
2394 {
2395         struct radeon_mode_info *mode_info = &rdev->mode_info;
2396         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2397         union pplib_power_state *power_state;
2398         int i, j, k, non_clock_array_index, clock_array_index;
2399         union pplib_clock_info *clock_info;
2400         struct _StateArray *state_array;
2401         struct _ClockInfoArray *clock_info_array;
2402         struct _NonClockInfoArray *non_clock_info_array;
2403         union power_info *power_info;
2404         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2405         u16 data_offset;
2406         u8 frev, crev;
2407         u8 *power_state_offset;
2408         struct kv_ps *ps;
2409
2410         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2411                                    &frev, &crev, &data_offset))
2412                 return -EINVAL;
2413         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2414
2415         state_array = (struct _StateArray *)
2416                 (mode_info->atom_context->bios + data_offset +
2417                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2418         clock_info_array = (struct _ClockInfoArray *)
2419                 (mode_info->atom_context->bios + data_offset +
2420                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2421         non_clock_info_array = (struct _NonClockInfoArray *)
2422                 (mode_info->atom_context->bios + data_offset +
2423                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2424
2425         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2426                                   state_array->ucNumEntries, GFP_KERNEL);
2427         if (!rdev->pm.dpm.ps)
2428                 return -ENOMEM;
2429         power_state_offset = (u8 *)state_array->states;
2430         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2431         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2432         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2433         for (i = 0; i < state_array->ucNumEntries; i++) {
2434                 power_state = (union pplib_power_state *)power_state_offset;
2435                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2436                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2437                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2438                 if (!rdev->pm.power_state[i].clock_info)
2439                         return -EINVAL;
2440                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2441                 if (ps == NULL) {
2442                         kfree(rdev->pm.dpm.ps);
2443                         return -ENOMEM;
2444                 }
2445                 rdev->pm.dpm.ps[i].ps_priv = ps;
2446                 k = 0;
2447                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2448                         clock_array_index = power_state->v2.clockInfoIndex[j];
2449                         if (clock_array_index >= clock_info_array->ucNumEntries)
2450                                 continue;
2451                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2452                                 break;
2453                         clock_info = (union pplib_clock_info *)
2454                                 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2455                         kv_parse_pplib_clock_info(rdev,
2456                                                   &rdev->pm.dpm.ps[i], k,
2457                                                   clock_info);
2458                         k++;
2459                 }
2460                 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2461                                               non_clock_info,
2462                                               non_clock_info_array->ucEntrySize);
2463                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2464         }
2465         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2466         return 0;
2467 }
2468
2469 int kv_dpm_init(struct radeon_device *rdev)
2470 {
2471         struct kv_power_info *pi;
2472         int ret, i;
2473
2474         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2475         if (pi == NULL)
2476                 return -ENOMEM;
2477         rdev->pm.dpm.priv = pi;
2478
2479         ret = r600_parse_extended_power_table(rdev);
2480         if (ret)
2481                 return ret;
2482
2483         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2484                 pi->at[i] = TRINITY_AT_DFLT;
2485
2486         pi->sram_end = SMC_RAM_END;
2487
2488         if (rdev->family == CHIP_KABINI)
2489                 pi->high_voltage_t = 4001;
2490
2491         pi->enable_nb_dpm = true;
2492
2493         pi->caps_power_containment = true;
2494         pi->caps_cac = true;
2495         pi->enable_didt = false;
2496         if (pi->enable_didt) {
2497                 pi->caps_sq_ramping = true;
2498                 pi->caps_db_ramping = true;
2499                 pi->caps_td_ramping = true;
2500                 pi->caps_tcp_ramping = true;
2501         }
2502
2503         pi->caps_sclk_ds = true;
2504         pi->enable_auto_thermal_throttling = true;
2505         pi->disable_nb_ps3_in_battery = false;
2506         pi->bapm_enable = true;
2507         pi->voltage_drop_t = 0;
2508         pi->caps_sclk_throttle_low_notification = false;
2509         pi->caps_fps = false; /* true? */
2510         pi->caps_uvd_pg = true;
2511         pi->caps_uvd_dpm = true;
2512         pi->caps_vce_pg = false;
2513         pi->caps_samu_pg = false;
2514         pi->caps_acp_pg = false;
2515         pi->caps_stable_p_state = false;
2516
2517         ret = kv_parse_sys_info_table(rdev);
2518         if (ret)
2519                 return ret;
2520
2521         kv_patch_voltage_values(rdev);
2522         kv_construct_boot_state(rdev);
2523
2524         ret = kv_parse_power_table(rdev);
2525         if (ret)
2526                 return ret;
2527
2528         pi->enable_dpm = true;
2529
2530         return 0;
2531 }
2532
2533 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2534                                                     struct seq_file *m)
2535 {
2536         struct kv_power_info *pi = kv_get_pi(rdev);
2537         u32 current_index =
2538                 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2539                 CURR_SCLK_INDEX_SHIFT;
2540         u32 sclk, tmp;
2541         u16 vddc;
2542
2543         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2544                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2545         } else {
2546                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2547                 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2548                         SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2549                 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2550                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2551                            current_index, sclk, vddc);
2552         }
2553 }
2554
2555 void kv_dpm_print_power_state(struct radeon_device *rdev,
2556                               struct radeon_ps *rps)
2557 {
2558         int i;
2559         struct kv_ps *ps = kv_get_ps(rps);
2560
2561         r600_dpm_print_class_info(rps->class, rps->class2);
2562         r600_dpm_print_cap_info(rps->caps);
2563         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2564         for (i = 0; i < ps->num_levels; i++) {
2565                 struct kv_pl *pl = &ps->levels[i];
2566                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2567                        i, pl->sclk,
2568                        kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2569         }
2570         r600_dpm_print_ps_status(rdev, rps);
2571 }
2572
2573 void kv_dpm_fini(struct radeon_device *rdev)
2574 {
2575         int i;
2576
2577         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2578                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2579         }
2580         kfree(rdev->pm.dpm.ps);
2581         kfree(rdev->pm.dpm.priv);
2582         r600_free_extended_power_table(rdev);
2583 }
2584
2585 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2586 {
2587
2588 }
2589
2590 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2591 {
2592         struct kv_power_info *pi = kv_get_pi(rdev);
2593         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2594
2595         if (low)
2596                 return requested_state->levels[0].sclk;
2597         else
2598                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2599 }
2600
2601 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2602 {
2603         struct kv_power_info *pi = kv_get_pi(rdev);
2604
2605         return pi->sys_info.bootup_uma_clk;
2606 }
2607