drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "nid.h"
  33 #include "atom.h"
  34 #include "ni_reg.h"
  35 #include "cayman_blit_shaders.h"
  36
  37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  40 extern void evergreen_mc_program(struct radeon_device *rdev);
  41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  42 extern int evergreen_mc_init(struct radeon_device *rdev);
  43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  45 extern void si_rlc_fini(struct radeon_device *rdev);
  46 extern int si_rlc_init(struct radeon_device *rdev);
  47
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define BTC_MC_UCODE_SIZE 6024
  52
  53 #define CAYMAN_PFP_UCODE_SIZE 2176
  54 #define CAYMAN_PM4_UCODE_SIZE 2176
  55 #define CAYMAN_RLC_UCODE_SIZE 1024
  56 #define CAYMAN_MC_UCODE_SIZE 6037
  57
  58 #define ARUBA_RLC_UCODE_SIZE 1536
  59
  60 /* Firmware Names */
  61 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  62 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  63 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  64 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  65 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  66 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  67 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  68 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  69 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  70 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  71 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  72 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  73 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  74 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  75 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
  76 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
  77 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
  78
  79 #define BTC_IO_MC_REGS_SIZE 29
  80
  81 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  82         {0x00000077, 0xff010100},
  83         {0x00000078, 0x00000000},
  84         {0x00000079, 0x00001434},
  85         {0x0000007a, 0xcc08ec08},
  86         {0x0000007b, 0x00040000},
  87         {0x0000007c, 0x000080c0},
  88         {0x0000007d, 0x09000000},
  89         {0x0000007e, 0x00210404},
  90         {0x00000081, 0x08a8e800},
  91         {0x00000082, 0x00030444},
  92         {0x00000083, 0x00000000},
  93         {0x00000085, 0x00000001},
  94         {0x00000086, 0x00000002},
  95         {0x00000087, 0x48490000},
  96         {0x00000088, 0x20244647},
  97         {0x00000089, 0x00000005},
  98         {0x0000008b, 0x66030000},
  99         {0x0000008c, 0x00006603},
 100         {0x0000008d, 0x00000100},
 101         {0x0000008f, 0x00001c0a},
 102         {0x00000090, 0xff000001},
 103         {0x00000094, 0x00101101},
 104         {0x00000095, 0x00000fff},
 105         {0x00000096, 0x00116fff},
 106         {0x00000097, 0x60010000},
 107         {0x00000098, 0x10010000},
 108         {0x00000099, 0x00006000},
 109         {0x0000009a, 0x00001000},
 110         {0x0000009f, 0x00946a00}
 111 };
 112
 113 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 114         {0x00000077, 0xff010100},
 115         {0x00000078, 0x00000000},
 116         {0x00000079, 0x00001434},
 117         {0x0000007a, 0xcc08ec08},
 118         {0x0000007b, 0x00040000},
 119         {0x0000007c, 0x000080c0},
 120         {0x0000007d, 0x09000000},
 121         {0x0000007e, 0x00210404},
 122         {0x00000081, 0x08a8e800},
 123         {0x00000082, 0x00030444},
 124         {0x00000083, 0x00000000},
 125         {0x00000085, 0x00000001},
 126         {0x00000086, 0x00000002},
 127         {0x00000087, 0x48490000},
 128         {0x00000088, 0x20244647},
 129         {0x00000089, 0x00000005},
 130         {0x0000008b, 0x66030000},
 131         {0x0000008c, 0x00006603},
 132         {0x0000008d, 0x00000100},
 133         {0x0000008f, 0x00001c0a},
 134         {0x00000090, 0xff000001},
 135         {0x00000094, 0x00101101},
 136         {0x00000095, 0x00000fff},
 137         {0x00000096, 0x00116fff},
 138         {0x00000097, 0x60010000},
 139         {0x00000098, 0x10010000},
 140         {0x00000099, 0x00006000},
 141         {0x0000009a, 0x00001000},
 142         {0x0000009f, 0x00936a00}
 143 };
 144
 145 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 146         {0x00000077, 0xff010100},
 147         {0x00000078, 0x00000000},
 148         {0x00000079, 0x00001434},
 149         {0x0000007a, 0xcc08ec08},
 150         {0x0000007b, 0x00040000},
 151         {0x0000007c, 0x000080c0},
 152         {0x0000007d, 0x09000000},
 153         {0x0000007e, 0x00210404},
 154         {0x00000081, 0x08a8e800},
 155         {0x00000082, 0x00030444},
 156         {0x00000083, 0x00000000},
 157         {0x00000085, 0x00000001},
 158         {0x00000086, 0x00000002},
 159         {0x00000087, 0x48490000},
 160         {0x00000088, 0x20244647},
 161         {0x00000089, 0x00000005},
 162         {0x0000008b, 0x66030000},
 163         {0x0000008c, 0x00006603},
 164         {0x0000008d, 0x00000100},
 165         {0x0000008f, 0x00001c0a},
 166         {0x00000090, 0xff000001},
 167         {0x00000094, 0x00101101},
 168         {0x00000095, 0x00000fff},
 169         {0x00000096, 0x00116fff},
 170         {0x00000097, 0x60010000},
 171         {0x00000098, 0x10010000},
 172         {0x00000099, 0x00006000},
 173         {0x0000009a, 0x00001000},
 174         {0x0000009f, 0x00916a00}
 175 };
 176
 177 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 178         {0x00000077, 0xff010100},
 179         {0x00000078, 0x00000000},
 180         {0x00000079, 0x00001434},
 181         {0x0000007a, 0xcc08ec08},
 182         {0x0000007b, 0x00040000},
 183         {0x0000007c, 0x000080c0},
 184         {0x0000007d, 0x09000000},
 185         {0x0000007e, 0x00210404},
 186         {0x00000081, 0x08a8e800},
 187         {0x00000082, 0x00030444},
 188         {0x00000083, 0x00000000},
 189         {0x00000085, 0x00000001},
 190         {0x00000086, 0x00000002},
 191         {0x00000087, 0x48490000},
 192         {0x00000088, 0x20244647},
 193         {0x00000089, 0x00000005},
 194         {0x0000008b, 0x66030000},
 195         {0x0000008c, 0x00006603},
 196         {0x0000008d, 0x00000100},
 197         {0x0000008f, 0x00001c0a},
 198         {0x00000090, 0xff000001},
 199         {0x00000094, 0x00101101},
 200         {0x00000095, 0x00000fff},
 201         {0x00000096, 0x00116fff},
 202         {0x00000097, 0x60010000},
 203         {0x00000098, 0x10010000},
 204         {0x00000099, 0x00006000},
 205         {0x0000009a, 0x00001000},
 206         {0x0000009f, 0x00976b00}
 207 };
 208
 209 int ni_mc_load_microcode(struct radeon_device *rdev)
 210 {
 211         const __be32 *fw_data;
 212         u32 mem_type, running, blackout = 0;
 213         u32 *io_mc_regs;
 214         int i, ucode_size, regs_size;
 215
 216         if (!rdev->mc_fw)
 217                 return -EINVAL;
 218
 219         switch (rdev->family) {
 220         case CHIP_BARTS:
 221                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 222                 ucode_size = BTC_MC_UCODE_SIZE;
 223                 regs_size = BTC_IO_MC_REGS_SIZE;
 224                 break;
 225         case CHIP_TURKS:
 226                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 227                 ucode_size = BTC_MC_UCODE_SIZE;
 228                 regs_size = BTC_IO_MC_REGS_SIZE;
 229                 break;
 230         case CHIP_CAICOS:
 231         default:
 232                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 233                 ucode_size = BTC_MC_UCODE_SIZE;
 234                 regs_size = BTC_IO_MC_REGS_SIZE;
 235                 break;
 236         case CHIP_CAYMAN:
 237                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 238                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 239                 regs_size = BTC_IO_MC_REGS_SIZE;
 240                 break;
 241         }
 242
 243         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 244         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 245
 246         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 247                 if (running) {
 248                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 249                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 250                 }
 251
 252                 /* reset the engine and set to writable */
 253                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 254                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 255
 256                 /* load mc io regs */
 257                 for (i = 0; i < regs_size; i++) {
 258                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 259                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 260                 }
 261                 /* load the MC ucode */
 262                 fw_data = (const __be32 *)rdev->mc_fw->data;
 263                 for (i = 0; i < ucode_size; i++)
 264                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 265
 266                 /* put the engine back into the active state */
 267                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 268                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 269                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 270
 271                 /* wait for training to complete */
 272                 for (i = 0; i < rdev->usec_timeout; i++) {
 273                         if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
 274                                 break;
 275                         udelay(1);
 276                 }
 277
 278                 if (running)
 279                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 280         }
 281
 282         return 0;
 283 }
 284
 285 int ni_init_microcode(struct radeon_device *rdev)
 286 {
 287         struct platform_device *pdev;
 288         const char *chip_name;
 289         const char *rlc_chip_name;
 290         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 291         char fw_name[30];
 292         int err;
 293
 294         DRM_DEBUG("\n");
 295
 296         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 297         err = IS_ERR(pdev);
 298         if (err) {
 299                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 300                 return -EINVAL;
 301         }
 302
 303         switch (rdev->family) {
 304         case CHIP_BARTS:
 305                 chip_name = "BARTS";
 306                 rlc_chip_name = "BTC";
 307                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 308                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 309                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 310                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 311                 break;
 312         case CHIP_TURKS:
 313                 chip_name = "TURKS";
 314                 rlc_chip_name = "BTC";
 315                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 316                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 317                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 318                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 319                 break;
 320         case CHIP_CAICOS:
 321                 chip_name = "CAICOS";
 322                 rlc_chip_name = "BTC";
 323                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 324                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 325                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 326                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 327                 break;
 328         case CHIP_CAYMAN:
 329                 chip_name = "CAYMAN";
 330                 rlc_chip_name = "CAYMAN";
 331                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 332                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 333                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 334                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 335                 break;
 336         case CHIP_ARUBA:
 337                 chip_name = "ARUBA";
 338                 rlc_chip_name = "ARUBA";
 339                 /* pfp/me same size as CAYMAN */
 340                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 341                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 342                 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
 343                 mc_req_size = 0;
 344                 break;
 345         default: BUG();
 346         }
 347
 348         DRM_INFO("Loading %s Microcode\n", chip_name);
 349
 350         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 351         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 352         if (err)
 353                 goto out;
 354         if (rdev->pfp_fw->size != pfp_req_size) {
 355                 printk(KERN_ERR
 356                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 357                        rdev->pfp_fw->size, fw_name);
 358                 err = -EINVAL;
 359                 goto out;
 360         }
 361
 362         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 363         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 364         if (err)
 365                 goto out;
 366         if (rdev->me_fw->size != me_req_size) {
 367                 printk(KERN_ERR
 368                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 369                        rdev->me_fw->size, fw_name);
 370                 err = -EINVAL;
 371         }
 372
 373         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 374         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 375         if (err)
 376                 goto out;
 377         if (rdev->rlc_fw->size != rlc_req_size) {
 378                 printk(KERN_ERR
 379                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 380                        rdev->rlc_fw->size, fw_name);
 381                 err = -EINVAL;
 382         }
 383
 384         /* no MC ucode on TN */
 385         if (!(rdev->flags & RADEON_IS_IGP)) {
 386                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 387                 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 388                 if (err)
 389                         goto out;
 390                 if (rdev->mc_fw->size != mc_req_size) {
 391                         printk(KERN_ERR
 392                                "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 393                                rdev->mc_fw->size, fw_name);
 394                         err = -EINVAL;
 395                 }
 396         }
 397 out:
 398         platform_device_unregister(pdev);
 399
 400         if (err) {
 401                 if (err != -EINVAL)
 402                         printk(KERN_ERR
 403                                "ni_cp: Failed to load firmware \"%s\"\n",
 404                                fw_name);
 405                 release_firmware(rdev->pfp_fw);
 406                 rdev->pfp_fw = NULL;
 407                 release_firmware(rdev->me_fw);
 408                 rdev->me_fw = NULL;
 409                 release_firmware(rdev->rlc_fw);
 410                 rdev->rlc_fw = NULL;
 411                 release_firmware(rdev->mc_fw);
 412                 rdev->mc_fw = NULL;
 413         }
 414         return err;
 415 }
 416
 417 /*
 418  * Core functions
 419  */
 420 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 421                                                u32 num_tile_pipes,
 422                                                u32 num_backends_per_asic,
 423                                                u32 *backend_disable_mask_per_asic,
 424                                                u32 num_shader_engines)
 425 {
 426         u32 backend_map = 0;
 427         u32 enabled_backends_mask = 0;
 428         u32 enabled_backends_count = 0;
 429         u32 num_backends_per_se;
 430         u32 cur_pipe;
 431         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 432         u32 cur_backend = 0;
 433         u32 i;
 434         bool force_no_swizzle;
 435
 436         /* force legal values */
 437         if (num_tile_pipes < 1)
 438                 num_tile_pipes = 1;
 439         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 440                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 441         if (num_shader_engines < 1)
 442                 num_shader_engines = 1;
 443         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 444                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 445         if (num_backends_per_asic < num_shader_engines)
 446                 num_backends_per_asic = num_shader_engines;
 447         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 448                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 449
 450         /* make sure we have the same number of backends per se */
 451         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 452         /* set up the number of backends per se */
 453         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 454         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 455                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 456                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 457         }
 458
 459         /* create enable mask and count for enabled backends */
 460         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 461                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 462                         enabled_backends_mask |= (1 << i);
 463                         ++enabled_backends_count;
 464                 }
 465                 if (enabled_backends_count == num_backends_per_asic)
 466                         break;
 467         }
 468
 469         /* force the backends mask to match the current number of backends */
 470         if (enabled_backends_count != num_backends_per_asic) {
 471                 u32 this_backend_enabled;
 472                 u32 shader_engine;
 473                 u32 backend_per_se;
 474
 475                 enabled_backends_mask = 0;
 476                 enabled_backends_count = 0;
 477                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 478                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 479                         /* calc the current se */
 480                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 481                         /* calc the backend per se */
 482                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 483                         /* default to not enabled */
 484                         this_backend_enabled = 0;
 485                         if ((shader_engine < num_shader_engines) &&
 486                             (backend_per_se < num_backends_per_se))
 487                                 this_backend_enabled = 1;
 488                         if (this_backend_enabled) {
 489                                 enabled_backends_mask |= (1 << i);
 490                                 *backend_disable_mask_per_asic &= ~(1 << i);
 491                                 ++enabled_backends_count;
 492                         }
 493                 }
 494         }
 495
 496
 497         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 498         switch (rdev->family) {
 499         case CHIP_CAYMAN:
 500         case CHIP_ARUBA:
 501                 force_no_swizzle = true;
 502                 break;
 503         default:
 504                 force_no_swizzle = false;
 505                 break;
 506         }
 507         if (force_no_swizzle) {
 508                 bool last_backend_enabled = false;
 509
 510                 force_no_swizzle = false;
 511                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 512                         if (((enabled_backends_mask >> i) & 1) == 1) {
 513                                 if (last_backend_enabled)
 514                                         force_no_swizzle = true;
 515                                 last_backend_enabled = true;
 516                         } else
 517                                 last_backend_enabled = false;
 518                 }
 519         }
 520
 521         switch (num_tile_pipes) {
 522         case 1:
 523         case 3:
 524         case 5:
 525         case 7:
 526                 DRM_ERROR("odd number of pipes!\n");
 527                 break;
 528         case 2:
 529                 swizzle_pipe[0] = 0;
 530                 swizzle_pipe[1] = 1;
 531                 break;
 532         case 4:
 533                 if (force_no_swizzle) {
 534                         swizzle_pipe[0] = 0;
 535                         swizzle_pipe[1] = 1;
 536                         swizzle_pipe[2] = 2;
 537                         swizzle_pipe[3] = 3;
 538                 } else {
 539                         swizzle_pipe[0] = 0;
 540                         swizzle_pipe[1] = 2;
 541                         swizzle_pipe[2] = 1;
 542                         swizzle_pipe[3] = 3;
 543                 }
 544                 break;
 545         case 6:
 546                 if (force_no_swizzle) {
 547                         swizzle_pipe[0] = 0;
 548                         swizzle_pipe[1] = 1;
 549                         swizzle_pipe[2] = 2;
 550                         swizzle_pipe[3] = 3;
 551                         swizzle_pipe[4] = 4;
 552                         swizzle_pipe[5] = 5;
 553                 } else {
 554                         swizzle_pipe[0] = 0;
 555                         swizzle_pipe[1] = 2;
 556                         swizzle_pipe[2] = 4;
 557                         swizzle_pipe[3] = 1;
 558                         swizzle_pipe[4] = 3;
 559                         swizzle_pipe[5] = 5;
 560                 }
 561                 break;
 562         case 8:
 563                 if (force_no_swizzle) {
 564                         swizzle_pipe[0] = 0;
 565                         swizzle_pipe[1] = 1;
 566                         swizzle_pipe[2] = 2;
 567                         swizzle_pipe[3] = 3;
 568                         swizzle_pipe[4] = 4;
 569                         swizzle_pipe[5] = 5;
 570                         swizzle_pipe[6] = 6;
 571                         swizzle_pipe[7] = 7;
 572                 } else {
 573                         swizzle_pipe[0] = 0;
 574                         swizzle_pipe[1] = 2;
 575                         swizzle_pipe[2] = 4;
 576                         swizzle_pipe[3] = 6;
 577                         swizzle_pipe[4] = 1;
 578                         swizzle_pipe[5] = 3;
 579                         swizzle_pipe[6] = 5;
 580                         swizzle_pipe[7] = 7;
 581                 }
 582                 break;
 583         }
 584
 585         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 586                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 587                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 588
 589                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 590
 591                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 592         }
 593
 594         return backend_map;
 595 }
 596
 597 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 598                                             u32 disable_mask_per_se,
 599                                             u32 max_disable_mask_per_se,
 600                                             u32 num_shader_engines)
 601 {
 602         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 603         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 604
 605         if (num_shader_engines == 1)
 606                 return disable_mask_per_asic;
 607         else if (num_shader_engines == 2)
 608                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 609         else
 610                 return 0xffffffff;
 611 }
 612
 613 static void cayman_gpu_init(struct radeon_device *rdev)
 614 {
 615         u32 cc_rb_backend_disable = 0;
 616         u32 cc_gc_shader_pipe_config;
 617         u32 gb_addr_config = 0;
 618         u32 mc_shared_chmap, mc_arb_ramcfg;
 619         u32 gb_backend_map;
 620         u32 cgts_tcc_disable;
 621         u32 sx_debug_1;
 622         u32 smx_dc_ctl0;
 623         u32 gc_user_shader_pipe_config;
 624         u32 gc_user_rb_backend_disable;
 625         u32 cgts_user_tcc_disable;
 626         u32 cgts_sm_ctrl_reg;
 627         u32 hdp_host_path_cntl;
 628         u32 tmp;
 629         int i, j;
 630
 631         switch (rdev->family) {
 632         case CHIP_CAYMAN:
 633                 rdev->config.cayman.max_shader_engines = 2;
 634                 rdev->config.cayman.max_pipes_per_simd = 4;
 635                 rdev->config.cayman.max_tile_pipes = 8;
 636                 rdev->config.cayman.max_simds_per_se = 12;
 637                 rdev->config.cayman.max_backends_per_se = 4;
 638                 rdev->config.cayman.max_texture_channel_caches = 8;
 639                 rdev->config.cayman.max_gprs = 256;
 640                 rdev->config.cayman.max_threads = 256;
 641                 rdev->config.cayman.max_gs_threads = 32;
 642                 rdev->config.cayman.max_stack_entries = 512;
 643                 rdev->config.cayman.sx_num_of_sets = 8;
 644                 rdev->config.cayman.sx_max_export_size = 256;
 645                 rdev->config.cayman.sx_max_export_pos_size = 64;
 646                 rdev->config.cayman.sx_max_export_smx_size = 192;
 647                 rdev->config.cayman.max_hw_contexts = 8;
 648                 rdev->config.cayman.sq_num_cf_insts = 2;
 649
 650                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 651                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 652                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 653                 break;
 654         case CHIP_ARUBA:
 655         default:
 656                 rdev->config.cayman.max_shader_engines = 1;
 657                 rdev->config.cayman.max_pipes_per_simd = 4;
 658                 rdev->config.cayman.max_tile_pipes = 2;
 659                 if ((rdev->pdev->device == 0x9900) ||
 660                     (rdev->pdev->device == 0x9901) ||
 661                     (rdev->pdev->device == 0x9905) ||
 662                     (rdev->pdev->device == 0x9906) ||
 663                     (rdev->pdev->device == 0x9907) ||
 664                     (rdev->pdev->device == 0x9908) ||
 665                     (rdev->pdev->device == 0x9909) ||
 666                     (rdev->pdev->device == 0x990B) ||
 667                     (rdev->pdev->device == 0x990C) ||
 668                     (rdev->pdev->device == 0x990F) ||
 669                     (rdev->pdev->device == 0x9910) ||
 670                     (rdev->pdev->device == 0x9917) ||
 671                     (rdev->pdev->device == 0x9999)) {
 672                         rdev->config.cayman.max_simds_per_se = 6;
 673                         rdev->config.cayman.max_backends_per_se = 2;
 674                 } else if ((rdev->pdev->device == 0x9903) ||
 675                            (rdev->pdev->device == 0x9904) ||
 676                            (rdev->pdev->device == 0x990A) ||
 677                            (rdev->pdev->device == 0x990D) ||
 678                            (rdev->pdev->device == 0x990E) ||
 679                            (rdev->pdev->device == 0x9913) ||
 680                            (rdev->pdev->device == 0x9918)) {
 681                         rdev->config.cayman.max_simds_per_se = 4;
 682                         rdev->config.cayman.max_backends_per_se = 2;
 683                 } else if ((rdev->pdev->device == 0x9919) ||
 684                            (rdev->pdev->device == 0x9990) ||
 685                            (rdev->pdev->device == 0x9991) ||
 686                            (rdev->pdev->device == 0x9994) ||
 687                            (rdev->pdev->device == 0x9995) ||
 688                            (rdev->pdev->device == 0x9996) ||
 689                            (rdev->pdev->device == 0x999A) ||
 690                            (rdev->pdev->device == 0x99A0)) {
 691                         rdev->config.cayman.max_simds_per_se = 3;
 692                         rdev->config.cayman.max_backends_per_se = 1;
 693                 } else {
 694                         rdev->config.cayman.max_simds_per_se = 2;
 695                         rdev->config.cayman.max_backends_per_se = 1;
 696                 }
 697                 rdev->config.cayman.max_texture_channel_caches = 2;
 698                 rdev->config.cayman.max_gprs = 256;
 699                 rdev->config.cayman.max_threads = 256;
 700                 rdev->config.cayman.max_gs_threads = 32;
 701                 rdev->config.cayman.max_stack_entries = 512;
 702                 rdev->config.cayman.sx_num_of_sets = 8;
 703                 rdev->config.cayman.sx_max_export_size = 256;
 704                 rdev->config.cayman.sx_max_export_pos_size = 64;
 705                 rdev->config.cayman.sx_max_export_smx_size = 192;
 706                 rdev->config.cayman.max_hw_contexts = 8;
 707                 rdev->config.cayman.sq_num_cf_insts = 2;
 708
 709                 rdev->config.cayman.sc_prim_fifo_size = 0x40;
 710                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 711                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 712                 break;
 713         }
 714
 715         /* Initialize HDP */
 716         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 717                 WREG32((0x2c14 + j), 0x00000000);
 718                 WREG32((0x2c18 + j), 0x00000000);
 719                 WREG32((0x2c1c + j), 0x00000000);
 720                 WREG32((0x2c20 + j), 0x00000000);
 721                 WREG32((0x2c24 + j), 0x00000000);
 722         }
 723
 724         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 725
 726         evergreen_fix_pci_max_read_req_size(rdev);
 727
 728         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 729         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 730
 731         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 732         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 733         cgts_tcc_disable = 0xffff0000;
 734         for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
 735                 cgts_tcc_disable &= ~(1 << (16 + i));
 736         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 737         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 738         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 739
 740         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 741         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 742         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 743         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 744         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 745         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 746         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 747         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 748         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 749         rdev->config.cayman.backend_disable_mask_per_asic =
 750                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 751                                                  rdev->config.cayman.num_shader_engines);
 752         rdev->config.cayman.backend_map =
 753                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 754                                                     rdev->config.cayman.num_backends_per_se *
 755                                                     rdev->config.cayman.num_shader_engines,
 756                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 757                                                     rdev->config.cayman.num_shader_engines);
 758         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 759         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 760         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 761         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 762         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 763                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 764         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 765         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 766         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 767                 rdev->config.cayman.mem_row_size_in_kb = 4;
 768         /* XXX use MC settings? */
 769         rdev->config.cayman.shader_engine_tile_size = 32;
 770         rdev->config.cayman.num_gpus = 1;
 771         rdev->config.cayman.multi_gpu_tile_size = 64;
 772
 773         //gb_addr_config = 0x02011003
 774 #if 0
 775         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 776 #else
 777         gb_addr_config = 0;
 778         switch (rdev->config.cayman.num_tile_pipes) {
 779         case 1:
 780         default:
 781                 gb_addr_config |= NUM_PIPES(0);
 782                 break;
 783         case 2:
 784                 gb_addr_config |= NUM_PIPES(1);
 785                 break;
 786         case 4:
 787                 gb_addr_config |= NUM_PIPES(2);
 788                 break;
 789         case 8:
 790                 gb_addr_config |= NUM_PIPES(3);
 791                 break;
 792         }
 793
 794         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 795         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 796         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 797         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 798         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 799         switch (rdev->config.cayman.num_gpus) {
 800         case 1:
 801         default:
 802                 gb_addr_config |= NUM_GPUS(0);
 803                 break;
 804         case 2:
 805                 gb_addr_config |= NUM_GPUS(1);
 806                 break;
 807         case 4:
 808                 gb_addr_config |= NUM_GPUS(2);
 809                 break;
 810         }
 811         switch (rdev->config.cayman.multi_gpu_tile_size) {
 812         case 16:
 813                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 814                 break;
 815         case 32:
 816         default:
 817                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 818                 break;
 819         case 64:
 820                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 821                 break;
 822         case 128:
 823                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 824                 break;
 825         }
 826         switch (rdev->config.cayman.mem_row_size_in_kb) {
 827         case 1:
 828         default:
 829                 gb_addr_config |= ROW_SIZE(0);
 830                 break;
 831         case 2:
 832                 gb_addr_config |= ROW_SIZE(1);
 833                 break;
 834         case 4:
 835                 gb_addr_config |= ROW_SIZE(2);
 836                 break;
 837         }
 838 #endif
 839
 840         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 841         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 842         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 843         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 844         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 845         rdev->config.cayman.num_shader_engines = tmp + 1;
 846         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 847         rdev->config.cayman.num_gpus = tmp + 1;
 848         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 849         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 850         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 851         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 852
 853         //gb_backend_map = 0x76541032;
 854 #if 0
 855         gb_backend_map = RREG32(GB_BACKEND_MAP);
 856 #else
 857         gb_backend_map =
 858                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 859                                                     rdev->config.cayman.num_backends_per_se *
 860                                                     rdev->config.cayman.num_shader_engines,
 861                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 862                                                     rdev->config.cayman.num_shader_engines);
 863 #endif
 864         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 865          * not have bank info, so create a custom tiling dword.
 866          * bits 3:0   num_pipes
 867          * bits 7:4   num_banks
 868          * bits 11:8  group_size
 869          * bits 15:12 row_size
 870          */
 871         rdev->config.cayman.tile_config = 0;
 872         switch (rdev->config.cayman.num_tile_pipes) {
 873         case 1:
 874         default:
 875                 rdev->config.cayman.tile_config |= (0 << 0);
 876                 break;
 877         case 2:
 878                 rdev->config.cayman.tile_config |= (1 << 0);
 879                 break;
 880         case 4:
 881                 rdev->config.cayman.tile_config |= (2 << 0);
 882                 break;
 883         case 8:
 884                 rdev->config.cayman.tile_config |= (3 << 0);
 885                 break;
 886         }
 887
 888         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
 889         if (rdev->flags & RADEON_IS_IGP)
 890                 rdev->config.cayman.tile_config |= 1 << 4;
 891         else {
 892                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
 893                 case 0: /* four banks */
 894                         rdev->config.cayman.tile_config |= 0 << 4;
 895                         break;
 896                 case 1: /* eight banks */
 897                         rdev->config.cayman.tile_config |= 1 << 4;
 898                         break;
 899                 case 2: /* sixteen banks */
 900                 default:
 901                         rdev->config.cayman.tile_config |= 2 << 4;
 902                         break;
 903                 }
 904         }
 905         rdev->config.cayman.tile_config |=
 906                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 907         rdev->config.cayman.tile_config |=
 908                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 909
 910         rdev->config.cayman.backend_map = gb_backend_map;
 911         WREG32(GB_BACKEND_MAP, gb_backend_map);
 912         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 913         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 914         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 915
 916         /* primary versions */
 917         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 918         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 919         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 920
 921         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 922         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 923
 924         /* user versions */
 925         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 926         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 927         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 928
 929         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 930         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 931
 932         /* reprogram the shader complex */
 933         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 934         for (i = 0; i < 16; i++)
 935                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 936         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 937
 938         /* set HW defaults for 3D engine */
 939         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 940
 941         sx_debug_1 = RREG32(SX_DEBUG_1);
 942         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 943         WREG32(SX_DEBUG_1, sx_debug_1);
 944
 945         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 946         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 947         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 948         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 949
 950         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 951
 952         /* need to be explicitly zero-ed */
 953         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 954         WREG32(SQ_LSTMP_RING_BASE, 0);
 955         WREG32(SQ_HSTMP_RING_BASE, 0);
 956         WREG32(SQ_ESTMP_RING_BASE, 0);
 957         WREG32(SQ_GSTMP_RING_BASE, 0);
 958         WREG32(SQ_VSTMP_RING_BASE, 0);
 959         WREG32(SQ_PSTMP_RING_BASE, 0);
 960
 961         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 962
 963         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 964                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 965                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 966
 967         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 968                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 969                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 970
 971
 972         WREG32(VGT_NUM_INSTANCES, 1);
 973
 974         WREG32(CP_PERFMON_CNTL, 0);
 975
 976         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 977                                   FETCH_FIFO_HIWATER(0x4) |
 978                                   DONE_FIFO_HIWATER(0xe0) |
 979                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 980
 981         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 982         WREG32(SQ_CONFIG, (VC_ENABLE |
 983                            EXPORT_SRC_C |
 984                            GFX_PRIO(0) |
 985                            CS1_PRIO(0) |
 986                            CS2_PRIO(1)));
 987         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 988
 989         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 990                                           FORCE_EOV_MAX_REZ_CNT(255)));
 991
 992         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 993                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 994
 995         WREG32(VGT_GS_VERTEX_REUSE, 16);
 996         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 997
 998         WREG32(CB_PERF_CTR0_SEL_0, 0);
 999         WREG32(CB_PERF_CTR0_SEL_1, 0);
1000         WREG32(CB_PERF_CTR1_SEL_0, 0);
1001         WREG32(CB_PERF_CTR1_SEL_1, 0);
1002         WREG32(CB_PERF_CTR2_SEL_0, 0);
1003         WREG32(CB_PERF_CTR2_SEL_1, 0);
1004         WREG32(CB_PERF_CTR3_SEL_0, 0);
1005         WREG32(CB_PERF_CTR3_SEL_1, 0);
1006
1007         tmp = RREG32(HDP_MISC_CNTL);
1008         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1009         WREG32(HDP_MISC_CNTL, tmp);
1010
1011         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1012         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1013
1014         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1015
1016         udelay(50);
1017 }
1018
1019 /*
1020  * GART
1021  */
1022 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1023 {
1024         /* flush hdp cache */
1025         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1026
1027         /* bits 0-7 are the VM contexts0-7 */
1028         WREG32(VM_INVALIDATE_REQUEST, 1);
1029 }
1030
1031 int cayman_pcie_gart_enable(struct radeon_device *rdev)
1032 {
1033         int i, r;
1034
1035         if (rdev->gart.robj == NULL) {
1036                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1037                 return -EINVAL;
1038         }
1039         r = radeon_gart_table_vram_pin(rdev);
1040         if (r)
1041                 return r;
1042         radeon_gart_restore(rdev);
1043         /* Setup TLB control */
1044         WREG32(MC_VM_MX_L1_TLB_CNTL,
1045                (0xA << 7) |
1046                ENABLE_L1_TLB |
1047                ENABLE_L1_FRAGMENT_PROCESSING |
1048                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1049                ENABLE_ADVANCED_DRIVER_MODEL |
1050                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1051         /* Setup L2 cache */
1052         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1053                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1054                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1055                EFFECTIVE_L2_QUEUE_SIZE(7) |
1056                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1057         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1058         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1059                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1060         /* setup context0 */
1061         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1062         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1063         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1064         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1065                         (u32)(rdev->dummy_page.addr >> 12));
1066         WREG32(VM_CONTEXT0_CNTL2, 0);
1067         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1068                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1069
1070         WREG32(0x15D4, 0);
1071         WREG32(0x15D8, 0);
1072         WREG32(0x15DC, 0);
1073
1074         /* empty context1-7 */
1075         for (i = 1; i < 8; i++) {
1076                 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1077                 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
1078                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1079                         rdev->gart.table_addr >> 12);
1080         }
1081
1082         /* enable context1-7 */
1083         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1084                (u32)(rdev->dummy_page.addr >> 12));
1085         WREG32(VM_CONTEXT1_CNTL2, 0);
1086         WREG32(VM_CONTEXT1_CNTL, 0);
1087         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1088                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1089
1090         cayman_pcie_gart_tlb_flush(rdev);
1091         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1092                  (unsigned)(rdev->mc.gtt_size >> 20),
1093                  (unsigned long long)rdev->gart.table_addr);
1094         rdev->gart.ready = true;
1095         return 0;
1096 }
1097
1098 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1099 {
1100         /* Disable all tables */
1101         WREG32(VM_CONTEXT0_CNTL, 0);
1102         WREG32(VM_CONTEXT1_CNTL, 0);
1103         /* Setup TLB control */
1104         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1105                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1106                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1107         /* Setup L2 cache */
1108         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1109                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1110                EFFECTIVE_L2_QUEUE_SIZE(7) |
1111                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1112         WREG32(VM_L2_CNTL2, 0);
1113         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1114                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1115         radeon_gart_table_vram_unpin(rdev);
1116 }
1117
1118 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1119 {
1120         cayman_pcie_gart_disable(rdev);
1121         radeon_gart_table_vram_free(rdev);
1122         radeon_gart_fini(rdev);
1123 }
1124
1125 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1126                               int ring, u32 cp_int_cntl)
1127 {
1128         u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1129
1130         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1131         WREG32(CP_INT_CNTL, cp_int_cntl);
1132 }
1133
1134 /*
1135  * CP.
1136  */
1137 void cayman_fence_ring_emit(struct radeon_device *rdev,
1138                             struct radeon_fence *fence)
1139 {
1140         struct radeon_ring *ring = &rdev->ring[fence->ring];
1141         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1142
1143         /* flush read cache over gart for this vmid */
1144         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1145         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1146         radeon_ring_write(ring, 0);
1147         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1148         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1149         radeon_ring_write(ring, 0xFFFFFFFF);
1150         radeon_ring_write(ring, 0);
1151         radeon_ring_write(ring, 10); /* poll interval */
1152         /* EVENT_WRITE_EOP - flush caches, send int */
1153         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1154         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1155         radeon_ring_write(ring, addr & 0xffffffff);
1156         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1157         radeon_ring_write(ring, fence->seq);
1158         radeon_ring_write(ring, 0);
1159 }
1160
1161 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1162 {
1163         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1164
1165         /* set to DX10/11 mode */
1166         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1167         radeon_ring_write(ring, 1);
1168         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1169         radeon_ring_write(ring,
1170 #ifdef __BIG_ENDIAN
1171                           (2 << 0) |
1172 #endif
1173                           (ib->gpu_addr & 0xFFFFFFFC));
1174         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1175         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1176
1177         /* flush read cache over gart for this vmid */
1178         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1179         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1180         radeon_ring_write(ring, ib->vm_id);
1181         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1182         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1183         radeon_ring_write(ring, 0xFFFFFFFF);
1184         radeon_ring_write(ring, 0);
1185         radeon_ring_write(ring, 10); /* poll interval */
1186 }
1187
1188 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1189 {
1190         if (enable)
1191                 WREG32(CP_ME_CNTL, 0);
1192         else {
1193                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1194                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1195                 WREG32(SCRATCH_UMSK, 0);
1196         }
1197 }
1198
1199 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1200 {
1201         const __be32 *fw_data;
1202         int i;
1203
1204         if (!rdev->me_fw || !rdev->pfp_fw)
1205                 return -EINVAL;
1206
1207         cayman_cp_enable(rdev, false);
1208
1209         fw_data = (const __be32 *)rdev->pfp_fw->data;
1210         WREG32(CP_PFP_UCODE_ADDR, 0);
1211         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1212                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1213         WREG32(CP_PFP_UCODE_ADDR, 0);
1214
1215         fw_data = (const __be32 *)rdev->me_fw->data;
1216         WREG32(CP_ME_RAM_WADDR, 0);
1217         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1218                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1219
1220         WREG32(CP_PFP_UCODE_ADDR, 0);
1221         WREG32(CP_ME_RAM_WADDR, 0);
1222         WREG32(CP_ME_RAM_RADDR, 0);
1223         return 0;
1224 }
1225
1226 static int cayman_cp_start(struct radeon_device *rdev)
1227 {
1228         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1229         int r, i;
1230
1231         r = radeon_ring_lock(rdev, ring, 7);
1232         if (r) {
1233                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1234                 return r;
1235         }
1236         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1237         radeon_ring_write(ring, 0x1);
1238         radeon_ring_write(ring, 0x0);
1239         radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1240         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1241         radeon_ring_write(ring, 0);
1242         radeon_ring_write(ring, 0);
1243         radeon_ring_unlock_commit(rdev, ring);
1244
1245         cayman_cp_enable(rdev, true);
1246
1247         r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1248         if (r) {
1249                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1250                 return r;
1251         }
1252
1253         /* setup clear context state */
1254         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1255         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1256
1257         for (i = 0; i < cayman_default_size; i++)
1258                 radeon_ring_write(ring, cayman_default_state[i]);
1259
1260         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1261         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1262
1263         /* set clear context state */
1264         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1265         radeon_ring_write(ring, 0);
1266
1267         /* SQ_VTX_BASE_VTX_LOC */
1268         radeon_ring_write(ring, 0xc0026f00);
1269         radeon_ring_write(ring, 0x00000000);
1270         radeon_ring_write(ring, 0x00000000);
1271         radeon_ring_write(ring, 0x00000000);
1272
1273         /* Clear consts */
1274         radeon_ring_write(ring, 0xc0036f00);
1275         radeon_ring_write(ring, 0x00000bc4);
1276         radeon_ring_write(ring, 0xffffffff);
1277         radeon_ring_write(ring, 0xffffffff);
1278         radeon_ring_write(ring, 0xffffffff);
1279
1280         radeon_ring_write(ring, 0xc0026900);
1281         radeon_ring_write(ring, 0x00000316);
1282         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1283         radeon_ring_write(ring, 0x00000010); /*  */
1284
1285         radeon_ring_unlock_commit(rdev, ring);
1286
1287         /* XXX init other rings */
1288
1289         return 0;
1290 }
1291
1292 static void cayman_cp_fini(struct radeon_device *rdev)
1293 {
1294         cayman_cp_enable(rdev, false);
1295         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1296 }
1297
1298 int cayman_cp_resume(struct radeon_device *rdev)
1299 {
1300         struct radeon_ring *ring;
1301         u32 tmp;
1302         u32 rb_bufsz;
1303         int r;
1304
1305         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1306         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1307                                  SOFT_RESET_PA |
1308                                  SOFT_RESET_SH |
1309                                  SOFT_RESET_VGT |
1310                                  SOFT_RESET_SPI |
1311                                  SOFT_RESET_SX));
1312         RREG32(GRBM_SOFT_RESET);
1313         mdelay(15);
1314         WREG32(GRBM_SOFT_RESET, 0);
1315         RREG32(GRBM_SOFT_RESET);
1316
1317         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1318         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1319
1320         /* Set the write pointer delay */
1321         WREG32(CP_RB_WPTR_DELAY, 0);
1322
1323         WREG32(CP_DEBUG, (1 << 27));
1324
1325         /* ring 0 - compute and gfx */
1326         /* Set ring buffer size */
1327         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1328         rb_bufsz = drm_order(ring->ring_size / 8);
1329         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1330 #ifdef __BIG_ENDIAN
1331         tmp |= BUF_SWAP_32BIT;
1332 #endif
1333         WREG32(CP_RB0_CNTL, tmp);
1334
1335         /* Initialize the ring buffer's read and write pointers */
1336         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1337         ring->wptr = 0;
1338         WREG32(CP_RB0_WPTR, ring->wptr);
1339
1340         /* set the wb address wether it's enabled or not */
1341         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1342         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1343         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1344
1345         if (rdev->wb.enabled)
1346                 WREG32(SCRATCH_UMSK, 0xff);
1347         else {
1348                 tmp |= RB_NO_UPDATE;
1349                 WREG32(SCRATCH_UMSK, 0);
1350         }
1351
1352         mdelay(1);
1353         WREG32(CP_RB0_CNTL, tmp);
1354
1355         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1356
1357         ring->rptr = RREG32(CP_RB0_RPTR);
1358
1359         /* ring1  - compute only */
1360         /* Set ring buffer size */
1361         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1362         rb_bufsz = drm_order(ring->ring_size / 8);
1363         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1364 #ifdef __BIG_ENDIAN
1365         tmp |= BUF_SWAP_32BIT;
1366 #endif
1367         WREG32(CP_RB1_CNTL, tmp);
1368
1369         /* Initialize the ring buffer's read and write pointers */
1370         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1371         ring->wptr = 0;
1372         WREG32(CP_RB1_WPTR, ring->wptr);
1373
1374         /* set the wb address wether it's enabled or not */
1375         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1376         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1377
1378         mdelay(1);
1379         WREG32(CP_RB1_CNTL, tmp);
1380
1381         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1382
1383         ring->rptr = RREG32(CP_RB1_RPTR);
1384
1385         /* ring2 - compute only */
1386         /* Set ring buffer size */
1387         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1388         rb_bufsz = drm_order(ring->ring_size / 8);
1389         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1390 #ifdef __BIG_ENDIAN
1391         tmp |= BUF_SWAP_32BIT;
1392 #endif
1393         WREG32(CP_RB2_CNTL, tmp);
1394
1395         /* Initialize the ring buffer's read and write pointers */
1396         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1397         ring->wptr = 0;
1398         WREG32(CP_RB2_WPTR, ring->wptr);
1399
1400         /* set the wb address wether it's enabled or not */
1401         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1402         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1403
1404         mdelay(1);
1405         WREG32(CP_RB2_CNTL, tmp);
1406
1407         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1408
1409         ring->rptr = RREG32(CP_RB2_RPTR);
1410
1411         /* start the rings */
1412         cayman_cp_start(rdev);
1413         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1414         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1415         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1416         /* this only test cp0 */
1417         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1418         if (r) {
1419                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1420                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1421                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1422                 return r;
1423         }
1424
1425         return 0;
1426 }
1427
1428 bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1429 {
1430         u32 srbm_status;
1431         u32 grbm_status;
1432         u32 grbm_status_se0, grbm_status_se1;
1433         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1434         int r;
1435
1436         srbm_status = RREG32(SRBM_STATUS);
1437         grbm_status = RREG32(GRBM_STATUS);
1438         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1439         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1440         if (!(grbm_status & GUI_ACTIVE)) {
1441                 r100_gpu_lockup_update(lockup, ring);
1442                 return false;
1443         }
1444         /* force CP activities */
1445         r = radeon_ring_lock(rdev, ring, 2);
1446         if (!r) {
1447                 /* PACKET2 NOP */
1448                 radeon_ring_write(ring, 0x80000000);
1449                 radeon_ring_write(ring, 0x80000000);
1450                 radeon_ring_unlock_commit(rdev, ring);
1451         }
1452         /* XXX deal with CP0,1,2 */
1453         ring->rptr = RREG32(ring->rptr_reg);
1454         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
1455 }
1456
1457 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1458 {
1459         struct evergreen_mc_save save;
1460         u32 grbm_reset = 0;
1461
1462         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1463                 return 0;
1464
1465         dev_info(rdev->dev, "GPU softreset \n");
1466         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1467                 RREG32(GRBM_STATUS));
1468         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1469                 RREG32(GRBM_STATUS_SE0));
1470         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1471                 RREG32(GRBM_STATUS_SE1));
1472         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1473                 RREG32(SRBM_STATUS));
1474         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1475                  RREG32(0x14F8));
1476         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1477                  RREG32(0x14D8));
1478         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1479                  RREG32(0x14FC));
1480         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1481                  RREG32(0x14DC));
1482
1483         evergreen_mc_stop(rdev, &save);
1484         if (evergreen_mc_wait_for_idle(rdev)) {
1485                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1486         }
1487         /* Disable CP parsing/prefetching */
1488         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1489
1490         /* reset all the gfx blocks */
1491         grbm_reset = (SOFT_RESET_CP |
1492                       SOFT_RESET_CB |
1493                       SOFT_RESET_DB |
1494                       SOFT_RESET_GDS |
1495                       SOFT_RESET_PA |
1496                       SOFT_RESET_SC |
1497                       SOFT_RESET_SPI |
1498                       SOFT_RESET_SH |
1499                       SOFT_RESET_SX |
1500                       SOFT_RESET_TC |
1501                       SOFT_RESET_TA |
1502                       SOFT_RESET_VGT |
1503                       SOFT_RESET_IA);
1504
1505         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1506         WREG32(GRBM_SOFT_RESET, grbm_reset);
1507         (void)RREG32(GRBM_SOFT_RESET);
1508         udelay(50);
1509         WREG32(GRBM_SOFT_RESET, 0);
1510         (void)RREG32(GRBM_SOFT_RESET);
1511         /* Wait a little for things to settle down */
1512         udelay(50);
1513
1514         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1515                 RREG32(GRBM_STATUS));
1516         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1517                 RREG32(GRBM_STATUS_SE0));
1518         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1519                 RREG32(GRBM_STATUS_SE1));
1520         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1521                 RREG32(SRBM_STATUS));
1522         evergreen_mc_resume(rdev, &save);
1523         return 0;
1524 }
1525
1526 int cayman_asic_reset(struct radeon_device *rdev)
1527 {
1528         return cayman_gpu_soft_reset(rdev);
1529 }
1530
1531 static int cayman_startup(struct radeon_device *rdev)
1532 {
1533         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1534         int r;
1535
1536         /* enable pcie gen2 link */
1537         evergreen_pcie_gen2_enable(rdev);
1538
1539         if (rdev->flags & RADEON_IS_IGP) {
1540                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1541                         r = ni_init_microcode(rdev);
1542                         if (r) {
1543                                 DRM_ERROR("Failed to load firmware!\n");
1544                                 return r;
1545                         }
1546                 }
1547         } else {
1548                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1549                         r = ni_init_microcode(rdev);
1550                         if (r) {
1551                                 DRM_ERROR("Failed to load firmware!\n");
1552                                 return r;
1553                         }
1554                 }
1555
1556                 r = ni_mc_load_microcode(rdev);
1557                 if (r) {
1558                         DRM_ERROR("Failed to load MC firmware!\n");
1559                         return r;
1560                 }
1561         }
1562
1563         r = r600_vram_scratch_init(rdev);
1564         if (r)
1565                 return r;
1566
1567         evergreen_mc_program(rdev);
1568         r = cayman_pcie_gart_enable(rdev);
1569         if (r)
1570                 return r;
1571         cayman_gpu_init(rdev);
1572
1573         r = evergreen_blit_init(rdev);
1574         if (r) {
1575                 r600_blit_fini(rdev);
1576                 rdev->asic->copy.copy = NULL;
1577                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1578         }
1579
1580         /* allocate rlc buffers */
1581         if (rdev->flags & RADEON_IS_IGP) {
1582                 r = si_rlc_init(rdev);
1583                 if (r) {
1584                         DRM_ERROR("Failed to init rlc BOs!\n");
1585                         return r;
1586                 }
1587         }
1588
1589         /* allocate wb buffer */
1590         r = radeon_wb_init(rdev);
1591         if (r)
1592                 return r;
1593
1594         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1595         if (r) {
1596                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1597                 return r;
1598         }
1599
1600         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1601         if (r) {
1602                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1603                 return r;
1604         }
1605
1606         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1607         if (r) {
1608                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1609                 return r;
1610         }
1611
1612         /* Enable IRQ */
1613         r = r600_irq_init(rdev);
1614         if (r) {
1615                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1616                 radeon_irq_kms_fini(rdev);
1617                 return r;
1618         }
1619         evergreen_irq_set(rdev);
1620
1621         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1622                              CP_RB0_RPTR, CP_RB0_WPTR,
1623                              0, 0xfffff, RADEON_CP_PACKET2);
1624         if (r)
1625                 return r;
1626         r = cayman_cp_load_microcode(rdev);
1627         if (r)
1628                 return r;
1629         r = cayman_cp_resume(rdev);
1630         if (r)
1631                 return r;
1632
1633         r = radeon_ib_pool_start(rdev);
1634         if (r)
1635                 return r;
1636
1637         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1638         if (r) {
1639                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1640                 rdev->accel_working = false;
1641                 return r;
1642         }
1643
1644         r = radeon_vm_manager_start(rdev);
1645         if (r)
1646                 return r;
1647
1648         return 0;
1649 }
1650
1651 int cayman_resume(struct radeon_device *rdev)
1652 {
1653         int r;
1654
1655         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1656          * posting will perform necessary task to bring back GPU into good
1657          * shape.
1658          */
1659         /* post card */
1660         atom_asic_init(rdev->mode_info.atom_context);
1661
1662         rdev->accel_working = true;
1663         r = cayman_startup(rdev);
1664         if (r) {
1665                 DRM_ERROR("cayman startup failed on resume\n");
1666                 rdev->accel_working = false;
1667                 return r;
1668         }
1669         return r;
1670 }
1671
1672 int cayman_suspend(struct radeon_device *rdev)
1673 {
1674         /* FIXME: we should wait for ring to be empty */
1675         radeon_ib_pool_suspend(rdev);
1676         radeon_vm_manager_suspend(rdev);
1677         r600_blit_suspend(rdev);
1678         cayman_cp_enable(rdev, false);
1679         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1680         evergreen_irq_suspend(rdev);
1681         radeon_wb_disable(rdev);
1682         cayman_pcie_gart_disable(rdev);
1683         return 0;
1684 }
1685
1686 /* Plan is to move initialization in that function and use
1687  * helper function so that radeon_device_init pretty much
1688  * do nothing more than calling asic specific function. This
1689  * should also allow to remove a bunch of callback function
1690  * like vram_info.
1691  */
1692 int cayman_init(struct radeon_device *rdev)
1693 {
1694         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1695         int r;
1696
1697         /* This don't do much */
1698         r = radeon_gem_init(rdev);
1699         if (r)
1700                 return r;
1701         /* Read BIOS */
1702         if (!radeon_get_bios(rdev)) {
1703                 if (ASIC_IS_AVIVO(rdev))
1704                         return -EINVAL;
1705         }
1706         /* Must be an ATOMBIOS */
1707         if (!rdev->is_atom_bios) {
1708                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1709                 return -EINVAL;
1710         }
1711         r = radeon_atombios_init(rdev);
1712         if (r)
1713                 return r;
1714
1715         /* Post card if necessary */
1716         if (!radeon_card_posted(rdev)) {
1717                 if (!rdev->bios) {
1718                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1719                         return -EINVAL;
1720                 }
1721                 DRM_INFO("GPU not posted. posting now...\n");
1722                 atom_asic_init(rdev->mode_info.atom_context);
1723         }
1724         /* Initialize scratch registers */
1725         r600_scratch_init(rdev);
1726         /* Initialize surface registers */
1727         radeon_surface_init(rdev);
1728         /* Initialize clocks */
1729         radeon_get_clock_info(rdev->ddev);
1730         /* Fence driver */
1731         r = radeon_fence_driver_init(rdev);
1732         if (r)
1733                 return r;
1734         /* initialize memory controller */
1735         r = evergreen_mc_init(rdev);
1736         if (r)
1737                 return r;
1738         /* Memory manager */
1739         r = radeon_bo_init(rdev);
1740         if (r)
1741                 return r;
1742
1743         r = radeon_irq_kms_init(rdev);
1744         if (r)
1745                 return r;
1746
1747         ring->ring_obj = NULL;
1748         r600_ring_init(rdev, ring, 1024 * 1024);
1749
1750         rdev->ih.ring_obj = NULL;
1751         r600_ih_ring_init(rdev, 64 * 1024);
1752
1753         r = r600_pcie_gart_init(rdev);
1754         if (r)
1755                 return r;
1756
1757         r = radeon_ib_pool_init(rdev);
1758         rdev->accel_working = true;
1759         if (r) {
1760                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1761                 rdev->accel_working = false;
1762         }
1763         r = radeon_vm_manager_init(rdev);
1764         if (r) {
1765                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1766         }
1767
1768         r = cayman_startup(rdev);
1769         if (r) {
1770                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1771                 cayman_cp_fini(rdev);
1772                 r600_irq_fini(rdev);
1773                 if (rdev->flags & RADEON_IS_IGP)
1774                         si_rlc_fini(rdev);
1775                 radeon_wb_fini(rdev);
1776                 r100_ib_fini(rdev);
1777                 radeon_vm_manager_fini(rdev);
1778                 radeon_irq_kms_fini(rdev);
1779                 cayman_pcie_gart_fini(rdev);
1780                 rdev->accel_working = false;
1781         }
1782
1783         /* Don't start up if the MC ucode is missing.
1784          * The default clocks and voltages before the MC ucode
1785          * is loaded are not suffient for advanced operations.
1786          *
1787          * We can skip this check for TN, because there is no MC
1788          * ucode.
1789          */
1790         if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1791                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1792                 return -EINVAL;
1793         }
1794
1795         return 0;
1796 }
1797
1798 void cayman_fini(struct radeon_device *rdev)
1799 {
1800         r600_blit_fini(rdev);
1801         cayman_cp_fini(rdev);
1802         r600_irq_fini(rdev);
1803         if (rdev->flags & RADEON_IS_IGP)
1804                 si_rlc_fini(rdev);
1805         radeon_wb_fini(rdev);
1806         radeon_vm_manager_fini(rdev);
1807         r100_ib_fini(rdev);
1808         radeon_irq_kms_fini(rdev);
1809         cayman_pcie_gart_fini(rdev);
1810         r600_vram_scratch_fini(rdev);
1811         radeon_gem_fini(rdev);
1812         radeon_semaphore_driver_fini(rdev);
1813         radeon_fence_driver_fini(rdev);
1814         radeon_bo_fini(rdev);
1815         radeon_atombios_fini(rdev);
1816         kfree(rdev->bios);
1817         rdev->bios = NULL;
1818 }
1819
1820 /*
1821  * vm
1822  */
1823 int cayman_vm_init(struct radeon_device *rdev)
1824 {
1825         /* number of VMs */
1826         rdev->vm_manager.nvm = 8;
1827         /* base offset of vram pages */
1828         if (rdev->flags & RADEON_IS_IGP) {
1829                 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1830                 tmp <<= 22;
1831                 rdev->vm_manager.vram_base_offset = tmp;
1832         } else
1833                 rdev->vm_manager.vram_base_offset = 0;
1834         return 0;
1835 }
1836
1837 void cayman_vm_fini(struct radeon_device *rdev)
1838 {
1839 }
1840
1841 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1842 {
1843         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1844         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1845         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1846         /* flush hdp cache */
1847         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1848         /* bits 0-7 are the VM contexts0-7 */
1849         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1850         return 0;
1851 }
1852
1853 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1854 {
1855         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1856         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1857         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1858         /* flush hdp cache */
1859         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1860         /* bits 0-7 are the VM contexts0-7 */
1861         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1862 }
1863
1864 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1865 {
1866         if (vm->id == -1)
1867                 return;
1868
1869         /* flush hdp cache */
1870         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1871         /* bits 0-7 are the VM contexts0-7 */
1872         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1873 }
1874
1875 #define R600_PTE_VALID     (1 << 0)
1876 #define R600_PTE_SYSTEM    (1 << 1)
1877 #define R600_PTE_SNOOPED   (1 << 2)
1878 #define R600_PTE_READABLE  (1 << 5)
1879 #define R600_PTE_WRITEABLE (1 << 6)
1880
1881 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1882                               struct radeon_vm *vm,
1883                               uint32_t flags)
1884 {
1885         uint32_t r600_flags = 0;
1886
1887         r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1888         r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1889         r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1890         if (flags & RADEON_VM_PAGE_SYSTEM) {
1891                 r600_flags |= R600_PTE_SYSTEM;
1892                 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1893         }
1894         return r600_flags;
1895 }
1896
1897 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1898                         unsigned pfn, uint64_t addr, uint32_t flags)
1899 {
1900         void __iomem *ptr = (void *)vm->pt;
1901
1902         addr = addr & 0xFFFFFFFFFFFFF000ULL;
1903         addr |= flags;
1904         writeq(addr, ptr + (pfn * 8));
1905 }