2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
38 static u32 tn_rlc_save_restore_register_list[] =
163 static u32 tn_rlc_save_restore_register_list_size = ARRAY_SIZE(tn_rlc_save_restore_register_list);
165 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
166 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
167 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
168 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
169 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
170 extern void evergreen_mc_program(struct radeon_device *rdev);
171 extern void evergreen_irq_suspend(struct radeon_device *rdev);
172 extern int evergreen_mc_init(struct radeon_device *rdev);
173 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
174 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
175 extern void evergreen_program_aspm(struct radeon_device *rdev);
176 extern void sumo_rlc_fini(struct radeon_device *rdev);
177 extern int sumo_rlc_init(struct radeon_device *rdev);
180 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
181 MODULE_FIRMWARE("radeon/BARTS_me.bin");
182 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
183 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
184 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
185 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
186 MODULE_FIRMWARE("radeon/TURKS_me.bin");
187 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
188 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
189 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
190 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
191 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
192 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
193 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
194 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
195 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
196 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
197 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
198 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
199 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
200 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
203 static const u32 cayman_golden_registers2[] =
205 0x3e5c, 0xffffffff, 0x00000000,
206 0x3e48, 0xffffffff, 0x00000000,
207 0x3e4c, 0xffffffff, 0x00000000,
208 0x3e64, 0xffffffff, 0x00000000,
209 0x3e50, 0xffffffff, 0x00000000,
210 0x3e60, 0xffffffff, 0x00000000
213 static const u32 cayman_golden_registers[] =
215 0x5eb4, 0xffffffff, 0x00000002,
216 0x5e78, 0x8f311ff1, 0x001000f0,
217 0x3f90, 0xffff0000, 0xff000000,
218 0x9148, 0xffff0000, 0xff000000,
219 0x3f94, 0xffff0000, 0xff000000,
220 0x914c, 0xffff0000, 0xff000000,
221 0xc78, 0x00000080, 0x00000080,
222 0xbd4, 0x70073777, 0x00011003,
223 0xd02c, 0xbfffff1f, 0x08421000,
224 0xd0b8, 0x73773777, 0x02011003,
225 0x5bc0, 0x00200000, 0x50100000,
226 0x98f8, 0x33773777, 0x02011003,
227 0x98fc, 0xffffffff, 0x76541032,
228 0x7030, 0x31000311, 0x00000011,
229 0x2f48, 0x33773777, 0x42010001,
230 0x6b28, 0x00000010, 0x00000012,
231 0x7728, 0x00000010, 0x00000012,
232 0x10328, 0x00000010, 0x00000012,
233 0x10f28, 0x00000010, 0x00000012,
234 0x11b28, 0x00000010, 0x00000012,
235 0x12728, 0x00000010, 0x00000012,
236 0x240c, 0x000007ff, 0x00000000,
237 0x8a14, 0xf000001f, 0x00000007,
238 0x8b24, 0x3fff3fff, 0x00ff0fff,
239 0x8b10, 0x0000ff0f, 0x00000000,
240 0x28a4c, 0x07ffffff, 0x06000000,
241 0x10c, 0x00000001, 0x00010003,
242 0xa02c, 0xffffffff, 0x0000009b,
243 0x913c, 0x0000010f, 0x01000100,
244 0x8c04, 0xf8ff00ff, 0x40600060,
245 0x28350, 0x00000f01, 0x00000000,
246 0x9508, 0x3700001f, 0x00000002,
247 0x960c, 0xffffffff, 0x54763210,
248 0x88c4, 0x001f3ae3, 0x00000082,
249 0x88d0, 0xffffffff, 0x0f40df40,
250 0x88d4, 0x0000001f, 0x00000010,
251 0x8974, 0xffffffff, 0x00000000
254 static const u32 dvst_golden_registers2[] =
256 0x8f8, 0xffffffff, 0,
257 0x8fc, 0x00380000, 0,
258 0x8f8, 0xffffffff, 1,
262 static const u32 dvst_golden_registers[] =
264 0x690, 0x3fff3fff, 0x20c00033,
265 0x918c, 0x0fff0fff, 0x00010006,
266 0x91a8, 0x0fff0fff, 0x00010006,
267 0x9150, 0xffffdfff, 0x6e944040,
268 0x917c, 0x0fff0fff, 0x00030002,
269 0x9198, 0x0fff0fff, 0x00030002,
270 0x915c, 0x0fff0fff, 0x00010000,
271 0x3f90, 0xffff0001, 0xff000000,
272 0x9178, 0x0fff0fff, 0x00070000,
273 0x9194, 0x0fff0fff, 0x00070000,
274 0x9148, 0xffff0001, 0xff000000,
275 0x9190, 0x0fff0fff, 0x00090008,
276 0x91ac, 0x0fff0fff, 0x00090008,
277 0x3f94, 0xffff0000, 0xff000000,
278 0x914c, 0xffff0000, 0xff000000,
279 0x929c, 0x00000fff, 0x00000001,
280 0x55e4, 0xff607fff, 0xfc000100,
281 0x8a18, 0xff000fff, 0x00000100,
282 0x8b28, 0xff000fff, 0x00000100,
283 0x9144, 0xfffc0fff, 0x00000100,
284 0x6ed8, 0x00010101, 0x00010000,
285 0x9830, 0xffffffff, 0x00000000,
286 0x9834, 0xf00fffff, 0x00000400,
287 0x9838, 0xfffffffe, 0x00000000,
288 0xd0c0, 0xff000fff, 0x00000100,
289 0xd02c, 0xbfffff1f, 0x08421000,
290 0xd0b8, 0x73773777, 0x12010001,
291 0x5bb0, 0x000000f0, 0x00000070,
292 0x98f8, 0x73773777, 0x12010001,
293 0x98fc, 0xffffffff, 0x00000010,
294 0x9b7c, 0x00ff0000, 0x00fc0000,
295 0x8030, 0x00001f0f, 0x0000100a,
296 0x2f48, 0x73773777, 0x12010001,
297 0x2408, 0x00030000, 0x000c007f,
298 0x8a14, 0xf000003f, 0x00000007,
299 0x8b24, 0x3fff3fff, 0x00ff0fff,
300 0x8b10, 0x0000ff0f, 0x00000000,
301 0x28a4c, 0x07ffffff, 0x06000000,
302 0x4d8, 0x00000fff, 0x00000100,
303 0xa008, 0xffffffff, 0x00010000,
304 0x913c, 0xffff03ff, 0x01000100,
305 0x8c00, 0x000000ff, 0x00000003,
306 0x8c04, 0xf8ff00ff, 0x40600060,
307 0x8cf0, 0x1fff1fff, 0x08e00410,
308 0x28350, 0x00000f01, 0x00000000,
309 0x9508, 0xf700071f, 0x00000002,
310 0x960c, 0xffffffff, 0x54763210,
311 0x20ef8, 0x01ff01ff, 0x00000002,
312 0x20e98, 0xfffffbff, 0x00200000,
313 0x2015c, 0xffffffff, 0x00000f40,
314 0x88c4, 0x001f3ae3, 0x00000082,
315 0x8978, 0x3fffffff, 0x04050140,
316 0x88d4, 0x0000001f, 0x00000010,
317 0x8974, 0xffffffff, 0x00000000
320 static const u32 scrapper_golden_registers[] =
322 0x690, 0x3fff3fff, 0x20c00033,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x929c, 0x00000fff, 0x00000001,
352 0x929c, 0x00000fff, 0x00000001,
353 0x55e4, 0xff607fff, 0xfc000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x6ed8, 0x00010101, 0x00010000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0xfffffffe, 0x00000000,
366 0x9838, 0xfffffffe, 0x00000000,
367 0xd0c0, 0xff000fff, 0x00000100,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd0b8, 0x73773777, 0x12010001,
371 0xd0b8, 0x73773777, 0x12010001,
372 0x5bb0, 0x000000f0, 0x00000070,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2408, 0x00030000, 0x000c007f,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x4d8, 0x00000fff, 0x00000100,
393 0x4d8, 0x00000fff, 0x00000100,
394 0xa008, 0xffffffff, 0x00010000,
395 0xa008, 0xffffffff, 0x00010000,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x90e8, 0x001fffff, 0x010400c0,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c30, 0x0000000f, 0x00040005,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x900c, 0x00ffffff, 0x0017071f,
407 0x28350, 0x00000f01, 0x00000000,
408 0x28350, 0x00000f01, 0x00000000,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9688, 0x00300000, 0x0017000f,
412 0x960c, 0xffffffff, 0x54763210,
413 0x960c, 0xffffffff, 0x54763210,
414 0x20ef8, 0x01ff01ff, 0x00000002,
415 0x20e98, 0xfffffbff, 0x00200000,
416 0x2015c, 0xffffffff, 0x00000f40,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x8974, 0xffffffff, 0x00000000,
424 0x8974, 0xffffffff, 0x00000000
427 static void ni_init_golden_registers(struct radeon_device *rdev)
429 switch (rdev->family) {
431 radeon_program_register_sequence(rdev,
432 cayman_golden_registers,
433 (const u32)ARRAY_SIZE(cayman_golden_registers));
434 radeon_program_register_sequence(rdev,
435 cayman_golden_registers2,
436 (const u32)ARRAY_SIZE(cayman_golden_registers2));
439 if ((rdev->pdev->device == 0x9900) ||
440 (rdev->pdev->device == 0x9901) ||
441 (rdev->pdev->device == 0x9903) ||
442 (rdev->pdev->device == 0x9904) ||
443 (rdev->pdev->device == 0x9905) ||
444 (rdev->pdev->device == 0x9906) ||
445 (rdev->pdev->device == 0x9907) ||
446 (rdev->pdev->device == 0x9908) ||
447 (rdev->pdev->device == 0x9909) ||
448 (rdev->pdev->device == 0x990A) ||
449 (rdev->pdev->device == 0x990B) ||
450 (rdev->pdev->device == 0x990C) ||
451 (rdev->pdev->device == 0x990D) ||
452 (rdev->pdev->device == 0x990E) ||
453 (rdev->pdev->device == 0x990F) ||
454 (rdev->pdev->device == 0x9910) ||
455 (rdev->pdev->device == 0x9913) ||
456 (rdev->pdev->device == 0x9917) ||
457 (rdev->pdev->device == 0x9918)) {
458 radeon_program_register_sequence(rdev,
459 dvst_golden_registers,
460 (const u32)ARRAY_SIZE(dvst_golden_registers));
461 radeon_program_register_sequence(rdev,
462 dvst_golden_registers2,
463 (const u32)ARRAY_SIZE(dvst_golden_registers2));
465 radeon_program_register_sequence(rdev,
466 scrapper_golden_registers,
467 (const u32)ARRAY_SIZE(scrapper_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
478 #define BTC_IO_MC_REGS_SIZE 29
480 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
481 {0x00000077, 0xff010100},
482 {0x00000078, 0x00000000},
483 {0x00000079, 0x00001434},
484 {0x0000007a, 0xcc08ec08},
485 {0x0000007b, 0x00040000},
486 {0x0000007c, 0x000080c0},
487 {0x0000007d, 0x09000000},
488 {0x0000007e, 0x00210404},
489 {0x00000081, 0x08a8e800},
490 {0x00000082, 0x00030444},
491 {0x00000083, 0x00000000},
492 {0x00000085, 0x00000001},
493 {0x00000086, 0x00000002},
494 {0x00000087, 0x48490000},
495 {0x00000088, 0x20244647},
496 {0x00000089, 0x00000005},
497 {0x0000008b, 0x66030000},
498 {0x0000008c, 0x00006603},
499 {0x0000008d, 0x00000100},
500 {0x0000008f, 0x00001c0a},
501 {0x00000090, 0xff000001},
502 {0x00000094, 0x00101101},
503 {0x00000095, 0x00000fff},
504 {0x00000096, 0x00116fff},
505 {0x00000097, 0x60010000},
506 {0x00000098, 0x10010000},
507 {0x00000099, 0x00006000},
508 {0x0000009a, 0x00001000},
509 {0x0000009f, 0x00946a00}
512 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
513 {0x00000077, 0xff010100},
514 {0x00000078, 0x00000000},
515 {0x00000079, 0x00001434},
516 {0x0000007a, 0xcc08ec08},
517 {0x0000007b, 0x00040000},
518 {0x0000007c, 0x000080c0},
519 {0x0000007d, 0x09000000},
520 {0x0000007e, 0x00210404},
521 {0x00000081, 0x08a8e800},
522 {0x00000082, 0x00030444},
523 {0x00000083, 0x00000000},
524 {0x00000085, 0x00000001},
525 {0x00000086, 0x00000002},
526 {0x00000087, 0x48490000},
527 {0x00000088, 0x20244647},
528 {0x00000089, 0x00000005},
529 {0x0000008b, 0x66030000},
530 {0x0000008c, 0x00006603},
531 {0x0000008d, 0x00000100},
532 {0x0000008f, 0x00001c0a},
533 {0x00000090, 0xff000001},
534 {0x00000094, 0x00101101},
535 {0x00000095, 0x00000fff},
536 {0x00000096, 0x00116fff},
537 {0x00000097, 0x60010000},
538 {0x00000098, 0x10010000},
539 {0x00000099, 0x00006000},
540 {0x0000009a, 0x00001000},
541 {0x0000009f, 0x00936a00}
544 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
545 {0x00000077, 0xff010100},
546 {0x00000078, 0x00000000},
547 {0x00000079, 0x00001434},
548 {0x0000007a, 0xcc08ec08},
549 {0x0000007b, 0x00040000},
550 {0x0000007c, 0x000080c0},
551 {0x0000007d, 0x09000000},
552 {0x0000007e, 0x00210404},
553 {0x00000081, 0x08a8e800},
554 {0x00000082, 0x00030444},
555 {0x00000083, 0x00000000},
556 {0x00000085, 0x00000001},
557 {0x00000086, 0x00000002},
558 {0x00000087, 0x48490000},
559 {0x00000088, 0x20244647},
560 {0x00000089, 0x00000005},
561 {0x0000008b, 0x66030000},
562 {0x0000008c, 0x00006603},
563 {0x0000008d, 0x00000100},
564 {0x0000008f, 0x00001c0a},
565 {0x00000090, 0xff000001},
566 {0x00000094, 0x00101101},
567 {0x00000095, 0x00000fff},
568 {0x00000096, 0x00116fff},
569 {0x00000097, 0x60010000},
570 {0x00000098, 0x10010000},
571 {0x00000099, 0x00006000},
572 {0x0000009a, 0x00001000},
573 {0x0000009f, 0x00916a00}
576 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
577 {0x00000077, 0xff010100},
578 {0x00000078, 0x00000000},
579 {0x00000079, 0x00001434},
580 {0x0000007a, 0xcc08ec08},
581 {0x0000007b, 0x00040000},
582 {0x0000007c, 0x000080c0},
583 {0x0000007d, 0x09000000},
584 {0x0000007e, 0x00210404},
585 {0x00000081, 0x08a8e800},
586 {0x00000082, 0x00030444},
587 {0x00000083, 0x00000000},
588 {0x00000085, 0x00000001},
589 {0x00000086, 0x00000002},
590 {0x00000087, 0x48490000},
591 {0x00000088, 0x20244647},
592 {0x00000089, 0x00000005},
593 {0x0000008b, 0x66030000},
594 {0x0000008c, 0x00006603},
595 {0x0000008d, 0x00000100},
596 {0x0000008f, 0x00001c0a},
597 {0x00000090, 0xff000001},
598 {0x00000094, 0x00101101},
599 {0x00000095, 0x00000fff},
600 {0x00000096, 0x00116fff},
601 {0x00000097, 0x60010000},
602 {0x00000098, 0x10010000},
603 {0x00000099, 0x00006000},
604 {0x0000009a, 0x00001000},
605 {0x0000009f, 0x00976b00}
608 int ni_mc_load_microcode(struct radeon_device *rdev)
610 const __be32 *fw_data;
611 u32 mem_type, running, blackout = 0;
613 int i, ucode_size, regs_size;
618 switch (rdev->family) {
620 io_mc_regs = (u32 *)&barts_io_mc_regs;
621 ucode_size = BTC_MC_UCODE_SIZE;
622 regs_size = BTC_IO_MC_REGS_SIZE;
625 io_mc_regs = (u32 *)&turks_io_mc_regs;
626 ucode_size = BTC_MC_UCODE_SIZE;
627 regs_size = BTC_IO_MC_REGS_SIZE;
631 io_mc_regs = (u32 *)&caicos_io_mc_regs;
632 ucode_size = BTC_MC_UCODE_SIZE;
633 regs_size = BTC_IO_MC_REGS_SIZE;
636 io_mc_regs = (u32 *)&cayman_io_mc_regs;
637 ucode_size = CAYMAN_MC_UCODE_SIZE;
638 regs_size = BTC_IO_MC_REGS_SIZE;
642 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
643 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
645 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
647 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
648 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
651 /* reset the engine and set to writable */
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
655 /* load mc io regs */
656 for (i = 0; i < regs_size; i++) {
657 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
658 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
660 /* load the MC ucode */
661 fw_data = (const __be32 *)rdev->mc_fw->data;
662 for (i = 0; i < ucode_size; i++)
663 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
665 /* put the engine back into the active state */
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
670 /* wait for training to complete */
671 for (i = 0; i < rdev->usec_timeout; i++) {
672 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
678 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
684 int ni_init_microcode(struct radeon_device *rdev)
686 const char *chip_name;
687 const char *rlc_chip_name;
688 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
689 size_t smc_req_size = 0;
695 switch (rdev->family) {
698 rlc_chip_name = "BTC";
699 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
700 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
701 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
702 mc_req_size = BTC_MC_UCODE_SIZE * 4;
703 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
707 rlc_chip_name = "BTC";
708 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
709 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
710 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
711 mc_req_size = BTC_MC_UCODE_SIZE * 4;
712 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
715 chip_name = "CAICOS";
716 rlc_chip_name = "BTC";
717 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
718 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
719 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
720 mc_req_size = BTC_MC_UCODE_SIZE * 4;
721 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
724 chip_name = "CAYMAN";
725 rlc_chip_name = "CAYMAN";
726 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
727 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
728 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
729 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
730 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
734 rlc_chip_name = "ARUBA";
735 /* pfp/me same size as CAYMAN */
736 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
737 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
738 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
744 DRM_INFO("Loading %s Microcode\n", chip_name);
746 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
747 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
750 if (rdev->pfp_fw->size != pfp_req_size) {
752 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
753 rdev->pfp_fw->size, fw_name);
758 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
759 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
762 if (rdev->me_fw->size != me_req_size) {
764 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
765 rdev->me_fw->size, fw_name);
769 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
770 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
773 if (rdev->rlc_fw->size != rlc_req_size) {
775 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
776 rdev->rlc_fw->size, fw_name);
780 /* no MC ucode on TN */
781 if (!(rdev->flags & RADEON_IS_IGP)) {
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
786 if (rdev->mc_fw->size != mc_req_size) {
788 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
789 rdev->mc_fw->size, fw_name);
794 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
796 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
799 "smc: error loading firmware \"%s\"\n",
801 release_firmware(rdev->smc_fw);
803 } else if (rdev->smc_fw->size != smc_req_size) {
805 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
806 rdev->mc_fw->size, fw_name);
815 "ni_cp: Failed to load firmware \"%s\"\n",
817 release_firmware(rdev->pfp_fw);
819 release_firmware(rdev->me_fw);
821 release_firmware(rdev->rlc_fw);
823 release_firmware(rdev->mc_fw);
829 int tn_get_temp(struct radeon_device *rdev)
831 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
832 int actual_temp = (temp / 8) - 49;
834 return actual_temp * 1000;
840 static void cayman_gpu_init(struct radeon_device *rdev)
842 u32 gb_addr_config = 0;
843 u32 mc_shared_chmap, mc_arb_ramcfg;
844 u32 cgts_tcc_disable;
847 u32 cgts_sm_ctrl_reg;
848 u32 hdp_host_path_cntl;
850 u32 disabled_rb_mask;
853 switch (rdev->family) {
855 rdev->config.cayman.max_shader_engines = 2;
856 rdev->config.cayman.max_pipes_per_simd = 4;
857 rdev->config.cayman.max_tile_pipes = 8;
858 rdev->config.cayman.max_simds_per_se = 12;
859 rdev->config.cayman.max_backends_per_se = 4;
860 rdev->config.cayman.max_texture_channel_caches = 8;
861 rdev->config.cayman.max_gprs = 256;
862 rdev->config.cayman.max_threads = 256;
863 rdev->config.cayman.max_gs_threads = 32;
864 rdev->config.cayman.max_stack_entries = 512;
865 rdev->config.cayman.sx_num_of_sets = 8;
866 rdev->config.cayman.sx_max_export_size = 256;
867 rdev->config.cayman.sx_max_export_pos_size = 64;
868 rdev->config.cayman.sx_max_export_smx_size = 192;
869 rdev->config.cayman.max_hw_contexts = 8;
870 rdev->config.cayman.sq_num_cf_insts = 2;
872 rdev->config.cayman.sc_prim_fifo_size = 0x100;
873 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
874 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
875 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
879 rdev->config.cayman.max_shader_engines = 1;
880 rdev->config.cayman.max_pipes_per_simd = 4;
881 rdev->config.cayman.max_tile_pipes = 2;
882 if ((rdev->pdev->device == 0x9900) ||
883 (rdev->pdev->device == 0x9901) ||
884 (rdev->pdev->device == 0x9905) ||
885 (rdev->pdev->device == 0x9906) ||
886 (rdev->pdev->device == 0x9907) ||
887 (rdev->pdev->device == 0x9908) ||
888 (rdev->pdev->device == 0x9909) ||
889 (rdev->pdev->device == 0x990B) ||
890 (rdev->pdev->device == 0x990C) ||
891 (rdev->pdev->device == 0x990F) ||
892 (rdev->pdev->device == 0x9910) ||
893 (rdev->pdev->device == 0x9917) ||
894 (rdev->pdev->device == 0x9999) ||
895 (rdev->pdev->device == 0x999C)) {
896 rdev->config.cayman.max_simds_per_se = 6;
897 rdev->config.cayman.max_backends_per_se = 2;
898 } else if ((rdev->pdev->device == 0x9903) ||
899 (rdev->pdev->device == 0x9904) ||
900 (rdev->pdev->device == 0x990A) ||
901 (rdev->pdev->device == 0x990D) ||
902 (rdev->pdev->device == 0x990E) ||
903 (rdev->pdev->device == 0x9913) ||
904 (rdev->pdev->device == 0x9918) ||
905 (rdev->pdev->device == 0x999D)) {
906 rdev->config.cayman.max_simds_per_se = 4;
907 rdev->config.cayman.max_backends_per_se = 2;
908 } else if ((rdev->pdev->device == 0x9919) ||
909 (rdev->pdev->device == 0x9990) ||
910 (rdev->pdev->device == 0x9991) ||
911 (rdev->pdev->device == 0x9994) ||
912 (rdev->pdev->device == 0x9995) ||
913 (rdev->pdev->device == 0x9996) ||
914 (rdev->pdev->device == 0x999A) ||
915 (rdev->pdev->device == 0x99A0)) {
916 rdev->config.cayman.max_simds_per_se = 3;
917 rdev->config.cayman.max_backends_per_se = 1;
919 rdev->config.cayman.max_simds_per_se = 2;
920 rdev->config.cayman.max_backends_per_se = 1;
922 rdev->config.cayman.max_texture_channel_caches = 2;
923 rdev->config.cayman.max_gprs = 256;
924 rdev->config.cayman.max_threads = 256;
925 rdev->config.cayman.max_gs_threads = 32;
926 rdev->config.cayman.max_stack_entries = 512;
927 rdev->config.cayman.sx_num_of_sets = 8;
928 rdev->config.cayman.sx_max_export_size = 256;
929 rdev->config.cayman.sx_max_export_pos_size = 64;
930 rdev->config.cayman.sx_max_export_smx_size = 192;
931 rdev->config.cayman.max_hw_contexts = 8;
932 rdev->config.cayman.sq_num_cf_insts = 2;
934 rdev->config.cayman.sc_prim_fifo_size = 0x40;
935 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
936 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
937 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
942 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
943 WREG32((0x2c14 + j), 0x00000000);
944 WREG32((0x2c18 + j), 0x00000000);
945 WREG32((0x2c1c + j), 0x00000000);
946 WREG32((0x2c20 + j), 0x00000000);
947 WREG32((0x2c24 + j), 0x00000000);
950 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
952 evergreen_fix_pci_max_read_req_size(rdev);
954 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
955 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
957 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
958 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
959 if (rdev->config.cayman.mem_row_size_in_kb > 4)
960 rdev->config.cayman.mem_row_size_in_kb = 4;
961 /* XXX use MC settings? */
962 rdev->config.cayman.shader_engine_tile_size = 32;
963 rdev->config.cayman.num_gpus = 1;
964 rdev->config.cayman.multi_gpu_tile_size = 64;
966 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
967 rdev->config.cayman.num_tile_pipes = (1 << tmp);
968 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
969 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
970 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
971 rdev->config.cayman.num_shader_engines = tmp + 1;
972 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
973 rdev->config.cayman.num_gpus = tmp + 1;
974 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
975 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
976 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
977 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
980 /* setup tiling info dword. gb_addr_config is not adequate since it does
981 * not have bank info, so create a custom tiling dword.
984 * bits 11:8 group_size
985 * bits 15:12 row_size
987 rdev->config.cayman.tile_config = 0;
988 switch (rdev->config.cayman.num_tile_pipes) {
991 rdev->config.cayman.tile_config |= (0 << 0);
994 rdev->config.cayman.tile_config |= (1 << 0);
997 rdev->config.cayman.tile_config |= (2 << 0);
1000 rdev->config.cayman.tile_config |= (3 << 0);
1004 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1005 if (rdev->flags & RADEON_IS_IGP)
1006 rdev->config.cayman.tile_config |= 1 << 4;
1008 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1009 case 0: /* four banks */
1010 rdev->config.cayman.tile_config |= 0 << 4;
1012 case 1: /* eight banks */
1013 rdev->config.cayman.tile_config |= 1 << 4;
1015 case 2: /* sixteen banks */
1017 rdev->config.cayman.tile_config |= 2 << 4;
1021 rdev->config.cayman.tile_config |=
1022 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1023 rdev->config.cayman.tile_config |=
1024 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1027 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1028 u32 rb_disable_bitmap;
1030 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1031 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1032 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1034 tmp |= rb_disable_bitmap;
1036 /* enabled rb are just the one not disabled :) */
1037 disabled_rb_mask = tmp;
1039 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1041 /* if all the backends are disabled, fix it up here */
1042 if ((disabled_rb_mask & tmp) == tmp) {
1043 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1044 disabled_rb_mask &= ~(1 << i);
1047 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1048 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1050 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1051 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1052 if (ASIC_IS_DCE6(rdev))
1053 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1054 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1055 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1056 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1057 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1058 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1059 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1061 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1062 (rdev->flags & RADEON_IS_IGP)) {
1063 if ((disabled_rb_mask & 3) == 1) {
1064 /* RB0 disabled, RB1 enabled */
1067 /* RB1 disabled, RB0 enabled */
1071 tmp = gb_addr_config & NUM_PIPES_MASK;
1072 tmp = r6xx_remap_render_backend(rdev, tmp,
1073 rdev->config.cayman.max_backends_per_se *
1074 rdev->config.cayman.max_shader_engines,
1075 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1077 WREG32(GB_BACKEND_MAP, tmp);
1079 cgts_tcc_disable = 0xffff0000;
1080 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1081 cgts_tcc_disable &= ~(1 << (16 + i));
1082 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1083 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1084 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1085 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1087 /* reprogram the shader complex */
1088 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1089 for (i = 0; i < 16; i++)
1090 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1091 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1093 /* set HW defaults for 3D engine */
1094 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1096 sx_debug_1 = RREG32(SX_DEBUG_1);
1097 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1098 WREG32(SX_DEBUG_1, sx_debug_1);
1100 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1101 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1102 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1103 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1105 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1107 /* need to be explicitly zero-ed */
1108 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1109 WREG32(SQ_LSTMP_RING_BASE, 0);
1110 WREG32(SQ_HSTMP_RING_BASE, 0);
1111 WREG32(SQ_ESTMP_RING_BASE, 0);
1112 WREG32(SQ_GSTMP_RING_BASE, 0);
1113 WREG32(SQ_VSTMP_RING_BASE, 0);
1114 WREG32(SQ_PSTMP_RING_BASE, 0);
1116 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1118 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1119 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1120 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1122 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1123 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1124 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1127 WREG32(VGT_NUM_INSTANCES, 1);
1129 WREG32(CP_PERFMON_CNTL, 0);
1131 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1132 FETCH_FIFO_HIWATER(0x4) |
1133 DONE_FIFO_HIWATER(0xe0) |
1134 ALU_UPDATE_FIFO_HIWATER(0x8)));
1136 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1137 WREG32(SQ_CONFIG, (VC_ENABLE |
1142 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1144 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1145 FORCE_EOV_MAX_REZ_CNT(255)));
1147 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1148 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1150 WREG32(VGT_GS_VERTEX_REUSE, 16);
1151 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1153 WREG32(CB_PERF_CTR0_SEL_0, 0);
1154 WREG32(CB_PERF_CTR0_SEL_1, 0);
1155 WREG32(CB_PERF_CTR1_SEL_0, 0);
1156 WREG32(CB_PERF_CTR1_SEL_1, 0);
1157 WREG32(CB_PERF_CTR2_SEL_0, 0);
1158 WREG32(CB_PERF_CTR2_SEL_1, 0);
1159 WREG32(CB_PERF_CTR3_SEL_0, 0);
1160 WREG32(CB_PERF_CTR3_SEL_1, 0);
1162 tmp = RREG32(HDP_MISC_CNTL);
1163 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1164 WREG32(HDP_MISC_CNTL, tmp);
1166 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1167 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1169 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1173 /* set clockgating golden values on TN */
1174 if (rdev->family == CHIP_ARUBA) {
1175 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1177 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1178 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1180 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1187 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1189 /* flush hdp cache */
1190 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1192 /* bits 0-7 are the VM contexts0-7 */
1193 WREG32(VM_INVALIDATE_REQUEST, 1);
1196 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1200 if (rdev->gart.robj == NULL) {
1201 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1204 r = radeon_gart_table_vram_pin(rdev);
1207 radeon_gart_restore(rdev);
1208 /* Setup TLB control */
1209 WREG32(MC_VM_MX_L1_TLB_CNTL,
1212 ENABLE_L1_FRAGMENT_PROCESSING |
1213 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1214 ENABLE_ADVANCED_DRIVER_MODEL |
1215 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1216 /* Setup L2 cache */
1217 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1218 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1219 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1220 EFFECTIVE_L2_QUEUE_SIZE(7) |
1221 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1222 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1223 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1224 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1225 /* setup context0 */
1226 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1227 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1228 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1229 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1230 (u32)(rdev->dummy_page.addr >> 12));
1231 WREG32(VM_CONTEXT0_CNTL2, 0);
1232 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1233 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1239 /* empty context1-7 */
1240 /* Assign the pt base to something valid for now; the pts used for
1241 * the VMs are determined by the application and setup and assigned
1242 * on the fly in the vm part of radeon_gart.c
1244 for (i = 1; i < 8; i++) {
1245 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1246 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1247 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1248 rdev->gart.table_addr >> 12);
1251 /* enable context1-7 */
1252 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1253 (u32)(rdev->dummy_page.addr >> 12));
1254 WREG32(VM_CONTEXT1_CNTL2, 4);
1255 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1256 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1257 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1258 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1259 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1260 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1261 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1262 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1263 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1264 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1265 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1266 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1267 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1269 cayman_pcie_gart_tlb_flush(rdev);
1270 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1271 (unsigned)(rdev->mc.gtt_size >> 20),
1272 (unsigned long long)rdev->gart.table_addr);
1273 rdev->gart.ready = true;
1277 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1279 /* Disable all tables */
1280 WREG32(VM_CONTEXT0_CNTL, 0);
1281 WREG32(VM_CONTEXT1_CNTL, 0);
1282 /* Setup TLB control */
1283 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1284 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1285 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1286 /* Setup L2 cache */
1287 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1288 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1289 EFFECTIVE_L2_QUEUE_SIZE(7) |
1290 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1291 WREG32(VM_L2_CNTL2, 0);
1292 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1293 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1294 radeon_gart_table_vram_unpin(rdev);
1297 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1299 cayman_pcie_gart_disable(rdev);
1300 radeon_gart_table_vram_free(rdev);
1301 radeon_gart_fini(rdev);
1304 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1305 int ring, u32 cp_int_cntl)
1307 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1309 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1310 WREG32(CP_INT_CNTL, cp_int_cntl);
1316 void cayman_fence_ring_emit(struct radeon_device *rdev,
1317 struct radeon_fence *fence)
1319 struct radeon_ring *ring = &rdev->ring[fence->ring];
1320 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1322 /* flush read cache over gart for this vmid */
1323 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1324 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1325 radeon_ring_write(ring, 0);
1326 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1327 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1328 radeon_ring_write(ring, 0xFFFFFFFF);
1329 radeon_ring_write(ring, 0);
1330 radeon_ring_write(ring, 10); /* poll interval */
1331 /* EVENT_WRITE_EOP - flush caches, send int */
1332 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1333 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1334 radeon_ring_write(ring, addr & 0xffffffff);
1335 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1336 radeon_ring_write(ring, fence->seq);
1337 radeon_ring_write(ring, 0);
1340 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1342 struct radeon_ring *ring = &rdev->ring[ib->ring];
1344 /* set to DX10/11 mode */
1345 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1346 radeon_ring_write(ring, 1);
1348 if (ring->rptr_save_reg) {
1349 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1350 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1351 radeon_ring_write(ring, ((ring->rptr_save_reg -
1352 PACKET3_SET_CONFIG_REG_START) >> 2));
1353 radeon_ring_write(ring, next_rptr);
1356 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1357 radeon_ring_write(ring,
1361 (ib->gpu_addr & 0xFFFFFFFC));
1362 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1363 radeon_ring_write(ring, ib->length_dw |
1364 (ib->vm ? (ib->vm->id << 24) : 0));
1366 /* flush read cache over gart for this vmid */
1367 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1368 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1369 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1370 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1371 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1372 radeon_ring_write(ring, 0xFFFFFFFF);
1373 radeon_ring_write(ring, 0);
1374 radeon_ring_write(ring, 10); /* poll interval */
1377 void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
1378 struct radeon_ring *ring,
1379 struct radeon_semaphore *semaphore,
1382 uint64_t addr = semaphore->gpu_addr;
1384 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
1385 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
1387 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
1388 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
1390 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
1391 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
1394 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1397 WREG32(CP_ME_CNTL, 0);
1399 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1400 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1401 WREG32(SCRATCH_UMSK, 0);
1402 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1406 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1408 const __be32 *fw_data;
1411 if (!rdev->me_fw || !rdev->pfp_fw)
1414 cayman_cp_enable(rdev, false);
1416 fw_data = (const __be32 *)rdev->pfp_fw->data;
1417 WREG32(CP_PFP_UCODE_ADDR, 0);
1418 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1419 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1420 WREG32(CP_PFP_UCODE_ADDR, 0);
1422 fw_data = (const __be32 *)rdev->me_fw->data;
1423 WREG32(CP_ME_RAM_WADDR, 0);
1424 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1425 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1427 WREG32(CP_PFP_UCODE_ADDR, 0);
1428 WREG32(CP_ME_RAM_WADDR, 0);
1429 WREG32(CP_ME_RAM_RADDR, 0);
1433 static int cayman_cp_start(struct radeon_device *rdev)
1435 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1438 r = radeon_ring_lock(rdev, ring, 7);
1440 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1443 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1444 radeon_ring_write(ring, 0x1);
1445 radeon_ring_write(ring, 0x0);
1446 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1447 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1448 radeon_ring_write(ring, 0);
1449 radeon_ring_write(ring, 0);
1450 radeon_ring_unlock_commit(rdev, ring);
1452 cayman_cp_enable(rdev, true);
1454 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1456 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1460 /* setup clear context state */
1461 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1462 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1464 for (i = 0; i < cayman_default_size; i++)
1465 radeon_ring_write(ring, cayman_default_state[i]);
1467 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1468 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1470 /* set clear context state */
1471 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1472 radeon_ring_write(ring, 0);
1474 /* SQ_VTX_BASE_VTX_LOC */
1475 radeon_ring_write(ring, 0xc0026f00);
1476 radeon_ring_write(ring, 0x00000000);
1477 radeon_ring_write(ring, 0x00000000);
1478 radeon_ring_write(ring, 0x00000000);
1481 radeon_ring_write(ring, 0xc0036f00);
1482 radeon_ring_write(ring, 0x00000bc4);
1483 radeon_ring_write(ring, 0xffffffff);
1484 radeon_ring_write(ring, 0xffffffff);
1485 radeon_ring_write(ring, 0xffffffff);
1487 radeon_ring_write(ring, 0xc0026900);
1488 radeon_ring_write(ring, 0x00000316);
1489 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1490 radeon_ring_write(ring, 0x00000010); /* */
1492 radeon_ring_unlock_commit(rdev, ring);
1494 /* XXX init other rings */
1499 static void cayman_cp_fini(struct radeon_device *rdev)
1501 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1502 cayman_cp_enable(rdev, false);
1503 radeon_ring_fini(rdev, ring);
1504 radeon_scratch_free(rdev, ring->rptr_save_reg);
1507 static int cayman_cp_resume(struct radeon_device *rdev)
1509 static const int ridx[] = {
1510 RADEON_RING_TYPE_GFX_INDEX,
1511 CAYMAN_RING_TYPE_CP1_INDEX,
1512 CAYMAN_RING_TYPE_CP2_INDEX
1514 static const unsigned cp_rb_cntl[] = {
1519 static const unsigned cp_rb_rptr_addr[] = {
1524 static const unsigned cp_rb_rptr_addr_hi[] = {
1525 CP_RB0_RPTR_ADDR_HI,
1526 CP_RB1_RPTR_ADDR_HI,
1529 static const unsigned cp_rb_base[] = {
1534 struct radeon_ring *ring;
1537 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1538 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1544 RREG32(GRBM_SOFT_RESET);
1546 WREG32(GRBM_SOFT_RESET, 0);
1547 RREG32(GRBM_SOFT_RESET);
1549 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1550 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1552 /* Set the write pointer delay */
1553 WREG32(CP_RB_WPTR_DELAY, 0);
1555 WREG32(CP_DEBUG, (1 << 27));
1557 /* set the wb address whether it's enabled or not */
1558 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1559 WREG32(SCRATCH_UMSK, 0xff);
1561 for (i = 0; i < 3; ++i) {
1565 /* Set ring buffer size */
1566 ring = &rdev->ring[ridx[i]];
1567 rb_cntl = drm_order(ring->ring_size / 8);
1568 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
1570 rb_cntl |= BUF_SWAP_32BIT;
1572 WREG32(cp_rb_cntl[i], rb_cntl);
1574 /* set the wb address whether it's enabled or not */
1575 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1576 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1577 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1580 /* set the rb base addr, this causes an internal reset of ALL rings */
1581 for (i = 0; i < 3; ++i) {
1582 ring = &rdev->ring[ridx[i]];
1583 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1586 for (i = 0; i < 3; ++i) {
1587 /* Initialize the ring buffer's read and write pointers */
1588 ring = &rdev->ring[ridx[i]];
1589 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1591 ring->rptr = ring->wptr = 0;
1592 WREG32(ring->rptr_reg, ring->rptr);
1593 WREG32(ring->wptr_reg, ring->wptr);
1596 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1599 /* start the rings */
1600 cayman_cp_start(rdev);
1601 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1602 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1603 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1604 /* this only test cp0 */
1605 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1607 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1608 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1609 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1618 * Starting with R600, the GPU has an asynchronous
1619 * DMA engine. The programming model is very similar
1620 * to the 3D engine (ring buffer, IBs, etc.), but the
1621 * DMA controller has it's own packet format that is
1622 * different form the PM4 format used by the 3D engine.
1623 * It supports copying data, writing embedded data,
1624 * solid fills, and a number of other things. It also
1625 * has support for tiling/detiling of buffers.
1626 * Cayman and newer support two asynchronous DMA engines.
1629 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1631 * @rdev: radeon_device pointer
1632 * @ib: IB object to schedule
1634 * Schedule an IB in the DMA ring (cayman-SI).
1636 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1637 struct radeon_ib *ib)
1639 struct radeon_ring *ring = &rdev->ring[ib->ring];
1641 if (rdev->wb.enabled) {
1642 u32 next_rptr = ring->wptr + 4;
1643 while ((next_rptr & 7) != 5)
1646 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1647 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1648 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1649 radeon_ring_write(ring, next_rptr);
1652 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1653 * Pad as necessary with NOPs.
1655 while ((ring->wptr & 7) != 5)
1656 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1657 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1658 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1659 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1664 * cayman_dma_stop - stop the async dma engines
1666 * @rdev: radeon_device pointer
1668 * Stop the async dma engines (cayman-SI).
1670 void cayman_dma_stop(struct radeon_device *rdev)
1674 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1677 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1678 rb_cntl &= ~DMA_RB_ENABLE;
1679 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1682 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1683 rb_cntl &= ~DMA_RB_ENABLE;
1684 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1686 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1687 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1691 * cayman_dma_resume - setup and start the async dma engines
1693 * @rdev: radeon_device pointer
1695 * Set up the DMA ring buffers and enable them. (cayman-SI).
1696 * Returns 0 for success, error for failure.
1698 int cayman_dma_resume(struct radeon_device *rdev)
1700 struct radeon_ring *ring;
1701 u32 rb_cntl, dma_cntl, ib_cntl;
1703 u32 reg_offset, wb_offset;
1707 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1708 RREG32(SRBM_SOFT_RESET);
1710 WREG32(SRBM_SOFT_RESET, 0);
1712 for (i = 0; i < 2; i++) {
1714 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1715 reg_offset = DMA0_REGISTER_OFFSET;
1716 wb_offset = R600_WB_DMA_RPTR_OFFSET;
1718 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1719 reg_offset = DMA1_REGISTER_OFFSET;
1720 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1723 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1724 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1726 /* Set ring buffer size in dwords */
1727 rb_bufsz = drm_order(ring->ring_size / 4);
1728 rb_cntl = rb_bufsz << 1;
1730 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1732 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1734 /* Initialize the ring buffer's read and write pointers */
1735 WREG32(DMA_RB_RPTR + reg_offset, 0);
1736 WREG32(DMA_RB_WPTR + reg_offset, 0);
1738 /* set the wb address whether it's enabled or not */
1739 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1740 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1741 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1742 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1744 if (rdev->wb.enabled)
1745 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1747 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1749 /* enable DMA IBs */
1750 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
1752 ib_cntl |= DMA_IB_SWAP_ENABLE;
1754 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
1756 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1757 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1758 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1761 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1763 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1765 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1769 r = radeon_ring_test(rdev, ring->idx, ring);
1771 ring->ready = false;
1776 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1782 * cayman_dma_fini - tear down the async dma engines
1784 * @rdev: radeon_device pointer
1786 * Stop the async dma engines and free the rings (cayman-SI).
1788 void cayman_dma_fini(struct radeon_device *rdev)
1790 cayman_dma_stop(rdev);
1791 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1792 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1795 static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1801 tmp = RREG32(GRBM_STATUS);
1802 if (tmp & (PA_BUSY | SC_BUSY |
1804 TA_BUSY | VGT_BUSY |
1806 GDS_BUSY | SPI_BUSY |
1807 IA_BUSY | IA_BUSY_NO_DMA))
1808 reset_mask |= RADEON_RESET_GFX;
1810 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1811 CP_BUSY | CP_COHERENCY_BUSY))
1812 reset_mask |= RADEON_RESET_CP;
1814 if (tmp & GRBM_EE_BUSY)
1815 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1817 /* DMA_STATUS_REG 0 */
1818 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1819 if (!(tmp & DMA_IDLE))
1820 reset_mask |= RADEON_RESET_DMA;
1822 /* DMA_STATUS_REG 1 */
1823 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1824 if (!(tmp & DMA_IDLE))
1825 reset_mask |= RADEON_RESET_DMA1;
1828 tmp = RREG32(SRBM_STATUS2);
1830 reset_mask |= RADEON_RESET_DMA;
1832 if (tmp & DMA1_BUSY)
1833 reset_mask |= RADEON_RESET_DMA1;
1836 tmp = RREG32(SRBM_STATUS);
1837 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1838 reset_mask |= RADEON_RESET_RLC;
1841 reset_mask |= RADEON_RESET_IH;
1844 reset_mask |= RADEON_RESET_SEM;
1846 if (tmp & GRBM_RQ_PENDING)
1847 reset_mask |= RADEON_RESET_GRBM;
1850 reset_mask |= RADEON_RESET_VMC;
1852 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1853 MCC_BUSY | MCD_BUSY))
1854 reset_mask |= RADEON_RESET_MC;
1856 if (evergreen_is_display_hung(rdev))
1857 reset_mask |= RADEON_RESET_DISPLAY;
1860 tmp = RREG32(VM_L2_STATUS);
1862 reset_mask |= RADEON_RESET_VMC;
1864 /* Skip MC reset as it's mostly likely not hung, just busy */
1865 if (reset_mask & RADEON_RESET_MC) {
1866 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1867 reset_mask &= ~RADEON_RESET_MC;
1873 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1875 struct evergreen_mc_save save;
1876 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1879 if (reset_mask == 0)
1882 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1884 evergreen_print_gpu_status_regs(rdev);
1885 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1887 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1889 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1891 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1894 /* Disable CP parsing/prefetching */
1895 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1897 if (reset_mask & RADEON_RESET_DMA) {
1899 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1900 tmp &= ~DMA_RB_ENABLE;
1901 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1904 if (reset_mask & RADEON_RESET_DMA1) {
1906 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1907 tmp &= ~DMA_RB_ENABLE;
1908 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1913 evergreen_mc_stop(rdev, &save);
1914 if (evergreen_mc_wait_for_idle(rdev)) {
1915 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1918 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1919 grbm_soft_reset = SOFT_RESET_CB |
1933 if (reset_mask & RADEON_RESET_CP) {
1934 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1936 srbm_soft_reset |= SOFT_RESET_GRBM;
1939 if (reset_mask & RADEON_RESET_DMA)
1940 srbm_soft_reset |= SOFT_RESET_DMA;
1942 if (reset_mask & RADEON_RESET_DMA1)
1943 srbm_soft_reset |= SOFT_RESET_DMA1;
1945 if (reset_mask & RADEON_RESET_DISPLAY)
1946 srbm_soft_reset |= SOFT_RESET_DC;
1948 if (reset_mask & RADEON_RESET_RLC)
1949 srbm_soft_reset |= SOFT_RESET_RLC;
1951 if (reset_mask & RADEON_RESET_SEM)
1952 srbm_soft_reset |= SOFT_RESET_SEM;
1954 if (reset_mask & RADEON_RESET_IH)
1955 srbm_soft_reset |= SOFT_RESET_IH;
1957 if (reset_mask & RADEON_RESET_GRBM)
1958 srbm_soft_reset |= SOFT_RESET_GRBM;
1960 if (reset_mask & RADEON_RESET_VMC)
1961 srbm_soft_reset |= SOFT_RESET_VMC;
1963 if (!(rdev->flags & RADEON_IS_IGP)) {
1964 if (reset_mask & RADEON_RESET_MC)
1965 srbm_soft_reset |= SOFT_RESET_MC;
1968 if (grbm_soft_reset) {
1969 tmp = RREG32(GRBM_SOFT_RESET);
1970 tmp |= grbm_soft_reset;
1971 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1972 WREG32(GRBM_SOFT_RESET, tmp);
1973 tmp = RREG32(GRBM_SOFT_RESET);
1977 tmp &= ~grbm_soft_reset;
1978 WREG32(GRBM_SOFT_RESET, tmp);
1979 tmp = RREG32(GRBM_SOFT_RESET);
1982 if (srbm_soft_reset) {
1983 tmp = RREG32(SRBM_SOFT_RESET);
1984 tmp |= srbm_soft_reset;
1985 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1986 WREG32(SRBM_SOFT_RESET, tmp);
1987 tmp = RREG32(SRBM_SOFT_RESET);
1991 tmp &= ~srbm_soft_reset;
1992 WREG32(SRBM_SOFT_RESET, tmp);
1993 tmp = RREG32(SRBM_SOFT_RESET);
1996 /* Wait a little for things to settle down */
1999 evergreen_mc_resume(rdev, &save);
2002 evergreen_print_gpu_status_regs(rdev);
2005 int cayman_asic_reset(struct radeon_device *rdev)
2009 reset_mask = cayman_gpu_check_soft_reset(rdev);
2012 r600_set_bios_scratch_engine_hung(rdev, true);
2014 cayman_gpu_soft_reset(rdev, reset_mask);
2016 reset_mask = cayman_gpu_check_soft_reset(rdev);
2019 r600_set_bios_scratch_engine_hung(rdev, false);
2025 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
2027 * @rdev: radeon_device pointer
2028 * @ring: radeon_ring structure holding ring information
2030 * Check if the GFX engine is locked up.
2031 * Returns true if the engine appears to be locked up, false if not.
2033 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2035 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
2037 if (!(reset_mask & (RADEON_RESET_GFX |
2038 RADEON_RESET_COMPUTE |
2039 RADEON_RESET_CP))) {
2040 radeon_ring_lockup_update(ring);
2043 /* force CP activities */
2044 radeon_ring_force_activity(rdev, ring);
2045 return radeon_ring_test_lockup(rdev, ring);
2049 * cayman_dma_is_lockup - Check if the DMA engine is locked up
2051 * @rdev: radeon_device pointer
2052 * @ring: radeon_ring structure holding ring information
2054 * Check if the async DMA engine is locked up.
2055 * Returns true if the engine appears to be locked up, false if not.
2057 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2059 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
2062 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2063 mask = RADEON_RESET_DMA;
2065 mask = RADEON_RESET_DMA1;
2067 if (!(reset_mask & mask)) {
2068 radeon_ring_lockup_update(ring);
2071 /* force ring activities */
2072 radeon_ring_force_activity(rdev, ring);
2073 return radeon_ring_test_lockup(rdev, ring);
2076 static int cayman_startup(struct radeon_device *rdev)
2078 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2081 /* enable pcie gen2 link */
2082 evergreen_pcie_gen2_enable(rdev);
2084 evergreen_program_aspm(rdev);
2086 evergreen_mc_program(rdev);
2088 if (rdev->flags & RADEON_IS_IGP) {
2089 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2090 r = ni_init_microcode(rdev);
2092 DRM_ERROR("Failed to load firmware!\n");
2097 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2098 r = ni_init_microcode(rdev);
2100 DRM_ERROR("Failed to load firmware!\n");
2105 r = ni_mc_load_microcode(rdev);
2107 DRM_ERROR("Failed to load MC firmware!\n");
2112 r = r600_vram_scratch_init(rdev);
2116 r = cayman_pcie_gart_enable(rdev);
2119 cayman_gpu_init(rdev);
2121 r = evergreen_blit_init(rdev);
2123 r600_blit_fini(rdev);
2124 rdev->asic->copy.copy = NULL;
2125 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2128 /* allocate rlc buffers */
2129 if (rdev->flags & RADEON_IS_IGP) {
2130 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2131 rdev->rlc.reg_list_size = tn_rlc_save_restore_register_list_size;
2132 rdev->rlc.cs_data = cayman_cs_data;
2133 r = sumo_rlc_init(rdev);
2135 DRM_ERROR("Failed to init rlc BOs!\n");
2140 /* allocate wb buffer */
2141 r = radeon_wb_init(rdev);
2145 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2147 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2151 r = rv770_uvd_resume(rdev);
2153 r = radeon_fence_driver_start_ring(rdev,
2154 R600_RING_TYPE_UVD_INDEX);
2156 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
2159 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2161 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2163 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2167 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2169 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2173 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2175 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2179 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2181 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2186 if (!rdev->irq.installed) {
2187 r = radeon_irq_kms_init(rdev);
2192 r = r600_irq_init(rdev);
2194 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2195 radeon_irq_kms_fini(rdev);
2198 evergreen_irq_set(rdev);
2200 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2201 CP_RB0_RPTR, CP_RB0_WPTR,
2202 0, 0xfffff, RADEON_CP_PACKET2);
2206 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2207 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2208 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
2209 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
2210 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2214 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2215 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2216 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
2217 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
2218 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2222 r = cayman_cp_load_microcode(rdev);
2225 r = cayman_cp_resume(rdev);
2229 r = cayman_dma_resume(rdev);
2233 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2234 if (ring->ring_size) {
2235 r = radeon_ring_init(rdev, ring, ring->ring_size,
2236 R600_WB_UVD_RPTR_OFFSET,
2237 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
2238 0, 0xfffff, RADEON_CP_PACKET2);
2240 r = r600_uvd_init(rdev);
2242 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2245 r = radeon_ib_pool_init(rdev);
2247 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2251 r = radeon_vm_manager_init(rdev);
2253 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2257 r = r600_audio_init(rdev);
2264 int cayman_resume(struct radeon_device *rdev)
2268 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2269 * posting will perform necessary task to bring back GPU into good
2273 atom_asic_init(rdev->mode_info.atom_context);
2275 /* init golden registers */
2276 ni_init_golden_registers(rdev);
2278 rdev->accel_working = true;
2279 r = cayman_startup(rdev);
2281 DRM_ERROR("cayman startup failed on resume\n");
2282 rdev->accel_working = false;
2288 int cayman_suspend(struct radeon_device *rdev)
2290 r600_audio_fini(rdev);
2291 radeon_vm_manager_fini(rdev);
2292 cayman_cp_enable(rdev, false);
2293 cayman_dma_stop(rdev);
2294 r600_uvd_stop(rdev);
2295 radeon_uvd_suspend(rdev);
2296 evergreen_irq_suspend(rdev);
2297 radeon_wb_disable(rdev);
2298 cayman_pcie_gart_disable(rdev);
2302 /* Plan is to move initialization in that function and use
2303 * helper function so that radeon_device_init pretty much
2304 * do nothing more than calling asic specific function. This
2305 * should also allow to remove a bunch of callback function
2308 int cayman_init(struct radeon_device *rdev)
2310 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2314 if (!radeon_get_bios(rdev)) {
2315 if (ASIC_IS_AVIVO(rdev))
2318 /* Must be an ATOMBIOS */
2319 if (!rdev->is_atom_bios) {
2320 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2323 r = radeon_atombios_init(rdev);
2327 /* Post card if necessary */
2328 if (!radeon_card_posted(rdev)) {
2330 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2333 DRM_INFO("GPU not posted. posting now...\n");
2334 atom_asic_init(rdev->mode_info.atom_context);
2336 /* init golden registers */
2337 ni_init_golden_registers(rdev);
2338 /* Initialize scratch registers */
2339 r600_scratch_init(rdev);
2340 /* Initialize surface registers */
2341 radeon_surface_init(rdev);
2342 /* Initialize clocks */
2343 radeon_get_clock_info(rdev->ddev);
2345 r = radeon_fence_driver_init(rdev);
2348 /* initialize memory controller */
2349 r = evergreen_mc_init(rdev);
2352 /* Memory manager */
2353 r = radeon_bo_init(rdev);
2357 ring->ring_obj = NULL;
2358 r600_ring_init(rdev, ring, 1024 * 1024);
2360 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2361 ring->ring_obj = NULL;
2362 r600_ring_init(rdev, ring, 64 * 1024);
2364 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2365 ring->ring_obj = NULL;
2366 r600_ring_init(rdev, ring, 64 * 1024);
2368 r = radeon_uvd_init(rdev);
2370 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2371 ring->ring_obj = NULL;
2372 r600_ring_init(rdev, ring, 4096);
2375 rdev->ih.ring_obj = NULL;
2376 r600_ih_ring_init(rdev, 64 * 1024);
2378 r = r600_pcie_gart_init(rdev);
2382 rdev->accel_working = true;
2383 r = cayman_startup(rdev);
2385 dev_err(rdev->dev, "disabling GPU acceleration\n");
2386 cayman_cp_fini(rdev);
2387 cayman_dma_fini(rdev);
2388 r600_irq_fini(rdev);
2389 if (rdev->flags & RADEON_IS_IGP)
2390 sumo_rlc_fini(rdev);
2391 radeon_wb_fini(rdev);
2392 radeon_ib_pool_fini(rdev);
2393 radeon_vm_manager_fini(rdev);
2394 radeon_irq_kms_fini(rdev);
2395 cayman_pcie_gart_fini(rdev);
2396 rdev->accel_working = false;
2399 /* Don't start up if the MC ucode is missing.
2400 * The default clocks and voltages before the MC ucode
2401 * is loaded are not suffient for advanced operations.
2403 * We can skip this check for TN, because there is no MC
2406 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2407 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2414 void cayman_fini(struct radeon_device *rdev)
2416 r600_blit_fini(rdev);
2417 cayman_cp_fini(rdev);
2418 cayman_dma_fini(rdev);
2419 r600_irq_fini(rdev);
2420 if (rdev->flags & RADEON_IS_IGP)
2421 sumo_rlc_fini(rdev);
2422 radeon_wb_fini(rdev);
2423 radeon_vm_manager_fini(rdev);
2424 radeon_ib_pool_fini(rdev);
2425 radeon_irq_kms_fini(rdev);
2426 r600_uvd_stop(rdev);
2427 radeon_uvd_fini(rdev);
2428 cayman_pcie_gart_fini(rdev);
2429 r600_vram_scratch_fini(rdev);
2430 radeon_gem_fini(rdev);
2431 radeon_fence_driver_fini(rdev);
2432 radeon_bo_fini(rdev);
2433 radeon_atombios_fini(rdev);
2441 int cayman_vm_init(struct radeon_device *rdev)
2444 rdev->vm_manager.nvm = 8;
2445 /* base offset of vram pages */
2446 if (rdev->flags & RADEON_IS_IGP) {
2447 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2449 rdev->vm_manager.vram_base_offset = tmp;
2451 rdev->vm_manager.vram_base_offset = 0;
2455 void cayman_vm_fini(struct radeon_device *rdev)
2460 * cayman_vm_decode_fault - print human readable fault info
2462 * @rdev: radeon_device pointer
2463 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2464 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2466 * Print human readable fault information (cayman/TN).
2468 void cayman_vm_decode_fault(struct radeon_device *rdev,
2469 u32 status, u32 addr)
2471 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2472 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2473 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2565 block = "TC_TFETCH";
2575 block = "TC_VFETCH";
2614 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2615 protections, vmid, addr,
2616 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2620 #define R600_ENTRY_VALID (1 << 0)
2621 #define R600_PTE_SYSTEM (1 << 1)
2622 #define R600_PTE_SNOOPED (1 << 2)
2623 #define R600_PTE_READABLE (1 << 5)
2624 #define R600_PTE_WRITEABLE (1 << 6)
2626 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
2628 uint32_t r600_flags = 0;
2629 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
2630 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
2631 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
2632 if (flags & RADEON_VM_PAGE_SYSTEM) {
2633 r600_flags |= R600_PTE_SYSTEM;
2634 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
2640 * cayman_vm_set_page - update the page tables using the CP
2642 * @rdev: radeon_device pointer
2643 * @ib: indirect buffer to fill with commands
2644 * @pe: addr of the page entry
2645 * @addr: dst addr to write into pe
2646 * @count: number of page entries to update
2647 * @incr: increase next addr by incr bytes
2648 * @flags: access flags
2650 * Update the page tables using the CP (cayman/TN).
2652 void cayman_vm_set_page(struct radeon_device *rdev,
2653 struct radeon_ib *ib,
2655 uint64_t addr, unsigned count,
2656 uint32_t incr, uint32_t flags)
2658 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2662 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2664 ndw = 1 + count * 2;
2668 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2669 ib->ptr[ib->length_dw++] = pe;
2670 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2671 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2672 if (flags & RADEON_VM_PAGE_SYSTEM) {
2673 value = radeon_vm_map_gart(rdev, addr);
2674 value &= 0xFFFFFFFFFFFFF000ULL;
2675 } else if (flags & RADEON_VM_PAGE_VALID) {
2681 value |= r600_flags;
2682 ib->ptr[ib->length_dw++] = value;
2683 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2687 if ((flags & RADEON_VM_PAGE_SYSTEM) ||
2694 /* for non-physically contiguous pages (system) */
2695 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2696 ib->ptr[ib->length_dw++] = pe;
2697 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2698 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2699 if (flags & RADEON_VM_PAGE_SYSTEM) {
2700 value = radeon_vm_map_gart(rdev, addr);
2701 value &= 0xFFFFFFFFFFFFF000ULL;
2702 } else if (flags & RADEON_VM_PAGE_VALID) {
2708 value |= r600_flags;
2709 ib->ptr[ib->length_dw++] = value;
2710 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2713 while (ib->length_dw & 0x7)
2714 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2721 if (flags & RADEON_VM_PAGE_VALID)
2725 /* for physically contiguous pages (vram) */
2726 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
2727 ib->ptr[ib->length_dw++] = pe; /* dst addr */
2728 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2729 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
2730 ib->ptr[ib->length_dw++] = 0;
2731 ib->ptr[ib->length_dw++] = value; /* value */
2732 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2733 ib->ptr[ib->length_dw++] = incr; /* increment size */
2734 ib->ptr[ib->length_dw++] = 0;
2736 addr += (ndw / 2) * incr;
2740 while (ib->length_dw & 0x7)
2741 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2746 * cayman_vm_flush - vm flush using the CP
2748 * @rdev: radeon_device pointer
2750 * Update the page table base and flush the VM TLB
2751 * using the CP (cayman-si).
2753 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2755 struct radeon_ring *ring = &rdev->ring[ridx];
2760 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2761 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2763 /* flush hdp cache */
2764 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2765 radeon_ring_write(ring, 0x1);
2767 /* bits 0-7 are the VM contexts0-7 */
2768 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2769 radeon_ring_write(ring, 1 << vm->id);
2771 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2772 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2773 radeon_ring_write(ring, 0x0);
2776 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2778 struct radeon_ring *ring = &rdev->ring[ridx];
2783 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2784 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2785 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2787 /* flush hdp cache */
2788 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2789 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2790 radeon_ring_write(ring, 1);
2792 /* bits 0-7 are the VM contexts0-7 */
2793 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2794 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2795 radeon_ring_write(ring, 1 << vm->id);