2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __NISLANDS_SMC_H__
24 #define __NISLANDS_SMC_H__
28 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
30 struct PP_NIslands_Dpm2PerfLevel
34 uint8_t MaxPS_StepInc;
35 uint8_t MaxPS_StepDec;
45 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel;
47 struct PP_NIslands_DPM2Parameters
50 uint32_t NearTDPLimit;
51 uint32_t SafePowerLimit;
52 uint32_t PowerBoostLimit;
54 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters;
56 struct NISLANDS_SMC_SCLK_VALUE
58 uint32_t vCG_SPLL_FUNC_CNTL;
59 uint32_t vCG_SPLL_FUNC_CNTL_2;
60 uint32_t vCG_SPLL_FUNC_CNTL_3;
61 uint32_t vCG_SPLL_FUNC_CNTL_4;
62 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
63 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
67 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE;
69 struct NISLANDS_SMC_MCLK_VALUE
71 uint32_t vMPLL_FUNC_CNTL;
72 uint32_t vMPLL_FUNC_CNTL_1;
73 uint32_t vMPLL_FUNC_CNTL_2;
74 uint32_t vMPLL_AD_FUNC_CNTL;
75 uint32_t vMPLL_AD_FUNC_CNTL_2;
76 uint32_t vMPLL_DQ_FUNC_CNTL;
77 uint32_t vMPLL_DQ_FUNC_CNTL_2;
78 uint32_t vMCLK_PWRMGT_CNTL;
85 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE;
87 struct NISLANDS_SMC_VOLTAGE_VALUE
94 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE;
96 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL
100 uint8_t displayWatermark;
108 NISLANDS_SMC_SCLK_VALUE sclk;
109 NISLANDS_SMC_MCLK_VALUE mclk;
110 NISLANDS_SMC_VOLTAGE_VALUE vddc;
111 NISLANDS_SMC_VOLTAGE_VALUE mvdd;
112 NISLANDS_SMC_VOLTAGE_VALUE vddci;
113 NISLANDS_SMC_VOLTAGE_VALUE std_vddc;
114 uint32_t powergate_en;
118 uint8_t arbRefreshState;
119 uint32_t SQPowerThrottle;
120 uint32_t SQPowerThrottle_2;
121 uint32_t reserved[2];
122 PP_NIslands_Dpm2PerfLevel dpm2;
125 #define NISLANDS_SMC_STROBE_RATIO 0x0F
126 #define NISLANDS_SMC_STROBE_ENABLE 0x10
128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
133 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL;
135 struct NISLANDS_SMC_SWSTATE
141 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1];
144 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE;
146 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
147 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1
148 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2
149 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4
151 struct NISLANDS_SMC_VOLTAGEMASKTABLE
153 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
154 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];
157 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE;
159 #define NISLANDS_MAX_NO_VREG_STEPS 32
161 struct NISLANDS_SMC_STATETABLE
163 uint8_t thermalProtectType;
165 uint8_t maxVDDCIndexInPPTable;
167 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS];
168 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];
169 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable;
170 PP_NIslands_DPM2Parameters dpm2Params;
171 NISLANDS_SMC_SWSTATE initialState;
172 NISLANDS_SMC_SWSTATE ACPIState;
173 NISLANDS_SMC_SWSTATE ULVState;
174 NISLANDS_SMC_SWSTATE driverState;
175 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
178 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE;
180 #define NI_SMC_SOFT_REGISTERS_START 0x108
182 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
183 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
184 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10
185 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C
186 #define NI_SMC_SOFT_REGISTER_seq_index 0x64
187 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
188 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
189 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80
190 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84
191 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98
193 #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16
194 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
195 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
196 #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4
198 struct SMC_NISLANDS_MC_TPP_CAC_TABLE
200 uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
201 uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];
204 typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE;
207 struct PP_NIslands_CACTABLES
209 uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];
210 uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
214 uint32_t dc_cacValue;
215 uint32_t bif_cacValue;
219 uint8_t window_size_p2;
221 uint8_t num_drop_lsb;
229 uint8_t padding_1[9];
231 uint8_t enableWinAvg;
233 uint8_t l2numWin_TDP;
236 uint32_t dynPwr_TDP[4];
237 uint32_t lkgePwr_TDP[4];
238 uint32_t power_TDP[4];
239 uint32_t avg_dynPwr_TDP;
240 uint32_t avg_lkgePwr_TDP;
241 uint32_t avg_power_TDP;
242 uint32_t lts_power_TDP;
243 uint8_t lts_truncate_n;
244 uint8_t padding_2[7];
247 typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES;
249 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32
250 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
252 struct SMC_NIslands_MCRegisterAddress
258 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress;
261 struct SMC_NIslands_MCRegisterSet
263 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
266 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet;
268 struct SMC_NIslands_MCRegisters
272 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
273 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
276 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters;
278 struct SMC_NIslands_MCArbDramTimingRegisterSet
280 uint32_t mc_arb_dram_timing;
281 uint32_t mc_arb_dram_timing2;
282 uint8_t mc_arb_rfsh_rate;
286 typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet;
288 struct SMC_NIslands_MCArbDramTimingRegisters
292 SMC_NIslands_MCArbDramTimingRegisterSet data[20];
295 typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters;
297 struct SMC_NISLANDS_SPLL_DIV_TABLE
303 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
304 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
305 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
306 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25
307 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
308 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
309 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
310 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20
312 typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE;
314 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100
316 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0
317 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
318 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8
319 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC
320 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10
321 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14
322 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20
323 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C
324 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30