2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
66 #include "r100_track.h"
68 /* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 * and others in some cases.
74 * r100_wait_for_vblank - vblank wait asic callback.
76 * @rdev: radeon_device pointer
77 * @crtc: crtc to wait for vblank on
79 * Wait for vblank on the requested crtc (r1xx-r4xx).
81 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
86 if (radeon_crtc->crtc_id == 0) {
87 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
100 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
101 for (i = 0; i < rdev->usec_timeout; i++) {
102 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
106 for (i = 0; i < rdev->usec_timeout; i++) {
107 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
116 * r100_pre_page_flip - pre-pageflip callback.
118 * @rdev: radeon_device pointer
119 * @crtc: crtc to prepare for pageflip on
121 * Pre-pageflip callback (r1xx-r4xx).
122 * Enables the pageflip irq (vblank irq).
124 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
126 /* enable the pflip int */
127 radeon_irq_kms_pflip_irq_get(rdev, crtc);
131 * r100_post_page_flip - pos-pageflip callback.
133 * @rdev: radeon_device pointer
134 * @crtc: crtc to cleanup pageflip on
136 * Post-pageflip callback (r1xx-r4xx).
137 * Disables the pageflip irq (vblank irq).
139 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
141 /* disable the pflip int */
142 radeon_irq_kms_pflip_irq_put(rdev, crtc);
146 * r100_page_flip - pageflip callback.
148 * @rdev: radeon_device pointer
149 * @crtc_id: crtc to cleanup pageflip on
150 * @crtc_base: new address of the crtc (GPU MC address)
152 * Does the actual pageflip (r1xx-r4xx).
153 * During vblank we take the crtc lock and wait for the update_pending
154 * bit to go high, when it does, we release the lock, and allow the
155 * double buffered update to take place.
156 * Returns the current update pending status.
158 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
160 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
161 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
164 /* Lock the graphics update lock */
165 /* update the scanout addresses */
166 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
168 /* Wait for update_pending to go high. */
169 for (i = 0; i < rdev->usec_timeout; i++) {
170 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
174 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
176 /* Unlock the lock, so double-buffering can take place inside vblank */
177 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
178 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
180 /* Return current update_pending status: */
181 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
185 * r100_pm_get_dynpm_state - look up dynpm power state callback.
187 * @rdev: radeon_device pointer
189 * Look up the optimal power state based on the
190 * current state of the GPU (r1xx-r5xx).
191 * Used for dynpm only.
193 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
196 rdev->pm.dynpm_can_upclock = true;
197 rdev->pm.dynpm_can_downclock = true;
199 switch (rdev->pm.dynpm_planned_action) {
200 case DYNPM_ACTION_MINIMUM:
201 rdev->pm.requested_power_state_index = 0;
202 rdev->pm.dynpm_can_downclock = false;
204 case DYNPM_ACTION_DOWNCLOCK:
205 if (rdev->pm.current_power_state_index == 0) {
206 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
207 rdev->pm.dynpm_can_downclock = false;
209 if (rdev->pm.active_crtc_count > 1) {
210 for (i = 0; i < rdev->pm.num_power_states; i++) {
211 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
213 else if (i >= rdev->pm.current_power_state_index) {
214 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
217 rdev->pm.requested_power_state_index = i;
222 rdev->pm.requested_power_state_index =
223 rdev->pm.current_power_state_index - 1;
225 /* don't use the power state if crtcs are active and no display flag is set */
226 if ((rdev->pm.active_crtc_count > 0) &&
227 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
228 RADEON_PM_MODE_NO_DISPLAY)) {
229 rdev->pm.requested_power_state_index++;
232 case DYNPM_ACTION_UPCLOCK:
233 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
234 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
235 rdev->pm.dynpm_can_upclock = false;
237 if (rdev->pm.active_crtc_count > 1) {
238 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
239 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
241 else if (i <= rdev->pm.current_power_state_index) {
242 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
245 rdev->pm.requested_power_state_index = i;
250 rdev->pm.requested_power_state_index =
251 rdev->pm.current_power_state_index + 1;
254 case DYNPM_ACTION_DEFAULT:
255 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
256 rdev->pm.dynpm_can_upclock = false;
258 case DYNPM_ACTION_NONE:
260 DRM_ERROR("Requested mode for not defined action\n");
263 /* only one clock mode per power state */
264 rdev->pm.requested_clock_mode_index = 0;
266 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].
268 clock_info[rdev->pm.requested_clock_mode_index].sclk,
269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].mclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
276 * r100_pm_init_profile - Initialize power profiles callback.
278 * @rdev: radeon_device pointer
280 * Initialize the power states used in profile mode
282 * Used for profile mode only.
284 void r100_pm_init_profile(struct radeon_device *rdev)
287 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
289 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
290 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
304 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
309 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
324 * r100_pm_misc - set additional pm hw parameters callback.
326 * @rdev: radeon_device pointer
328 * Set non-clock parameters associated with a power state
329 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
331 void r100_pm_misc(struct radeon_device *rdev)
333 int requested_index = rdev->pm.requested_power_state_index;
334 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
335 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
336 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
338 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
339 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
340 tmp = RREG32(voltage->gpio.reg);
341 if (voltage->active_high)
342 tmp |= voltage->gpio.mask;
344 tmp &= ~(voltage->gpio.mask);
345 WREG32(voltage->gpio.reg, tmp);
347 udelay(voltage->delay);
349 tmp = RREG32(voltage->gpio.reg);
350 if (voltage->active_high)
351 tmp &= ~voltage->gpio.mask;
353 tmp |= voltage->gpio.mask;
354 WREG32(voltage->gpio.reg, tmp);
356 udelay(voltage->delay);
360 sclk_cntl = RREG32_PLL(SCLK_CNTL);
361 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
362 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
363 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
364 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
365 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
366 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
367 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
368 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
370 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
371 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
372 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
373 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
376 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
378 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
379 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
380 if (voltage->delay) {
381 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
382 switch (voltage->delay) {
384 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
387 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
390 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
393 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
397 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
399 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
401 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
402 sclk_cntl &= ~FORCE_HDP;
404 sclk_cntl |= FORCE_HDP;
406 WREG32_PLL(SCLK_CNTL, sclk_cntl);
407 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
408 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
411 if ((rdev->flags & RADEON_IS_PCIE) &&
412 !(rdev->flags & RADEON_IS_IGP) &&
413 rdev->asic->pm.set_pcie_lanes &&
415 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
416 radeon_set_pcie_lanes(rdev,
418 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
423 * r100_pm_prepare - pre-power state change callback.
425 * @rdev: radeon_device pointer
427 * Prepare for a power state change (r1xx-r4xx).
429 void r100_pm_prepare(struct radeon_device *rdev)
431 struct drm_device *ddev = rdev->ddev;
432 struct drm_crtc *crtc;
433 struct radeon_crtc *radeon_crtc;
436 /* disable any active CRTCs */
437 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
438 radeon_crtc = to_radeon_crtc(crtc);
439 if (radeon_crtc->enabled) {
440 if (radeon_crtc->crtc_id) {
441 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
442 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
443 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
445 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
446 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
447 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
454 * r100_pm_finish - post-power state change callback.
456 * @rdev: radeon_device pointer
458 * Clean up after a power state change (r1xx-r4xx).
460 void r100_pm_finish(struct radeon_device *rdev)
462 struct drm_device *ddev = rdev->ddev;
463 struct drm_crtc *crtc;
464 struct radeon_crtc *radeon_crtc;
467 /* enable any active CRTCs */
468 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
469 radeon_crtc = to_radeon_crtc(crtc);
470 if (radeon_crtc->enabled) {
471 if (radeon_crtc->crtc_id) {
472 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
473 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
474 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
476 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
477 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
478 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
485 * r100_gui_idle - gui idle callback.
487 * @rdev: radeon_device pointer
489 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
490 * Returns true if idle, false if not.
492 bool r100_gui_idle(struct radeon_device *rdev)
494 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
500 /* hpd for digital panel detect/disconnect */
502 * r100_hpd_sense - hpd sense callback.
504 * @rdev: radeon_device pointer
505 * @hpd: hpd (hotplug detect) pin
507 * Checks if a digital monitor is connected (r1xx-r4xx).
508 * Returns true if connected, false if not connected.
510 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
512 bool connected = false;
516 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
520 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 * r100_hpd_set_polarity - hpd set polarity callback.
532 * @rdev: radeon_device pointer
533 * @hpd: hpd (hotplug detect) pin
535 * Set the polarity of the hpd pin (r1xx-r4xx).
537 void r100_hpd_set_polarity(struct radeon_device *rdev,
538 enum radeon_hpd_id hpd)
541 bool connected = r100_hpd_sense(rdev, hpd);
545 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 tmp |= RADEON_FP_DETECT_INT_POL;
550 WREG32(RADEON_FP_GEN_CNTL, tmp);
553 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 tmp |= RADEON_FP2_DETECT_INT_POL;
558 WREG32(RADEON_FP2_GEN_CNTL, tmp);
566 * r100_hpd_init - hpd setup callback.
568 * @rdev: radeon_device pointer
570 * Setup the hpd pins used by the card (r1xx-r4xx).
571 * Set the polarity, and enable the hpd interrupts.
573 void r100_hpd_init(struct radeon_device *rdev)
575 struct drm_device *dev = rdev->ddev;
576 struct drm_connector *connector;
579 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
580 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
581 enable |= 1 << radeon_connector->hpd.hpd;
582 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
584 radeon_irq_kms_enable_hpd(rdev, enable);
588 * r100_hpd_fini - hpd tear down callback.
590 * @rdev: radeon_device pointer
592 * Tear down the hpd pins used by the card (r1xx-r4xx).
593 * Disable the hpd interrupts.
595 void r100_hpd_fini(struct radeon_device *rdev)
597 struct drm_device *dev = rdev->ddev;
598 struct drm_connector *connector;
599 unsigned disable = 0;
601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
602 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
603 disable |= 1 << radeon_connector->hpd.hpd;
605 radeon_irq_kms_disable_hpd(rdev, disable);
611 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613 /* TODO: can we do somethings here ? */
614 /* It seems hw only cache one entry so we should discard this
615 * entry otherwise if first GPU GART read hit this entry it
616 * could end up in wrong address. */
619 int r100_pci_gart_init(struct radeon_device *rdev)
623 if (rdev->gart.ptr) {
624 WARN(1, "R100 PCI GART already initialized\n");
627 /* Initialize common gart structure */
628 r = radeon_gart_init(rdev);
631 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
632 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
633 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
634 return radeon_gart_table_ram_alloc(rdev);
637 int r100_pci_gart_enable(struct radeon_device *rdev)
641 radeon_gart_restore(rdev);
642 /* discard memory request outside of configured range */
643 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
644 WREG32(RADEON_AIC_CNTL, tmp);
645 /* set address range for PCI address translate */
646 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
647 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
648 /* set PCI GART page-table base address */
649 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
650 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
651 WREG32(RADEON_AIC_CNTL, tmp);
652 r100_pci_gart_tlb_flush(rdev);
653 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
654 (unsigned)(rdev->mc.gtt_size >> 20),
655 (unsigned long long)rdev->gart.table_addr);
656 rdev->gart.ready = true;
660 void r100_pci_gart_disable(struct radeon_device *rdev)
664 /* discard memory request outside of configured range */
665 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
666 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
667 WREG32(RADEON_AIC_LO_ADDR, 0);
668 WREG32(RADEON_AIC_HI_ADDR, 0);
671 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
673 u32 *gtt = rdev->gart.ptr;
675 if (i < 0 || i > rdev->gart.num_gpu_pages) {
678 gtt[i] = cpu_to_le32(lower_32_bits(addr));
682 void r100_pci_gart_fini(struct radeon_device *rdev)
684 radeon_gart_fini(rdev);
685 r100_pci_gart_disable(rdev);
686 radeon_gart_table_ram_free(rdev);
689 int r100_irq_set(struct radeon_device *rdev)
693 if (!rdev->irq.installed) {
694 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
695 WREG32(R_000040_GEN_INT_CNTL, 0);
698 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
699 tmp |= RADEON_SW_INT_ENABLE;
701 if (rdev->irq.gui_idle) {
702 tmp |= RADEON_GUI_IDLE_MASK;
704 if (rdev->irq.crtc_vblank_int[0] ||
705 atomic_read(&rdev->irq.pflip[0])) {
706 tmp |= RADEON_CRTC_VBLANK_MASK;
708 if (rdev->irq.crtc_vblank_int[1] ||
709 atomic_read(&rdev->irq.pflip[1])) {
710 tmp |= RADEON_CRTC2_VBLANK_MASK;
712 if (rdev->irq.hpd[0]) {
713 tmp |= RADEON_FP_DETECT_MASK;
715 if (rdev->irq.hpd[1]) {
716 tmp |= RADEON_FP2_DETECT_MASK;
718 WREG32(RADEON_GEN_INT_CNTL, tmp);
722 void r100_irq_disable(struct radeon_device *rdev)
726 WREG32(R_000040_GEN_INT_CNTL, 0);
727 /* Wait and acknowledge irq */
729 tmp = RREG32(R_000044_GEN_INT_STATUS);
730 WREG32(R_000044_GEN_INT_STATUS, tmp);
733 static uint32_t r100_irq_ack(struct radeon_device *rdev)
735 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
736 uint32_t irq_mask = RADEON_SW_INT_TEST |
737 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
738 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
740 /* the interrupt works, but the status bit is permanently asserted */
741 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
742 if (!rdev->irq.gui_idle_acked)
743 irq_mask |= RADEON_GUI_IDLE_STAT;
747 WREG32(RADEON_GEN_INT_STATUS, irqs);
749 return irqs & irq_mask;
752 int r100_irq_process(struct radeon_device *rdev)
754 uint32_t status, msi_rearm;
755 bool queue_hotplug = false;
757 /* reset gui idle ack. the status bit is broken */
758 rdev->irq.gui_idle_acked = false;
760 status = r100_irq_ack(rdev);
764 if (rdev->shutdown) {
769 if (status & RADEON_SW_INT_TEST) {
770 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
772 /* gui idle interrupt */
773 if (status & RADEON_GUI_IDLE_STAT) {
774 rdev->irq.gui_idle_acked = true;
775 wake_up(&rdev->irq.idle_queue);
777 /* Vertical blank interrupts */
778 if (status & RADEON_CRTC_VBLANK_STAT) {
779 if (rdev->irq.crtc_vblank_int[0]) {
780 drm_handle_vblank(rdev->ddev, 0);
781 rdev->pm.vblank_sync = true;
782 wake_up(&rdev->irq.vblank_queue);
784 if (atomic_read(&rdev->irq.pflip[0]))
785 radeon_crtc_handle_flip(rdev, 0);
787 if (status & RADEON_CRTC2_VBLANK_STAT) {
788 if (rdev->irq.crtc_vblank_int[1]) {
789 drm_handle_vblank(rdev->ddev, 1);
790 rdev->pm.vblank_sync = true;
791 wake_up(&rdev->irq.vblank_queue);
793 if (atomic_read(&rdev->irq.pflip[1]))
794 radeon_crtc_handle_flip(rdev, 1);
796 if (status & RADEON_FP_DETECT_STAT) {
797 queue_hotplug = true;
800 if (status & RADEON_FP2_DETECT_STAT) {
801 queue_hotplug = true;
804 status = r100_irq_ack(rdev);
806 /* reset gui idle ack. the status bit is broken */
807 rdev->irq.gui_idle_acked = false;
809 schedule_work(&rdev->hotplug_work);
810 if (rdev->msi_enabled) {
811 switch (rdev->family) {
814 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
815 WREG32(RADEON_AIC_CNTL, msi_rearm);
816 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
819 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
826 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
829 return RREG32(RADEON_CRTC_CRNT_FRAME);
831 return RREG32(RADEON_CRTC2_CRNT_FRAME);
834 /* Who ever call radeon_fence_emit should call ring_lock and ask
835 * for enough space (today caller are ib schedule and buffer move) */
836 void r100_fence_ring_emit(struct radeon_device *rdev,
837 struct radeon_fence *fence)
839 struct radeon_ring *ring = &rdev->ring[fence->ring];
841 /* We have to make sure that caches are flushed before
842 * CPU might read something from VRAM. */
843 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
844 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
845 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
846 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
847 /* Wait until IDLE & CLEAN */
848 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
849 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
850 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
851 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
852 RADEON_HDP_READ_BUFFER_INVALIDATE);
853 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
854 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
855 /* Emit fence sequence & fire IRQ */
856 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
857 radeon_ring_write(ring, fence->seq);
858 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
859 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
862 void r100_semaphore_ring_emit(struct radeon_device *rdev,
863 struct radeon_ring *ring,
864 struct radeon_semaphore *semaphore,
867 /* Unused on older asics, since we don't have semaphores or multiple rings */
871 int r100_copy_blit(struct radeon_device *rdev,
874 unsigned num_gpu_pages,
875 struct radeon_fence **fence)
877 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
879 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
881 uint32_t stride_pixels;
886 /* radeon limited to 16k stride */
887 stride_bytes &= 0x3fff;
888 /* radeon pitch is /64 */
889 pitch = stride_bytes / 64;
890 stride_pixels = stride_bytes / 4;
891 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
893 /* Ask for enough room for blit + flush + fence */
894 ndw = 64 + (10 * num_loops);
895 r = radeon_ring_lock(rdev, ring, ndw);
897 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
900 while (num_gpu_pages > 0) {
901 cur_pages = num_gpu_pages;
902 if (cur_pages > 8191) {
905 num_gpu_pages -= cur_pages;
907 /* pages are in Y direction - height
908 page width in X direction - width */
909 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
910 radeon_ring_write(ring,
911 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
912 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
913 RADEON_GMC_SRC_CLIPPING |
914 RADEON_GMC_DST_CLIPPING |
915 RADEON_GMC_BRUSH_NONE |
916 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
917 RADEON_GMC_SRC_DATATYPE_COLOR |
919 RADEON_DP_SRC_SOURCE_MEMORY |
920 RADEON_GMC_CLR_CMP_CNTL_DIS |
921 RADEON_GMC_WR_MSK_DIS);
922 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
923 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
924 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
925 radeon_ring_write(ring, 0);
926 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
927 radeon_ring_write(ring, num_gpu_pages);
928 radeon_ring_write(ring, num_gpu_pages);
929 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
931 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
932 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
933 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
934 radeon_ring_write(ring,
935 RADEON_WAIT_2D_IDLECLEAN |
936 RADEON_WAIT_HOST_IDLECLEAN |
937 RADEON_WAIT_DMA_GUI_IDLE);
939 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
941 radeon_ring_unlock_commit(rdev, ring);
945 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
950 for (i = 0; i < rdev->usec_timeout; i++) {
951 tmp = RREG32(R_000E40_RBBM_STATUS);
952 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
960 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
964 r = radeon_ring_lock(rdev, ring, 2);
968 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
969 radeon_ring_write(ring,
970 RADEON_ISYNC_ANY2D_IDLE3D |
971 RADEON_ISYNC_ANY3D_IDLE2D |
972 RADEON_ISYNC_WAIT_IDLEGUI |
973 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
974 radeon_ring_unlock_commit(rdev, ring);
978 /* Load the microcode for the CP */
979 static int r100_cp_init_microcode(struct radeon_device *rdev)
981 struct platform_device *pdev;
982 const char *fw_name = NULL;
987 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
990 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
993 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
994 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
995 (rdev->family == CHIP_RS200)) {
996 DRM_INFO("Loading R100 Microcode\n");
997 fw_name = FIRMWARE_R100;
998 } else if ((rdev->family == CHIP_R200) ||
999 (rdev->family == CHIP_RV250) ||
1000 (rdev->family == CHIP_RV280) ||
1001 (rdev->family == CHIP_RS300)) {
1002 DRM_INFO("Loading R200 Microcode\n");
1003 fw_name = FIRMWARE_R200;
1004 } else if ((rdev->family == CHIP_R300) ||
1005 (rdev->family == CHIP_R350) ||
1006 (rdev->family == CHIP_RV350) ||
1007 (rdev->family == CHIP_RV380) ||
1008 (rdev->family == CHIP_RS400) ||
1009 (rdev->family == CHIP_RS480)) {
1010 DRM_INFO("Loading R300 Microcode\n");
1011 fw_name = FIRMWARE_R300;
1012 } else if ((rdev->family == CHIP_R420) ||
1013 (rdev->family == CHIP_R423) ||
1014 (rdev->family == CHIP_RV410)) {
1015 DRM_INFO("Loading R400 Microcode\n");
1016 fw_name = FIRMWARE_R420;
1017 } else if ((rdev->family == CHIP_RS690) ||
1018 (rdev->family == CHIP_RS740)) {
1019 DRM_INFO("Loading RS690/RS740 Microcode\n");
1020 fw_name = FIRMWARE_RS690;
1021 } else if (rdev->family == CHIP_RS600) {
1022 DRM_INFO("Loading RS600 Microcode\n");
1023 fw_name = FIRMWARE_RS600;
1024 } else if ((rdev->family == CHIP_RV515) ||
1025 (rdev->family == CHIP_R520) ||
1026 (rdev->family == CHIP_RV530) ||
1027 (rdev->family == CHIP_R580) ||
1028 (rdev->family == CHIP_RV560) ||
1029 (rdev->family == CHIP_RV570)) {
1030 DRM_INFO("Loading R500 Microcode\n");
1031 fw_name = FIRMWARE_R520;
1034 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1035 platform_device_unregister(pdev);
1037 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1039 } else if (rdev->me_fw->size % 8) {
1041 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1042 rdev->me_fw->size, fw_name);
1044 release_firmware(rdev->me_fw);
1050 static void r100_cp_load_microcode(struct radeon_device *rdev)
1052 const __be32 *fw_data;
1055 if (r100_gui_wait_for_idle(rdev)) {
1056 printk(KERN_WARNING "Failed to wait GUI idle while "
1057 "programming pipes. Bad things might happen.\n");
1061 size = rdev->me_fw->size / 4;
1062 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1063 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1064 for (i = 0; i < size; i += 2) {
1065 WREG32(RADEON_CP_ME_RAM_DATAH,
1066 be32_to_cpup(&fw_data[i]));
1067 WREG32(RADEON_CP_ME_RAM_DATAL,
1068 be32_to_cpup(&fw_data[i + 1]));
1073 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1075 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1079 unsigned pre_write_timer;
1080 unsigned pre_write_limit;
1081 unsigned indirect2_start;
1082 unsigned indirect1_start;
1086 if (r100_debugfs_cp_init(rdev)) {
1087 DRM_ERROR("Failed to register debugfs file for CP !\n");
1090 r = r100_cp_init_microcode(rdev);
1092 DRM_ERROR("Failed to load firmware!\n");
1097 /* Align ring size */
1098 rb_bufsz = drm_order(ring_size / 8);
1099 ring_size = (1 << (rb_bufsz + 1)) * 4;
1100 r100_cp_load_microcode(rdev);
1101 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1102 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1103 0, 0x7fffff, RADEON_CP_PACKET2);
1107 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1108 * the rptr copy in system ram */
1110 /* cp will read 128bytes at a time (4 dwords) */
1112 ring->align_mask = 16 - 1;
1113 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1114 pre_write_timer = 64;
1115 /* Force CP_RB_WPTR write if written more than one time before the
1118 pre_write_limit = 0;
1119 /* Setup the cp cache like this (cache size is 96 dwords) :
1121 * INDIRECT1 16 to 79
1122 * INDIRECT2 80 to 95
1123 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1124 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1125 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126 * Idea being that most of the gpu cmd will be through indirect1 buffer
1127 * so it gets the bigger cache.
1129 indirect2_start = 80;
1130 indirect1_start = 16;
1132 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1133 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1134 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1135 REG_SET(RADEON_MAX_FETCH, max_fetch));
1137 tmp |= RADEON_BUF_SWAP_32BIT;
1139 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1141 /* Set ring address */
1142 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1143 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1144 /* Force read & write ptr to 0 */
1145 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1146 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1148 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1150 /* set the wb address whether it's enabled or not */
1151 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1152 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1153 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1155 if (rdev->wb.enabled)
1156 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1158 tmp |= RADEON_RB_NO_UPDATE;
1159 WREG32(R_000770_SCRATCH_UMSK, 0);
1162 WREG32(RADEON_CP_RB_CNTL, tmp);
1164 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1165 /* Set cp mode to bus mastering & enable cp*/
1166 WREG32(RADEON_CP_CSQ_MODE,
1167 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1168 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1169 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1170 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1171 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1173 /* at this point everything should be setup correctly to enable master */
1174 pci_set_master(rdev->pdev);
1176 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1177 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1179 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1183 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1185 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
1186 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1188 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1189 ring->rptr_save_reg = 0;
1195 void r100_cp_fini(struct radeon_device *rdev)
1197 if (r100_cp_wait_for_idle(rdev)) {
1198 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1201 r100_cp_disable(rdev);
1202 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1203 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1204 DRM_INFO("radeon: cp finalized\n");
1207 void r100_cp_disable(struct radeon_device *rdev)
1210 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1211 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1212 WREG32(RADEON_CP_CSQ_MODE, 0);
1213 WREG32(RADEON_CP_CSQ_CNTL, 0);
1214 WREG32(R_000770_SCRATCH_UMSK, 0);
1215 if (r100_gui_wait_for_idle(rdev)) {
1216 printk(KERN_WARNING "Failed to wait GUI idle while "
1217 "programming pipes. Bad things might happen.\n");
1224 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1225 struct radeon_cs_packet *pkt,
1232 struct radeon_cs_reloc *reloc;
1235 r = r100_cs_packet_next_reloc(p, &reloc);
1237 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1239 r100_cs_dump_packet(p, pkt);
1243 value = radeon_get_ib_value(p, idx);
1244 tmp = value & 0x003fffff;
1245 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1247 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1248 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1249 tile_flags |= RADEON_DST_TILE_MACRO;
1250 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1251 if (reg == RADEON_SRC_PITCH_OFFSET) {
1252 DRM_ERROR("Cannot src blit from microtiled surface\n");
1253 r100_cs_dump_packet(p, pkt);
1256 tile_flags |= RADEON_DST_TILE_MICRO;
1260 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1262 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1266 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1267 struct radeon_cs_packet *pkt,
1271 struct radeon_cs_reloc *reloc;
1272 struct r100_cs_track *track;
1274 volatile uint32_t *ib;
1278 track = (struct r100_cs_track *)p->track;
1279 c = radeon_get_ib_value(p, idx++) & 0x1F;
1281 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1283 r100_cs_dump_packet(p, pkt);
1286 track->num_arrays = c;
1287 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1288 r = r100_cs_packet_next_reloc(p, &reloc);
1290 DRM_ERROR("No reloc for packet3 %d\n",
1292 r100_cs_dump_packet(p, pkt);
1295 idx_value = radeon_get_ib_value(p, idx);
1296 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1298 track->arrays[i + 0].esize = idx_value >> 8;
1299 track->arrays[i + 0].robj = reloc->robj;
1300 track->arrays[i + 0].esize &= 0x7F;
1301 r = r100_cs_packet_next_reloc(p, &reloc);
1303 DRM_ERROR("No reloc for packet3 %d\n",
1305 r100_cs_dump_packet(p, pkt);
1308 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1309 track->arrays[i + 1].robj = reloc->robj;
1310 track->arrays[i + 1].esize = idx_value >> 24;
1311 track->arrays[i + 1].esize &= 0x7F;
1314 r = r100_cs_packet_next_reloc(p, &reloc);
1316 DRM_ERROR("No reloc for packet3 %d\n",
1318 r100_cs_dump_packet(p, pkt);
1321 idx_value = radeon_get_ib_value(p, idx);
1322 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1323 track->arrays[i + 0].robj = reloc->robj;
1324 track->arrays[i + 0].esize = idx_value >> 8;
1325 track->arrays[i + 0].esize &= 0x7F;
1330 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1331 struct radeon_cs_packet *pkt,
1332 const unsigned *auth, unsigned n,
1333 radeon_packet0_check_t check)
1342 /* Check that register fall into register range
1343 * determined by the number of entry (n) in the
1344 * safe register bitmap.
1346 if (pkt->one_reg_wr) {
1347 if ((reg >> 7) > n) {
1351 if (((reg + (pkt->count << 2)) >> 7) > n) {
1355 for (i = 0; i <= pkt->count; i++, idx++) {
1357 m = 1 << ((reg >> 2) & 31);
1359 r = check(p, pkt, idx, reg);
1364 if (pkt->one_reg_wr) {
1365 if (!(auth[j] & m)) {
1375 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1376 struct radeon_cs_packet *pkt)
1378 volatile uint32_t *ib;
1384 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1385 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1390 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1391 * @parser: parser structure holding parsing context.
1392 * @pkt: where to store packet informations
1394 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1395 * if packet is bigger than remaining ib size. or if packets is unknown.
1397 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1398 struct radeon_cs_packet *pkt,
1401 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1404 if (idx >= ib_chunk->length_dw) {
1405 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1406 idx, ib_chunk->length_dw);
1409 header = radeon_get_ib_value(p, idx);
1411 pkt->type = CP_PACKET_GET_TYPE(header);
1412 pkt->count = CP_PACKET_GET_COUNT(header);
1413 switch (pkt->type) {
1415 pkt->reg = CP_PACKET0_GET_REG(header);
1416 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1419 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1425 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1428 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1429 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1430 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1437 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1438 * @parser: parser structure holding parsing context.
1440 * Userspace sends a special sequence for VLINE waits.
1441 * PACKET0 - VLINE_START_END + value
1442 * PACKET0 - WAIT_UNTIL +_value
1443 * RELOC (P3) - crtc_id in reloc.
1445 * This function parses this and relocates the VLINE START END
1446 * and WAIT UNTIL packets to the correct crtc.
1447 * It also detects a switched off crtc and nulls out the
1448 * wait in that case.
1450 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1452 struct drm_mode_object *obj;
1453 struct drm_crtc *crtc;
1454 struct radeon_crtc *radeon_crtc;
1455 struct radeon_cs_packet p3reloc, waitreloc;
1458 uint32_t header, h_idx, reg;
1459 volatile uint32_t *ib;
1463 /* parse the wait until */
1464 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1468 /* check its a wait until and only 1 count */
1469 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1470 waitreloc.count != 0) {
1471 DRM_ERROR("vline wait had illegal wait until segment\n");
1475 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1476 DRM_ERROR("vline wait had illegal wait until\n");
1480 /* jump over the NOP */
1481 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1486 p->idx += waitreloc.count + 2;
1487 p->idx += p3reloc.count + 2;
1489 header = radeon_get_ib_value(p, h_idx);
1490 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1491 reg = CP_PACKET0_GET_REG(header);
1492 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1494 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1497 crtc = obj_to_crtc(obj);
1498 radeon_crtc = to_radeon_crtc(crtc);
1499 crtc_id = radeon_crtc->crtc_id;
1501 if (!crtc->enabled) {
1502 /* if the CRTC isn't enabled - we need to nop out the wait until */
1503 ib[h_idx + 2] = PACKET2(0);
1504 ib[h_idx + 3] = PACKET2(0);
1505 } else if (crtc_id == 1) {
1507 case AVIVO_D1MODE_VLINE_START_END:
1508 header &= ~R300_CP_PACKET0_REG_MASK;
1509 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1511 case RADEON_CRTC_GUI_TRIG_VLINE:
1512 header &= ~R300_CP_PACKET0_REG_MASK;
1513 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1516 DRM_ERROR("unknown crtc reloc\n");
1520 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1527 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1528 * @parser: parser structure holding parsing context.
1529 * @data: pointer to relocation data
1530 * @offset_start: starting offset
1531 * @offset_mask: offset mask (to align start offset on)
1532 * @reloc: reloc informations
1534 * Check next packet is relocation packet3, do bo validation and compute
1535 * GPU offset using the provided start.
1537 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1538 struct radeon_cs_reloc **cs_reloc)
1540 struct radeon_cs_chunk *relocs_chunk;
1541 struct radeon_cs_packet p3reloc;
1545 if (p->chunk_relocs_idx == -1) {
1546 DRM_ERROR("No relocation chunk !\n");
1550 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1551 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1555 p->idx += p3reloc.count + 2;
1556 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1557 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1559 r100_cs_dump_packet(p, &p3reloc);
1562 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1563 if (idx >= relocs_chunk->length_dw) {
1564 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1565 idx, relocs_chunk->length_dw);
1566 r100_cs_dump_packet(p, &p3reloc);
1569 /* FIXME: we assume reloc size is 4 dwords */
1570 *cs_reloc = p->relocs_ptr[(idx / 4)];
1574 static int r100_get_vtx_size(uint32_t vtx_fmt)
1578 /* ordered according to bits in spec */
1579 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1581 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1583 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1585 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1587 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1589 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1591 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1593 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1595 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1597 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1599 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1601 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1603 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1605 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1607 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1610 if (vtx_fmt & (0x7 << 15))
1611 vtx_size += (vtx_fmt >> 15) & 0x7;
1612 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1614 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1616 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1618 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1620 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1622 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1627 static int r100_packet0_check(struct radeon_cs_parser *p,
1628 struct radeon_cs_packet *pkt,
1629 unsigned idx, unsigned reg)
1631 struct radeon_cs_reloc *reloc;
1632 struct r100_cs_track *track;
1633 volatile uint32_t *ib;
1641 track = (struct r100_cs_track *)p->track;
1643 idx_value = radeon_get_ib_value(p, idx);
1646 case RADEON_CRTC_GUI_TRIG_VLINE:
1647 r = r100_cs_packet_parse_vline(p);
1649 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1651 r100_cs_dump_packet(p, pkt);
1655 /* FIXME: only allow PACKET3 blit? easier to check for out of
1657 case RADEON_DST_PITCH_OFFSET:
1658 case RADEON_SRC_PITCH_OFFSET:
1659 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1663 case RADEON_RB3D_DEPTHOFFSET:
1664 r = r100_cs_packet_next_reloc(p, &reloc);
1666 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1668 r100_cs_dump_packet(p, pkt);
1671 track->zb.robj = reloc->robj;
1672 track->zb.offset = idx_value;
1673 track->zb_dirty = true;
1674 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1676 case RADEON_RB3D_COLOROFFSET:
1677 r = r100_cs_packet_next_reloc(p, &reloc);
1679 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1681 r100_cs_dump_packet(p, pkt);
1684 track->cb[0].robj = reloc->robj;
1685 track->cb[0].offset = idx_value;
1686 track->cb_dirty = true;
1687 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1689 case RADEON_PP_TXOFFSET_0:
1690 case RADEON_PP_TXOFFSET_1:
1691 case RADEON_PP_TXOFFSET_2:
1692 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1693 r = r100_cs_packet_next_reloc(p, &reloc);
1695 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1697 r100_cs_dump_packet(p, pkt);
1700 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1701 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1702 tile_flags |= RADEON_TXO_MACRO_TILE;
1703 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1704 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1706 tmp = idx_value & ~(0x7 << 2);
1708 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1710 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1711 track->textures[i].robj = reloc->robj;
1712 track->tex_dirty = true;
1714 case RADEON_PP_CUBIC_OFFSET_T0_0:
1715 case RADEON_PP_CUBIC_OFFSET_T0_1:
1716 case RADEON_PP_CUBIC_OFFSET_T0_2:
1717 case RADEON_PP_CUBIC_OFFSET_T0_3:
1718 case RADEON_PP_CUBIC_OFFSET_T0_4:
1719 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1720 r = r100_cs_packet_next_reloc(p, &reloc);
1722 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1724 r100_cs_dump_packet(p, pkt);
1727 track->textures[0].cube_info[i].offset = idx_value;
1728 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1729 track->textures[0].cube_info[i].robj = reloc->robj;
1730 track->tex_dirty = true;
1732 case RADEON_PP_CUBIC_OFFSET_T1_0:
1733 case RADEON_PP_CUBIC_OFFSET_T1_1:
1734 case RADEON_PP_CUBIC_OFFSET_T1_2:
1735 case RADEON_PP_CUBIC_OFFSET_T1_3:
1736 case RADEON_PP_CUBIC_OFFSET_T1_4:
1737 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1738 r = r100_cs_packet_next_reloc(p, &reloc);
1740 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1742 r100_cs_dump_packet(p, pkt);
1745 track->textures[1].cube_info[i].offset = idx_value;
1746 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1747 track->textures[1].cube_info[i].robj = reloc->robj;
1748 track->tex_dirty = true;
1750 case RADEON_PP_CUBIC_OFFSET_T2_0:
1751 case RADEON_PP_CUBIC_OFFSET_T2_1:
1752 case RADEON_PP_CUBIC_OFFSET_T2_2:
1753 case RADEON_PP_CUBIC_OFFSET_T2_3:
1754 case RADEON_PP_CUBIC_OFFSET_T2_4:
1755 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1756 r = r100_cs_packet_next_reloc(p, &reloc);
1758 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1760 r100_cs_dump_packet(p, pkt);
1763 track->textures[2].cube_info[i].offset = idx_value;
1764 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1765 track->textures[2].cube_info[i].robj = reloc->robj;
1766 track->tex_dirty = true;
1768 case RADEON_RE_WIDTH_HEIGHT:
1769 track->maxy = ((idx_value >> 16) & 0x7FF);
1770 track->cb_dirty = true;
1771 track->zb_dirty = true;
1773 case RADEON_RB3D_COLORPITCH:
1774 r = r100_cs_packet_next_reloc(p, &reloc);
1776 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1778 r100_cs_dump_packet(p, pkt);
1781 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1782 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1783 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1784 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1785 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1787 tmp = idx_value & ~(0x7 << 16);
1791 ib[idx] = idx_value;
1793 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1794 track->cb_dirty = true;
1796 case RADEON_RB3D_DEPTHPITCH:
1797 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1798 track->zb_dirty = true;
1800 case RADEON_RB3D_CNTL:
1801 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1807 track->cb[0].cpp = 1;
1812 track->cb[0].cpp = 2;
1815 track->cb[0].cpp = 4;
1818 DRM_ERROR("Invalid color buffer format (%d) !\n",
1819 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1822 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1823 track->cb_dirty = true;
1824 track->zb_dirty = true;
1826 case RADEON_RB3D_ZSTENCILCNTL:
1827 switch (idx_value & 0xf) {
1842 track->zb_dirty = true;
1844 case RADEON_RB3D_ZPASS_ADDR:
1845 r = r100_cs_packet_next_reloc(p, &reloc);
1847 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1849 r100_cs_dump_packet(p, pkt);
1852 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1854 case RADEON_PP_CNTL:
1856 uint32_t temp = idx_value >> 4;
1857 for (i = 0; i < track->num_texture; i++)
1858 track->textures[i].enabled = !!(temp & (1 << i));
1859 track->tex_dirty = true;
1862 case RADEON_SE_VF_CNTL:
1863 track->vap_vf_cntl = idx_value;
1865 case RADEON_SE_VTX_FMT:
1866 track->vtx_size = r100_get_vtx_size(idx_value);
1868 case RADEON_PP_TEX_SIZE_0:
1869 case RADEON_PP_TEX_SIZE_1:
1870 case RADEON_PP_TEX_SIZE_2:
1871 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1872 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1873 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1874 track->tex_dirty = true;
1876 case RADEON_PP_TEX_PITCH_0:
1877 case RADEON_PP_TEX_PITCH_1:
1878 case RADEON_PP_TEX_PITCH_2:
1879 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1880 track->textures[i].pitch = idx_value + 32;
1881 track->tex_dirty = true;
1883 case RADEON_PP_TXFILTER_0:
1884 case RADEON_PP_TXFILTER_1:
1885 case RADEON_PP_TXFILTER_2:
1886 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1887 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1888 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1889 tmp = (idx_value >> 23) & 0x7;
1890 if (tmp == 2 || tmp == 6)
1891 track->textures[i].roundup_w = false;
1892 tmp = (idx_value >> 27) & 0x7;
1893 if (tmp == 2 || tmp == 6)
1894 track->textures[i].roundup_h = false;
1895 track->tex_dirty = true;
1897 case RADEON_PP_TXFORMAT_0:
1898 case RADEON_PP_TXFORMAT_1:
1899 case RADEON_PP_TXFORMAT_2:
1900 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1901 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1902 track->textures[i].use_pitch = 1;
1904 track->textures[i].use_pitch = 0;
1905 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1906 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1908 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1909 track->textures[i].tex_coord_type = 2;
1910 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1911 case RADEON_TXFORMAT_I8:
1912 case RADEON_TXFORMAT_RGB332:
1913 case RADEON_TXFORMAT_Y8:
1914 track->textures[i].cpp = 1;
1915 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1917 case RADEON_TXFORMAT_AI88:
1918 case RADEON_TXFORMAT_ARGB1555:
1919 case RADEON_TXFORMAT_RGB565:
1920 case RADEON_TXFORMAT_ARGB4444:
1921 case RADEON_TXFORMAT_VYUY422:
1922 case RADEON_TXFORMAT_YVYU422:
1923 case RADEON_TXFORMAT_SHADOW16:
1924 case RADEON_TXFORMAT_LDUDV655:
1925 case RADEON_TXFORMAT_DUDV88:
1926 track->textures[i].cpp = 2;
1927 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1929 case RADEON_TXFORMAT_ARGB8888:
1930 case RADEON_TXFORMAT_RGBA8888:
1931 case RADEON_TXFORMAT_SHADOW32:
1932 case RADEON_TXFORMAT_LDUDUV8888:
1933 track->textures[i].cpp = 4;
1934 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1936 case RADEON_TXFORMAT_DXT1:
1937 track->textures[i].cpp = 1;
1938 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1940 case RADEON_TXFORMAT_DXT23:
1941 case RADEON_TXFORMAT_DXT45:
1942 track->textures[i].cpp = 1;
1943 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1946 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1947 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1948 track->tex_dirty = true;
1950 case RADEON_PP_CUBIC_FACES_0:
1951 case RADEON_PP_CUBIC_FACES_1:
1952 case RADEON_PP_CUBIC_FACES_2:
1954 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1955 for (face = 0; face < 4; face++) {
1956 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1957 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1959 track->tex_dirty = true;
1962 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1969 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1970 struct radeon_cs_packet *pkt,
1971 struct radeon_bo *robj)
1976 value = radeon_get_ib_value(p, idx + 2);
1977 if ((value + 1) > radeon_bo_size(robj)) {
1978 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1979 "(need %u have %lu) !\n",
1981 radeon_bo_size(robj));
1987 static int r100_packet3_check(struct radeon_cs_parser *p,
1988 struct radeon_cs_packet *pkt)
1990 struct radeon_cs_reloc *reloc;
1991 struct r100_cs_track *track;
1993 volatile uint32_t *ib;
1998 track = (struct r100_cs_track *)p->track;
1999 switch (pkt->opcode) {
2000 case PACKET3_3D_LOAD_VBPNTR:
2001 r = r100_packet3_load_vbpntr(p, pkt, idx);
2005 case PACKET3_INDX_BUFFER:
2006 r = r100_cs_packet_next_reloc(p, &reloc);
2008 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2009 r100_cs_dump_packet(p, pkt);
2012 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
2013 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
2019 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2020 r = r100_cs_packet_next_reloc(p, &reloc);
2022 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2023 r100_cs_dump_packet(p, pkt);
2026 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
2027 track->num_arrays = 1;
2028 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
2030 track->arrays[0].robj = reloc->robj;
2031 track->arrays[0].esize = track->vtx_size;
2033 track->max_indx = radeon_get_ib_value(p, idx+1);
2035 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
2036 track->immd_dwords = pkt->count - 1;
2037 r = r100_cs_track_check(p->rdev, track);
2041 case PACKET3_3D_DRAW_IMMD:
2042 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
2043 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2046 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
2047 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2048 track->immd_dwords = pkt->count - 1;
2049 r = r100_cs_track_check(p->rdev, track);
2053 /* triggers drawing using in-packet vertex data */
2054 case PACKET3_3D_DRAW_IMMD_2:
2055 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
2056 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2059 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2060 track->immd_dwords = pkt->count;
2061 r = r100_cs_track_check(p->rdev, track);
2065 /* triggers drawing using in-packet vertex data */
2066 case PACKET3_3D_DRAW_VBUF_2:
2067 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2068 r = r100_cs_track_check(p->rdev, track);
2072 /* triggers drawing of vertex buffers setup elsewhere */
2073 case PACKET3_3D_DRAW_INDX_2:
2074 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2075 r = r100_cs_track_check(p->rdev, track);
2079 /* triggers drawing using indices to vertex buffer */
2080 case PACKET3_3D_DRAW_VBUF:
2081 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2082 r = r100_cs_track_check(p->rdev, track);
2086 /* triggers drawing of vertex buffers setup elsewhere */
2087 case PACKET3_3D_DRAW_INDX:
2088 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2089 r = r100_cs_track_check(p->rdev, track);
2093 /* triggers drawing using indices to vertex buffer */
2094 case PACKET3_3D_CLEAR_HIZ:
2095 case PACKET3_3D_CLEAR_ZMASK:
2096 if (p->rdev->hyperz_filp != p->filp)
2102 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2108 int r100_cs_parse(struct radeon_cs_parser *p)
2110 struct radeon_cs_packet pkt;
2111 struct r100_cs_track *track;
2114 track = kzalloc(sizeof(*track), GFP_KERNEL);
2117 r100_cs_track_clear(p->rdev, track);
2120 r = r100_cs_packet_parse(p, &pkt, p->idx);
2124 p->idx += pkt.count + 2;
2127 if (p->rdev->family >= CHIP_R200)
2128 r = r100_cs_parse_packet0(p, &pkt,
2129 p->rdev->config.r100.reg_safe_bm,
2130 p->rdev->config.r100.reg_safe_bm_size,
2131 &r200_packet0_check);
2133 r = r100_cs_parse_packet0(p, &pkt,
2134 p->rdev->config.r100.reg_safe_bm,
2135 p->rdev->config.r100.reg_safe_bm_size,
2136 &r100_packet0_check);
2141 r = r100_packet3_check(p, &pkt);
2144 DRM_ERROR("Unknown packet type %d !\n",
2151 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2155 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2157 DRM_ERROR("pitch %d\n", t->pitch);
2158 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2159 DRM_ERROR("width %d\n", t->width);
2160 DRM_ERROR("width_11 %d\n", t->width_11);
2161 DRM_ERROR("height %d\n", t->height);
2162 DRM_ERROR("height_11 %d\n", t->height_11);
2163 DRM_ERROR("num levels %d\n", t->num_levels);
2164 DRM_ERROR("depth %d\n", t->txdepth);
2165 DRM_ERROR("bpp %d\n", t->cpp);
2166 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2167 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2168 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2169 DRM_ERROR("compress format %d\n", t->compress_format);
2172 static int r100_track_compress_size(int compress_format, int w, int h)
2174 int block_width, block_height, block_bytes;
2175 int wblocks, hblocks;
2182 switch (compress_format) {
2183 case R100_TRACK_COMP_DXT1:
2188 case R100_TRACK_COMP_DXT35:
2194 hblocks = (h + block_height - 1) / block_height;
2195 wblocks = (w + block_width - 1) / block_width;
2196 if (wblocks < min_wblocks)
2197 wblocks = min_wblocks;
2198 sz = wblocks * hblocks * block_bytes;
2202 static int r100_cs_track_cube(struct radeon_device *rdev,
2203 struct r100_cs_track *track, unsigned idx)
2205 unsigned face, w, h;
2206 struct radeon_bo *cube_robj;
2208 unsigned compress_format = track->textures[idx].compress_format;
2210 for (face = 0; face < 5; face++) {
2211 cube_robj = track->textures[idx].cube_info[face].robj;
2212 w = track->textures[idx].cube_info[face].width;
2213 h = track->textures[idx].cube_info[face].height;
2215 if (compress_format) {
2216 size = r100_track_compress_size(compress_format, w, h);
2219 size *= track->textures[idx].cpp;
2221 size += track->textures[idx].cube_info[face].offset;
2223 if (size > radeon_bo_size(cube_robj)) {
2224 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2225 size, radeon_bo_size(cube_robj));
2226 r100_cs_track_texture_print(&track->textures[idx]);
2233 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2234 struct r100_cs_track *track)
2236 struct radeon_bo *robj;
2238 unsigned u, i, w, h, d;
2241 for (u = 0; u < track->num_texture; u++) {
2242 if (!track->textures[u].enabled)
2244 if (track->textures[u].lookup_disable)
2246 robj = track->textures[u].robj;
2248 DRM_ERROR("No texture bound to unit %u\n", u);
2252 for (i = 0; i <= track->textures[u].num_levels; i++) {
2253 if (track->textures[u].use_pitch) {
2254 if (rdev->family < CHIP_R300)
2255 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2257 w = track->textures[u].pitch / (1 << i);
2259 w = track->textures[u].width;
2260 if (rdev->family >= CHIP_RV515)
2261 w |= track->textures[u].width_11;
2263 if (track->textures[u].roundup_w)
2264 w = roundup_pow_of_two(w);
2266 h = track->textures[u].height;
2267 if (rdev->family >= CHIP_RV515)
2268 h |= track->textures[u].height_11;
2270 if (track->textures[u].roundup_h)
2271 h = roundup_pow_of_two(h);
2272 if (track->textures[u].tex_coord_type == 1) {
2273 d = (1 << track->textures[u].txdepth) / (1 << i);
2279 if (track->textures[u].compress_format) {
2281 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2282 /* compressed textures are block based */
2286 size *= track->textures[u].cpp;
2288 switch (track->textures[u].tex_coord_type) {
2293 if (track->separate_cube) {
2294 ret = r100_cs_track_cube(rdev, track, u);
2301 DRM_ERROR("Invalid texture coordinate type %u for unit "
2302 "%u\n", track->textures[u].tex_coord_type, u);
2305 if (size > radeon_bo_size(robj)) {
2306 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2307 "%lu\n", u, size, radeon_bo_size(robj));
2308 r100_cs_track_texture_print(&track->textures[u]);
2315 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2321 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2323 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2324 !track->blend_read_enable)
2327 for (i = 0; i < num_cb; i++) {
2328 if (track->cb[i].robj == NULL) {
2329 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2332 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2333 size += track->cb[i].offset;
2334 if (size > radeon_bo_size(track->cb[i].robj)) {
2335 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2336 "(need %lu have %lu) !\n", i, size,
2337 radeon_bo_size(track->cb[i].robj));
2338 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2339 i, track->cb[i].pitch, track->cb[i].cpp,
2340 track->cb[i].offset, track->maxy);
2344 track->cb_dirty = false;
2346 if (track->zb_dirty && track->z_enabled) {
2347 if (track->zb.robj == NULL) {
2348 DRM_ERROR("[drm] No buffer for z buffer !\n");
2351 size = track->zb.pitch * track->zb.cpp * track->maxy;
2352 size += track->zb.offset;
2353 if (size > radeon_bo_size(track->zb.robj)) {
2354 DRM_ERROR("[drm] Buffer too small for z buffer "
2355 "(need %lu have %lu) !\n", size,
2356 radeon_bo_size(track->zb.robj));
2357 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2358 track->zb.pitch, track->zb.cpp,
2359 track->zb.offset, track->maxy);
2363 track->zb_dirty = false;
2365 if (track->aa_dirty && track->aaresolve) {
2366 if (track->aa.robj == NULL) {
2367 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2370 /* I believe the format comes from colorbuffer0. */
2371 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2372 size += track->aa.offset;
2373 if (size > radeon_bo_size(track->aa.robj)) {
2374 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2375 "(need %lu have %lu) !\n", i, size,
2376 radeon_bo_size(track->aa.robj));
2377 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2378 i, track->aa.pitch, track->cb[0].cpp,
2379 track->aa.offset, track->maxy);
2383 track->aa_dirty = false;
2385 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2386 if (track->vap_vf_cntl & (1 << 14)) {
2387 nverts = track->vap_alt_nverts;
2389 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2391 switch (prim_walk) {
2393 for (i = 0; i < track->num_arrays; i++) {
2394 size = track->arrays[i].esize * track->max_indx * 4;
2395 if (track->arrays[i].robj == NULL) {
2396 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2397 "bound\n", prim_walk, i);
2400 if (size > radeon_bo_size(track->arrays[i].robj)) {
2401 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2402 "need %lu dwords have %lu dwords\n",
2403 prim_walk, i, size >> 2,
2404 radeon_bo_size(track->arrays[i].robj)
2406 DRM_ERROR("Max indices %u\n", track->max_indx);
2412 for (i = 0; i < track->num_arrays; i++) {
2413 size = track->arrays[i].esize * (nverts - 1) * 4;
2414 if (track->arrays[i].robj == NULL) {
2415 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2416 "bound\n", prim_walk, i);
2419 if (size > radeon_bo_size(track->arrays[i].robj)) {
2420 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2421 "need %lu dwords have %lu dwords\n",
2422 prim_walk, i, size >> 2,
2423 radeon_bo_size(track->arrays[i].robj)
2430 size = track->vtx_size * nverts;
2431 if (size != track->immd_dwords) {
2432 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2433 track->immd_dwords, size);
2434 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2435 nverts, track->vtx_size);
2440 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2445 if (track->tex_dirty) {
2446 track->tex_dirty = false;
2447 return r100_cs_track_texture_check(rdev, track);
2452 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2456 track->cb_dirty = true;
2457 track->zb_dirty = true;
2458 track->tex_dirty = true;
2459 track->aa_dirty = true;
2461 if (rdev->family < CHIP_R300) {
2463 if (rdev->family <= CHIP_RS200)
2464 track->num_texture = 3;
2466 track->num_texture = 6;
2468 track->separate_cube = 1;
2471 track->num_texture = 16;
2473 track->separate_cube = 0;
2474 track->aaresolve = false;
2475 track->aa.robj = NULL;
2478 for (i = 0; i < track->num_cb; i++) {
2479 track->cb[i].robj = NULL;
2480 track->cb[i].pitch = 8192;
2481 track->cb[i].cpp = 16;
2482 track->cb[i].offset = 0;
2484 track->z_enabled = true;
2485 track->zb.robj = NULL;
2486 track->zb.pitch = 8192;
2488 track->zb.offset = 0;
2489 track->vtx_size = 0x7F;
2490 track->immd_dwords = 0xFFFFFFFFUL;
2491 track->num_arrays = 11;
2492 track->max_indx = 0x00FFFFFFUL;
2493 for (i = 0; i < track->num_arrays; i++) {
2494 track->arrays[i].robj = NULL;
2495 track->arrays[i].esize = 0x7F;
2497 for (i = 0; i < track->num_texture; i++) {
2498 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2499 track->textures[i].pitch = 16536;
2500 track->textures[i].width = 16536;
2501 track->textures[i].height = 16536;
2502 track->textures[i].width_11 = 1 << 11;
2503 track->textures[i].height_11 = 1 << 11;
2504 track->textures[i].num_levels = 12;
2505 if (rdev->family <= CHIP_RS200) {
2506 track->textures[i].tex_coord_type = 0;
2507 track->textures[i].txdepth = 0;
2509 track->textures[i].txdepth = 16;
2510 track->textures[i].tex_coord_type = 1;
2512 track->textures[i].cpp = 64;
2513 track->textures[i].robj = NULL;
2514 /* CS IB emission code makes sure texture unit are disabled */
2515 track->textures[i].enabled = false;
2516 track->textures[i].lookup_disable = false;
2517 track->textures[i].roundup_w = true;
2518 track->textures[i].roundup_h = true;
2519 if (track->separate_cube)
2520 for (face = 0; face < 5; face++) {
2521 track->textures[i].cube_info[face].robj = NULL;
2522 track->textures[i].cube_info[face].width = 16536;
2523 track->textures[i].cube_info[face].height = 16536;
2524 track->textures[i].cube_info[face].offset = 0;
2530 * Global GPU functions
2532 void r100_errata(struct radeon_device *rdev)
2534 rdev->pll_errata = 0;
2536 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2537 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2540 if (rdev->family == CHIP_RV100 ||
2541 rdev->family == CHIP_RS100 ||
2542 rdev->family == CHIP_RS200) {
2543 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2547 /* Wait for vertical sync on primary CRTC */
2548 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2550 uint32_t crtc_gen_cntl, tmp;
2553 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2554 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2555 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2558 /* Clear the CRTC_VBLANK_SAVE bit */
2559 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2560 for (i = 0; i < rdev->usec_timeout; i++) {
2561 tmp = RREG32(RADEON_CRTC_STATUS);
2562 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2569 /* Wait for vertical sync on secondary CRTC */
2570 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2572 uint32_t crtc2_gen_cntl, tmp;
2575 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2576 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2577 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2580 /* Clear the CRTC_VBLANK_SAVE bit */
2581 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2582 for (i = 0; i < rdev->usec_timeout; i++) {
2583 tmp = RREG32(RADEON_CRTC2_STATUS);
2584 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2591 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2596 for (i = 0; i < rdev->usec_timeout; i++) {
2597 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2606 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2611 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2612 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2613 " Bad things might happen.\n");
2615 for (i = 0; i < rdev->usec_timeout; i++) {
2616 tmp = RREG32(RADEON_RBBM_STATUS);
2617 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2625 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2630 for (i = 0; i < rdev->usec_timeout; i++) {
2631 /* read MC_STATUS */
2632 tmp = RREG32(RADEON_MC_STATUS);
2633 if (tmp & RADEON_MC_IDLE) {
2641 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2645 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2646 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2647 radeon_ring_lockup_update(ring);
2650 /* force CP activities */
2651 radeon_ring_force_activity(rdev, ring);
2652 return radeon_ring_test_lockup(rdev, ring);
2655 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2656 void r100_enable_bm(struct radeon_device *rdev)
2659 /* Enable bus mastering */
2660 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2661 WREG32(RADEON_BUS_CNTL, tmp);
2664 void r100_bm_disable(struct radeon_device *rdev)
2668 /* disable bus mastering */
2669 tmp = RREG32(R_000030_BUS_CNTL);
2670 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2672 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2674 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2675 tmp = RREG32(RADEON_BUS_CNTL);
2677 pci_clear_master(rdev->pdev);
2681 int r100_asic_reset(struct radeon_device *rdev)
2683 struct r100_mc_save save;
2687 status = RREG32(R_000E40_RBBM_STATUS);
2688 if (!G_000E40_GUI_ACTIVE(status)) {
2691 r100_mc_stop(rdev, &save);
2692 status = RREG32(R_000E40_RBBM_STATUS);
2693 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2695 WREG32(RADEON_CP_CSQ_CNTL, 0);
2696 tmp = RREG32(RADEON_CP_RB_CNTL);
2697 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2698 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2699 WREG32(RADEON_CP_RB_WPTR, 0);
2700 WREG32(RADEON_CP_RB_CNTL, tmp);
2701 /* save PCI state */
2702 pci_save_state(rdev->pdev);
2703 /* disable bus mastering */
2704 r100_bm_disable(rdev);
2705 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2706 S_0000F0_SOFT_RESET_RE(1) |
2707 S_0000F0_SOFT_RESET_PP(1) |
2708 S_0000F0_SOFT_RESET_RB(1));
2709 RREG32(R_0000F0_RBBM_SOFT_RESET);
2711 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2713 status = RREG32(R_000E40_RBBM_STATUS);
2714 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2716 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2717 RREG32(R_0000F0_RBBM_SOFT_RESET);
2719 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2721 status = RREG32(R_000E40_RBBM_STATUS);
2722 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2723 /* restore PCI & busmastering */
2724 pci_restore_state(rdev->pdev);
2725 r100_enable_bm(rdev);
2726 /* Check if GPU is idle */
2727 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2728 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2729 dev_err(rdev->dev, "failed to reset GPU\n");
2732 dev_info(rdev->dev, "GPU reset succeed\n");
2733 r100_mc_resume(rdev, &save);
2737 void r100_set_common_regs(struct radeon_device *rdev)
2739 struct drm_device *dev = rdev->ddev;
2740 bool force_dac2 = false;
2743 /* set these so they don't interfere with anything */
2744 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2745 WREG32(RADEON_SUBPIC_CNTL, 0);
2746 WREG32(RADEON_VIPH_CONTROL, 0);
2747 WREG32(RADEON_I2C_CNTL_1, 0);
2748 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2749 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2750 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2752 /* always set up dac2 on rn50 and some rv100 as lots
2753 * of servers seem to wire it up to a VGA port but
2754 * don't report it in the bios connector
2757 switch (dev->pdev->device) {
2766 /* DELL triple head servers */
2767 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2768 ((dev->pdev->subsystem_device == 0x016c) ||
2769 (dev->pdev->subsystem_device == 0x016d) ||
2770 (dev->pdev->subsystem_device == 0x016e) ||
2771 (dev->pdev->subsystem_device == 0x016f) ||
2772 (dev->pdev->subsystem_device == 0x0170) ||
2773 (dev->pdev->subsystem_device == 0x017d) ||
2774 (dev->pdev->subsystem_device == 0x017e) ||
2775 (dev->pdev->subsystem_device == 0x0183) ||
2776 (dev->pdev->subsystem_device == 0x018a) ||
2777 (dev->pdev->subsystem_device == 0x019a)))
2783 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2784 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2785 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2787 /* For CRT on DAC2, don't turn it on if BIOS didn't
2788 enable it, even it's detected.
2791 /* force it to crtc0 */
2792 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2793 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2794 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2796 /* set up the TV DAC */
2797 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2798 RADEON_TV_DAC_STD_MASK |
2799 RADEON_TV_DAC_RDACPD |
2800 RADEON_TV_DAC_GDACPD |
2801 RADEON_TV_DAC_BDACPD |
2802 RADEON_TV_DAC_BGADJ_MASK |
2803 RADEON_TV_DAC_DACADJ_MASK);
2804 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2805 RADEON_TV_DAC_NHOLD |
2806 RADEON_TV_DAC_STD_PS2 |
2809 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2810 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2811 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2814 /* switch PM block to ACPI mode */
2815 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2816 tmp &= ~RADEON_PM_MODE_SEL;
2817 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2824 static void r100_vram_get_type(struct radeon_device *rdev)
2828 rdev->mc.vram_is_ddr = false;
2829 if (rdev->flags & RADEON_IS_IGP)
2830 rdev->mc.vram_is_ddr = true;
2831 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2832 rdev->mc.vram_is_ddr = true;
2833 if ((rdev->family == CHIP_RV100) ||
2834 (rdev->family == CHIP_RS100) ||
2835 (rdev->family == CHIP_RS200)) {
2836 tmp = RREG32(RADEON_MEM_CNTL);
2837 if (tmp & RV100_HALF_MODE) {
2838 rdev->mc.vram_width = 32;
2840 rdev->mc.vram_width = 64;
2842 if (rdev->flags & RADEON_SINGLE_CRTC) {
2843 rdev->mc.vram_width /= 4;
2844 rdev->mc.vram_is_ddr = true;
2846 } else if (rdev->family <= CHIP_RV280) {
2847 tmp = RREG32(RADEON_MEM_CNTL);
2848 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2849 rdev->mc.vram_width = 128;
2851 rdev->mc.vram_width = 64;
2855 rdev->mc.vram_width = 128;
2859 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2864 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2866 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2867 * that is has the 2nd generation multifunction PCI interface
2869 if (rdev->family == CHIP_RV280 ||
2870 rdev->family >= CHIP_RV350) {
2871 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2872 ~RADEON_HDP_APER_CNTL);
2873 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2874 return aper_size * 2;
2877 /* Older cards have all sorts of funny issues to deal with. First
2878 * check if it's a multifunction card by reading the PCI config
2879 * header type... Limit those to one aperture size
2881 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2883 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2884 DRM_INFO("Limiting VRAM to one aperture\n");
2888 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2889 * have set it up. We don't write this as it's broken on some ASICs but
2890 * we expect the BIOS to have done the right thing (might be too optimistic...)
2892 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2893 return aper_size * 2;
2897 void r100_vram_init_sizes(struct radeon_device *rdev)
2899 u64 config_aper_size;
2901 /* work out accessible VRAM */
2902 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2903 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2904 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2905 /* FIXME we don't use the second aperture yet when we could use it */
2906 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2907 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2908 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2909 if (rdev->flags & RADEON_IS_IGP) {
2911 /* read NB_TOM to get the amount of ram stolen for the GPU */
2912 tom = RREG32(RADEON_NB_TOM);
2913 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2914 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2915 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2917 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2918 /* Some production boards of m6 will report 0
2921 if (rdev->mc.real_vram_size == 0) {
2922 rdev->mc.real_vram_size = 8192 * 1024;
2923 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2925 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2926 * Novell bug 204882 + along with lots of ubuntu ones
2928 if (rdev->mc.aper_size > config_aper_size)
2929 config_aper_size = rdev->mc.aper_size;
2931 if (config_aper_size > rdev->mc.real_vram_size)
2932 rdev->mc.mc_vram_size = config_aper_size;
2934 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2938 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2942 temp = RREG32(RADEON_CONFIG_CNTL);
2943 if (state == false) {
2944 temp &= ~RADEON_CFG_VGA_RAM_EN;
2945 temp |= RADEON_CFG_VGA_IO_DIS;
2947 temp &= ~RADEON_CFG_VGA_IO_DIS;
2949 WREG32(RADEON_CONFIG_CNTL, temp);
2952 void r100_mc_init(struct radeon_device *rdev)
2956 r100_vram_get_type(rdev);
2957 r100_vram_init_sizes(rdev);
2958 base = rdev->mc.aper_base;
2959 if (rdev->flags & RADEON_IS_IGP)
2960 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2961 radeon_vram_location(rdev, &rdev->mc, base);
2962 rdev->mc.gtt_base_align = 0;
2963 if (!(rdev->flags & RADEON_IS_AGP))
2964 radeon_gtt_location(rdev, &rdev->mc);
2965 radeon_update_bandwidth_info(rdev);
2970 * Indirect registers accessor
2972 void r100_pll_errata_after_index(struct radeon_device *rdev)
2974 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2975 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2976 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2980 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2982 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2983 * or the chip could hang on a subsequent access
2985 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2989 /* This function is required to workaround a hardware bug in some (all?)
2990 * revisions of the R300. This workaround should be called after every
2991 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2992 * may not be correct.
2994 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2997 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2998 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2999 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
3000 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
3001 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
3005 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
3009 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
3010 r100_pll_errata_after_index(rdev);
3011 data = RREG32(RADEON_CLOCK_CNTL_DATA);
3012 r100_pll_errata_after_data(rdev);
3016 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3018 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3019 r100_pll_errata_after_index(rdev);
3020 WREG32(RADEON_CLOCK_CNTL_DATA, v);
3021 r100_pll_errata_after_data(rdev);
3024 void r100_set_safe_registers(struct radeon_device *rdev)
3026 if (ASIC_IS_RN50(rdev)) {
3027 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3028 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3029 } else if (rdev->family < CHIP_R200) {
3030 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3031 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
3033 r200_set_safe_registers(rdev);
3040 #if defined(CONFIG_DEBUG_FS)
3041 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
3043 struct drm_info_node *node = (struct drm_info_node *) m->private;
3044 struct drm_device *dev = node->minor->dev;
3045 struct radeon_device *rdev = dev->dev_private;
3046 uint32_t reg, value;
3049 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
3050 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
3051 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3052 for (i = 0; i < 64; i++) {
3053 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
3054 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
3055 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
3056 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
3057 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
3062 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
3064 struct drm_info_node *node = (struct drm_info_node *) m->private;
3065 struct drm_device *dev = node->minor->dev;
3066 struct radeon_device *rdev = dev->dev_private;
3067 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3069 unsigned count, i, j;
3071 radeon_ring_free_size(rdev, ring);
3072 rdp = RREG32(RADEON_CP_RB_RPTR);
3073 wdp = RREG32(RADEON_CP_RB_WPTR);
3074 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
3075 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3076 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
3077 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
3078 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
3079 seq_printf(m, "%u dwords in ring\n", count);
3080 for (j = 0; j <= count; j++) {
3081 i = (rdp + j) & ring->ptr_mask;
3082 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3088 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
3090 struct drm_info_node *node = (struct drm_info_node *) m->private;
3091 struct drm_device *dev = node->minor->dev;
3092 struct radeon_device *rdev = dev->dev_private;
3093 uint32_t csq_stat, csq2_stat, tmp;
3094 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3097 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3098 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3099 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3100 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3101 r_rptr = (csq_stat >> 0) & 0x3ff;
3102 r_wptr = (csq_stat >> 10) & 0x3ff;
3103 ib1_rptr = (csq_stat >> 20) & 0x3ff;
3104 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3105 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3106 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3107 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3108 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3109 seq_printf(m, "Ring rptr %u\n", r_rptr);
3110 seq_printf(m, "Ring wptr %u\n", r_wptr);
3111 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3112 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3113 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3114 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3115 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3116 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3117 seq_printf(m, "Ring fifo:\n");
3118 for (i = 0; i < 256; i++) {
3119 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3120 tmp = RREG32(RADEON_CP_CSQ_DATA);
3121 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3123 seq_printf(m, "Indirect1 fifo:\n");
3124 for (i = 256; i <= 512; i++) {
3125 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3126 tmp = RREG32(RADEON_CP_CSQ_DATA);
3127 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3129 seq_printf(m, "Indirect2 fifo:\n");
3130 for (i = 640; i < ib1_wptr; i++) {
3131 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3132 tmp = RREG32(RADEON_CP_CSQ_DATA);
3133 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3138 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3140 struct drm_info_node *node = (struct drm_info_node *) m->private;
3141 struct drm_device *dev = node->minor->dev;
3142 struct radeon_device *rdev = dev->dev_private;
3145 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3146 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3147 tmp = RREG32(RADEON_MC_FB_LOCATION);
3148 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3149 tmp = RREG32(RADEON_BUS_CNTL);
3150 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3151 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3152 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3153 tmp = RREG32(RADEON_AGP_BASE);
3154 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3155 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3156 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3157 tmp = RREG32(0x01D0);
3158 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3159 tmp = RREG32(RADEON_AIC_LO_ADDR);
3160 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3161 tmp = RREG32(RADEON_AIC_HI_ADDR);
3162 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3163 tmp = RREG32(0x01E4);
3164 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3168 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3169 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3172 static struct drm_info_list r100_debugfs_cp_list[] = {
3173 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3174 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3177 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3178 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3182 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3184 #if defined(CONFIG_DEBUG_FS)
3185 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3191 int r100_debugfs_cp_init(struct radeon_device *rdev)
3193 #if defined(CONFIG_DEBUG_FS)
3194 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3200 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3202 #if defined(CONFIG_DEBUG_FS)
3203 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3209 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3210 uint32_t tiling_flags, uint32_t pitch,
3211 uint32_t offset, uint32_t obj_size)
3213 int surf_index = reg * 16;
3216 if (rdev->family <= CHIP_RS200) {
3217 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3218 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3219 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3220 if (tiling_flags & RADEON_TILING_MACRO)
3221 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3222 } else if (rdev->family <= CHIP_RV280) {
3223 if (tiling_flags & (RADEON_TILING_MACRO))
3224 flags |= R200_SURF_TILE_COLOR_MACRO;
3225 if (tiling_flags & RADEON_TILING_MICRO)
3226 flags |= R200_SURF_TILE_COLOR_MICRO;
3228 if (tiling_flags & RADEON_TILING_MACRO)
3229 flags |= R300_SURF_TILE_MACRO;
3230 if (tiling_flags & RADEON_TILING_MICRO)
3231 flags |= R300_SURF_TILE_MICRO;
3234 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3235 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3236 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3237 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3239 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3240 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3241 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3242 if (ASIC_IS_RN50(rdev))
3246 /* r100/r200 divide by 16 */
3247 if (rdev->family < CHIP_R300)
3248 flags |= pitch / 16;
3253 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3254 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3255 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3256 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3260 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3262 int surf_index = reg * 16;
3263 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3266 void r100_bandwidth_update(struct radeon_device *rdev)
3268 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3269 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3270 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3271 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3272 fixed20_12 memtcas_ff[8] = {
3277 dfixed_init_half(1),
3278 dfixed_init_half(2),
3281 fixed20_12 memtcas_rs480_ff[8] = {
3287 dfixed_init_half(1),
3288 dfixed_init_half(2),
3289 dfixed_init_half(3),
3291 fixed20_12 memtcas2_ff[8] = {
3301 fixed20_12 memtrbs[8] = {
3303 dfixed_init_half(1),
3305 dfixed_init_half(2),
3307 dfixed_init_half(3),
3311 fixed20_12 memtrbs_r4xx[8] = {
3321 fixed20_12 min_mem_eff;
3322 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3323 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3324 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3325 disp_drain_rate2, read_return_rate;
3326 fixed20_12 time_disp1_drop_priority;
3328 int cur_size = 16; /* in octawords */
3329 int critical_point = 0, critical_point2;
3330 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3331 int stop_req, max_stop_req;
3332 struct drm_display_mode *mode1 = NULL;
3333 struct drm_display_mode *mode2 = NULL;
3334 uint32_t pixel_bytes1 = 0;
3335 uint32_t pixel_bytes2 = 0;
3337 radeon_update_display_priority(rdev);
3339 if (rdev->mode_info.crtcs[0]->base.enabled) {
3340 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3341 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3343 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3344 if (rdev->mode_info.crtcs[1]->base.enabled) {
3345 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3346 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3350 min_mem_eff.full = dfixed_const_8(0);
3352 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3353 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3354 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3355 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3356 /* check crtc enables */
3358 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3360 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3361 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3365 * determine is there is enough bw for current mode
3367 sclk_ff = rdev->pm.sclk;
3368 mclk_ff = rdev->pm.mclk;
3370 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3371 temp_ff.full = dfixed_const(temp);
3372 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3376 peak_disp_bw.full = 0;
3378 temp_ff.full = dfixed_const(1000);
3379 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3380 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3381 temp_ff.full = dfixed_const(pixel_bytes1);
3382 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3385 temp_ff.full = dfixed_const(1000);
3386 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3387 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3388 temp_ff.full = dfixed_const(pixel_bytes2);
3389 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3392 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3393 if (peak_disp_bw.full >= mem_bw.full) {
3394 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3395 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3398 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3399 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3400 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3401 mem_trcd = ((temp >> 2) & 0x3) + 1;
3402 mem_trp = ((temp & 0x3)) + 1;
3403 mem_tras = ((temp & 0x70) >> 4) + 1;
3404 } else if (rdev->family == CHIP_R300 ||
3405 rdev->family == CHIP_R350) { /* r300, r350 */
3406 mem_trcd = (temp & 0x7) + 1;
3407 mem_trp = ((temp >> 8) & 0x7) + 1;
3408 mem_tras = ((temp >> 11) & 0xf) + 4;
3409 } else if (rdev->family == CHIP_RV350 ||
3410 rdev->family <= CHIP_RV380) {
3412 mem_trcd = (temp & 0x7) + 3;
3413 mem_trp = ((temp >> 8) & 0x7) + 3;
3414 mem_tras = ((temp >> 11) & 0xf) + 6;
3415 } else if (rdev->family == CHIP_R420 ||
3416 rdev->family == CHIP_R423 ||
3417 rdev->family == CHIP_RV410) {
3419 mem_trcd = (temp & 0xf) + 3;
3422 mem_trp = ((temp >> 8) & 0xf) + 3;
3425 mem_tras = ((temp >> 12) & 0x1f) + 6;
3428 } else { /* RV200, R200 */
3429 mem_trcd = (temp & 0x7) + 1;
3430 mem_trp = ((temp >> 8) & 0x7) + 1;
3431 mem_tras = ((temp >> 12) & 0xf) + 4;
3434 trcd_ff.full = dfixed_const(mem_trcd);
3435 trp_ff.full = dfixed_const(mem_trp);
3436 tras_ff.full = dfixed_const(mem_tras);
3438 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3439 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3440 data = (temp & (7 << 20)) >> 20;
3441 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3442 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3443 tcas_ff = memtcas_rs480_ff[data];
3445 tcas_ff = memtcas_ff[data];
3447 tcas_ff = memtcas2_ff[data];
3449 if (rdev->family == CHIP_RS400 ||
3450 rdev->family == CHIP_RS480) {
3451 /* extra cas latency stored in bits 23-25 0-4 clocks */
3452 data = (temp >> 23) & 0x7;
3454 tcas_ff.full += dfixed_const(data);
3457 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3458 /* on the R300, Tcas is included in Trbs.
3460 temp = RREG32(RADEON_MEM_CNTL);
3461 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3463 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3464 temp = RREG32(R300_MC_IND_INDEX);
3465 temp &= ~R300_MC_IND_ADDR_MASK;
3466 temp |= R300_MC_READ_CNTL_CD_mcind;
3467 WREG32(R300_MC_IND_INDEX, temp);
3468 temp = RREG32(R300_MC_IND_DATA);
3469 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3471 temp = RREG32(R300_MC_READ_CNTL_AB);
3472 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3475 temp = RREG32(R300_MC_READ_CNTL_AB);
3476 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3478 if (rdev->family == CHIP_RV410 ||
3479 rdev->family == CHIP_R420 ||
3480 rdev->family == CHIP_R423)
3481 trbs_ff = memtrbs_r4xx[data];
3483 trbs_ff = memtrbs[data];
3484 tcas_ff.full += trbs_ff.full;
3487 sclk_eff_ff.full = sclk_ff.full;
3489 if (rdev->flags & RADEON_IS_AGP) {
3490 fixed20_12 agpmode_ff;
3491 agpmode_ff.full = dfixed_const(radeon_agpmode);
3492 temp_ff.full = dfixed_const_666(16);
3493 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3495 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3497 if (ASIC_IS_R300(rdev)) {
3498 sclk_delay_ff.full = dfixed_const(250);
3500 if ((rdev->family == CHIP_RV100) ||
3501 rdev->flags & RADEON_IS_IGP) {
3502 if (rdev->mc.vram_is_ddr)
3503 sclk_delay_ff.full = dfixed_const(41);
3505 sclk_delay_ff.full = dfixed_const(33);
3507 if (rdev->mc.vram_width == 128)
3508 sclk_delay_ff.full = dfixed_const(57);
3510 sclk_delay_ff.full = dfixed_const(41);
3514 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3516 if (rdev->mc.vram_is_ddr) {
3517 if (rdev->mc.vram_width == 32) {
3518 k1.full = dfixed_const(40);
3521 k1.full = dfixed_const(20);
3525 k1.full = dfixed_const(40);
3529 temp_ff.full = dfixed_const(2);
3530 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3531 temp_ff.full = dfixed_const(c);
3532 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3533 temp_ff.full = dfixed_const(4);
3534 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3535 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3536 mc_latency_mclk.full += k1.full;
3538 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3539 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3542 HW cursor time assuming worst case of full size colour cursor.
3544 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3545 temp_ff.full += trcd_ff.full;
3546 if (temp_ff.full < tras_ff.full)
3547 temp_ff.full = tras_ff.full;
3548 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3550 temp_ff.full = dfixed_const(cur_size);
3551 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3553 Find the total latency for the display data.
3555 disp_latency_overhead.full = dfixed_const(8);
3556 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3557 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3558 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3560 if (mc_latency_mclk.full > mc_latency_sclk.full)
3561 disp_latency.full = mc_latency_mclk.full;
3563 disp_latency.full = mc_latency_sclk.full;
3565 /* setup Max GRPH_STOP_REQ default value */
3566 if (ASIC_IS_RV100(rdev))
3567 max_stop_req = 0x5c;
3569 max_stop_req = 0x7c;
3573 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3574 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3576 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3578 if (stop_req > max_stop_req)
3579 stop_req = max_stop_req;
3582 Find the drain rate of the display buffer.
3584 temp_ff.full = dfixed_const((16/pixel_bytes1));
3585 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3588 Find the critical point of the display buffer.
3590 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3591 crit_point_ff.full += dfixed_const_half(0);
3593 critical_point = dfixed_trunc(crit_point_ff);
3595 if (rdev->disp_priority == 2) {
3600 The critical point should never be above max_stop_req-4. Setting
3601 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3603 if (max_stop_req - critical_point < 4)
3606 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3607 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3608 critical_point = 0x10;
3611 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3612 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3613 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3614 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3615 if ((rdev->family == CHIP_R350) &&
3616 (stop_req > 0x15)) {
3619 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3620 temp |= RADEON_GRPH_BUFFER_SIZE;
3621 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3622 RADEON_GRPH_CRITICAL_AT_SOF |
3623 RADEON_GRPH_STOP_CNTL);
3625 Write the result into the register.
3627 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3628 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3631 if ((rdev->family == CHIP_RS400) ||
3632 (rdev->family == CHIP_RS480)) {
3633 /* attempt to program RS400 disp regs correctly ??? */
3634 temp = RREG32(RS400_DISP1_REG_CNTL);
3635 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3636 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3637 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3638 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3639 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3640 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3641 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3642 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3643 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3644 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3645 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3649 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3650 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3651 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3656 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3658 if (stop_req > max_stop_req)
3659 stop_req = max_stop_req;
3662 Find the drain rate of the display buffer.
3664 temp_ff.full = dfixed_const((16/pixel_bytes2));
3665 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3667 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3668 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3669 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3670 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3671 if ((rdev->family == CHIP_R350) &&
3672 (stop_req > 0x15)) {
3675 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3676 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3677 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3678 RADEON_GRPH_CRITICAL_AT_SOF |
3679 RADEON_GRPH_STOP_CNTL);
3681 if ((rdev->family == CHIP_RS100) ||
3682 (rdev->family == CHIP_RS200))
3683 critical_point2 = 0;
3685 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3686 temp_ff.full = dfixed_const(temp);
3687 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3688 if (sclk_ff.full < temp_ff.full)
3689 temp_ff.full = sclk_ff.full;
3691 read_return_rate.full = temp_ff.full;
3694 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3695 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3697 time_disp1_drop_priority.full = 0;
3699 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3700 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3701 crit_point_ff.full += dfixed_const_half(0);
3703 critical_point2 = dfixed_trunc(crit_point_ff);
3705 if (rdev->disp_priority == 2) {
3706 critical_point2 = 0;
3709 if (max_stop_req - critical_point2 < 4)
3710 critical_point2 = 0;
3714 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3715 /* some R300 cards have problem with this set to 0 */
3716 critical_point2 = 0x10;
3719 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3720 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3722 if ((rdev->family == CHIP_RS400) ||
3723 (rdev->family == CHIP_RS480)) {
3725 /* attempt to program RS400 disp2 regs correctly ??? */
3726 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3727 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3728 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3729 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3730 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3731 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3732 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3733 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3734 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3735 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3736 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3737 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3739 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3740 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3741 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3742 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3745 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3746 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3750 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3757 r = radeon_scratch_get(rdev, &scratch);
3759 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3762 WREG32(scratch, 0xCAFEDEAD);
3763 r = radeon_ring_lock(rdev, ring, 2);
3765 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3766 radeon_scratch_free(rdev, scratch);
3769 radeon_ring_write(ring, PACKET0(scratch, 0));
3770 radeon_ring_write(ring, 0xDEADBEEF);
3771 radeon_ring_unlock_commit(rdev, ring);
3772 for (i = 0; i < rdev->usec_timeout; i++) {
3773 tmp = RREG32(scratch);
3774 if (tmp == 0xDEADBEEF) {
3779 if (i < rdev->usec_timeout) {
3780 DRM_INFO("ring test succeeded in %d usecs\n", i);
3782 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3786 radeon_scratch_free(rdev, scratch);
3790 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3792 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3794 if (ring->rptr_save_reg) {
3795 u32 next_rptr = ring->wptr + 2 + 3;
3796 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3797 radeon_ring_write(ring, next_rptr);
3800 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3801 radeon_ring_write(ring, ib->gpu_addr);
3802 radeon_ring_write(ring, ib->length_dw);
3805 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3807 struct radeon_ib ib;
3813 r = radeon_scratch_get(rdev, &scratch);
3815 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3818 WREG32(scratch, 0xCAFEDEAD);
3819 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3823 ib.ptr[0] = PACKET0(scratch, 0);
3824 ib.ptr[1] = 0xDEADBEEF;
3825 ib.ptr[2] = PACKET2(0);
3826 ib.ptr[3] = PACKET2(0);
3827 ib.ptr[4] = PACKET2(0);
3828 ib.ptr[5] = PACKET2(0);
3829 ib.ptr[6] = PACKET2(0);
3830 ib.ptr[7] = PACKET2(0);
3832 r = radeon_ib_schedule(rdev, &ib, NULL);
3834 radeon_scratch_free(rdev, scratch);
3835 radeon_ib_free(rdev, &ib);
3838 r = radeon_fence_wait(ib.fence, false);
3842 for (i = 0; i < rdev->usec_timeout; i++) {
3843 tmp = RREG32(scratch);
3844 if (tmp == 0xDEADBEEF) {
3849 if (i < rdev->usec_timeout) {
3850 DRM_INFO("ib test succeeded in %u usecs\n", i);
3852 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3856 radeon_scratch_free(rdev, scratch);
3857 radeon_ib_free(rdev, &ib);
3861 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3863 /* Shutdown CP we shouldn't need to do that but better be safe than
3866 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3867 WREG32(R_000740_CP_CSQ_CNTL, 0);
3869 /* Save few CRTC registers */
3870 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3871 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3872 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3873 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3874 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3875 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3876 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3879 /* Disable VGA aperture access */
3880 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3881 /* Disable cursor, overlay, crtc */
3882 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3883 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3884 S_000054_CRTC_DISPLAY_DIS(1));
3885 WREG32(R_000050_CRTC_GEN_CNTL,
3886 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3887 S_000050_CRTC_DISP_REQ_EN_B(1));
3888 WREG32(R_000420_OV0_SCALE_CNTL,
3889 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3890 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3891 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3892 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3893 S_000360_CUR2_LOCK(1));
3894 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3895 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3896 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3897 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3898 WREG32(R_000360_CUR2_OFFSET,
3899 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3903 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3905 /* Update base address for crtc */
3906 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3907 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3908 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3910 /* Restore CRTC registers */
3911 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3912 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3913 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3914 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3915 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3919 void r100_vga_render_disable(struct radeon_device *rdev)
3923 tmp = RREG8(R_0003C2_GENMO_WT);
3924 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3927 static void r100_debugfs(struct radeon_device *rdev)
3931 r = r100_debugfs_mc_info_init(rdev);
3933 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3936 static void r100_mc_program(struct radeon_device *rdev)
3938 struct r100_mc_save save;
3940 /* Stops all mc clients */
3941 r100_mc_stop(rdev, &save);
3942 if (rdev->flags & RADEON_IS_AGP) {
3943 WREG32(R_00014C_MC_AGP_LOCATION,
3944 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3945 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3946 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3947 if (rdev->family > CHIP_RV200)
3948 WREG32(R_00015C_AGP_BASE_2,
3949 upper_32_bits(rdev->mc.agp_base) & 0xff);
3951 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3952 WREG32(R_000170_AGP_BASE, 0);
3953 if (rdev->family > CHIP_RV200)
3954 WREG32(R_00015C_AGP_BASE_2, 0);
3956 /* Wait for mc idle */
3957 if (r100_mc_wait_for_idle(rdev))
3958 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3959 /* Program MC, should be a 32bits limited address space */
3960 WREG32(R_000148_MC_FB_LOCATION,
3961 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3962 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3963 r100_mc_resume(rdev, &save);
3966 void r100_clock_startup(struct radeon_device *rdev)
3970 if (radeon_dynclks != -1 && radeon_dynclks)
3971 radeon_legacy_set_clock_gating(rdev, 1);
3972 /* We need to force on some of the block */
3973 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3974 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3975 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3976 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3977 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3980 static int r100_startup(struct radeon_device *rdev)
3984 /* set common regs */
3985 r100_set_common_regs(rdev);
3987 r100_mc_program(rdev);
3989 r100_clock_startup(rdev);
3990 /* Initialize GART (initialize after TTM so we can allocate
3991 * memory through TTM but finalize after TTM) */
3992 r100_enable_bm(rdev);
3993 if (rdev->flags & RADEON_IS_PCI) {
3994 r = r100_pci_gart_enable(rdev);
3999 /* allocate wb buffer */
4000 r = radeon_wb_init(rdev);
4004 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4006 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4012 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
4013 /* 1M ring buffer */
4014 r = r100_cp_init(rdev, 1024 * 1024);
4016 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
4020 r = radeon_ib_pool_init(rdev);
4022 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4029 int r100_resume(struct radeon_device *rdev)
4033 /* Make sur GART are not working */
4034 if (rdev->flags & RADEON_IS_PCI)
4035 r100_pci_gart_disable(rdev);
4036 /* Resume clock before doing reset */
4037 r100_clock_startup(rdev);
4038 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4039 if (radeon_asic_reset(rdev)) {
4040 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4041 RREG32(R_000E40_RBBM_STATUS),
4042 RREG32(R_0007C0_CP_STAT));
4045 radeon_combios_asic_init(rdev->ddev);
4046 /* Resume clock after posting */
4047 r100_clock_startup(rdev);
4048 /* Initialize surface registers */
4049 radeon_surface_init(rdev);
4051 rdev->accel_working = true;
4052 r = r100_startup(rdev);
4054 rdev->accel_working = false;
4059 int r100_suspend(struct radeon_device *rdev)
4061 r100_cp_disable(rdev);
4062 radeon_wb_disable(rdev);
4063 r100_irq_disable(rdev);
4064 if (rdev->flags & RADEON_IS_PCI)
4065 r100_pci_gart_disable(rdev);
4069 void r100_fini(struct radeon_device *rdev)
4072 radeon_wb_fini(rdev);
4073 radeon_ib_pool_fini(rdev);
4074 radeon_gem_fini(rdev);
4075 if (rdev->flags & RADEON_IS_PCI)
4076 r100_pci_gart_fini(rdev);
4077 radeon_agp_fini(rdev);
4078 radeon_irq_kms_fini(rdev);
4079 radeon_fence_driver_fini(rdev);
4080 radeon_bo_fini(rdev);
4081 radeon_atombios_fini(rdev);
4087 * Due to how kexec works, it can leave the hw fully initialised when it
4088 * boots the new kernel. However doing our init sequence with the CP and
4089 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4090 * do some quick sanity checks and restore sane values to avoid this
4093 void r100_restore_sanity(struct radeon_device *rdev)
4097 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4099 WREG32(RADEON_CP_CSQ_CNTL, 0);
4101 tmp = RREG32(RADEON_CP_RB_CNTL);
4103 WREG32(RADEON_CP_RB_CNTL, 0);
4105 tmp = RREG32(RADEON_SCRATCH_UMSK);
4107 WREG32(RADEON_SCRATCH_UMSK, 0);
4111 int r100_init(struct radeon_device *rdev)
4115 /* Register debugfs file specific to this group of asics */
4118 r100_vga_render_disable(rdev);
4119 /* Initialize scratch registers */
4120 radeon_scratch_init(rdev);
4121 /* Initialize surface registers */
4122 radeon_surface_init(rdev);
4123 /* sanity check some register to avoid hangs like after kexec */
4124 r100_restore_sanity(rdev);
4125 /* TODO: disable VGA need to use VGA request */
4127 if (!radeon_get_bios(rdev)) {
4128 if (ASIC_IS_AVIVO(rdev))
4131 if (rdev->is_atom_bios) {
4132 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4135 r = radeon_combios_init(rdev);
4139 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4140 if (radeon_asic_reset(rdev)) {
4142 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4143 RREG32(R_000E40_RBBM_STATUS),
4144 RREG32(R_0007C0_CP_STAT));
4146 /* check if cards are posted or not */
4147 if (radeon_boot_test_post_card(rdev) == false)
4149 /* Set asic errata */
4151 /* Initialize clocks */
4152 radeon_get_clock_info(rdev->ddev);
4153 /* initialize AGP */
4154 if (rdev->flags & RADEON_IS_AGP) {
4155 r = radeon_agp_init(rdev);
4157 radeon_agp_disable(rdev);
4160 /* initialize VRAM */
4163 r = radeon_fence_driver_init(rdev);
4166 r = radeon_irq_kms_init(rdev);
4169 /* Memory manager */
4170 r = radeon_bo_init(rdev);
4173 if (rdev->flags & RADEON_IS_PCI) {
4174 r = r100_pci_gart_init(rdev);
4178 r100_set_safe_registers(rdev);
4180 rdev->accel_working = true;
4181 r = r100_startup(rdev);
4183 /* Somethings want wront with the accel init stop accel */
4184 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4186 radeon_wb_fini(rdev);
4187 radeon_ib_pool_fini(rdev);
4188 radeon_irq_kms_fini(rdev);
4189 if (rdev->flags & RADEON_IS_PCI)
4190 r100_pci_gart_fini(rdev);
4191 rdev->accel_working = false;
4196 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4198 if (reg < rdev->rmmio_size)
4199 return readl(((void __iomem *)rdev->rmmio) + reg);
4201 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4202 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4206 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4208 if (reg < rdev->rmmio_size)
4209 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4211 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4212 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4216 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4218 if (reg < rdev->rio_mem_size)
4219 return ioread32(rdev->rio_mem + reg);
4221 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4222 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4226 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4228 if (reg < rdev->rio_mem_size)
4229 iowrite32(v, rdev->rio_mem + reg);
4231 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4232 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);