2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/platform_device.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
64 #include "r100_track.h"
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 /* hpd for digital panel detect/disconnect */
71 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
73 bool connected = false;
77 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
81 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
90 void r100_hpd_set_polarity(struct radeon_device *rdev,
91 enum radeon_hpd_id hpd)
94 bool connected = r100_hpd_sense(rdev, hpd);
98 tmp = RREG32(RADEON_FP_GEN_CNTL);
100 tmp &= ~RADEON_FP_DETECT_INT_POL;
102 tmp |= RADEON_FP_DETECT_INT_POL;
103 WREG32(RADEON_FP_GEN_CNTL, tmp);
106 tmp = RREG32(RADEON_FP2_GEN_CNTL);
108 tmp &= ~RADEON_FP2_DETECT_INT_POL;
110 tmp |= RADEON_FP2_DETECT_INT_POL;
111 WREG32(RADEON_FP2_GEN_CNTL, tmp);
118 void r100_hpd_init(struct radeon_device *rdev)
120 struct drm_device *dev = rdev->ddev;
121 struct drm_connector *connector;
123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
124 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
125 switch (radeon_connector->hpd.hpd) {
127 rdev->irq.hpd[0] = true;
130 rdev->irq.hpd[1] = true;
136 if (rdev->irq.installed)
140 void r100_hpd_fini(struct radeon_device *rdev)
142 struct drm_device *dev = rdev->ddev;
143 struct drm_connector *connector;
145 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
146 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
147 switch (radeon_connector->hpd.hpd) {
149 rdev->irq.hpd[0] = false;
152 rdev->irq.hpd[1] = false;
163 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
165 /* TODO: can we do somethings here ? */
166 /* It seems hw only cache one entry so we should discard this
167 * entry otherwise if first GPU GART read hit this entry it
168 * could end up in wrong address. */
171 int r100_pci_gart_init(struct radeon_device *rdev)
175 if (rdev->gart.table.ram.ptr) {
176 WARN(1, "R100 PCI GART already initialized.\n");
179 /* Initialize common gart structure */
180 r = radeon_gart_init(rdev);
183 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
184 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
185 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
186 return radeon_gart_table_ram_alloc(rdev);
189 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
190 void r100_enable_bm(struct radeon_device *rdev)
193 /* Enable bus mastering */
194 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
195 WREG32(RADEON_BUS_CNTL, tmp);
198 int r100_pci_gart_enable(struct radeon_device *rdev)
202 radeon_gart_restore(rdev);
203 /* discard memory request outside of configured range */
204 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
205 WREG32(RADEON_AIC_CNTL, tmp);
206 /* set address range for PCI address translate */
207 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
208 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
209 /* set PCI GART page-table base address */
210 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
211 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
212 WREG32(RADEON_AIC_CNTL, tmp);
213 r100_pci_gart_tlb_flush(rdev);
214 rdev->gart.ready = true;
218 void r100_pci_gart_disable(struct radeon_device *rdev)
222 /* discard memory request outside of configured range */
223 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
224 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
225 WREG32(RADEON_AIC_LO_ADDR, 0);
226 WREG32(RADEON_AIC_HI_ADDR, 0);
229 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
231 if (i < 0 || i > rdev->gart.num_gpu_pages) {
234 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
238 void r100_pci_gart_fini(struct radeon_device *rdev)
240 radeon_gart_fini(rdev);
241 r100_pci_gart_disable(rdev);
242 radeon_gart_table_ram_free(rdev);
245 int r100_irq_set(struct radeon_device *rdev)
249 if (!rdev->irq.installed) {
250 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
251 WREG32(R_000040_GEN_INT_CNTL, 0);
254 if (rdev->irq.sw_int) {
255 tmp |= RADEON_SW_INT_ENABLE;
257 if (rdev->irq.crtc_vblank_int[0]) {
258 tmp |= RADEON_CRTC_VBLANK_MASK;
260 if (rdev->irq.crtc_vblank_int[1]) {
261 tmp |= RADEON_CRTC2_VBLANK_MASK;
263 if (rdev->irq.hpd[0]) {
264 tmp |= RADEON_FP_DETECT_MASK;
266 if (rdev->irq.hpd[1]) {
267 tmp |= RADEON_FP2_DETECT_MASK;
269 WREG32(RADEON_GEN_INT_CNTL, tmp);
273 void r100_irq_disable(struct radeon_device *rdev)
277 WREG32(R_000040_GEN_INT_CNTL, 0);
278 /* Wait and acknowledge irq */
280 tmp = RREG32(R_000044_GEN_INT_STATUS);
281 WREG32(R_000044_GEN_INT_STATUS, tmp);
284 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
286 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
287 uint32_t irq_mask = RADEON_SW_INT_TEST |
288 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
289 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
292 WREG32(RADEON_GEN_INT_STATUS, irqs);
294 return irqs & irq_mask;
297 int r100_irq_process(struct radeon_device *rdev)
299 uint32_t status, msi_rearm;
300 bool queue_hotplug = false;
302 status = r100_irq_ack(rdev);
306 if (rdev->shutdown) {
311 if (status & RADEON_SW_INT_TEST) {
312 radeon_fence_process(rdev);
314 /* Vertical blank interrupts */
315 if (status & RADEON_CRTC_VBLANK_STAT) {
316 drm_handle_vblank(rdev->ddev, 0);
317 rdev->pm.vblank_sync = true;
318 wake_up(&rdev->irq.vblank_queue);
320 if (status & RADEON_CRTC2_VBLANK_STAT) {
321 drm_handle_vblank(rdev->ddev, 1);
322 rdev->pm.vblank_sync = true;
323 wake_up(&rdev->irq.vblank_queue);
325 if (status & RADEON_FP_DETECT_STAT) {
326 queue_hotplug = true;
329 if (status & RADEON_FP2_DETECT_STAT) {
330 queue_hotplug = true;
333 status = r100_irq_ack(rdev);
336 queue_work(rdev->wq, &rdev->hotplug_work);
337 if (rdev->msi_enabled) {
338 switch (rdev->family) {
341 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
342 WREG32(RADEON_AIC_CNTL, msi_rearm);
343 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
346 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
347 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
348 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
355 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
358 return RREG32(RADEON_CRTC_CRNT_FRAME);
360 return RREG32(RADEON_CRTC2_CRNT_FRAME);
363 /* Who ever call radeon_fence_emit should call ring_lock and ask
364 * for enough space (today caller are ib schedule and buffer move) */
365 void r100_fence_ring_emit(struct radeon_device *rdev,
366 struct radeon_fence *fence)
368 /* We have to make sure that caches are flushed before
369 * CPU might read something from VRAM. */
370 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
371 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
372 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
373 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
374 /* Wait until IDLE & CLEAN */
375 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
376 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
377 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
378 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
379 RADEON_HDP_READ_BUFFER_INVALIDATE);
380 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
381 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
382 /* Emit fence sequence & fire IRQ */
383 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
384 radeon_ring_write(rdev, fence->seq);
385 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
386 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
389 int r100_wb_init(struct radeon_device *rdev)
393 if (rdev->wb.wb_obj == NULL) {
394 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
395 RADEON_GEM_DOMAIN_GTT,
398 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
401 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
402 if (unlikely(r != 0))
404 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
407 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
408 radeon_bo_unreserve(rdev->wb.wb_obj);
411 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
412 radeon_bo_unreserve(rdev->wb.wb_obj);
414 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
418 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
419 WREG32(R_00070C_CP_RB_RPTR_ADDR,
420 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
421 WREG32(R_000770_SCRATCH_UMSK, 0xff);
425 void r100_wb_disable(struct radeon_device *rdev)
427 WREG32(R_000770_SCRATCH_UMSK, 0);
430 void r100_wb_fini(struct radeon_device *rdev)
434 r100_wb_disable(rdev);
435 if (rdev->wb.wb_obj) {
436 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
437 if (unlikely(r != 0)) {
438 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
441 radeon_bo_kunmap(rdev->wb.wb_obj);
442 radeon_bo_unpin(rdev->wb.wb_obj);
443 radeon_bo_unreserve(rdev->wb.wb_obj);
444 radeon_bo_unref(&rdev->wb.wb_obj);
446 rdev->wb.wb_obj = NULL;
450 int r100_copy_blit(struct radeon_device *rdev,
454 struct radeon_fence *fence)
457 uint32_t stride_bytes = PAGE_SIZE;
459 uint32_t stride_pixels;
464 /* radeon limited to 16k stride */
465 stride_bytes &= 0x3fff;
466 /* radeon pitch is /64 */
467 pitch = stride_bytes / 64;
468 stride_pixels = stride_bytes / 4;
469 num_loops = DIV_ROUND_UP(num_pages, 8191);
471 /* Ask for enough room for blit + flush + fence */
472 ndw = 64 + (10 * num_loops);
473 r = radeon_ring_lock(rdev, ndw);
475 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
478 while (num_pages > 0) {
479 cur_pages = num_pages;
480 if (cur_pages > 8191) {
483 num_pages -= cur_pages;
485 /* pages are in Y direction - height
486 page width in X direction - width */
487 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
488 radeon_ring_write(rdev,
489 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
490 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
491 RADEON_GMC_SRC_CLIPPING |
492 RADEON_GMC_DST_CLIPPING |
493 RADEON_GMC_BRUSH_NONE |
494 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
495 RADEON_GMC_SRC_DATATYPE_COLOR |
497 RADEON_DP_SRC_SOURCE_MEMORY |
498 RADEON_GMC_CLR_CMP_CNTL_DIS |
499 RADEON_GMC_WR_MSK_DIS);
500 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
501 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
502 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
503 radeon_ring_write(rdev, 0);
504 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
505 radeon_ring_write(rdev, num_pages);
506 radeon_ring_write(rdev, num_pages);
507 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
509 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
510 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
511 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
512 radeon_ring_write(rdev,
513 RADEON_WAIT_2D_IDLECLEAN |
514 RADEON_WAIT_HOST_IDLECLEAN |
515 RADEON_WAIT_DMA_GUI_IDLE);
517 r = radeon_fence_emit(rdev, fence);
519 radeon_ring_unlock_commit(rdev);
523 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
528 for (i = 0; i < rdev->usec_timeout; i++) {
529 tmp = RREG32(R_000E40_RBBM_STATUS);
530 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
538 void r100_ring_start(struct radeon_device *rdev)
542 r = radeon_ring_lock(rdev, 2);
546 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
547 radeon_ring_write(rdev,
548 RADEON_ISYNC_ANY2D_IDLE3D |
549 RADEON_ISYNC_ANY3D_IDLE2D |
550 RADEON_ISYNC_WAIT_IDLEGUI |
551 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
552 radeon_ring_unlock_commit(rdev);
556 /* Load the microcode for the CP */
557 static int r100_cp_init_microcode(struct radeon_device *rdev)
559 struct platform_device *pdev;
560 const char *fw_name = NULL;
565 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
568 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
571 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
572 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
573 (rdev->family == CHIP_RS200)) {
574 DRM_INFO("Loading R100 Microcode\n");
575 fw_name = FIRMWARE_R100;
576 } else if ((rdev->family == CHIP_R200) ||
577 (rdev->family == CHIP_RV250) ||
578 (rdev->family == CHIP_RV280) ||
579 (rdev->family == CHIP_RS300)) {
580 DRM_INFO("Loading R200 Microcode\n");
581 fw_name = FIRMWARE_R200;
582 } else if ((rdev->family == CHIP_R300) ||
583 (rdev->family == CHIP_R350) ||
584 (rdev->family == CHIP_RV350) ||
585 (rdev->family == CHIP_RV380) ||
586 (rdev->family == CHIP_RS400) ||
587 (rdev->family == CHIP_RS480)) {
588 DRM_INFO("Loading R300 Microcode\n");
589 fw_name = FIRMWARE_R300;
590 } else if ((rdev->family == CHIP_R420) ||
591 (rdev->family == CHIP_R423) ||
592 (rdev->family == CHIP_RV410)) {
593 DRM_INFO("Loading R400 Microcode\n");
594 fw_name = FIRMWARE_R420;
595 } else if ((rdev->family == CHIP_RS690) ||
596 (rdev->family == CHIP_RS740)) {
597 DRM_INFO("Loading RS690/RS740 Microcode\n");
598 fw_name = FIRMWARE_RS690;
599 } else if (rdev->family == CHIP_RS600) {
600 DRM_INFO("Loading RS600 Microcode\n");
601 fw_name = FIRMWARE_RS600;
602 } else if ((rdev->family == CHIP_RV515) ||
603 (rdev->family == CHIP_R520) ||
604 (rdev->family == CHIP_RV530) ||
605 (rdev->family == CHIP_R580) ||
606 (rdev->family == CHIP_RV560) ||
607 (rdev->family == CHIP_RV570)) {
608 DRM_INFO("Loading R500 Microcode\n");
609 fw_name = FIRMWARE_R520;
612 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
613 platform_device_unregister(pdev);
615 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
617 } else if (rdev->me_fw->size % 8) {
619 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
620 rdev->me_fw->size, fw_name);
622 release_firmware(rdev->me_fw);
628 static void r100_cp_load_microcode(struct radeon_device *rdev)
630 const __be32 *fw_data;
633 if (r100_gui_wait_for_idle(rdev)) {
634 printk(KERN_WARNING "Failed to wait GUI idle while "
635 "programming pipes. Bad things might happen.\n");
639 size = rdev->me_fw->size / 4;
640 fw_data = (const __be32 *)&rdev->me_fw->data[0];
641 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
642 for (i = 0; i < size; i += 2) {
643 WREG32(RADEON_CP_ME_RAM_DATAH,
644 be32_to_cpup(&fw_data[i]));
645 WREG32(RADEON_CP_ME_RAM_DATAL,
646 be32_to_cpup(&fw_data[i + 1]));
651 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
656 unsigned pre_write_timer;
657 unsigned pre_write_limit;
658 unsigned indirect2_start;
659 unsigned indirect1_start;
663 if (r100_debugfs_cp_init(rdev)) {
664 DRM_ERROR("Failed to register debugfs file for CP !\n");
667 r = r100_cp_init_microcode(rdev);
669 DRM_ERROR("Failed to load firmware!\n");
674 /* Align ring size */
675 rb_bufsz = drm_order(ring_size / 8);
676 ring_size = (1 << (rb_bufsz + 1)) * 4;
677 r100_cp_load_microcode(rdev);
678 r = radeon_ring_init(rdev, ring_size);
682 /* Each time the cp read 1024 bytes (16 dword/quadword) update
683 * the rptr copy in system ram */
685 /* cp will read 128bytes at a time (4 dwords) */
687 rdev->cp.align_mask = 16 - 1;
688 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
689 pre_write_timer = 64;
690 /* Force CP_RB_WPTR write if written more than one time before the
694 /* Setup the cp cache like this (cache size is 96 dwords) :
698 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
699 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
700 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
701 * Idea being that most of the gpu cmd will be through indirect1 buffer
702 * so it gets the bigger cache.
704 indirect2_start = 80;
705 indirect1_start = 16;
707 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
708 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
709 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
710 REG_SET(RADEON_MAX_FETCH, max_fetch) |
711 RADEON_RB_NO_UPDATE);
713 tmp |= RADEON_BUF_SWAP_32BIT;
715 WREG32(RADEON_CP_RB_CNTL, tmp);
717 /* Set ring address */
718 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
719 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
720 /* Force read & write ptr to 0 */
721 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
722 WREG32(RADEON_CP_RB_RPTR_WR, 0);
723 WREG32(RADEON_CP_RB_WPTR, 0);
724 WREG32(RADEON_CP_RB_CNTL, tmp);
726 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
727 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
728 /* protect against crazy HW on resume */
729 rdev->cp.wptr &= rdev->cp.ptr_mask;
730 /* Set cp mode to bus mastering & enable cp*/
731 WREG32(RADEON_CP_CSQ_MODE,
732 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
733 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
735 WREG32(0x744, 0x00004D4D);
736 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
737 radeon_ring_start(rdev);
738 r = radeon_ring_test(rdev);
740 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
743 rdev->cp.ready = true;
747 void r100_cp_fini(struct radeon_device *rdev)
749 if (r100_cp_wait_for_idle(rdev)) {
750 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
753 r100_cp_disable(rdev);
754 radeon_ring_fini(rdev);
755 DRM_INFO("radeon: cp finalized\n");
758 void r100_cp_disable(struct radeon_device *rdev)
761 rdev->cp.ready = false;
762 WREG32(RADEON_CP_CSQ_MODE, 0);
763 WREG32(RADEON_CP_CSQ_CNTL, 0);
764 if (r100_gui_wait_for_idle(rdev)) {
765 printk(KERN_WARNING "Failed to wait GUI idle while "
766 "programming pipes. Bad things might happen.\n");
770 void r100_cp_commit(struct radeon_device *rdev)
772 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
773 (void)RREG32(RADEON_CP_RB_WPTR);
780 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
781 struct radeon_cs_packet *pkt,
782 const unsigned *auth, unsigned n,
783 radeon_packet0_check_t check)
792 /* Check that register fall into register range
793 * determined by the number of entry (n) in the
794 * safe register bitmap.
796 if (pkt->one_reg_wr) {
797 if ((reg >> 7) > n) {
801 if (((reg + (pkt->count << 2)) >> 7) > n) {
805 for (i = 0; i <= pkt->count; i++, idx++) {
807 m = 1 << ((reg >> 2) & 31);
809 r = check(p, pkt, idx, reg);
814 if (pkt->one_reg_wr) {
815 if (!(auth[j] & m)) {
825 void r100_cs_dump_packet(struct radeon_cs_parser *p,
826 struct radeon_cs_packet *pkt)
828 volatile uint32_t *ib;
834 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
835 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
840 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
841 * @parser: parser structure holding parsing context.
842 * @pkt: where to store packet informations
844 * Assume that chunk_ib_index is properly set. Will return -EINVAL
845 * if packet is bigger than remaining ib size. or if packets is unknown.
847 int r100_cs_packet_parse(struct radeon_cs_parser *p,
848 struct radeon_cs_packet *pkt,
851 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
854 if (idx >= ib_chunk->length_dw) {
855 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
856 idx, ib_chunk->length_dw);
859 header = radeon_get_ib_value(p, idx);
861 pkt->type = CP_PACKET_GET_TYPE(header);
862 pkt->count = CP_PACKET_GET_COUNT(header);
865 pkt->reg = CP_PACKET0_GET_REG(header);
866 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
869 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
875 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
878 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
879 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
880 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
887 * r100_cs_packet_next_vline() - parse userspace VLINE packet
888 * @parser: parser structure holding parsing context.
890 * Userspace sends a special sequence for VLINE waits.
891 * PACKET0 - VLINE_START_END + value
892 * PACKET0 - WAIT_UNTIL +_value
893 * RELOC (P3) - crtc_id in reloc.
895 * This function parses this and relocates the VLINE START END
896 * and WAIT UNTIL packets to the correct crtc.
897 * It also detects a switched off crtc and nulls out the
900 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
902 struct drm_mode_object *obj;
903 struct drm_crtc *crtc;
904 struct radeon_crtc *radeon_crtc;
905 struct radeon_cs_packet p3reloc, waitreloc;
908 uint32_t header, h_idx, reg;
909 volatile uint32_t *ib;
913 /* parse the wait until */
914 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
918 /* check its a wait until and only 1 count */
919 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
920 waitreloc.count != 0) {
921 DRM_ERROR("vline wait had illegal wait until segment\n");
926 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
927 DRM_ERROR("vline wait had illegal wait until\n");
932 /* jump over the NOP */
933 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
938 p->idx += waitreloc.count + 2;
939 p->idx += p3reloc.count + 2;
941 header = radeon_get_ib_value(p, h_idx);
942 crtc_id = radeon_get_ib_value(p, h_idx + 5);
943 reg = CP_PACKET0_GET_REG(header);
944 mutex_lock(&p->rdev->ddev->mode_config.mutex);
945 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
947 DRM_ERROR("cannot find crtc %d\n", crtc_id);
951 crtc = obj_to_crtc(obj);
952 radeon_crtc = to_radeon_crtc(crtc);
953 crtc_id = radeon_crtc->crtc_id;
955 if (!crtc->enabled) {
956 /* if the CRTC isn't enabled - we need to nop out the wait until */
957 ib[h_idx + 2] = PACKET2(0);
958 ib[h_idx + 3] = PACKET2(0);
959 } else if (crtc_id == 1) {
961 case AVIVO_D1MODE_VLINE_START_END:
962 header &= ~R300_CP_PACKET0_REG_MASK;
963 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
965 case RADEON_CRTC_GUI_TRIG_VLINE:
966 header &= ~R300_CP_PACKET0_REG_MASK;
967 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
970 DRM_ERROR("unknown crtc reloc\n");
975 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
978 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
983 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
984 * @parser: parser structure holding parsing context.
985 * @data: pointer to relocation data
986 * @offset_start: starting offset
987 * @offset_mask: offset mask (to align start offset on)
988 * @reloc: reloc informations
990 * Check next packet is relocation packet3, do bo validation and compute
991 * GPU offset using the provided start.
993 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
994 struct radeon_cs_reloc **cs_reloc)
996 struct radeon_cs_chunk *relocs_chunk;
997 struct radeon_cs_packet p3reloc;
1001 if (p->chunk_relocs_idx == -1) {
1002 DRM_ERROR("No relocation chunk !\n");
1006 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1007 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1011 p->idx += p3reloc.count + 2;
1012 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1013 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1015 r100_cs_dump_packet(p, &p3reloc);
1018 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1019 if (idx >= relocs_chunk->length_dw) {
1020 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1021 idx, relocs_chunk->length_dw);
1022 r100_cs_dump_packet(p, &p3reloc);
1025 /* FIXME: we assume reloc size is 4 dwords */
1026 *cs_reloc = p->relocs_ptr[(idx / 4)];
1030 static int r100_get_vtx_size(uint32_t vtx_fmt)
1034 /* ordered according to bits in spec */
1035 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1037 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1039 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1041 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1043 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1045 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1047 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1049 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1051 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1053 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1055 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1057 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1059 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1061 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1063 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1066 if (vtx_fmt & (0x7 << 15))
1067 vtx_size += (vtx_fmt >> 15) & 0x7;
1068 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1070 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1072 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1076 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1078 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1083 static int r100_packet0_check(struct radeon_cs_parser *p,
1084 struct radeon_cs_packet *pkt,
1085 unsigned idx, unsigned reg)
1087 struct radeon_cs_reloc *reloc;
1088 struct r100_cs_track *track;
1089 volatile uint32_t *ib;
1097 track = (struct r100_cs_track *)p->track;
1099 idx_value = radeon_get_ib_value(p, idx);
1102 case RADEON_CRTC_GUI_TRIG_VLINE:
1103 r = r100_cs_packet_parse_vline(p);
1105 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1107 r100_cs_dump_packet(p, pkt);
1111 /* FIXME: only allow PACKET3 blit? easier to check for out of
1113 case RADEON_DST_PITCH_OFFSET:
1114 case RADEON_SRC_PITCH_OFFSET:
1115 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1119 case RADEON_RB3D_DEPTHOFFSET:
1120 r = r100_cs_packet_next_reloc(p, &reloc);
1122 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1124 r100_cs_dump_packet(p, pkt);
1127 track->zb.robj = reloc->robj;
1128 track->zb.offset = idx_value;
1129 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1131 case RADEON_RB3D_COLOROFFSET:
1132 r = r100_cs_packet_next_reloc(p, &reloc);
1134 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1136 r100_cs_dump_packet(p, pkt);
1139 track->cb[0].robj = reloc->robj;
1140 track->cb[0].offset = idx_value;
1141 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1143 case RADEON_PP_TXOFFSET_0:
1144 case RADEON_PP_TXOFFSET_1:
1145 case RADEON_PP_TXOFFSET_2:
1146 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1147 r = r100_cs_packet_next_reloc(p, &reloc);
1149 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1151 r100_cs_dump_packet(p, pkt);
1154 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1155 track->textures[i].robj = reloc->robj;
1157 case RADEON_PP_CUBIC_OFFSET_T0_0:
1158 case RADEON_PP_CUBIC_OFFSET_T0_1:
1159 case RADEON_PP_CUBIC_OFFSET_T0_2:
1160 case RADEON_PP_CUBIC_OFFSET_T0_3:
1161 case RADEON_PP_CUBIC_OFFSET_T0_4:
1162 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1163 r = r100_cs_packet_next_reloc(p, &reloc);
1165 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1167 r100_cs_dump_packet(p, pkt);
1170 track->textures[0].cube_info[i].offset = idx_value;
1171 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1172 track->textures[0].cube_info[i].robj = reloc->robj;
1174 case RADEON_PP_CUBIC_OFFSET_T1_0:
1175 case RADEON_PP_CUBIC_OFFSET_T1_1:
1176 case RADEON_PP_CUBIC_OFFSET_T1_2:
1177 case RADEON_PP_CUBIC_OFFSET_T1_3:
1178 case RADEON_PP_CUBIC_OFFSET_T1_4:
1179 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1180 r = r100_cs_packet_next_reloc(p, &reloc);
1182 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1184 r100_cs_dump_packet(p, pkt);
1187 track->textures[1].cube_info[i].offset = idx_value;
1188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1189 track->textures[1].cube_info[i].robj = reloc->robj;
1191 case RADEON_PP_CUBIC_OFFSET_T2_0:
1192 case RADEON_PP_CUBIC_OFFSET_T2_1:
1193 case RADEON_PP_CUBIC_OFFSET_T2_2:
1194 case RADEON_PP_CUBIC_OFFSET_T2_3:
1195 case RADEON_PP_CUBIC_OFFSET_T2_4:
1196 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1197 r = r100_cs_packet_next_reloc(p, &reloc);
1199 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1201 r100_cs_dump_packet(p, pkt);
1204 track->textures[2].cube_info[i].offset = idx_value;
1205 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1206 track->textures[2].cube_info[i].robj = reloc->robj;
1208 case RADEON_RE_WIDTH_HEIGHT:
1209 track->maxy = ((idx_value >> 16) & 0x7FF);
1211 case RADEON_RB3D_COLORPITCH:
1212 r = r100_cs_packet_next_reloc(p, &reloc);
1214 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1216 r100_cs_dump_packet(p, pkt);
1220 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1221 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1222 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1223 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1225 tmp = idx_value & ~(0x7 << 16);
1229 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1231 case RADEON_RB3D_DEPTHPITCH:
1232 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1234 case RADEON_RB3D_CNTL:
1235 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1241 track->cb[0].cpp = 1;
1246 track->cb[0].cpp = 2;
1249 track->cb[0].cpp = 4;
1252 DRM_ERROR("Invalid color buffer format (%d) !\n",
1253 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1256 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1258 case RADEON_RB3D_ZSTENCILCNTL:
1259 switch (idx_value & 0xf) {
1275 case RADEON_RB3D_ZPASS_ADDR:
1276 r = r100_cs_packet_next_reloc(p, &reloc);
1278 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1280 r100_cs_dump_packet(p, pkt);
1283 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1285 case RADEON_PP_CNTL:
1287 uint32_t temp = idx_value >> 4;
1288 for (i = 0; i < track->num_texture; i++)
1289 track->textures[i].enabled = !!(temp & (1 << i));
1292 case RADEON_SE_VF_CNTL:
1293 track->vap_vf_cntl = idx_value;
1295 case RADEON_SE_VTX_FMT:
1296 track->vtx_size = r100_get_vtx_size(idx_value);
1298 case RADEON_PP_TEX_SIZE_0:
1299 case RADEON_PP_TEX_SIZE_1:
1300 case RADEON_PP_TEX_SIZE_2:
1301 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1302 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1303 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1305 case RADEON_PP_TEX_PITCH_0:
1306 case RADEON_PP_TEX_PITCH_1:
1307 case RADEON_PP_TEX_PITCH_2:
1308 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1309 track->textures[i].pitch = idx_value + 32;
1311 case RADEON_PP_TXFILTER_0:
1312 case RADEON_PP_TXFILTER_1:
1313 case RADEON_PP_TXFILTER_2:
1314 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1315 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1316 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1317 tmp = (idx_value >> 23) & 0x7;
1318 if (tmp == 2 || tmp == 6)
1319 track->textures[i].roundup_w = false;
1320 tmp = (idx_value >> 27) & 0x7;
1321 if (tmp == 2 || tmp == 6)
1322 track->textures[i].roundup_h = false;
1324 case RADEON_PP_TXFORMAT_0:
1325 case RADEON_PP_TXFORMAT_1:
1326 case RADEON_PP_TXFORMAT_2:
1327 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1328 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1329 track->textures[i].use_pitch = 1;
1331 track->textures[i].use_pitch = 0;
1332 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1333 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1335 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1336 track->textures[i].tex_coord_type = 2;
1337 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1338 case RADEON_TXFORMAT_I8:
1339 case RADEON_TXFORMAT_RGB332:
1340 case RADEON_TXFORMAT_Y8:
1341 track->textures[i].cpp = 1;
1343 case RADEON_TXFORMAT_AI88:
1344 case RADEON_TXFORMAT_ARGB1555:
1345 case RADEON_TXFORMAT_RGB565:
1346 case RADEON_TXFORMAT_ARGB4444:
1347 case RADEON_TXFORMAT_VYUY422:
1348 case RADEON_TXFORMAT_YVYU422:
1349 case RADEON_TXFORMAT_SHADOW16:
1350 case RADEON_TXFORMAT_LDUDV655:
1351 case RADEON_TXFORMAT_DUDV88:
1352 track->textures[i].cpp = 2;
1354 case RADEON_TXFORMAT_ARGB8888:
1355 case RADEON_TXFORMAT_RGBA8888:
1356 case RADEON_TXFORMAT_SHADOW32:
1357 case RADEON_TXFORMAT_LDUDUV8888:
1358 track->textures[i].cpp = 4;
1360 case RADEON_TXFORMAT_DXT1:
1361 track->textures[i].cpp = 1;
1362 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1364 case RADEON_TXFORMAT_DXT23:
1365 case RADEON_TXFORMAT_DXT45:
1366 track->textures[i].cpp = 1;
1367 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1370 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1371 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1373 case RADEON_PP_CUBIC_FACES_0:
1374 case RADEON_PP_CUBIC_FACES_1:
1375 case RADEON_PP_CUBIC_FACES_2:
1377 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1378 for (face = 0; face < 4; face++) {
1379 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1380 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1384 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1391 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1392 struct radeon_cs_packet *pkt,
1393 struct radeon_bo *robj)
1398 value = radeon_get_ib_value(p, idx + 2);
1399 if ((value + 1) > radeon_bo_size(robj)) {
1400 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1401 "(need %u have %lu) !\n",
1403 radeon_bo_size(robj));
1409 static int r100_packet3_check(struct radeon_cs_parser *p,
1410 struct radeon_cs_packet *pkt)
1412 struct radeon_cs_reloc *reloc;
1413 struct r100_cs_track *track;
1415 volatile uint32_t *ib;
1420 track = (struct r100_cs_track *)p->track;
1421 switch (pkt->opcode) {
1422 case PACKET3_3D_LOAD_VBPNTR:
1423 r = r100_packet3_load_vbpntr(p, pkt, idx);
1427 case PACKET3_INDX_BUFFER:
1428 r = r100_cs_packet_next_reloc(p, &reloc);
1430 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1431 r100_cs_dump_packet(p, pkt);
1434 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1435 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1441 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1442 r = r100_cs_packet_next_reloc(p, &reloc);
1444 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1445 r100_cs_dump_packet(p, pkt);
1448 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1449 track->num_arrays = 1;
1450 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1452 track->arrays[0].robj = reloc->robj;
1453 track->arrays[0].esize = track->vtx_size;
1455 track->max_indx = radeon_get_ib_value(p, idx+1);
1457 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1458 track->immd_dwords = pkt->count - 1;
1459 r = r100_cs_track_check(p->rdev, track);
1463 case PACKET3_3D_DRAW_IMMD:
1464 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1465 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1468 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1469 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1470 track->immd_dwords = pkt->count - 1;
1471 r = r100_cs_track_check(p->rdev, track);
1475 /* triggers drawing using in-packet vertex data */
1476 case PACKET3_3D_DRAW_IMMD_2:
1477 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1478 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1481 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1482 track->immd_dwords = pkt->count;
1483 r = r100_cs_track_check(p->rdev, track);
1487 /* triggers drawing using in-packet vertex data */
1488 case PACKET3_3D_DRAW_VBUF_2:
1489 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1490 r = r100_cs_track_check(p->rdev, track);
1494 /* triggers drawing of vertex buffers setup elsewhere */
1495 case PACKET3_3D_DRAW_INDX_2:
1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1497 r = r100_cs_track_check(p->rdev, track);
1501 /* triggers drawing using indices to vertex buffer */
1502 case PACKET3_3D_DRAW_VBUF:
1503 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1504 r = r100_cs_track_check(p->rdev, track);
1508 /* triggers drawing of vertex buffers setup elsewhere */
1509 case PACKET3_3D_DRAW_INDX:
1510 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1511 r = r100_cs_track_check(p->rdev, track);
1515 /* triggers drawing using indices to vertex buffer */
1519 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1525 int r100_cs_parse(struct radeon_cs_parser *p)
1527 struct radeon_cs_packet pkt;
1528 struct r100_cs_track *track;
1531 track = kzalloc(sizeof(*track), GFP_KERNEL);
1532 r100_cs_track_clear(p->rdev, track);
1535 r = r100_cs_packet_parse(p, &pkt, p->idx);
1539 p->idx += pkt.count + 2;
1542 if (p->rdev->family >= CHIP_R200)
1543 r = r100_cs_parse_packet0(p, &pkt,
1544 p->rdev->config.r100.reg_safe_bm,
1545 p->rdev->config.r100.reg_safe_bm_size,
1546 &r200_packet0_check);
1548 r = r100_cs_parse_packet0(p, &pkt,
1549 p->rdev->config.r100.reg_safe_bm,
1550 p->rdev->config.r100.reg_safe_bm_size,
1551 &r100_packet0_check);
1556 r = r100_packet3_check(p, &pkt);
1559 DRM_ERROR("Unknown packet type %d !\n",
1566 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1572 * Global GPU functions
1574 void r100_errata(struct radeon_device *rdev)
1576 rdev->pll_errata = 0;
1578 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1579 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1582 if (rdev->family == CHIP_RV100 ||
1583 rdev->family == CHIP_RS100 ||
1584 rdev->family == CHIP_RS200) {
1585 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1589 /* Wait for vertical sync on primary CRTC */
1590 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1592 uint32_t crtc_gen_cntl, tmp;
1595 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1596 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1597 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1600 /* Clear the CRTC_VBLANK_SAVE bit */
1601 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1602 for (i = 0; i < rdev->usec_timeout; i++) {
1603 tmp = RREG32(RADEON_CRTC_STATUS);
1604 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1611 /* Wait for vertical sync on secondary CRTC */
1612 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1614 uint32_t crtc2_gen_cntl, tmp;
1617 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1618 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1619 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1622 /* Clear the CRTC_VBLANK_SAVE bit */
1623 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1624 for (i = 0; i < rdev->usec_timeout; i++) {
1625 tmp = RREG32(RADEON_CRTC2_STATUS);
1626 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1633 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1638 for (i = 0; i < rdev->usec_timeout; i++) {
1639 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1648 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1653 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1654 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1655 " Bad things might happen.\n");
1657 for (i = 0; i < rdev->usec_timeout; i++) {
1658 tmp = RREG32(RADEON_RBBM_STATUS);
1659 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1667 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1672 for (i = 0; i < rdev->usec_timeout; i++) {
1673 /* read MC_STATUS */
1674 tmp = RREG32(RADEON_MC_STATUS);
1675 if (tmp & RADEON_MC_IDLE) {
1683 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1685 lockup->last_cp_rptr = cp->rptr;
1686 lockup->last_jiffies = jiffies;
1690 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1691 * @rdev: radeon device structure
1692 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1693 * @cp: radeon_cp structure holding CP information
1695 * We don't need to initialize the lockup tracking information as we will either
1696 * have CP rptr to a different value of jiffies wrap around which will force
1697 * initialization of the lockup tracking informations.
1699 * A possible false positivie is if we get call after while and last_cp_rptr ==
1700 * the current CP rptr, even if it's unlikely it might happen. To avoid this
1701 * if the elapsed time since last call is bigger than 2 second than we return
1702 * false and update the tracking information. Due to this the caller must call
1703 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1704 * the fencing code should be cautious about that.
1706 * Caller should write to the ring to force CP to do something so we don't get
1707 * false positive when CP is just gived nothing to do.
1710 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1712 unsigned long cjiffies, elapsed;
1715 if (!time_after(cjiffies, lockup->last_jiffies)) {
1716 /* likely a wrap around */
1717 lockup->last_cp_rptr = cp->rptr;
1718 lockup->last_jiffies = jiffies;
1721 if (cp->rptr != lockup->last_cp_rptr) {
1722 /* CP is still working no lockup */
1723 lockup->last_cp_rptr = cp->rptr;
1724 lockup->last_jiffies = jiffies;
1727 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
1728 if (elapsed >= 3000) {
1729 /* very likely the improbable case where current
1730 * rptr is equal to last recorded, a while ago, rptr
1731 * this is more likely a false positive update tracking
1732 * information which should force us to be recall at
1735 lockup->last_cp_rptr = cp->rptr;
1736 lockup->last_jiffies = jiffies;
1739 if (elapsed >= 1000) {
1740 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
1743 /* give a chance to the GPU ... */
1747 bool r100_gpu_is_lockup(struct radeon_device *rdev)
1752 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
1753 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1754 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
1757 /* force CP activities */
1758 r = radeon_ring_lock(rdev, 2);
1761 radeon_ring_write(rdev, 0x80000000);
1762 radeon_ring_write(rdev, 0x80000000);
1763 radeon_ring_unlock_commit(rdev);
1765 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1766 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1769 void r100_bm_disable(struct radeon_device *rdev)
1773 /* disable bus mastering */
1774 tmp = RREG32(R_000030_BUS_CNTL);
1775 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
1777 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
1779 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
1780 tmp = RREG32(RADEON_BUS_CNTL);
1782 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
1783 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
1787 int r100_asic_reset(struct radeon_device *rdev)
1789 struct r100_mc_save save;
1792 r100_mc_stop(rdev, &save);
1793 status = RREG32(R_000E40_RBBM_STATUS);
1794 if (!G_000E40_GUI_ACTIVE(status)) {
1797 status = RREG32(R_000E40_RBBM_STATUS);
1798 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1800 WREG32(RADEON_CP_CSQ_CNTL, 0);
1801 tmp = RREG32(RADEON_CP_RB_CNTL);
1802 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1803 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1804 WREG32(RADEON_CP_RB_WPTR, 0);
1805 WREG32(RADEON_CP_RB_CNTL, tmp);
1806 /* save PCI state */
1807 pci_save_state(rdev->pdev);
1808 /* disable bus mastering */
1809 r100_bm_disable(rdev);
1810 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
1811 S_0000F0_SOFT_RESET_RE(1) |
1812 S_0000F0_SOFT_RESET_PP(1) |
1813 S_0000F0_SOFT_RESET_RB(1));
1814 RREG32(R_0000F0_RBBM_SOFT_RESET);
1816 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1818 status = RREG32(R_000E40_RBBM_STATUS);
1819 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1821 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
1822 RREG32(R_0000F0_RBBM_SOFT_RESET);
1824 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
1826 status = RREG32(R_000E40_RBBM_STATUS);
1827 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1828 /* restore PCI & busmastering */
1829 pci_restore_state(rdev->pdev);
1830 r100_enable_bm(rdev);
1831 /* Check if GPU is idle */
1832 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
1833 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
1834 dev_err(rdev->dev, "failed to reset GPU\n");
1835 rdev->gpu_lockup = true;
1838 r100_mc_resume(rdev, &save);
1839 dev_info(rdev->dev, "GPU reset succeed\n");
1843 void r100_set_common_regs(struct radeon_device *rdev)
1845 struct drm_device *dev = rdev->ddev;
1846 bool force_dac2 = false;
1849 /* set these so they don't interfere with anything */
1850 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1851 WREG32(RADEON_SUBPIC_CNTL, 0);
1852 WREG32(RADEON_VIPH_CONTROL, 0);
1853 WREG32(RADEON_I2C_CNTL_1, 0);
1854 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1855 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1856 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1858 /* always set up dac2 on rn50 and some rv100 as lots
1859 * of servers seem to wire it up to a VGA port but
1860 * don't report it in the bios connector
1863 switch (dev->pdev->device) {
1872 /* DELL triple head servers */
1873 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1874 ((dev->pdev->subsystem_device == 0x016c) ||
1875 (dev->pdev->subsystem_device == 0x016d) ||
1876 (dev->pdev->subsystem_device == 0x016e) ||
1877 (dev->pdev->subsystem_device == 0x016f) ||
1878 (dev->pdev->subsystem_device == 0x0170) ||
1879 (dev->pdev->subsystem_device == 0x017d) ||
1880 (dev->pdev->subsystem_device == 0x017e) ||
1881 (dev->pdev->subsystem_device == 0x0183) ||
1882 (dev->pdev->subsystem_device == 0x018a) ||
1883 (dev->pdev->subsystem_device == 0x019a)))
1889 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1890 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1891 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1893 /* For CRT on DAC2, don't turn it on if BIOS didn't
1894 enable it, even it's detected.
1897 /* force it to crtc0 */
1898 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1899 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1900 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1902 /* set up the TV DAC */
1903 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1904 RADEON_TV_DAC_STD_MASK |
1905 RADEON_TV_DAC_RDACPD |
1906 RADEON_TV_DAC_GDACPD |
1907 RADEON_TV_DAC_BDACPD |
1908 RADEON_TV_DAC_BGADJ_MASK |
1909 RADEON_TV_DAC_DACADJ_MASK);
1910 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1911 RADEON_TV_DAC_NHOLD |
1912 RADEON_TV_DAC_STD_PS2 |
1915 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1916 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1917 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1920 /* switch PM block to ACPI mode */
1921 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1922 tmp &= ~RADEON_PM_MODE_SEL;
1923 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1930 static void r100_vram_get_type(struct radeon_device *rdev)
1934 rdev->mc.vram_is_ddr = false;
1935 if (rdev->flags & RADEON_IS_IGP)
1936 rdev->mc.vram_is_ddr = true;
1937 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1938 rdev->mc.vram_is_ddr = true;
1939 if ((rdev->family == CHIP_RV100) ||
1940 (rdev->family == CHIP_RS100) ||
1941 (rdev->family == CHIP_RS200)) {
1942 tmp = RREG32(RADEON_MEM_CNTL);
1943 if (tmp & RV100_HALF_MODE) {
1944 rdev->mc.vram_width = 32;
1946 rdev->mc.vram_width = 64;
1948 if (rdev->flags & RADEON_SINGLE_CRTC) {
1949 rdev->mc.vram_width /= 4;
1950 rdev->mc.vram_is_ddr = true;
1952 } else if (rdev->family <= CHIP_RV280) {
1953 tmp = RREG32(RADEON_MEM_CNTL);
1954 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1955 rdev->mc.vram_width = 128;
1957 rdev->mc.vram_width = 64;
1961 rdev->mc.vram_width = 128;
1965 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1970 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1972 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1973 * that is has the 2nd generation multifunction PCI interface
1975 if (rdev->family == CHIP_RV280 ||
1976 rdev->family >= CHIP_RV350) {
1977 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1978 ~RADEON_HDP_APER_CNTL);
1979 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1980 return aper_size * 2;
1983 /* Older cards have all sorts of funny issues to deal with. First
1984 * check if it's a multifunction card by reading the PCI config
1985 * header type... Limit those to one aperture size
1987 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1989 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1990 DRM_INFO("Limiting VRAM to one aperture\n");
1994 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1995 * have set it up. We don't write this as it's broken on some ASICs but
1996 * we expect the BIOS to have done the right thing (might be too optimistic...)
1998 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1999 return aper_size * 2;
2003 void r100_vram_init_sizes(struct radeon_device *rdev)
2005 u64 config_aper_size;
2007 /* work out accessible VRAM */
2008 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2009 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2010 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2011 /* FIXME we don't use the second aperture yet when we could use it */
2012 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2013 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2014 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2015 if (rdev->flags & RADEON_IS_IGP) {
2017 /* read NB_TOM to get the amount of ram stolen for the GPU */
2018 tom = RREG32(RADEON_NB_TOM);
2019 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2020 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2021 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2023 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2024 /* Some production boards of m6 will report 0
2027 if (rdev->mc.real_vram_size == 0) {
2028 rdev->mc.real_vram_size = 8192 * 1024;
2029 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2031 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2032 * Novell bug 204882 + along with lots of ubuntu ones
2034 if (config_aper_size > rdev->mc.real_vram_size)
2035 rdev->mc.mc_vram_size = config_aper_size;
2037 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2039 /* FIXME remove this once we support unmappable VRAM */
2040 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
2041 rdev->mc.mc_vram_size = rdev->mc.aper_size;
2042 rdev->mc.real_vram_size = rdev->mc.aper_size;
2046 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2050 temp = RREG32(RADEON_CONFIG_CNTL);
2051 if (state == false) {
2057 WREG32(RADEON_CONFIG_CNTL, temp);
2060 void r100_mc_init(struct radeon_device *rdev)
2064 r100_vram_get_type(rdev);
2065 r100_vram_init_sizes(rdev);
2066 base = rdev->mc.aper_base;
2067 if (rdev->flags & RADEON_IS_IGP)
2068 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2069 radeon_vram_location(rdev, &rdev->mc, base);
2070 if (!(rdev->flags & RADEON_IS_AGP))
2071 radeon_gtt_location(rdev, &rdev->mc);
2072 radeon_update_bandwidth_info(rdev);
2077 * Indirect registers accessor
2079 void r100_pll_errata_after_index(struct radeon_device *rdev)
2081 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2084 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2085 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2088 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2090 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2091 * or the chip could hang on a subsequent access
2093 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2097 /* This function is required to workaround a hardware bug in some (all?)
2098 * revisions of the R300. This workaround should be called after every
2099 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2100 * may not be correct.
2102 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2105 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2106 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2107 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2108 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2109 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2113 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2117 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2118 r100_pll_errata_after_index(rdev);
2119 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2120 r100_pll_errata_after_data(rdev);
2124 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2126 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2127 r100_pll_errata_after_index(rdev);
2128 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2129 r100_pll_errata_after_data(rdev);
2132 void r100_set_safe_registers(struct radeon_device *rdev)
2134 if (ASIC_IS_RN50(rdev)) {
2135 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2136 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2137 } else if (rdev->family < CHIP_R200) {
2138 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2139 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2141 r200_set_safe_registers(rdev);
2148 #if defined(CONFIG_DEBUG_FS)
2149 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2151 struct drm_info_node *node = (struct drm_info_node *) m->private;
2152 struct drm_device *dev = node->minor->dev;
2153 struct radeon_device *rdev = dev->dev_private;
2154 uint32_t reg, value;
2157 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2158 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2159 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2160 for (i = 0; i < 64; i++) {
2161 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2162 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2163 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2164 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2165 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2170 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2172 struct drm_info_node *node = (struct drm_info_node *) m->private;
2173 struct drm_device *dev = node->minor->dev;
2174 struct radeon_device *rdev = dev->dev_private;
2176 unsigned count, i, j;
2178 radeon_ring_free_size(rdev);
2179 rdp = RREG32(RADEON_CP_RB_RPTR);
2180 wdp = RREG32(RADEON_CP_RB_WPTR);
2181 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2182 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2183 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2184 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2185 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2186 seq_printf(m, "%u dwords in ring\n", count);
2187 for (j = 0; j <= count; j++) {
2188 i = (rdp + j) & rdev->cp.ptr_mask;
2189 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2195 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2197 struct drm_info_node *node = (struct drm_info_node *) m->private;
2198 struct drm_device *dev = node->minor->dev;
2199 struct radeon_device *rdev = dev->dev_private;
2200 uint32_t csq_stat, csq2_stat, tmp;
2201 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2204 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2205 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2206 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2207 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2208 r_rptr = (csq_stat >> 0) & 0x3ff;
2209 r_wptr = (csq_stat >> 10) & 0x3ff;
2210 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2211 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2212 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2213 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2214 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2215 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2216 seq_printf(m, "Ring rptr %u\n", r_rptr);
2217 seq_printf(m, "Ring wptr %u\n", r_wptr);
2218 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2219 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2220 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2221 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2222 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2223 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2224 seq_printf(m, "Ring fifo:\n");
2225 for (i = 0; i < 256; i++) {
2226 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2227 tmp = RREG32(RADEON_CP_CSQ_DATA);
2228 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2230 seq_printf(m, "Indirect1 fifo:\n");
2231 for (i = 256; i <= 512; i++) {
2232 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2233 tmp = RREG32(RADEON_CP_CSQ_DATA);
2234 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2236 seq_printf(m, "Indirect2 fifo:\n");
2237 for (i = 640; i < ib1_wptr; i++) {
2238 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2239 tmp = RREG32(RADEON_CP_CSQ_DATA);
2240 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2245 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2247 struct drm_info_node *node = (struct drm_info_node *) m->private;
2248 struct drm_device *dev = node->minor->dev;
2249 struct radeon_device *rdev = dev->dev_private;
2252 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2253 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2254 tmp = RREG32(RADEON_MC_FB_LOCATION);
2255 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2256 tmp = RREG32(RADEON_BUS_CNTL);
2257 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2258 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2259 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2260 tmp = RREG32(RADEON_AGP_BASE);
2261 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2262 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2263 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2264 tmp = RREG32(0x01D0);
2265 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2266 tmp = RREG32(RADEON_AIC_LO_ADDR);
2267 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2268 tmp = RREG32(RADEON_AIC_HI_ADDR);
2269 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2270 tmp = RREG32(0x01E4);
2271 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2275 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2276 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2279 static struct drm_info_list r100_debugfs_cp_list[] = {
2280 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2281 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2284 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2285 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2289 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2291 #if defined(CONFIG_DEBUG_FS)
2292 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2298 int r100_debugfs_cp_init(struct radeon_device *rdev)
2300 #if defined(CONFIG_DEBUG_FS)
2301 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2307 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2309 #if defined(CONFIG_DEBUG_FS)
2310 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2316 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2317 uint32_t tiling_flags, uint32_t pitch,
2318 uint32_t offset, uint32_t obj_size)
2320 int surf_index = reg * 16;
2323 /* r100/r200 divide by 16 */
2324 if (rdev->family < CHIP_R300)
2329 if (rdev->family <= CHIP_RS200) {
2330 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2331 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2332 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2333 if (tiling_flags & RADEON_TILING_MACRO)
2334 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2335 } else if (rdev->family <= CHIP_RV280) {
2336 if (tiling_flags & (RADEON_TILING_MACRO))
2337 flags |= R200_SURF_TILE_COLOR_MACRO;
2338 if (tiling_flags & RADEON_TILING_MICRO)
2339 flags |= R200_SURF_TILE_COLOR_MICRO;
2341 if (tiling_flags & RADEON_TILING_MACRO)
2342 flags |= R300_SURF_TILE_MACRO;
2343 if (tiling_flags & RADEON_TILING_MICRO)
2344 flags |= R300_SURF_TILE_MICRO;
2347 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2348 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2349 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2350 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2352 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2353 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2354 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2355 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2359 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2361 int surf_index = reg * 16;
2362 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2365 void r100_bandwidth_update(struct radeon_device *rdev)
2367 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2368 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2369 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2370 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2371 fixed20_12 memtcas_ff[8] = {
2380 fixed20_12 memtcas_rs480_ff[8] = {
2390 fixed20_12 memtcas2_ff[8] = {
2400 fixed20_12 memtrbs[8] = {
2410 fixed20_12 memtrbs_r4xx[8] = {
2420 fixed20_12 min_mem_eff;
2421 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2422 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2423 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2424 disp_drain_rate2, read_return_rate;
2425 fixed20_12 time_disp1_drop_priority;
2427 int cur_size = 16; /* in octawords */
2428 int critical_point = 0, critical_point2;
2429 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2430 int stop_req, max_stop_req;
2431 struct drm_display_mode *mode1 = NULL;
2432 struct drm_display_mode *mode2 = NULL;
2433 uint32_t pixel_bytes1 = 0;
2434 uint32_t pixel_bytes2 = 0;
2436 radeon_update_display_priority(rdev);
2438 if (rdev->mode_info.crtcs[0]->base.enabled) {
2439 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2440 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2442 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2443 if (rdev->mode_info.crtcs[1]->base.enabled) {
2444 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2445 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2449 min_mem_eff.full = rfixed_const_8(0);
2451 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2452 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2453 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2454 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2455 /* check crtc enables */
2457 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2459 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2460 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2464 * determine is there is enough bw for current mode
2466 sclk_ff = rdev->pm.sclk;
2467 mclk_ff = rdev->pm.mclk;
2469 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2470 temp_ff.full = rfixed_const(temp);
2471 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2475 peak_disp_bw.full = 0;
2477 temp_ff.full = rfixed_const(1000);
2478 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2479 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2480 temp_ff.full = rfixed_const(pixel_bytes1);
2481 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2484 temp_ff.full = rfixed_const(1000);
2485 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2486 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2487 temp_ff.full = rfixed_const(pixel_bytes2);
2488 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2491 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2492 if (peak_disp_bw.full >= mem_bw.full) {
2493 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2494 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2497 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2498 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2499 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2500 mem_trcd = ((temp >> 2) & 0x3) + 1;
2501 mem_trp = ((temp & 0x3)) + 1;
2502 mem_tras = ((temp & 0x70) >> 4) + 1;
2503 } else if (rdev->family == CHIP_R300 ||
2504 rdev->family == CHIP_R350) { /* r300, r350 */
2505 mem_trcd = (temp & 0x7) + 1;
2506 mem_trp = ((temp >> 8) & 0x7) + 1;
2507 mem_tras = ((temp >> 11) & 0xf) + 4;
2508 } else if (rdev->family == CHIP_RV350 ||
2509 rdev->family <= CHIP_RV380) {
2511 mem_trcd = (temp & 0x7) + 3;
2512 mem_trp = ((temp >> 8) & 0x7) + 3;
2513 mem_tras = ((temp >> 11) & 0xf) + 6;
2514 } else if (rdev->family == CHIP_R420 ||
2515 rdev->family == CHIP_R423 ||
2516 rdev->family == CHIP_RV410) {
2518 mem_trcd = (temp & 0xf) + 3;
2521 mem_trp = ((temp >> 8) & 0xf) + 3;
2524 mem_tras = ((temp >> 12) & 0x1f) + 6;
2527 } else { /* RV200, R200 */
2528 mem_trcd = (temp & 0x7) + 1;
2529 mem_trp = ((temp >> 8) & 0x7) + 1;
2530 mem_tras = ((temp >> 12) & 0xf) + 4;
2533 trcd_ff.full = rfixed_const(mem_trcd);
2534 trp_ff.full = rfixed_const(mem_trp);
2535 tras_ff.full = rfixed_const(mem_tras);
2537 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2538 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2539 data = (temp & (7 << 20)) >> 20;
2540 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2541 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2542 tcas_ff = memtcas_rs480_ff[data];
2544 tcas_ff = memtcas_ff[data];
2546 tcas_ff = memtcas2_ff[data];
2548 if (rdev->family == CHIP_RS400 ||
2549 rdev->family == CHIP_RS480) {
2550 /* extra cas latency stored in bits 23-25 0-4 clocks */
2551 data = (temp >> 23) & 0x7;
2553 tcas_ff.full += rfixed_const(data);
2556 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2557 /* on the R300, Tcas is included in Trbs.
2559 temp = RREG32(RADEON_MEM_CNTL);
2560 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2562 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2563 temp = RREG32(R300_MC_IND_INDEX);
2564 temp &= ~R300_MC_IND_ADDR_MASK;
2565 temp |= R300_MC_READ_CNTL_CD_mcind;
2566 WREG32(R300_MC_IND_INDEX, temp);
2567 temp = RREG32(R300_MC_IND_DATA);
2568 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2570 temp = RREG32(R300_MC_READ_CNTL_AB);
2571 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2574 temp = RREG32(R300_MC_READ_CNTL_AB);
2575 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2577 if (rdev->family == CHIP_RV410 ||
2578 rdev->family == CHIP_R420 ||
2579 rdev->family == CHIP_R423)
2580 trbs_ff = memtrbs_r4xx[data];
2582 trbs_ff = memtrbs[data];
2583 tcas_ff.full += trbs_ff.full;
2586 sclk_eff_ff.full = sclk_ff.full;
2588 if (rdev->flags & RADEON_IS_AGP) {
2589 fixed20_12 agpmode_ff;
2590 agpmode_ff.full = rfixed_const(radeon_agpmode);
2591 temp_ff.full = rfixed_const_666(16);
2592 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2594 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2596 if (ASIC_IS_R300(rdev)) {
2597 sclk_delay_ff.full = rfixed_const(250);
2599 if ((rdev->family == CHIP_RV100) ||
2600 rdev->flags & RADEON_IS_IGP) {
2601 if (rdev->mc.vram_is_ddr)
2602 sclk_delay_ff.full = rfixed_const(41);
2604 sclk_delay_ff.full = rfixed_const(33);
2606 if (rdev->mc.vram_width == 128)
2607 sclk_delay_ff.full = rfixed_const(57);
2609 sclk_delay_ff.full = rfixed_const(41);
2613 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2615 if (rdev->mc.vram_is_ddr) {
2616 if (rdev->mc.vram_width == 32) {
2617 k1.full = rfixed_const(40);
2620 k1.full = rfixed_const(20);
2624 k1.full = rfixed_const(40);
2628 temp_ff.full = rfixed_const(2);
2629 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2630 temp_ff.full = rfixed_const(c);
2631 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2632 temp_ff.full = rfixed_const(4);
2633 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2634 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2635 mc_latency_mclk.full += k1.full;
2637 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2638 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2641 HW cursor time assuming worst case of full size colour cursor.
2643 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2644 temp_ff.full += trcd_ff.full;
2645 if (temp_ff.full < tras_ff.full)
2646 temp_ff.full = tras_ff.full;
2647 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2649 temp_ff.full = rfixed_const(cur_size);
2650 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2652 Find the total latency for the display data.
2654 disp_latency_overhead.full = rfixed_const(8);
2655 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2656 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2657 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2659 if (mc_latency_mclk.full > mc_latency_sclk.full)
2660 disp_latency.full = mc_latency_mclk.full;
2662 disp_latency.full = mc_latency_sclk.full;
2664 /* setup Max GRPH_STOP_REQ default value */
2665 if (ASIC_IS_RV100(rdev))
2666 max_stop_req = 0x5c;
2668 max_stop_req = 0x7c;
2672 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2673 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2675 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2677 if (stop_req > max_stop_req)
2678 stop_req = max_stop_req;
2681 Find the drain rate of the display buffer.
2683 temp_ff.full = rfixed_const((16/pixel_bytes1));
2684 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2687 Find the critical point of the display buffer.
2689 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2690 crit_point_ff.full += rfixed_const_half(0);
2692 critical_point = rfixed_trunc(crit_point_ff);
2694 if (rdev->disp_priority == 2) {
2699 The critical point should never be above max_stop_req-4. Setting
2700 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2702 if (max_stop_req - critical_point < 4)
2705 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2706 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2707 critical_point = 0x10;
2710 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2711 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2712 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2713 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2714 if ((rdev->family == CHIP_R350) &&
2715 (stop_req > 0x15)) {
2718 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2719 temp |= RADEON_GRPH_BUFFER_SIZE;
2720 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2721 RADEON_GRPH_CRITICAL_AT_SOF |
2722 RADEON_GRPH_STOP_CNTL);
2724 Write the result into the register.
2726 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2727 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2730 if ((rdev->family == CHIP_RS400) ||
2731 (rdev->family == CHIP_RS480)) {
2732 /* attempt to program RS400 disp regs correctly ??? */
2733 temp = RREG32(RS400_DISP1_REG_CNTL);
2734 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2735 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2736 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2737 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2738 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2739 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2740 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2741 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2742 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2743 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2744 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2748 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2749 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2750 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2755 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2757 if (stop_req > max_stop_req)
2758 stop_req = max_stop_req;
2761 Find the drain rate of the display buffer.
2763 temp_ff.full = rfixed_const((16/pixel_bytes2));
2764 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2766 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2767 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2768 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2769 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2770 if ((rdev->family == CHIP_R350) &&
2771 (stop_req > 0x15)) {
2774 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2775 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2776 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2777 RADEON_GRPH_CRITICAL_AT_SOF |
2778 RADEON_GRPH_STOP_CNTL);
2780 if ((rdev->family == CHIP_RS100) ||
2781 (rdev->family == CHIP_RS200))
2782 critical_point2 = 0;
2784 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2785 temp_ff.full = rfixed_const(temp);
2786 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2787 if (sclk_ff.full < temp_ff.full)
2788 temp_ff.full = sclk_ff.full;
2790 read_return_rate.full = temp_ff.full;
2793 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2794 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2796 time_disp1_drop_priority.full = 0;
2798 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2799 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2800 crit_point_ff.full += rfixed_const_half(0);
2802 critical_point2 = rfixed_trunc(crit_point_ff);
2804 if (rdev->disp_priority == 2) {
2805 critical_point2 = 0;
2808 if (max_stop_req - critical_point2 < 4)
2809 critical_point2 = 0;
2813 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2814 /* some R300 cards have problem with this set to 0 */
2815 critical_point2 = 0x10;
2818 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2819 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2821 if ((rdev->family == CHIP_RS400) ||
2822 (rdev->family == CHIP_RS480)) {
2824 /* attempt to program RS400 disp2 regs correctly ??? */
2825 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2826 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2827 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2828 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2829 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2830 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2831 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2832 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2833 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2834 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2835 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2836 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2838 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2839 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2840 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2841 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2844 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2845 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2849 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2851 DRM_ERROR("pitch %d\n", t->pitch);
2852 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2853 DRM_ERROR("width %d\n", t->width);
2854 DRM_ERROR("width_11 %d\n", t->width_11);
2855 DRM_ERROR("height %d\n", t->height);
2856 DRM_ERROR("height_11 %d\n", t->height_11);
2857 DRM_ERROR("num levels %d\n", t->num_levels);
2858 DRM_ERROR("depth %d\n", t->txdepth);
2859 DRM_ERROR("bpp %d\n", t->cpp);
2860 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2861 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2862 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2863 DRM_ERROR("compress format %d\n", t->compress_format);
2866 static int r100_cs_track_cube(struct radeon_device *rdev,
2867 struct r100_cs_track *track, unsigned idx)
2869 unsigned face, w, h;
2870 struct radeon_bo *cube_robj;
2873 for (face = 0; face < 5; face++) {
2874 cube_robj = track->textures[idx].cube_info[face].robj;
2875 w = track->textures[idx].cube_info[face].width;
2876 h = track->textures[idx].cube_info[face].height;
2879 size *= track->textures[idx].cpp;
2881 size += track->textures[idx].cube_info[face].offset;
2883 if (size > radeon_bo_size(cube_robj)) {
2884 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2885 size, radeon_bo_size(cube_robj));
2886 r100_cs_track_texture_print(&track->textures[idx]);
2893 static int r100_track_compress_size(int compress_format, int w, int h)
2895 int block_width, block_height, block_bytes;
2896 int wblocks, hblocks;
2903 switch (compress_format) {
2904 case R100_TRACK_COMP_DXT1:
2909 case R100_TRACK_COMP_DXT35:
2915 hblocks = (h + block_height - 1) / block_height;
2916 wblocks = (w + block_width - 1) / block_width;
2917 if (wblocks < min_wblocks)
2918 wblocks = min_wblocks;
2919 sz = wblocks * hblocks * block_bytes;
2923 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2924 struct r100_cs_track *track)
2926 struct radeon_bo *robj;
2928 unsigned u, i, w, h, d;
2931 for (u = 0; u < track->num_texture; u++) {
2932 if (!track->textures[u].enabled)
2934 robj = track->textures[u].robj;
2936 DRM_ERROR("No texture bound to unit %u\n", u);
2940 for (i = 0; i <= track->textures[u].num_levels; i++) {
2941 if (track->textures[u].use_pitch) {
2942 if (rdev->family < CHIP_R300)
2943 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2945 w = track->textures[u].pitch / (1 << i);
2947 w = track->textures[u].width;
2948 if (rdev->family >= CHIP_RV515)
2949 w |= track->textures[u].width_11;
2951 if (track->textures[u].roundup_w)
2952 w = roundup_pow_of_two(w);
2954 h = track->textures[u].height;
2955 if (rdev->family >= CHIP_RV515)
2956 h |= track->textures[u].height_11;
2958 if (track->textures[u].roundup_h)
2959 h = roundup_pow_of_two(h);
2960 if (track->textures[u].tex_coord_type == 1) {
2961 d = (1 << track->textures[u].txdepth) / (1 << i);
2967 if (track->textures[u].compress_format) {
2969 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2970 /* compressed textures are block based */
2974 size *= track->textures[u].cpp;
2976 switch (track->textures[u].tex_coord_type) {
2981 if (track->separate_cube) {
2982 ret = r100_cs_track_cube(rdev, track, u);
2989 DRM_ERROR("Invalid texture coordinate type %u for unit "
2990 "%u\n", track->textures[u].tex_coord_type, u);
2993 if (size > radeon_bo_size(robj)) {
2994 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2995 "%lu\n", u, size, radeon_bo_size(robj));
2996 r100_cs_track_texture_print(&track->textures[u]);
3003 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3010 for (i = 0; i < track->num_cb; i++) {
3011 if (track->cb[i].robj == NULL) {
3012 if (!(track->fastfill || track->color_channel_mask ||
3013 track->blend_read_enable)) {
3016 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3019 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3020 size += track->cb[i].offset;
3021 if (size > radeon_bo_size(track->cb[i].robj)) {
3022 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3023 "(need %lu have %lu) !\n", i, size,
3024 radeon_bo_size(track->cb[i].robj));
3025 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3026 i, track->cb[i].pitch, track->cb[i].cpp,
3027 track->cb[i].offset, track->maxy);
3031 if (track->z_enabled) {
3032 if (track->zb.robj == NULL) {
3033 DRM_ERROR("[drm] No buffer for z buffer !\n");
3036 size = track->zb.pitch * track->zb.cpp * track->maxy;
3037 size += track->zb.offset;
3038 if (size > radeon_bo_size(track->zb.robj)) {
3039 DRM_ERROR("[drm] Buffer too small for z buffer "
3040 "(need %lu have %lu) !\n", size,
3041 radeon_bo_size(track->zb.robj));
3042 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3043 track->zb.pitch, track->zb.cpp,
3044 track->zb.offset, track->maxy);
3048 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3049 if (track->vap_vf_cntl & (1 << 14)) {
3050 nverts = track->vap_alt_nverts;
3052 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3054 switch (prim_walk) {
3056 for (i = 0; i < track->num_arrays; i++) {
3057 size = track->arrays[i].esize * track->max_indx * 4;
3058 if (track->arrays[i].robj == NULL) {
3059 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3060 "bound\n", prim_walk, i);
3063 if (size > radeon_bo_size(track->arrays[i].robj)) {
3064 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3065 "need %lu dwords have %lu dwords\n",
3066 prim_walk, i, size >> 2,
3067 radeon_bo_size(track->arrays[i].robj)
3069 DRM_ERROR("Max indices %u\n", track->max_indx);
3075 for (i = 0; i < track->num_arrays; i++) {
3076 size = track->arrays[i].esize * (nverts - 1) * 4;
3077 if (track->arrays[i].robj == NULL) {
3078 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3079 "bound\n", prim_walk, i);
3082 if (size > radeon_bo_size(track->arrays[i].robj)) {
3083 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3084 "need %lu dwords have %lu dwords\n",
3085 prim_walk, i, size >> 2,
3086 radeon_bo_size(track->arrays[i].robj)
3093 size = track->vtx_size * nverts;
3094 if (size != track->immd_dwords) {
3095 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3096 track->immd_dwords, size);
3097 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3098 nverts, track->vtx_size);
3103 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3107 return r100_cs_track_texture_check(rdev, track);
3110 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3114 if (rdev->family < CHIP_R300) {
3116 if (rdev->family <= CHIP_RS200)
3117 track->num_texture = 3;
3119 track->num_texture = 6;
3121 track->separate_cube = 1;
3124 track->num_texture = 16;
3126 track->separate_cube = 0;
3129 for (i = 0; i < track->num_cb; i++) {
3130 track->cb[i].robj = NULL;
3131 track->cb[i].pitch = 8192;
3132 track->cb[i].cpp = 16;
3133 track->cb[i].offset = 0;
3135 track->z_enabled = true;
3136 track->zb.robj = NULL;
3137 track->zb.pitch = 8192;
3139 track->zb.offset = 0;
3140 track->vtx_size = 0x7F;
3141 track->immd_dwords = 0xFFFFFFFFUL;
3142 track->num_arrays = 11;
3143 track->max_indx = 0x00FFFFFFUL;
3144 for (i = 0; i < track->num_arrays; i++) {
3145 track->arrays[i].robj = NULL;
3146 track->arrays[i].esize = 0x7F;
3148 for (i = 0; i < track->num_texture; i++) {
3149 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3150 track->textures[i].pitch = 16536;
3151 track->textures[i].width = 16536;
3152 track->textures[i].height = 16536;
3153 track->textures[i].width_11 = 1 << 11;
3154 track->textures[i].height_11 = 1 << 11;
3155 track->textures[i].num_levels = 12;
3156 if (rdev->family <= CHIP_RS200) {
3157 track->textures[i].tex_coord_type = 0;
3158 track->textures[i].txdepth = 0;
3160 track->textures[i].txdepth = 16;
3161 track->textures[i].tex_coord_type = 1;
3163 track->textures[i].cpp = 64;
3164 track->textures[i].robj = NULL;
3165 /* CS IB emission code makes sure texture unit are disabled */
3166 track->textures[i].enabled = false;
3167 track->textures[i].roundup_w = true;
3168 track->textures[i].roundup_h = true;
3169 if (track->separate_cube)
3170 for (face = 0; face < 5; face++) {
3171 track->textures[i].cube_info[face].robj = NULL;
3172 track->textures[i].cube_info[face].width = 16536;
3173 track->textures[i].cube_info[face].height = 16536;
3174 track->textures[i].cube_info[face].offset = 0;
3179 int r100_ring_test(struct radeon_device *rdev)
3186 r = radeon_scratch_get(rdev, &scratch);
3188 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3191 WREG32(scratch, 0xCAFEDEAD);
3192 r = radeon_ring_lock(rdev, 2);
3194 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3195 radeon_scratch_free(rdev, scratch);
3198 radeon_ring_write(rdev, PACKET0(scratch, 0));
3199 radeon_ring_write(rdev, 0xDEADBEEF);
3200 radeon_ring_unlock_commit(rdev);
3201 for (i = 0; i < rdev->usec_timeout; i++) {
3202 tmp = RREG32(scratch);
3203 if (tmp == 0xDEADBEEF) {
3208 if (i < rdev->usec_timeout) {
3209 DRM_INFO("ring test succeeded in %d usecs\n", i);
3211 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3215 radeon_scratch_free(rdev, scratch);
3219 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3221 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3222 radeon_ring_write(rdev, ib->gpu_addr);
3223 radeon_ring_write(rdev, ib->length_dw);
3226 int r100_ib_test(struct radeon_device *rdev)
3228 struct radeon_ib *ib;
3234 r = radeon_scratch_get(rdev, &scratch);
3236 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3239 WREG32(scratch, 0xCAFEDEAD);
3240 r = radeon_ib_get(rdev, &ib);
3244 ib->ptr[0] = PACKET0(scratch, 0);
3245 ib->ptr[1] = 0xDEADBEEF;
3246 ib->ptr[2] = PACKET2(0);
3247 ib->ptr[3] = PACKET2(0);
3248 ib->ptr[4] = PACKET2(0);
3249 ib->ptr[5] = PACKET2(0);
3250 ib->ptr[6] = PACKET2(0);
3251 ib->ptr[7] = PACKET2(0);
3253 r = radeon_ib_schedule(rdev, ib);
3255 radeon_scratch_free(rdev, scratch);
3256 radeon_ib_free(rdev, &ib);
3259 r = radeon_fence_wait(ib->fence, false);
3263 for (i = 0; i < rdev->usec_timeout; i++) {
3264 tmp = RREG32(scratch);
3265 if (tmp == 0xDEADBEEF) {
3270 if (i < rdev->usec_timeout) {
3271 DRM_INFO("ib test succeeded in %u usecs\n", i);
3273 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3277 radeon_scratch_free(rdev, scratch);
3278 radeon_ib_free(rdev, &ib);
3282 void r100_ib_fini(struct radeon_device *rdev)
3284 radeon_ib_pool_fini(rdev);
3287 int r100_ib_init(struct radeon_device *rdev)
3291 r = radeon_ib_pool_init(rdev);
3293 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3297 r = r100_ib_test(rdev);
3299 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3306 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3308 /* Shutdown CP we shouldn't need to do that but better be safe than
3311 rdev->cp.ready = false;
3312 WREG32(R_000740_CP_CSQ_CNTL, 0);
3314 /* Save few CRTC registers */
3315 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3316 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3317 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3318 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3319 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3320 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3321 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3324 /* Disable VGA aperture access */
3325 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3326 /* Disable cursor, overlay, crtc */
3327 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3328 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3329 S_000054_CRTC_DISPLAY_DIS(1));
3330 WREG32(R_000050_CRTC_GEN_CNTL,
3331 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3332 S_000050_CRTC_DISP_REQ_EN_B(1));
3333 WREG32(R_000420_OV0_SCALE_CNTL,
3334 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3335 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3336 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3337 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3338 S_000360_CUR2_LOCK(1));
3339 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3340 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3341 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3342 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3343 WREG32(R_000360_CUR2_OFFSET,
3344 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3348 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3350 /* Update base address for crtc */
3351 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3352 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3353 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3355 /* Restore CRTC registers */
3356 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3357 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3358 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3359 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3360 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3364 void r100_vga_render_disable(struct radeon_device *rdev)
3368 tmp = RREG8(R_0003C2_GENMO_WT);
3369 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3372 static void r100_debugfs(struct radeon_device *rdev)
3376 r = r100_debugfs_mc_info_init(rdev);
3378 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3381 static void r100_mc_program(struct radeon_device *rdev)
3383 struct r100_mc_save save;
3385 /* Stops all mc clients */
3386 r100_mc_stop(rdev, &save);
3387 if (rdev->flags & RADEON_IS_AGP) {
3388 WREG32(R_00014C_MC_AGP_LOCATION,
3389 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3390 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3391 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3392 if (rdev->family > CHIP_RV200)
3393 WREG32(R_00015C_AGP_BASE_2,
3394 upper_32_bits(rdev->mc.agp_base) & 0xff);
3396 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3397 WREG32(R_000170_AGP_BASE, 0);
3398 if (rdev->family > CHIP_RV200)
3399 WREG32(R_00015C_AGP_BASE_2, 0);
3401 /* Wait for mc idle */
3402 if (r100_mc_wait_for_idle(rdev))
3403 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3404 /* Program MC, should be a 32bits limited address space */
3405 WREG32(R_000148_MC_FB_LOCATION,
3406 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3407 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3408 r100_mc_resume(rdev, &save);
3411 void r100_clock_startup(struct radeon_device *rdev)
3415 if (radeon_dynclks != -1 && radeon_dynclks)
3416 radeon_legacy_set_clock_gating(rdev, 1);
3417 /* We need to force on some of the block */
3418 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3419 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3420 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3421 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3422 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3425 static int r100_startup(struct radeon_device *rdev)
3429 /* set common regs */
3430 r100_set_common_regs(rdev);
3432 r100_mc_program(rdev);
3434 r100_clock_startup(rdev);
3435 /* Initialize GPU configuration (# pipes, ...) */
3436 // r100_gpu_init(rdev);
3437 /* Initialize GART (initialize after TTM so we can allocate
3438 * memory through TTM but finalize after TTM) */
3439 r100_enable_bm(rdev);
3440 if (rdev->flags & RADEON_IS_PCI) {
3441 r = r100_pci_gart_enable(rdev);
3447 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3448 /* 1M ring buffer */
3449 r = r100_cp_init(rdev, 1024 * 1024);
3451 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3454 r = r100_wb_init(rdev);
3456 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3457 r = r100_ib_init(rdev);
3459 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3465 int r100_resume(struct radeon_device *rdev)
3467 /* Make sur GART are not working */
3468 if (rdev->flags & RADEON_IS_PCI)
3469 r100_pci_gart_disable(rdev);
3470 /* Resume clock before doing reset */
3471 r100_clock_startup(rdev);
3472 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3473 if (radeon_asic_reset(rdev)) {
3474 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3475 RREG32(R_000E40_RBBM_STATUS),
3476 RREG32(R_0007C0_CP_STAT));
3479 radeon_combios_asic_init(rdev->ddev);
3480 /* Resume clock after posting */
3481 r100_clock_startup(rdev);
3482 /* Initialize surface registers */
3483 radeon_surface_init(rdev);
3484 return r100_startup(rdev);
3487 int r100_suspend(struct radeon_device *rdev)
3489 r100_cp_disable(rdev);
3490 r100_wb_disable(rdev);
3491 r100_irq_disable(rdev);
3492 if (rdev->flags & RADEON_IS_PCI)
3493 r100_pci_gart_disable(rdev);
3497 void r100_fini(struct radeon_device *rdev)
3499 radeon_pm_fini(rdev);
3503 radeon_gem_fini(rdev);
3504 if (rdev->flags & RADEON_IS_PCI)
3505 r100_pci_gart_fini(rdev);
3506 radeon_agp_fini(rdev);
3507 radeon_irq_kms_fini(rdev);
3508 radeon_fence_driver_fini(rdev);
3509 radeon_bo_fini(rdev);
3510 radeon_atombios_fini(rdev);
3515 int r100_init(struct radeon_device *rdev)
3519 /* Register debugfs file specific to this group of asics */
3522 r100_vga_render_disable(rdev);
3523 /* Initialize scratch registers */
3524 radeon_scratch_init(rdev);
3525 /* Initialize surface registers */
3526 radeon_surface_init(rdev);
3527 /* TODO: disable VGA need to use VGA request */
3529 if (!radeon_get_bios(rdev)) {
3530 if (ASIC_IS_AVIVO(rdev))
3533 if (rdev->is_atom_bios) {
3534 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3537 r = radeon_combios_init(rdev);
3541 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3542 if (radeon_asic_reset(rdev)) {
3544 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3545 RREG32(R_000E40_RBBM_STATUS),
3546 RREG32(R_0007C0_CP_STAT));
3548 /* check if cards are posted or not */
3549 if (radeon_boot_test_post_card(rdev) == false)
3551 /* Set asic errata */
3553 /* Initialize clocks */
3554 radeon_get_clock_info(rdev->ddev);
3555 /* Initialize power management */
3556 radeon_pm_init(rdev);
3557 /* initialize AGP */
3558 if (rdev->flags & RADEON_IS_AGP) {
3559 r = radeon_agp_init(rdev);
3561 radeon_agp_disable(rdev);
3564 /* initialize VRAM */
3567 r = radeon_fence_driver_init(rdev);
3570 r = radeon_irq_kms_init(rdev);
3573 /* Memory manager */
3574 r = radeon_bo_init(rdev);
3577 if (rdev->flags & RADEON_IS_PCI) {
3578 r = r100_pci_gart_init(rdev);
3582 r100_set_safe_registers(rdev);
3583 rdev->accel_working = true;
3584 r = r100_startup(rdev);
3586 /* Somethings want wront with the accel init stop accel */
3587 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3591 radeon_irq_kms_fini(rdev);
3592 if (rdev->flags & RADEON_IS_PCI)
3593 r100_pci_gart_fini(rdev);
3594 rdev->accel_working = false;