2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
39 #include <linux/firmware.h>
40 #include <linux/platform_device.h>
42 #include "r100_reg_safe.h"
43 #include "rn50_reg_safe.h"
46 #define FIRMWARE_R100 "radeon/R100_cp.bin"
47 #define FIRMWARE_R200 "radeon/R200_cp.bin"
48 #define FIRMWARE_R300 "radeon/R300_cp.bin"
49 #define FIRMWARE_R420 "radeon/R420_cp.bin"
50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52 #define FIRMWARE_R520 "radeon/R520_cp.bin"
54 MODULE_FIRMWARE(FIRMWARE_R100);
55 MODULE_FIRMWARE(FIRMWARE_R200);
56 MODULE_FIRMWARE(FIRMWARE_R300);
57 MODULE_FIRMWARE(FIRMWARE_R420);
58 MODULE_FIRMWARE(FIRMWARE_RS690);
59 MODULE_FIRMWARE(FIRMWARE_RS600);
60 MODULE_FIRMWARE(FIRMWARE_R520);
62 #include "r100_track.h"
64 /* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 /* hpd for digital panel detect/disconnect */
69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71 bool connected = false;
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
88 void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
92 bool connected = r100_hpd_sense(rdev, hpd);
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
116 void r100_hpd_init(struct radeon_device *rdev)
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
125 rdev->irq.hpd[0] = true;
128 rdev->irq.hpd[1] = true;
134 if (rdev->irq.installed)
138 void r100_hpd_fini(struct radeon_device *rdev)
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
147 rdev->irq.hpd[0] = false;
150 rdev->irq.hpd[1] = false;
161 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
169 int r100_pci_gart_init(struct radeon_device *rdev)
173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188 void r100_enable_bm(struct radeon_device *rdev)
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
196 int r100_pci_gart_enable(struct radeon_device *rdev)
200 /* discard memory request outside of configured range */
201 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
202 WREG32(RADEON_AIC_CNTL, tmp);
203 /* set address range for PCI address translate */
204 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
205 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
206 WREG32(RADEON_AIC_HI_ADDR, tmp);
207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
216 void r100_pci_gart_disable(struct radeon_device *rdev)
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
227 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
236 void r100_pci_gart_fini(struct radeon_device *rdev)
238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
243 int r100_irq_set(struct radeon_device *rdev)
247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
267 WREG32(RADEON_GEN_INT_CNTL, tmp);
271 void r100_irq_disable(struct radeon_device *rdev)
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
282 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
292 return irqs & irq_mask;
295 int r100_irq_process(struct radeon_device *rdev)
297 uint32_t status, msi_rearm;
298 bool queue_hotplug = false;
300 status = r100_irq_ack(rdev);
304 if (rdev->shutdown) {
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
316 if (status & RADEON_CRTC2_VBLANK_STAT) {
317 drm_handle_vblank(rdev->ddev, 1);
319 if (status & RADEON_FP_DETECT_STAT) {
320 queue_hotplug = true;
323 if (status & RADEON_FP2_DETECT_STAT) {
324 queue_hotplug = true;
327 status = r100_irq_ack(rdev);
330 queue_work(rdev->wq, &rdev->hotplug_work);
331 if (rdev->msi_enabled) {
332 switch (rdev->family) {
335 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
336 WREG32(RADEON_AIC_CNTL, msi_rearm);
337 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
340 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
341 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
342 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
349 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
352 return RREG32(RADEON_CRTC_CRNT_FRAME);
354 return RREG32(RADEON_CRTC2_CRNT_FRAME);
357 void r100_fence_ring_emit(struct radeon_device *rdev,
358 struct radeon_fence *fence)
360 /* Who ever call radeon_fence_emit should call ring_lock and ask
361 * for enough space (today caller are ib schedule and buffer move) */
362 /* Wait until IDLE & CLEAN */
363 radeon_ring_write(rdev, PACKET0(0x1720, 0));
364 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
365 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
366 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
367 RADEON_HDP_READ_BUFFER_INVALIDATE);
368 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
369 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
370 /* Emit fence sequence & fire IRQ */
371 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
372 radeon_ring_write(rdev, fence->seq);
373 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
374 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
377 int r100_wb_init(struct radeon_device *rdev)
381 if (rdev->wb.wb_obj == NULL) {
382 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
383 RADEON_GEM_DOMAIN_GTT,
386 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
389 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
390 if (unlikely(r != 0))
392 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
395 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
396 radeon_bo_unreserve(rdev->wb.wb_obj);
399 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
400 radeon_bo_unreserve(rdev->wb.wb_obj);
402 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
406 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
407 WREG32(R_00070C_CP_RB_RPTR_ADDR,
408 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
409 WREG32(R_000770_SCRATCH_UMSK, 0xff);
413 void r100_wb_disable(struct radeon_device *rdev)
415 WREG32(R_000770_SCRATCH_UMSK, 0);
418 void r100_wb_fini(struct radeon_device *rdev)
422 r100_wb_disable(rdev);
423 if (rdev->wb.wb_obj) {
424 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
425 if (unlikely(r != 0)) {
426 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
429 radeon_bo_kunmap(rdev->wb.wb_obj);
430 radeon_bo_unpin(rdev->wb.wb_obj);
431 radeon_bo_unreserve(rdev->wb.wb_obj);
432 radeon_bo_unref(&rdev->wb.wb_obj);
434 rdev->wb.wb_obj = NULL;
438 int r100_copy_blit(struct radeon_device *rdev,
442 struct radeon_fence *fence)
445 uint32_t stride_bytes = PAGE_SIZE;
447 uint32_t stride_pixels;
452 /* radeon limited to 16k stride */
453 stride_bytes &= 0x3fff;
454 /* radeon pitch is /64 */
455 pitch = stride_bytes / 64;
456 stride_pixels = stride_bytes / 4;
457 num_loops = DIV_ROUND_UP(num_pages, 8191);
459 /* Ask for enough room for blit + flush + fence */
460 ndw = 64 + (10 * num_loops);
461 r = radeon_ring_lock(rdev, ndw);
463 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
466 while (num_pages > 0) {
467 cur_pages = num_pages;
468 if (cur_pages > 8191) {
471 num_pages -= cur_pages;
473 /* pages are in Y direction - height
474 page width in X direction - width */
475 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
476 radeon_ring_write(rdev,
477 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
478 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
479 RADEON_GMC_SRC_CLIPPING |
480 RADEON_GMC_DST_CLIPPING |
481 RADEON_GMC_BRUSH_NONE |
482 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
483 RADEON_GMC_SRC_DATATYPE_COLOR |
485 RADEON_DP_SRC_SOURCE_MEMORY |
486 RADEON_GMC_CLR_CMP_CNTL_DIS |
487 RADEON_GMC_WR_MSK_DIS);
488 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
489 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
490 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
491 radeon_ring_write(rdev, 0);
492 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
493 radeon_ring_write(rdev, num_pages);
494 radeon_ring_write(rdev, num_pages);
495 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
497 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
498 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
499 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
500 radeon_ring_write(rdev,
501 RADEON_WAIT_2D_IDLECLEAN |
502 RADEON_WAIT_HOST_IDLECLEAN |
503 RADEON_WAIT_DMA_GUI_IDLE);
505 r = radeon_fence_emit(rdev, fence);
507 radeon_ring_unlock_commit(rdev);
511 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
526 void r100_ring_start(struct radeon_device *rdev)
530 r = radeon_ring_lock(rdev, 2);
534 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
535 radeon_ring_write(rdev,
536 RADEON_ISYNC_ANY2D_IDLE3D |
537 RADEON_ISYNC_ANY3D_IDLE2D |
538 RADEON_ISYNC_WAIT_IDLEGUI |
539 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
540 radeon_ring_unlock_commit(rdev);
544 /* Load the microcode for the CP */
545 static int r100_cp_init_microcode(struct radeon_device *rdev)
547 struct platform_device *pdev;
548 const char *fw_name = NULL;
553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
561 (rdev->family == CHIP_RS200)) {
562 DRM_INFO("Loading R100 Microcode\n");
563 fw_name = FIRMWARE_R100;
564 } else if ((rdev->family == CHIP_R200) ||
565 (rdev->family == CHIP_RV250) ||
566 (rdev->family == CHIP_RV280) ||
567 (rdev->family == CHIP_RS300)) {
568 DRM_INFO("Loading R200 Microcode\n");
569 fw_name = FIRMWARE_R200;
570 } else if ((rdev->family == CHIP_R300) ||
571 (rdev->family == CHIP_R350) ||
572 (rdev->family == CHIP_RV350) ||
573 (rdev->family == CHIP_RV380) ||
574 (rdev->family == CHIP_RS400) ||
575 (rdev->family == CHIP_RS480)) {
576 DRM_INFO("Loading R300 Microcode\n");
577 fw_name = FIRMWARE_R300;
578 } else if ((rdev->family == CHIP_R420) ||
579 (rdev->family == CHIP_R423) ||
580 (rdev->family == CHIP_RV410)) {
581 DRM_INFO("Loading R400 Microcode\n");
582 fw_name = FIRMWARE_R420;
583 } else if ((rdev->family == CHIP_RS690) ||
584 (rdev->family == CHIP_RS740)) {
585 DRM_INFO("Loading RS690/RS740 Microcode\n");
586 fw_name = FIRMWARE_RS690;
587 } else if (rdev->family == CHIP_RS600) {
588 DRM_INFO("Loading RS600 Microcode\n");
589 fw_name = FIRMWARE_RS600;
590 } else if ((rdev->family == CHIP_RV515) ||
591 (rdev->family == CHIP_R520) ||
592 (rdev->family == CHIP_RV530) ||
593 (rdev->family == CHIP_R580) ||
594 (rdev->family == CHIP_RV560) ||
595 (rdev->family == CHIP_RV570)) {
596 DRM_INFO("Loading R500 Microcode\n");
597 fw_name = FIRMWARE_R520;
600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
601 platform_device_unregister(pdev);
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
605 } else if (rdev->me_fw->size % 8) {
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
608 rdev->me_fw->size, fw_name);
610 release_firmware(rdev->me_fw);
616 static void r100_cp_load_microcode(struct radeon_device *rdev)
618 const __be32 *fw_data;
621 if (r100_gui_wait_for_idle(rdev)) {
622 printk(KERN_WARNING "Failed to wait GUI idle while "
623 "programming pipes. Bad things might happen.\n");
627 size = rdev->me_fw->size / 4;
628 fw_data = (const __be32 *)&rdev->me_fw->data[0];
629 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
630 for (i = 0; i < size; i += 2) {
631 WREG32(RADEON_CP_ME_RAM_DATAH,
632 be32_to_cpup(&fw_data[i]));
633 WREG32(RADEON_CP_ME_RAM_DATAL,
634 be32_to_cpup(&fw_data[i + 1]));
639 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
644 unsigned pre_write_timer;
645 unsigned pre_write_limit;
646 unsigned indirect2_start;
647 unsigned indirect1_start;
651 if (r100_debugfs_cp_init(rdev)) {
652 DRM_ERROR("Failed to register debugfs file for CP !\n");
655 tmp = RREG32(RADEON_CP_CSQ_STAT);
656 if ((tmp & (1 << 31))) {
657 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
658 WREG32(RADEON_CP_CSQ_MODE, 0);
659 WREG32(RADEON_CP_CSQ_CNTL, 0);
660 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
661 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
663 WREG32(RADEON_RBBM_SOFT_RESET, 0);
664 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
666 tmp = RREG32(RADEON_CP_CSQ_STAT);
667 if ((tmp & (1 << 31))) {
668 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
671 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
675 r = r100_cp_init_microcode(rdev);
677 DRM_ERROR("Failed to load firmware!\n");
682 /* Align ring size */
683 rb_bufsz = drm_order(ring_size / 8);
684 ring_size = (1 << (rb_bufsz + 1)) * 4;
685 r100_cp_load_microcode(rdev);
686 r = radeon_ring_init(rdev, ring_size);
690 /* Each time the cp read 1024 bytes (16 dword/quadword) update
691 * the rptr copy in system ram */
693 /* cp will read 128bytes at a time (4 dwords) */
695 rdev->cp.align_mask = 16 - 1;
696 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
697 pre_write_timer = 64;
698 /* Force CP_RB_WPTR write if written more than one time before the
702 /* Setup the cp cache like this (cache size is 96 dwords) :
706 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
707 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
708 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
709 * Idea being that most of the gpu cmd will be through indirect1 buffer
710 * so it gets the bigger cache.
712 indirect2_start = 80;
713 indirect1_start = 16;
715 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
716 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
717 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
718 REG_SET(RADEON_MAX_FETCH, max_fetch) |
719 RADEON_RB_NO_UPDATE);
721 tmp |= RADEON_BUF_SWAP_32BIT;
723 WREG32(RADEON_CP_RB_CNTL, tmp);
725 /* Set ring address */
726 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
727 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
728 /* Force read & write ptr to 0 */
729 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
730 WREG32(RADEON_CP_RB_RPTR_WR, 0);
731 WREG32(RADEON_CP_RB_WPTR, 0);
732 WREG32(RADEON_CP_RB_CNTL, tmp);
734 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
735 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
736 /* Set cp mode to bus mastering & enable cp*/
737 WREG32(RADEON_CP_CSQ_MODE,
738 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
739 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
741 WREG32(0x744, 0x00004D4D);
742 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
743 radeon_ring_start(rdev);
744 r = radeon_ring_test(rdev);
746 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
749 rdev->cp.ready = true;
753 void r100_cp_fini(struct radeon_device *rdev)
755 if (r100_cp_wait_for_idle(rdev)) {
756 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
759 r100_cp_disable(rdev);
760 radeon_ring_fini(rdev);
761 DRM_INFO("radeon: cp finalized\n");
764 void r100_cp_disable(struct radeon_device *rdev)
767 rdev->cp.ready = false;
768 WREG32(RADEON_CP_CSQ_MODE, 0);
769 WREG32(RADEON_CP_CSQ_CNTL, 0);
770 if (r100_gui_wait_for_idle(rdev)) {
771 printk(KERN_WARNING "Failed to wait GUI idle while "
772 "programming pipes. Bad things might happen.\n");
776 int r100_cp_reset(struct radeon_device *rdev)
782 reinit_cp = rdev->cp.ready;
783 rdev->cp.ready = false;
784 WREG32(RADEON_CP_CSQ_MODE, 0);
785 WREG32(RADEON_CP_CSQ_CNTL, 0);
786 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
787 (void)RREG32(RADEON_RBBM_SOFT_RESET);
789 WREG32(RADEON_RBBM_SOFT_RESET, 0);
790 /* Wait to prevent race in RBBM_STATUS */
792 for (i = 0; i < rdev->usec_timeout; i++) {
793 tmp = RREG32(RADEON_RBBM_STATUS);
794 if (!(tmp & (1 << 16))) {
795 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
798 return r100_cp_init(rdev, rdev->cp.ring_size);
804 tmp = RREG32(RADEON_RBBM_STATUS);
805 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
809 void r100_cp_commit(struct radeon_device *rdev)
811 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
812 (void)RREG32(RADEON_CP_RB_WPTR);
819 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
820 struct radeon_cs_packet *pkt,
821 const unsigned *auth, unsigned n,
822 radeon_packet0_check_t check)
831 /* Check that register fall into register range
832 * determined by the number of entry (n) in the
833 * safe register bitmap.
835 if (pkt->one_reg_wr) {
836 if ((reg >> 7) > n) {
840 if (((reg + (pkt->count << 2)) >> 7) > n) {
844 for (i = 0; i <= pkt->count; i++, idx++) {
846 m = 1 << ((reg >> 2) & 31);
848 r = check(p, pkt, idx, reg);
853 if (pkt->one_reg_wr) {
854 if (!(auth[j] & m)) {
864 void r100_cs_dump_packet(struct radeon_cs_parser *p,
865 struct radeon_cs_packet *pkt)
867 volatile uint32_t *ib;
873 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
874 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
879 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
880 * @parser: parser structure holding parsing context.
881 * @pkt: where to store packet informations
883 * Assume that chunk_ib_index is properly set. Will return -EINVAL
884 * if packet is bigger than remaining ib size. or if packets is unknown.
886 int r100_cs_packet_parse(struct radeon_cs_parser *p,
887 struct radeon_cs_packet *pkt,
890 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
893 if (idx >= ib_chunk->length_dw) {
894 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
895 idx, ib_chunk->length_dw);
898 header = radeon_get_ib_value(p, idx);
900 pkt->type = CP_PACKET_GET_TYPE(header);
901 pkt->count = CP_PACKET_GET_COUNT(header);
904 pkt->reg = CP_PACKET0_GET_REG(header);
905 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
908 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
914 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
917 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
918 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
919 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
926 * r100_cs_packet_next_vline() - parse userspace VLINE packet
927 * @parser: parser structure holding parsing context.
929 * Userspace sends a special sequence for VLINE waits.
930 * PACKET0 - VLINE_START_END + value
931 * PACKET0 - WAIT_UNTIL +_value
932 * RELOC (P3) - crtc_id in reloc.
934 * This function parses this and relocates the VLINE START END
935 * and WAIT UNTIL packets to the correct crtc.
936 * It also detects a switched off crtc and nulls out the
939 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
941 struct drm_mode_object *obj;
942 struct drm_crtc *crtc;
943 struct radeon_crtc *radeon_crtc;
944 struct radeon_cs_packet p3reloc, waitreloc;
947 uint32_t header, h_idx, reg;
948 volatile uint32_t *ib;
952 /* parse the wait until */
953 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
957 /* check its a wait until and only 1 count */
958 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
959 waitreloc.count != 0) {
960 DRM_ERROR("vline wait had illegal wait until segment\n");
965 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
966 DRM_ERROR("vline wait had illegal wait until\n");
971 /* jump over the NOP */
972 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
977 p->idx += waitreloc.count + 2;
978 p->idx += p3reloc.count + 2;
980 header = radeon_get_ib_value(p, h_idx);
981 crtc_id = radeon_get_ib_value(p, h_idx + 5);
982 reg = CP_PACKET0_GET_REG(header);
983 mutex_lock(&p->rdev->ddev->mode_config.mutex);
984 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
986 DRM_ERROR("cannot find crtc %d\n", crtc_id);
990 crtc = obj_to_crtc(obj);
991 radeon_crtc = to_radeon_crtc(crtc);
992 crtc_id = radeon_crtc->crtc_id;
994 if (!crtc->enabled) {
995 /* if the CRTC isn't enabled - we need to nop out the wait until */
996 ib[h_idx + 2] = PACKET2(0);
997 ib[h_idx + 3] = PACKET2(0);
998 } else if (crtc_id == 1) {
1000 case AVIVO_D1MODE_VLINE_START_END:
1001 header &= ~R300_CP_PACKET0_REG_MASK;
1002 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1004 case RADEON_CRTC_GUI_TRIG_VLINE:
1005 header &= ~R300_CP_PACKET0_REG_MASK;
1006 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1009 DRM_ERROR("unknown crtc reloc\n");
1014 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1017 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1022 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1023 * @parser: parser structure holding parsing context.
1024 * @data: pointer to relocation data
1025 * @offset_start: starting offset
1026 * @offset_mask: offset mask (to align start offset on)
1027 * @reloc: reloc informations
1029 * Check next packet is relocation packet3, do bo validation and compute
1030 * GPU offset using the provided start.
1032 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1033 struct radeon_cs_reloc **cs_reloc)
1035 struct radeon_cs_chunk *relocs_chunk;
1036 struct radeon_cs_packet p3reloc;
1040 if (p->chunk_relocs_idx == -1) {
1041 DRM_ERROR("No relocation chunk !\n");
1045 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1046 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1050 p->idx += p3reloc.count + 2;
1051 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1052 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1054 r100_cs_dump_packet(p, &p3reloc);
1057 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1058 if (idx >= relocs_chunk->length_dw) {
1059 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1060 idx, relocs_chunk->length_dw);
1061 r100_cs_dump_packet(p, &p3reloc);
1064 /* FIXME: we assume reloc size is 4 dwords */
1065 *cs_reloc = p->relocs_ptr[(idx / 4)];
1069 static int r100_get_vtx_size(uint32_t vtx_fmt)
1073 /* ordered according to bits in spec */
1074 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1076 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1078 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1080 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1105 if (vtx_fmt & (0x7 << 15))
1106 vtx_size += (vtx_fmt >> 15) & 0x7;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1122 static int r100_packet0_check(struct radeon_cs_parser *p,
1123 struct radeon_cs_packet *pkt,
1124 unsigned idx, unsigned reg)
1126 struct radeon_cs_reloc *reloc;
1127 struct r100_cs_track *track;
1128 volatile uint32_t *ib;
1136 track = (struct r100_cs_track *)p->track;
1138 idx_value = radeon_get_ib_value(p, idx);
1141 case RADEON_CRTC_GUI_TRIG_VLINE:
1142 r = r100_cs_packet_parse_vline(p);
1144 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1146 r100_cs_dump_packet(p, pkt);
1150 /* FIXME: only allow PACKET3 blit? easier to check for out of
1152 case RADEON_DST_PITCH_OFFSET:
1153 case RADEON_SRC_PITCH_OFFSET:
1154 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1158 case RADEON_RB3D_DEPTHOFFSET:
1159 r = r100_cs_packet_next_reloc(p, &reloc);
1161 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1163 r100_cs_dump_packet(p, pkt);
1166 track->zb.robj = reloc->robj;
1167 track->zb.offset = idx_value;
1168 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1170 case RADEON_RB3D_COLOROFFSET:
1171 r = r100_cs_packet_next_reloc(p, &reloc);
1173 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1175 r100_cs_dump_packet(p, pkt);
1178 track->cb[0].robj = reloc->robj;
1179 track->cb[0].offset = idx_value;
1180 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1182 case RADEON_PP_TXOFFSET_0:
1183 case RADEON_PP_TXOFFSET_1:
1184 case RADEON_PP_TXOFFSET_2:
1185 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1186 r = r100_cs_packet_next_reloc(p, &reloc);
1188 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1190 r100_cs_dump_packet(p, pkt);
1193 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1194 track->textures[i].robj = reloc->robj;
1196 case RADEON_PP_CUBIC_OFFSET_T0_0:
1197 case RADEON_PP_CUBIC_OFFSET_T0_1:
1198 case RADEON_PP_CUBIC_OFFSET_T0_2:
1199 case RADEON_PP_CUBIC_OFFSET_T0_3:
1200 case RADEON_PP_CUBIC_OFFSET_T0_4:
1201 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1202 r = r100_cs_packet_next_reloc(p, &reloc);
1204 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1206 r100_cs_dump_packet(p, pkt);
1209 track->textures[0].cube_info[i].offset = idx_value;
1210 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1211 track->textures[0].cube_info[i].robj = reloc->robj;
1213 case RADEON_PP_CUBIC_OFFSET_T1_0:
1214 case RADEON_PP_CUBIC_OFFSET_T1_1:
1215 case RADEON_PP_CUBIC_OFFSET_T1_2:
1216 case RADEON_PP_CUBIC_OFFSET_T1_3:
1217 case RADEON_PP_CUBIC_OFFSET_T1_4:
1218 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1219 r = r100_cs_packet_next_reloc(p, &reloc);
1221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1223 r100_cs_dump_packet(p, pkt);
1226 track->textures[1].cube_info[i].offset = idx_value;
1227 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1228 track->textures[1].cube_info[i].robj = reloc->robj;
1230 case RADEON_PP_CUBIC_OFFSET_T2_0:
1231 case RADEON_PP_CUBIC_OFFSET_T2_1:
1232 case RADEON_PP_CUBIC_OFFSET_T2_2:
1233 case RADEON_PP_CUBIC_OFFSET_T2_3:
1234 case RADEON_PP_CUBIC_OFFSET_T2_4:
1235 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1236 r = r100_cs_packet_next_reloc(p, &reloc);
1238 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1240 r100_cs_dump_packet(p, pkt);
1243 track->textures[2].cube_info[i].offset = idx_value;
1244 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1245 track->textures[2].cube_info[i].robj = reloc->robj;
1247 case RADEON_RE_WIDTH_HEIGHT:
1248 track->maxy = ((idx_value >> 16) & 0x7FF);
1250 case RADEON_RB3D_COLORPITCH:
1251 r = r100_cs_packet_next_reloc(p, &reloc);
1253 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1255 r100_cs_dump_packet(p, pkt);
1259 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1260 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1261 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1262 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1264 tmp = idx_value & ~(0x7 << 16);
1268 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1270 case RADEON_RB3D_DEPTHPITCH:
1271 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1273 case RADEON_RB3D_CNTL:
1274 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1280 track->cb[0].cpp = 1;
1285 track->cb[0].cpp = 2;
1288 track->cb[0].cpp = 4;
1291 DRM_ERROR("Invalid color buffer format (%d) !\n",
1292 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1295 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1297 case RADEON_RB3D_ZSTENCILCNTL:
1298 switch (idx_value & 0xf) {
1314 case RADEON_RB3D_ZPASS_ADDR:
1315 r = r100_cs_packet_next_reloc(p, &reloc);
1317 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1319 r100_cs_dump_packet(p, pkt);
1322 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1324 case RADEON_PP_CNTL:
1326 uint32_t temp = idx_value >> 4;
1327 for (i = 0; i < track->num_texture; i++)
1328 track->textures[i].enabled = !!(temp & (1 << i));
1331 case RADEON_SE_VF_CNTL:
1332 track->vap_vf_cntl = idx_value;
1334 case RADEON_SE_VTX_FMT:
1335 track->vtx_size = r100_get_vtx_size(idx_value);
1337 case RADEON_PP_TEX_SIZE_0:
1338 case RADEON_PP_TEX_SIZE_1:
1339 case RADEON_PP_TEX_SIZE_2:
1340 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1341 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1342 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1344 case RADEON_PP_TEX_PITCH_0:
1345 case RADEON_PP_TEX_PITCH_1:
1346 case RADEON_PP_TEX_PITCH_2:
1347 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1348 track->textures[i].pitch = idx_value + 32;
1350 case RADEON_PP_TXFILTER_0:
1351 case RADEON_PP_TXFILTER_1:
1352 case RADEON_PP_TXFILTER_2:
1353 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1354 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1355 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1356 tmp = (idx_value >> 23) & 0x7;
1357 if (tmp == 2 || tmp == 6)
1358 track->textures[i].roundup_w = false;
1359 tmp = (idx_value >> 27) & 0x7;
1360 if (tmp == 2 || tmp == 6)
1361 track->textures[i].roundup_h = false;
1363 case RADEON_PP_TXFORMAT_0:
1364 case RADEON_PP_TXFORMAT_1:
1365 case RADEON_PP_TXFORMAT_2:
1366 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1367 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1368 track->textures[i].use_pitch = 1;
1370 track->textures[i].use_pitch = 0;
1371 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1372 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1374 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1375 track->textures[i].tex_coord_type = 2;
1376 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1377 case RADEON_TXFORMAT_I8:
1378 case RADEON_TXFORMAT_RGB332:
1379 case RADEON_TXFORMAT_Y8:
1380 track->textures[i].cpp = 1;
1382 case RADEON_TXFORMAT_AI88:
1383 case RADEON_TXFORMAT_ARGB1555:
1384 case RADEON_TXFORMAT_RGB565:
1385 case RADEON_TXFORMAT_ARGB4444:
1386 case RADEON_TXFORMAT_VYUY422:
1387 case RADEON_TXFORMAT_YVYU422:
1388 case RADEON_TXFORMAT_SHADOW16:
1389 case RADEON_TXFORMAT_LDUDV655:
1390 case RADEON_TXFORMAT_DUDV88:
1391 track->textures[i].cpp = 2;
1393 case RADEON_TXFORMAT_ARGB8888:
1394 case RADEON_TXFORMAT_RGBA8888:
1395 case RADEON_TXFORMAT_SHADOW32:
1396 case RADEON_TXFORMAT_LDUDUV8888:
1397 track->textures[i].cpp = 4;
1399 case RADEON_TXFORMAT_DXT1:
1400 track->textures[i].cpp = 1;
1401 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1403 case RADEON_TXFORMAT_DXT23:
1404 case RADEON_TXFORMAT_DXT45:
1405 track->textures[i].cpp = 1;
1406 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1409 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1410 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1412 case RADEON_PP_CUBIC_FACES_0:
1413 case RADEON_PP_CUBIC_FACES_1:
1414 case RADEON_PP_CUBIC_FACES_2:
1416 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1417 for (face = 0; face < 4; face++) {
1418 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1419 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1423 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1430 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1431 struct radeon_cs_packet *pkt,
1432 struct radeon_bo *robj)
1437 value = radeon_get_ib_value(p, idx + 2);
1438 if ((value + 1) > radeon_bo_size(robj)) {
1439 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1440 "(need %u have %lu) !\n",
1442 radeon_bo_size(robj));
1448 static int r100_packet3_check(struct radeon_cs_parser *p,
1449 struct radeon_cs_packet *pkt)
1451 struct radeon_cs_reloc *reloc;
1452 struct r100_cs_track *track;
1454 volatile uint32_t *ib;
1459 track = (struct r100_cs_track *)p->track;
1460 switch (pkt->opcode) {
1461 case PACKET3_3D_LOAD_VBPNTR:
1462 r = r100_packet3_load_vbpntr(p, pkt, idx);
1466 case PACKET3_INDX_BUFFER:
1467 r = r100_cs_packet_next_reloc(p, &reloc);
1469 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1470 r100_cs_dump_packet(p, pkt);
1473 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1474 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1480 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1481 r = r100_cs_packet_next_reloc(p, &reloc);
1483 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1484 r100_cs_dump_packet(p, pkt);
1487 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1488 track->num_arrays = 1;
1489 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1491 track->arrays[0].robj = reloc->robj;
1492 track->arrays[0].esize = track->vtx_size;
1494 track->max_indx = radeon_get_ib_value(p, idx+1);
1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1497 track->immd_dwords = pkt->count - 1;
1498 r = r100_cs_track_check(p->rdev, track);
1502 case PACKET3_3D_DRAW_IMMD:
1503 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1504 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1507 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1508 track->immd_dwords = pkt->count - 1;
1509 r = r100_cs_track_check(p->rdev, track);
1513 /* triggers drawing using in-packet vertex data */
1514 case PACKET3_3D_DRAW_IMMD_2:
1515 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1516 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1519 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1520 track->immd_dwords = pkt->count;
1521 r = r100_cs_track_check(p->rdev, track);
1525 /* triggers drawing using in-packet vertex data */
1526 case PACKET3_3D_DRAW_VBUF_2:
1527 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1528 r = r100_cs_track_check(p->rdev, track);
1532 /* triggers drawing of vertex buffers setup elsewhere */
1533 case PACKET3_3D_DRAW_INDX_2:
1534 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1535 r = r100_cs_track_check(p->rdev, track);
1539 /* triggers drawing using indices to vertex buffer */
1540 case PACKET3_3D_DRAW_VBUF:
1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1542 r = r100_cs_track_check(p->rdev, track);
1546 /* triggers drawing of vertex buffers setup elsewhere */
1547 case PACKET3_3D_DRAW_INDX:
1548 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1549 r = r100_cs_track_check(p->rdev, track);
1553 /* triggers drawing using indices to vertex buffer */
1557 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1563 int r100_cs_parse(struct radeon_cs_parser *p)
1565 struct radeon_cs_packet pkt;
1566 struct r100_cs_track *track;
1569 track = kzalloc(sizeof(*track), GFP_KERNEL);
1570 r100_cs_track_clear(p->rdev, track);
1573 r = r100_cs_packet_parse(p, &pkt, p->idx);
1577 p->idx += pkt.count + 2;
1580 if (p->rdev->family >= CHIP_R200)
1581 r = r100_cs_parse_packet0(p, &pkt,
1582 p->rdev->config.r100.reg_safe_bm,
1583 p->rdev->config.r100.reg_safe_bm_size,
1584 &r200_packet0_check);
1586 r = r100_cs_parse_packet0(p, &pkt,
1587 p->rdev->config.r100.reg_safe_bm,
1588 p->rdev->config.r100.reg_safe_bm_size,
1589 &r100_packet0_check);
1594 r = r100_packet3_check(p, &pkt);
1597 DRM_ERROR("Unknown packet type %d !\n",
1604 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1610 * Global GPU functions
1612 void r100_errata(struct radeon_device *rdev)
1614 rdev->pll_errata = 0;
1616 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1617 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1620 if (rdev->family == CHIP_RV100 ||
1621 rdev->family == CHIP_RS100 ||
1622 rdev->family == CHIP_RS200) {
1623 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1627 /* Wait for vertical sync on primary CRTC */
1628 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1630 uint32_t crtc_gen_cntl, tmp;
1633 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1634 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1635 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1638 /* Clear the CRTC_VBLANK_SAVE bit */
1639 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1640 for (i = 0; i < rdev->usec_timeout; i++) {
1641 tmp = RREG32(RADEON_CRTC_STATUS);
1642 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1649 /* Wait for vertical sync on secondary CRTC */
1650 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1652 uint32_t crtc2_gen_cntl, tmp;
1655 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1656 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1657 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1660 /* Clear the CRTC_VBLANK_SAVE bit */
1661 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1662 for (i = 0; i < rdev->usec_timeout; i++) {
1663 tmp = RREG32(RADEON_CRTC2_STATUS);
1664 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1671 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1676 for (i = 0; i < rdev->usec_timeout; i++) {
1677 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1686 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1691 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1692 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1693 " Bad things might happen.\n");
1695 for (i = 0; i < rdev->usec_timeout; i++) {
1696 tmp = RREG32(RADEON_RBBM_STATUS);
1697 if (!(tmp & (1 << 31))) {
1705 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1710 for (i = 0; i < rdev->usec_timeout; i++) {
1711 /* read MC_STATUS */
1712 tmp = RREG32(0x0150);
1713 if (tmp & (1 << 2)) {
1721 void r100_gpu_init(struct radeon_device *rdev)
1723 /* TODO: anythings to do here ? pipes ? */
1724 r100_hdp_reset(rdev);
1727 void r100_hdp_reset(struct radeon_device *rdev)
1731 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1733 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1734 (void)RREG32(RADEON_HOST_PATH_CNTL);
1736 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1737 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1738 (void)RREG32(RADEON_HOST_PATH_CNTL);
1741 int r100_rb2d_reset(struct radeon_device *rdev)
1746 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1747 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1749 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1750 /* Wait to prevent race in RBBM_STATUS */
1752 for (i = 0; i < rdev->usec_timeout; i++) {
1753 tmp = RREG32(RADEON_RBBM_STATUS);
1754 if (!(tmp & (1 << 26))) {
1755 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1761 tmp = RREG32(RADEON_RBBM_STATUS);
1762 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1766 int r100_gpu_reset(struct radeon_device *rdev)
1770 /* reset order likely matter */
1771 status = RREG32(RADEON_RBBM_STATUS);
1773 r100_hdp_reset(rdev);
1775 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1776 r100_rb2d_reset(rdev);
1778 /* TODO: reset 3D engine */
1780 status = RREG32(RADEON_RBBM_STATUS);
1781 if (status & (1 << 16)) {
1782 r100_cp_reset(rdev);
1784 /* Check if GPU is idle */
1785 status = RREG32(RADEON_RBBM_STATUS);
1786 if (status & (1 << 31)) {
1787 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1790 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1794 void r100_set_common_regs(struct radeon_device *rdev)
1796 /* set these so they don't interfere with anything */
1797 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1798 WREG32(RADEON_SUBPIC_CNTL, 0);
1799 WREG32(RADEON_VIPH_CONTROL, 0);
1800 WREG32(RADEON_I2C_CNTL_1, 0);
1801 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1802 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1803 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1809 static void r100_vram_get_type(struct radeon_device *rdev)
1813 rdev->mc.vram_is_ddr = false;
1814 if (rdev->flags & RADEON_IS_IGP)
1815 rdev->mc.vram_is_ddr = true;
1816 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1817 rdev->mc.vram_is_ddr = true;
1818 if ((rdev->family == CHIP_RV100) ||
1819 (rdev->family == CHIP_RS100) ||
1820 (rdev->family == CHIP_RS200)) {
1821 tmp = RREG32(RADEON_MEM_CNTL);
1822 if (tmp & RV100_HALF_MODE) {
1823 rdev->mc.vram_width = 32;
1825 rdev->mc.vram_width = 64;
1827 if (rdev->flags & RADEON_SINGLE_CRTC) {
1828 rdev->mc.vram_width /= 4;
1829 rdev->mc.vram_is_ddr = true;
1831 } else if (rdev->family <= CHIP_RV280) {
1832 tmp = RREG32(RADEON_MEM_CNTL);
1833 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1834 rdev->mc.vram_width = 128;
1836 rdev->mc.vram_width = 64;
1840 rdev->mc.vram_width = 128;
1844 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1849 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1851 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1852 * that is has the 2nd generation multifunction PCI interface
1854 if (rdev->family == CHIP_RV280 ||
1855 rdev->family >= CHIP_RV350) {
1856 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1857 ~RADEON_HDP_APER_CNTL);
1858 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1859 return aper_size * 2;
1862 /* Older cards have all sorts of funny issues to deal with. First
1863 * check if it's a multifunction card by reading the PCI config
1864 * header type... Limit those to one aperture size
1866 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1868 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1869 DRM_INFO("Limiting VRAM to one aperture\n");
1873 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1874 * have set it up. We don't write this as it's broken on some ASICs but
1875 * we expect the BIOS to have done the right thing (might be too optimistic...)
1877 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1878 return aper_size * 2;
1882 void r100_vram_init_sizes(struct radeon_device *rdev)
1884 u64 config_aper_size;
1887 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1889 if (rdev->flags & RADEON_IS_IGP) {
1891 /* read NB_TOM to get the amount of ram stolen for the GPU */
1892 tom = RREG32(RADEON_NB_TOM);
1893 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1894 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1895 rdev->mc.vram_location = (tom & 0xffff) << 16;
1896 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1897 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1899 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1900 /* Some production boards of m6 will report 0
1903 if (rdev->mc.real_vram_size == 0) {
1904 rdev->mc.real_vram_size = 8192 * 1024;
1905 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1907 /* let driver place VRAM */
1908 rdev->mc.vram_location = 0xFFFFFFFFUL;
1909 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1910 * Novell bug 204882 + along with lots of ubuntu ones */
1911 if (config_aper_size > rdev->mc.real_vram_size)
1912 rdev->mc.mc_vram_size = config_aper_size;
1914 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1917 /* work out accessible VRAM */
1918 accessible = r100_get_accessible_vram(rdev);
1920 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1921 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1923 if (accessible > rdev->mc.aper_size)
1924 accessible = rdev->mc.aper_size;
1926 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1927 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1929 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1930 rdev->mc.real_vram_size = rdev->mc.aper_size;
1933 void r100_vga_set_state(struct radeon_device *rdev, bool state)
1937 temp = RREG32(RADEON_CONFIG_CNTL);
1938 if (state == false) {
1944 WREG32(RADEON_CONFIG_CNTL, temp);
1947 void r100_vram_info(struct radeon_device *rdev)
1949 r100_vram_get_type(rdev);
1951 r100_vram_init_sizes(rdev);
1956 * Indirect registers accessor
1958 void r100_pll_errata_after_index(struct radeon_device *rdev)
1960 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1963 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1964 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1967 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1969 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1970 * or the chip could hang on a subsequent access
1972 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1976 /* This function is required to workaround a hardware bug in some (all?)
1977 * revisions of the R300. This workaround should be called after every
1978 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1979 * may not be correct.
1981 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1984 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1985 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1986 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1987 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1988 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1992 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1996 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1997 r100_pll_errata_after_index(rdev);
1998 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1999 r100_pll_errata_after_data(rdev);
2003 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2005 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2006 r100_pll_errata_after_index(rdev);
2007 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2008 r100_pll_errata_after_data(rdev);
2011 void r100_set_safe_registers(struct radeon_device *rdev)
2013 if (ASIC_IS_RN50(rdev)) {
2014 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2015 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2016 } else if (rdev->family < CHIP_R200) {
2017 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2018 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2020 r200_set_safe_registers(rdev);
2027 #if defined(CONFIG_DEBUG_FS)
2028 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2030 struct drm_info_node *node = (struct drm_info_node *) m->private;
2031 struct drm_device *dev = node->minor->dev;
2032 struct radeon_device *rdev = dev->dev_private;
2033 uint32_t reg, value;
2036 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2037 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2038 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2039 for (i = 0; i < 64; i++) {
2040 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2041 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2042 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2043 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2044 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2049 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2051 struct drm_info_node *node = (struct drm_info_node *) m->private;
2052 struct drm_device *dev = node->minor->dev;
2053 struct radeon_device *rdev = dev->dev_private;
2055 unsigned count, i, j;
2057 radeon_ring_free_size(rdev);
2058 rdp = RREG32(RADEON_CP_RB_RPTR);
2059 wdp = RREG32(RADEON_CP_RB_WPTR);
2060 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2061 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2062 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2063 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2064 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2065 seq_printf(m, "%u dwords in ring\n", count);
2066 for (j = 0; j <= count; j++) {
2067 i = (rdp + j) & rdev->cp.ptr_mask;
2068 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2074 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2076 struct drm_info_node *node = (struct drm_info_node *) m->private;
2077 struct drm_device *dev = node->minor->dev;
2078 struct radeon_device *rdev = dev->dev_private;
2079 uint32_t csq_stat, csq2_stat, tmp;
2080 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2083 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2084 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2085 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2086 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2087 r_rptr = (csq_stat >> 0) & 0x3ff;
2088 r_wptr = (csq_stat >> 10) & 0x3ff;
2089 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2090 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2091 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2092 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2093 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2094 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2095 seq_printf(m, "Ring rptr %u\n", r_rptr);
2096 seq_printf(m, "Ring wptr %u\n", r_wptr);
2097 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2098 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2099 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2100 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2101 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2102 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2103 seq_printf(m, "Ring fifo:\n");
2104 for (i = 0; i < 256; i++) {
2105 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2106 tmp = RREG32(RADEON_CP_CSQ_DATA);
2107 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2109 seq_printf(m, "Indirect1 fifo:\n");
2110 for (i = 256; i <= 512; i++) {
2111 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2112 tmp = RREG32(RADEON_CP_CSQ_DATA);
2113 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2115 seq_printf(m, "Indirect2 fifo:\n");
2116 for (i = 640; i < ib1_wptr; i++) {
2117 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2118 tmp = RREG32(RADEON_CP_CSQ_DATA);
2119 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2124 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2126 struct drm_info_node *node = (struct drm_info_node *) m->private;
2127 struct drm_device *dev = node->minor->dev;
2128 struct radeon_device *rdev = dev->dev_private;
2131 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2132 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2133 tmp = RREG32(RADEON_MC_FB_LOCATION);
2134 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2135 tmp = RREG32(RADEON_BUS_CNTL);
2136 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2137 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2138 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2139 tmp = RREG32(RADEON_AGP_BASE);
2140 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2141 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2142 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2143 tmp = RREG32(0x01D0);
2144 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2145 tmp = RREG32(RADEON_AIC_LO_ADDR);
2146 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2147 tmp = RREG32(RADEON_AIC_HI_ADDR);
2148 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2149 tmp = RREG32(0x01E4);
2150 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2154 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2155 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2158 static struct drm_info_list r100_debugfs_cp_list[] = {
2159 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2160 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2163 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2164 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2168 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2170 #if defined(CONFIG_DEBUG_FS)
2171 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2177 int r100_debugfs_cp_init(struct radeon_device *rdev)
2179 #if defined(CONFIG_DEBUG_FS)
2180 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2186 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2188 #if defined(CONFIG_DEBUG_FS)
2189 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2195 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2196 uint32_t tiling_flags, uint32_t pitch,
2197 uint32_t offset, uint32_t obj_size)
2199 int surf_index = reg * 16;
2202 /* r100/r200 divide by 16 */
2203 if (rdev->family < CHIP_R300)
2208 if (rdev->family <= CHIP_RS200) {
2209 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2210 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2211 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2212 if (tiling_flags & RADEON_TILING_MACRO)
2213 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2214 } else if (rdev->family <= CHIP_RV280) {
2215 if (tiling_flags & (RADEON_TILING_MACRO))
2216 flags |= R200_SURF_TILE_COLOR_MACRO;
2217 if (tiling_flags & RADEON_TILING_MICRO)
2218 flags |= R200_SURF_TILE_COLOR_MICRO;
2220 if (tiling_flags & RADEON_TILING_MACRO)
2221 flags |= R300_SURF_TILE_MACRO;
2222 if (tiling_flags & RADEON_TILING_MICRO)
2223 flags |= R300_SURF_TILE_MICRO;
2226 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2227 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2228 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2229 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2231 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2232 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2233 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2234 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2238 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2240 int surf_index = reg * 16;
2241 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2244 void r100_bandwidth_update(struct radeon_device *rdev)
2246 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2247 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2248 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2249 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2250 fixed20_12 memtcas_ff[8] = {
2259 fixed20_12 memtcas_rs480_ff[8] = {
2269 fixed20_12 memtcas2_ff[8] = {
2279 fixed20_12 memtrbs[8] = {
2289 fixed20_12 memtrbs_r4xx[8] = {
2299 fixed20_12 min_mem_eff;
2300 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2301 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2302 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2303 disp_drain_rate2, read_return_rate;
2304 fixed20_12 time_disp1_drop_priority;
2306 int cur_size = 16; /* in octawords */
2307 int critical_point = 0, critical_point2;
2308 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2309 int stop_req, max_stop_req;
2310 struct drm_display_mode *mode1 = NULL;
2311 struct drm_display_mode *mode2 = NULL;
2312 uint32_t pixel_bytes1 = 0;
2313 uint32_t pixel_bytes2 = 0;
2315 if (rdev->mode_info.crtcs[0]->base.enabled) {
2316 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2317 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2319 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2320 if (rdev->mode_info.crtcs[1]->base.enabled) {
2321 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2322 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2326 min_mem_eff.full = rfixed_const_8(0);
2328 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2329 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2330 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2331 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2332 /* check crtc enables */
2334 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2336 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2337 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2341 * determine is there is enough bw for current mode
2343 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2344 temp_ff.full = rfixed_const(100);
2345 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2346 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2347 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2349 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2350 temp_ff.full = rfixed_const(temp);
2351 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2355 peak_disp_bw.full = 0;
2357 temp_ff.full = rfixed_const(1000);
2358 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2359 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2360 temp_ff.full = rfixed_const(pixel_bytes1);
2361 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2364 temp_ff.full = rfixed_const(1000);
2365 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2366 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2367 temp_ff.full = rfixed_const(pixel_bytes2);
2368 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2371 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2372 if (peak_disp_bw.full >= mem_bw.full) {
2373 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2374 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2377 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2378 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2379 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2380 mem_trcd = ((temp >> 2) & 0x3) + 1;
2381 mem_trp = ((temp & 0x3)) + 1;
2382 mem_tras = ((temp & 0x70) >> 4) + 1;
2383 } else if (rdev->family == CHIP_R300 ||
2384 rdev->family == CHIP_R350) { /* r300, r350 */
2385 mem_trcd = (temp & 0x7) + 1;
2386 mem_trp = ((temp >> 8) & 0x7) + 1;
2387 mem_tras = ((temp >> 11) & 0xf) + 4;
2388 } else if (rdev->family == CHIP_RV350 ||
2389 rdev->family <= CHIP_RV380) {
2391 mem_trcd = (temp & 0x7) + 3;
2392 mem_trp = ((temp >> 8) & 0x7) + 3;
2393 mem_tras = ((temp >> 11) & 0xf) + 6;
2394 } else if (rdev->family == CHIP_R420 ||
2395 rdev->family == CHIP_R423 ||
2396 rdev->family == CHIP_RV410) {
2398 mem_trcd = (temp & 0xf) + 3;
2401 mem_trp = ((temp >> 8) & 0xf) + 3;
2404 mem_tras = ((temp >> 12) & 0x1f) + 6;
2407 } else { /* RV200, R200 */
2408 mem_trcd = (temp & 0x7) + 1;
2409 mem_trp = ((temp >> 8) & 0x7) + 1;
2410 mem_tras = ((temp >> 12) & 0xf) + 4;
2413 trcd_ff.full = rfixed_const(mem_trcd);
2414 trp_ff.full = rfixed_const(mem_trp);
2415 tras_ff.full = rfixed_const(mem_tras);
2417 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2418 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2419 data = (temp & (7 << 20)) >> 20;
2420 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2421 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2422 tcas_ff = memtcas_rs480_ff[data];
2424 tcas_ff = memtcas_ff[data];
2426 tcas_ff = memtcas2_ff[data];
2428 if (rdev->family == CHIP_RS400 ||
2429 rdev->family == CHIP_RS480) {
2430 /* extra cas latency stored in bits 23-25 0-4 clocks */
2431 data = (temp >> 23) & 0x7;
2433 tcas_ff.full += rfixed_const(data);
2436 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2437 /* on the R300, Tcas is included in Trbs.
2439 temp = RREG32(RADEON_MEM_CNTL);
2440 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2442 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2443 temp = RREG32(R300_MC_IND_INDEX);
2444 temp &= ~R300_MC_IND_ADDR_MASK;
2445 temp |= R300_MC_READ_CNTL_CD_mcind;
2446 WREG32(R300_MC_IND_INDEX, temp);
2447 temp = RREG32(R300_MC_IND_DATA);
2448 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2450 temp = RREG32(R300_MC_READ_CNTL_AB);
2451 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2454 temp = RREG32(R300_MC_READ_CNTL_AB);
2455 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2457 if (rdev->family == CHIP_RV410 ||
2458 rdev->family == CHIP_R420 ||
2459 rdev->family == CHIP_R423)
2460 trbs_ff = memtrbs_r4xx[data];
2462 trbs_ff = memtrbs[data];
2463 tcas_ff.full += trbs_ff.full;
2466 sclk_eff_ff.full = sclk_ff.full;
2468 if (rdev->flags & RADEON_IS_AGP) {
2469 fixed20_12 agpmode_ff;
2470 agpmode_ff.full = rfixed_const(radeon_agpmode);
2471 temp_ff.full = rfixed_const_666(16);
2472 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2474 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2476 if (ASIC_IS_R300(rdev)) {
2477 sclk_delay_ff.full = rfixed_const(250);
2479 if ((rdev->family == CHIP_RV100) ||
2480 rdev->flags & RADEON_IS_IGP) {
2481 if (rdev->mc.vram_is_ddr)
2482 sclk_delay_ff.full = rfixed_const(41);
2484 sclk_delay_ff.full = rfixed_const(33);
2486 if (rdev->mc.vram_width == 128)
2487 sclk_delay_ff.full = rfixed_const(57);
2489 sclk_delay_ff.full = rfixed_const(41);
2493 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2495 if (rdev->mc.vram_is_ddr) {
2496 if (rdev->mc.vram_width == 32) {
2497 k1.full = rfixed_const(40);
2500 k1.full = rfixed_const(20);
2504 k1.full = rfixed_const(40);
2508 temp_ff.full = rfixed_const(2);
2509 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2510 temp_ff.full = rfixed_const(c);
2511 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2512 temp_ff.full = rfixed_const(4);
2513 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2514 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2515 mc_latency_mclk.full += k1.full;
2517 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2518 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2521 HW cursor time assuming worst case of full size colour cursor.
2523 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2524 temp_ff.full += trcd_ff.full;
2525 if (temp_ff.full < tras_ff.full)
2526 temp_ff.full = tras_ff.full;
2527 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2529 temp_ff.full = rfixed_const(cur_size);
2530 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2532 Find the total latency for the display data.
2534 disp_latency_overhead.full = rfixed_const(8);
2535 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2536 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2537 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2539 if (mc_latency_mclk.full > mc_latency_sclk.full)
2540 disp_latency.full = mc_latency_mclk.full;
2542 disp_latency.full = mc_latency_sclk.full;
2544 /* setup Max GRPH_STOP_REQ default value */
2545 if (ASIC_IS_RV100(rdev))
2546 max_stop_req = 0x5c;
2548 max_stop_req = 0x7c;
2552 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2553 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2555 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2557 if (stop_req > max_stop_req)
2558 stop_req = max_stop_req;
2561 Find the drain rate of the display buffer.
2563 temp_ff.full = rfixed_const((16/pixel_bytes1));
2564 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2567 Find the critical point of the display buffer.
2569 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2570 crit_point_ff.full += rfixed_const_half(0);
2572 critical_point = rfixed_trunc(crit_point_ff);
2574 if (rdev->disp_priority == 2) {
2579 The critical point should never be above max_stop_req-4. Setting
2580 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2582 if (max_stop_req - critical_point < 4)
2585 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2586 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2587 critical_point = 0x10;
2590 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2591 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2592 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2593 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2594 if ((rdev->family == CHIP_R350) &&
2595 (stop_req > 0x15)) {
2598 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2599 temp |= RADEON_GRPH_BUFFER_SIZE;
2600 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2601 RADEON_GRPH_CRITICAL_AT_SOF |
2602 RADEON_GRPH_STOP_CNTL);
2604 Write the result into the register.
2606 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2607 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2610 if ((rdev->family == CHIP_RS400) ||
2611 (rdev->family == CHIP_RS480)) {
2612 /* attempt to program RS400 disp regs correctly ??? */
2613 temp = RREG32(RS400_DISP1_REG_CNTL);
2614 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2615 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2616 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2617 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2618 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2619 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2620 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2621 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2622 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2623 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2624 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2628 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2629 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2630 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2635 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2637 if (stop_req > max_stop_req)
2638 stop_req = max_stop_req;
2641 Find the drain rate of the display buffer.
2643 temp_ff.full = rfixed_const((16/pixel_bytes2));
2644 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2646 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2647 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2648 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2649 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2650 if ((rdev->family == CHIP_R350) &&
2651 (stop_req > 0x15)) {
2654 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2655 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2656 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2657 RADEON_GRPH_CRITICAL_AT_SOF |
2658 RADEON_GRPH_STOP_CNTL);
2660 if ((rdev->family == CHIP_RS100) ||
2661 (rdev->family == CHIP_RS200))
2662 critical_point2 = 0;
2664 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2665 temp_ff.full = rfixed_const(temp);
2666 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2667 if (sclk_ff.full < temp_ff.full)
2668 temp_ff.full = sclk_ff.full;
2670 read_return_rate.full = temp_ff.full;
2673 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2674 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2676 time_disp1_drop_priority.full = 0;
2678 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2679 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2680 crit_point_ff.full += rfixed_const_half(0);
2682 critical_point2 = rfixed_trunc(crit_point_ff);
2684 if (rdev->disp_priority == 2) {
2685 critical_point2 = 0;
2688 if (max_stop_req - critical_point2 < 4)
2689 critical_point2 = 0;
2693 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2694 /* some R300 cards have problem with this set to 0 */
2695 critical_point2 = 0x10;
2698 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2699 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2701 if ((rdev->family == CHIP_RS400) ||
2702 (rdev->family == CHIP_RS480)) {
2704 /* attempt to program RS400 disp2 regs correctly ??? */
2705 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2706 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2707 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2708 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2709 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2710 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2711 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2712 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2713 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2714 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2715 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2716 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2718 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2719 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2720 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2721 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2724 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2725 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2729 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2731 DRM_ERROR("pitch %d\n", t->pitch);
2732 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2733 DRM_ERROR("width %d\n", t->width);
2734 DRM_ERROR("width_11 %d\n", t->width_11);
2735 DRM_ERROR("height %d\n", t->height);
2736 DRM_ERROR("height_11 %d\n", t->height_11);
2737 DRM_ERROR("num levels %d\n", t->num_levels);
2738 DRM_ERROR("depth %d\n", t->txdepth);
2739 DRM_ERROR("bpp %d\n", t->cpp);
2740 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2741 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2742 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2743 DRM_ERROR("compress format %d\n", t->compress_format);
2746 static int r100_cs_track_cube(struct radeon_device *rdev,
2747 struct r100_cs_track *track, unsigned idx)
2749 unsigned face, w, h;
2750 struct radeon_bo *cube_robj;
2753 for (face = 0; face < 5; face++) {
2754 cube_robj = track->textures[idx].cube_info[face].robj;
2755 w = track->textures[idx].cube_info[face].width;
2756 h = track->textures[idx].cube_info[face].height;
2759 size *= track->textures[idx].cpp;
2761 size += track->textures[idx].cube_info[face].offset;
2763 if (size > radeon_bo_size(cube_robj)) {
2764 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2765 size, radeon_bo_size(cube_robj));
2766 r100_cs_track_texture_print(&track->textures[idx]);
2773 static int r100_track_compress_size(int compress_format, int w, int h)
2775 int block_width, block_height, block_bytes;
2776 int wblocks, hblocks;
2783 switch (compress_format) {
2784 case R100_TRACK_COMP_DXT1:
2789 case R100_TRACK_COMP_DXT35:
2795 hblocks = (h + block_height - 1) / block_height;
2796 wblocks = (w + block_width - 1) / block_width;
2797 if (wblocks < min_wblocks)
2798 wblocks = min_wblocks;
2799 sz = wblocks * hblocks * block_bytes;
2803 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2804 struct r100_cs_track *track)
2806 struct radeon_bo *robj;
2808 unsigned u, i, w, h;
2811 for (u = 0; u < track->num_texture; u++) {
2812 if (!track->textures[u].enabled)
2814 robj = track->textures[u].robj;
2816 DRM_ERROR("No texture bound to unit %u\n", u);
2820 for (i = 0; i <= track->textures[u].num_levels; i++) {
2821 if (track->textures[u].use_pitch) {
2822 if (rdev->family < CHIP_R300)
2823 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2825 w = track->textures[u].pitch / (1 << i);
2827 w = track->textures[u].width;
2828 if (rdev->family >= CHIP_RV515)
2829 w |= track->textures[u].width_11;
2831 if (track->textures[u].roundup_w)
2832 w = roundup_pow_of_two(w);
2834 h = track->textures[u].height;
2835 if (rdev->family >= CHIP_RV515)
2836 h |= track->textures[u].height_11;
2838 if (track->textures[u].roundup_h)
2839 h = roundup_pow_of_two(h);
2840 if (track->textures[u].compress_format) {
2842 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2843 /* compressed textures are block based */
2847 size *= track->textures[u].cpp;
2849 switch (track->textures[u].tex_coord_type) {
2853 size *= (1 << track->textures[u].txdepth);
2856 if (track->separate_cube) {
2857 ret = r100_cs_track_cube(rdev, track, u);
2864 DRM_ERROR("Invalid texture coordinate type %u for unit "
2865 "%u\n", track->textures[u].tex_coord_type, u);
2868 if (size > radeon_bo_size(robj)) {
2869 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2870 "%lu\n", u, size, radeon_bo_size(robj));
2871 r100_cs_track_texture_print(&track->textures[u]);
2878 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2885 for (i = 0; i < track->num_cb; i++) {
2886 if (track->cb[i].robj == NULL) {
2887 if (!(track->fastfill || track->color_channel_mask ||
2888 track->blend_read_enable)) {
2891 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2894 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2895 size += track->cb[i].offset;
2896 if (size > radeon_bo_size(track->cb[i].robj)) {
2897 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2898 "(need %lu have %lu) !\n", i, size,
2899 radeon_bo_size(track->cb[i].robj));
2900 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2901 i, track->cb[i].pitch, track->cb[i].cpp,
2902 track->cb[i].offset, track->maxy);
2906 if (track->z_enabled) {
2907 if (track->zb.robj == NULL) {
2908 DRM_ERROR("[drm] No buffer for z buffer !\n");
2911 size = track->zb.pitch * track->zb.cpp * track->maxy;
2912 size += track->zb.offset;
2913 if (size > radeon_bo_size(track->zb.robj)) {
2914 DRM_ERROR("[drm] Buffer too small for z buffer "
2915 "(need %lu have %lu) !\n", size,
2916 radeon_bo_size(track->zb.robj));
2917 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2918 track->zb.pitch, track->zb.cpp,
2919 track->zb.offset, track->maxy);
2923 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2924 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2925 switch (prim_walk) {
2927 for (i = 0; i < track->num_arrays; i++) {
2928 size = track->arrays[i].esize * track->max_indx * 4;
2929 if (track->arrays[i].robj == NULL) {
2930 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2931 "bound\n", prim_walk, i);
2934 if (size > radeon_bo_size(track->arrays[i].robj)) {
2935 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2936 "need %lu dwords have %lu dwords\n",
2937 prim_walk, i, size >> 2,
2938 radeon_bo_size(track->arrays[i].robj)
2940 DRM_ERROR("Max indices %u\n", track->max_indx);
2946 for (i = 0; i < track->num_arrays; i++) {
2947 size = track->arrays[i].esize * (nverts - 1) * 4;
2948 if (track->arrays[i].robj == NULL) {
2949 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2950 "bound\n", prim_walk, i);
2953 if (size > radeon_bo_size(track->arrays[i].robj)) {
2954 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2955 "need %lu dwords have %lu dwords\n",
2956 prim_walk, i, size >> 2,
2957 radeon_bo_size(track->arrays[i].robj)
2964 size = track->vtx_size * nverts;
2965 if (size != track->immd_dwords) {
2966 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2967 track->immd_dwords, size);
2968 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2969 nverts, track->vtx_size);
2974 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2978 return r100_cs_track_texture_check(rdev, track);
2981 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2985 if (rdev->family < CHIP_R300) {
2987 if (rdev->family <= CHIP_RS200)
2988 track->num_texture = 3;
2990 track->num_texture = 6;
2992 track->separate_cube = 1;
2995 track->num_texture = 16;
2997 track->separate_cube = 0;
3000 for (i = 0; i < track->num_cb; i++) {
3001 track->cb[i].robj = NULL;
3002 track->cb[i].pitch = 8192;
3003 track->cb[i].cpp = 16;
3004 track->cb[i].offset = 0;
3006 track->z_enabled = true;
3007 track->zb.robj = NULL;
3008 track->zb.pitch = 8192;
3010 track->zb.offset = 0;
3011 track->vtx_size = 0x7F;
3012 track->immd_dwords = 0xFFFFFFFFUL;
3013 track->num_arrays = 11;
3014 track->max_indx = 0x00FFFFFFUL;
3015 for (i = 0; i < track->num_arrays; i++) {
3016 track->arrays[i].robj = NULL;
3017 track->arrays[i].esize = 0x7F;
3019 for (i = 0; i < track->num_texture; i++) {
3020 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3021 track->textures[i].pitch = 16536;
3022 track->textures[i].width = 16536;
3023 track->textures[i].height = 16536;
3024 track->textures[i].width_11 = 1 << 11;
3025 track->textures[i].height_11 = 1 << 11;
3026 track->textures[i].num_levels = 12;
3027 if (rdev->family <= CHIP_RS200) {
3028 track->textures[i].tex_coord_type = 0;
3029 track->textures[i].txdepth = 0;
3031 track->textures[i].txdepth = 16;
3032 track->textures[i].tex_coord_type = 1;
3034 track->textures[i].cpp = 64;
3035 track->textures[i].robj = NULL;
3036 /* CS IB emission code makes sure texture unit are disabled */
3037 track->textures[i].enabled = false;
3038 track->textures[i].roundup_w = true;
3039 track->textures[i].roundup_h = true;
3040 if (track->separate_cube)
3041 for (face = 0; face < 5; face++) {
3042 track->textures[i].cube_info[face].robj = NULL;
3043 track->textures[i].cube_info[face].width = 16536;
3044 track->textures[i].cube_info[face].height = 16536;
3045 track->textures[i].cube_info[face].offset = 0;
3050 int r100_ring_test(struct radeon_device *rdev)
3057 r = radeon_scratch_get(rdev, &scratch);
3059 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3062 WREG32(scratch, 0xCAFEDEAD);
3063 r = radeon_ring_lock(rdev, 2);
3065 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3066 radeon_scratch_free(rdev, scratch);
3069 radeon_ring_write(rdev, PACKET0(scratch, 0));
3070 radeon_ring_write(rdev, 0xDEADBEEF);
3071 radeon_ring_unlock_commit(rdev);
3072 for (i = 0; i < rdev->usec_timeout; i++) {
3073 tmp = RREG32(scratch);
3074 if (tmp == 0xDEADBEEF) {
3079 if (i < rdev->usec_timeout) {
3080 DRM_INFO("ring test succeeded in %d usecs\n", i);
3082 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3086 radeon_scratch_free(rdev, scratch);
3090 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3092 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3093 radeon_ring_write(rdev, ib->gpu_addr);
3094 radeon_ring_write(rdev, ib->length_dw);
3097 int r100_ib_test(struct radeon_device *rdev)
3099 struct radeon_ib *ib;
3105 r = radeon_scratch_get(rdev, &scratch);
3107 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3110 WREG32(scratch, 0xCAFEDEAD);
3111 r = radeon_ib_get(rdev, &ib);
3115 ib->ptr[0] = PACKET0(scratch, 0);
3116 ib->ptr[1] = 0xDEADBEEF;
3117 ib->ptr[2] = PACKET2(0);
3118 ib->ptr[3] = PACKET2(0);
3119 ib->ptr[4] = PACKET2(0);
3120 ib->ptr[5] = PACKET2(0);
3121 ib->ptr[6] = PACKET2(0);
3122 ib->ptr[7] = PACKET2(0);
3124 r = radeon_ib_schedule(rdev, ib);
3126 radeon_scratch_free(rdev, scratch);
3127 radeon_ib_free(rdev, &ib);
3130 r = radeon_fence_wait(ib->fence, false);
3134 for (i = 0; i < rdev->usec_timeout; i++) {
3135 tmp = RREG32(scratch);
3136 if (tmp == 0xDEADBEEF) {
3141 if (i < rdev->usec_timeout) {
3142 DRM_INFO("ib test succeeded in %u usecs\n", i);
3144 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3148 radeon_scratch_free(rdev, scratch);
3149 radeon_ib_free(rdev, &ib);
3153 void r100_ib_fini(struct radeon_device *rdev)
3155 radeon_ib_pool_fini(rdev);
3158 int r100_ib_init(struct radeon_device *rdev)
3162 r = radeon_ib_pool_init(rdev);
3164 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3168 r = r100_ib_test(rdev);
3170 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3177 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3179 /* Shutdown CP we shouldn't need to do that but better be safe than
3182 rdev->cp.ready = false;
3183 WREG32(R_000740_CP_CSQ_CNTL, 0);
3185 /* Save few CRTC registers */
3186 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3187 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3188 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3189 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3190 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3191 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3192 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3195 /* Disable VGA aperture access */
3196 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3197 /* Disable cursor, overlay, crtc */
3198 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3199 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3200 S_000054_CRTC_DISPLAY_DIS(1));
3201 WREG32(R_000050_CRTC_GEN_CNTL,
3202 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3203 S_000050_CRTC_DISP_REQ_EN_B(1));
3204 WREG32(R_000420_OV0_SCALE_CNTL,
3205 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3206 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3207 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3208 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3209 S_000360_CUR2_LOCK(1));
3210 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3211 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3212 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3213 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3214 WREG32(R_000360_CUR2_OFFSET,
3215 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3219 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3221 /* Update base address for crtc */
3222 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3223 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3224 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3225 rdev->mc.vram_location);
3227 /* Restore CRTC registers */
3228 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3229 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3230 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3231 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3232 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3236 void r100_vga_render_disable(struct radeon_device *rdev)
3240 tmp = RREG8(R_0003C2_GENMO_WT);
3241 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3244 static void r100_debugfs(struct radeon_device *rdev)
3248 r = r100_debugfs_mc_info_init(rdev);
3250 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3253 static void r100_mc_program(struct radeon_device *rdev)
3255 struct r100_mc_save save;
3257 /* Stops all mc clients */
3258 r100_mc_stop(rdev, &save);
3259 if (rdev->flags & RADEON_IS_AGP) {
3260 WREG32(R_00014C_MC_AGP_LOCATION,
3261 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3262 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3263 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3264 if (rdev->family > CHIP_RV200)
3265 WREG32(R_00015C_AGP_BASE_2,
3266 upper_32_bits(rdev->mc.agp_base) & 0xff);
3268 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3269 WREG32(R_000170_AGP_BASE, 0);
3270 if (rdev->family > CHIP_RV200)
3271 WREG32(R_00015C_AGP_BASE_2, 0);
3273 /* Wait for mc idle */
3274 if (r100_mc_wait_for_idle(rdev))
3275 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3276 /* Program MC, should be a 32bits limited address space */
3277 WREG32(R_000148_MC_FB_LOCATION,
3278 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3279 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3280 r100_mc_resume(rdev, &save);
3283 void r100_clock_startup(struct radeon_device *rdev)
3287 if (radeon_dynclks != -1 && radeon_dynclks)
3288 radeon_legacy_set_clock_gating(rdev, 1);
3289 /* We need to force on some of the block */
3290 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3291 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3292 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3293 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3294 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3297 static int r100_startup(struct radeon_device *rdev)
3301 /* set common regs */
3302 r100_set_common_regs(rdev);
3304 r100_mc_program(rdev);
3306 r100_clock_startup(rdev);
3307 /* Initialize GPU configuration (# pipes, ...) */
3308 r100_gpu_init(rdev);
3309 /* Initialize GART (initialize after TTM so we can allocate
3310 * memory through TTM but finalize after TTM) */
3311 r100_enable_bm(rdev);
3312 if (rdev->flags & RADEON_IS_PCI) {
3313 r = r100_pci_gart_enable(rdev);
3319 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3320 /* 1M ring buffer */
3321 r = r100_cp_init(rdev, 1024 * 1024);
3323 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3326 r = r100_wb_init(rdev);
3328 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3329 r = r100_ib_init(rdev);
3331 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3337 int r100_resume(struct radeon_device *rdev)
3339 /* Make sur GART are not working */
3340 if (rdev->flags & RADEON_IS_PCI)
3341 r100_pci_gart_disable(rdev);
3342 /* Resume clock before doing reset */
3343 r100_clock_startup(rdev);
3344 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3345 if (radeon_gpu_reset(rdev)) {
3346 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3347 RREG32(R_000E40_RBBM_STATUS),
3348 RREG32(R_0007C0_CP_STAT));
3351 radeon_combios_asic_init(rdev->ddev);
3352 /* Resume clock after posting */
3353 r100_clock_startup(rdev);
3354 /* Initialize surface registers */
3355 radeon_surface_init(rdev);
3356 return r100_startup(rdev);
3359 int r100_suspend(struct radeon_device *rdev)
3361 r100_cp_disable(rdev);
3362 r100_wb_disable(rdev);
3363 r100_irq_disable(rdev);
3364 if (rdev->flags & RADEON_IS_PCI)
3365 r100_pci_gart_disable(rdev);
3369 void r100_fini(struct radeon_device *rdev)
3375 radeon_gem_fini(rdev);
3376 if (rdev->flags & RADEON_IS_PCI)
3377 r100_pci_gart_fini(rdev);
3378 radeon_agp_fini(rdev);
3379 radeon_irq_kms_fini(rdev);
3380 radeon_fence_driver_fini(rdev);
3381 radeon_bo_fini(rdev);
3382 radeon_atombios_fini(rdev);
3387 int r100_mc_init(struct radeon_device *rdev)
3392 /* Setup GPU memory space */
3393 rdev->mc.vram_location = 0xFFFFFFFFUL;
3394 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3395 if (rdev->flags & RADEON_IS_IGP) {
3396 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3397 rdev->mc.vram_location = tmp << 16;
3399 if (rdev->flags & RADEON_IS_AGP) {
3400 r = radeon_agp_init(rdev);
3402 printk(KERN_WARNING "[drm] Disabling AGP\n");
3403 rdev->flags &= ~RADEON_IS_AGP;
3404 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3406 rdev->mc.gtt_location = rdev->mc.agp_base;
3409 r = radeon_mc_setup(rdev);
3415 int r100_init(struct radeon_device *rdev)
3419 /* Register debugfs file specific to this group of asics */
3422 r100_vga_render_disable(rdev);
3423 /* Initialize scratch registers */
3424 radeon_scratch_init(rdev);
3425 /* Initialize surface registers */
3426 radeon_surface_init(rdev);
3427 /* TODO: disable VGA need to use VGA request */
3429 if (!radeon_get_bios(rdev)) {
3430 if (ASIC_IS_AVIVO(rdev))
3433 if (rdev->is_atom_bios) {
3434 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3437 r = radeon_combios_init(rdev);
3441 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3442 if (radeon_gpu_reset(rdev)) {
3444 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3445 RREG32(R_000E40_RBBM_STATUS),
3446 RREG32(R_0007C0_CP_STAT));
3448 /* check if cards are posted or not */
3449 if (radeon_boot_test_post_card(rdev) == false)
3451 /* Set asic errata */
3453 /* Initialize clocks */
3454 radeon_get_clock_info(rdev->ddev);
3455 /* Initialize power management */
3456 radeon_pm_init(rdev);
3457 /* Get vram informations */
3458 r100_vram_info(rdev);
3459 /* Initialize memory controller (also test AGP) */
3460 r = r100_mc_init(rdev);
3464 r = radeon_fence_driver_init(rdev);
3467 r = radeon_irq_kms_init(rdev);
3470 /* Memory manager */
3471 r = radeon_bo_init(rdev);
3474 if (rdev->flags & RADEON_IS_PCI) {
3475 r = r100_pci_gart_init(rdev);
3479 r100_set_safe_registers(rdev);
3480 rdev->accel_working = true;
3481 r = r100_startup(rdev);
3483 /* Somethings want wront with the accel init stop accel */
3484 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3489 if (rdev->flags & RADEON_IS_PCI)
3490 r100_pci_gart_fini(rdev);
3491 radeon_irq_kms_fini(rdev);
3492 rdev->accel_working = false;