2 #define R100_TRACK_MAX_TEXTURE 3
3 #define R200_TRACK_MAX_TEXTURE 6
4 #define R300_TRACK_MAX_TEXTURE 16
12 struct r100_cs_track_cb {
13 struct radeon_object *robj;
19 struct r100_cs_track_array {
20 struct radeon_object *robj;
24 struct r100_cs_cube_info {
25 struct radeon_object *robj;
31 struct r100_cs_track_texture {
32 struct radeon_object *robj;
33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
39 unsigned tex_coord_type;
49 struct r100_cs_track_limits {
55 struct r100_cs_track {
56 struct radeon_device *rdev;
65 struct r100_cs_track_array arrays[11];
66 struct r100_cs_track_cb cb[R300_MAX_CB];
67 struct r100_cs_track_cb zb;
68 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
74 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
75 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
76 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
77 struct radeon_cs_reloc **cs_reloc);
78 void r100_cs_dump_packet(struct radeon_cs_parser *p,
79 struct radeon_cs_packet *pkt);
81 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
83 int r200_packet0_check(struct radeon_cs_parser *p,
84 struct radeon_cs_packet *pkt,
85 unsigned idx, unsigned reg);
89 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
90 struct radeon_cs_packet *pkt,
97 struct radeon_cs_reloc *reloc;
100 r = r100_cs_packet_next_reloc(p, &reloc);
102 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
104 r100_cs_dump_packet(p, pkt);
107 value = radeon_get_ib_value(p, idx);
108 tmp = value & 0x003fffff;
109 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
111 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
112 tile_flags |= RADEON_DST_TILE_MACRO;
113 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
114 if (reg == RADEON_SRC_PITCH_OFFSET) {
115 DRM_ERROR("Cannot src blit from microtiled surface\n");
116 r100_cs_dump_packet(p, pkt);
119 tile_flags |= RADEON_DST_TILE_MICRO;
123 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
127 static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
128 struct radeon_cs_packet *pkt,
132 struct radeon_cs_reloc *reloc;
133 struct r100_cs_track *track;
135 volatile uint32_t *ib;
139 track = (struct r100_cs_track *)p->track;
140 c = radeon_get_ib_value(p, idx++) & 0x1F;
141 track->num_arrays = c;
142 for (i = 0; i < (c - 1); i+=2, idx+=3) {
143 r = r100_cs_packet_next_reloc(p, &reloc);
145 DRM_ERROR("No reloc for packet3 %d\n",
147 r100_cs_dump_packet(p, pkt);
150 idx_value = radeon_get_ib_value(p, idx);
151 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
153 track->arrays[i + 0].esize = idx_value >> 8;
154 track->arrays[i + 0].robj = reloc->robj;
155 track->arrays[i + 0].esize &= 0x7F;
156 r = r100_cs_packet_next_reloc(p, &reloc);
158 DRM_ERROR("No reloc for packet3 %d\n",
160 r100_cs_dump_packet(p, pkt);
163 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
164 track->arrays[i + 1].robj = reloc->robj;
165 track->arrays[i + 1].esize = idx_value >> 24;
166 track->arrays[i + 1].esize &= 0x7F;
169 r = r100_cs_packet_next_reloc(p, &reloc);
171 DRM_ERROR("No reloc for packet3 %d\n",
173 r100_cs_dump_packet(p, pkt);
176 idx_value = radeon_get_ib_value(p, idx);
177 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
178 track->arrays[i + 0].robj = reloc->robj;
179 track->arrays[i + 0].esize = idx_value >> 8;
180 track->arrays[i + 0].esize &= 0x7F;