2 #define R100_TRACK_MAX_TEXTURE 3
3 #define R200_TRACK_MAX_TEXTURE 6
4 #define R300_TRACK_MAX_TEXTURE 16
12 struct r100_cs_track_cb {
13 struct radeon_bo *robj;
19 struct r100_cs_track_array {
20 struct radeon_bo *robj;
24 struct r100_cs_cube_info {
25 struct radeon_bo *robj;
31 #define R100_TRACK_COMP_NONE 0
32 #define R100_TRACK_COMP_DXT1 1
33 #define R100_TRACK_COMP_DXT35 2
35 struct r100_cs_track_texture {
36 struct radeon_bo *robj;
37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
43 unsigned tex_coord_type;
51 unsigned compress_format;
54 struct r100_cs_track_limits {
60 struct r100_cs_track {
61 struct radeon_device *rdev;
67 unsigned vap_alt_nverts;
71 unsigned color_channel_mask;
72 struct r100_cs_track_array arrays[11];
73 struct r100_cs_track_cb cb[R300_MAX_CB];
74 struct r100_cs_track_cb zb;
75 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
79 bool blend_read_enable;
82 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
83 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
84 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
85 struct radeon_cs_reloc **cs_reloc);
86 void r100_cs_dump_packet(struct radeon_cs_parser *p,
87 struct radeon_cs_packet *pkt);
89 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
91 int r200_packet0_check(struct radeon_cs_parser *p,
92 struct radeon_cs_packet *pkt,
93 unsigned idx, unsigned reg);
97 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
98 struct radeon_cs_packet *pkt,
105 struct radeon_cs_reloc *reloc;
108 r = r100_cs_packet_next_reloc(p, &reloc);
110 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
112 r100_cs_dump_packet(p, pkt);
115 value = radeon_get_ib_value(p, idx);
116 tmp = value & 0x003fffff;
117 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
119 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
120 tile_flags |= RADEON_DST_TILE_MACRO;
121 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
122 if (reg == RADEON_SRC_PITCH_OFFSET) {
123 DRM_ERROR("Cannot src blit from microtiled surface\n");
124 r100_cs_dump_packet(p, pkt);
127 tile_flags |= RADEON_DST_TILE_MICRO;
131 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
135 static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
136 struct radeon_cs_packet *pkt,
140 struct radeon_cs_reloc *reloc;
141 struct r100_cs_track *track;
143 volatile uint32_t *ib;
147 track = (struct r100_cs_track *)p->track;
148 c = radeon_get_ib_value(p, idx++) & 0x1F;
149 track->num_arrays = c;
150 for (i = 0; i < (c - 1); i+=2, idx+=3) {
151 r = r100_cs_packet_next_reloc(p, &reloc);
153 DRM_ERROR("No reloc for packet3 %d\n",
155 r100_cs_dump_packet(p, pkt);
158 idx_value = radeon_get_ib_value(p, idx);
159 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
161 track->arrays[i + 0].esize = idx_value >> 8;
162 track->arrays[i + 0].robj = reloc->robj;
163 track->arrays[i + 0].esize &= 0x7F;
164 r = r100_cs_packet_next_reloc(p, &reloc);
166 DRM_ERROR("No reloc for packet3 %d\n",
168 r100_cs_dump_packet(p, pkt);
171 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
172 track->arrays[i + 1].robj = reloc->robj;
173 track->arrays[i + 1].esize = idx_value >> 24;
174 track->arrays[i + 1].esize &= 0x7F;
177 r = r100_cs_packet_next_reloc(p, &reloc);
179 DRM_ERROR("No reloc for packet3 %d\n",
181 r100_cs_dump_packet(p, pkt);
184 idx_value = radeon_get_ib_value(p, idx);
185 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
186 track->arrays[i + 0].robj = reloc->robj;
187 track->arrays[i + 0].esize = idx_value >> 8;
188 track->arrays[i + 0].esize &= 0x7F;