2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "radeon_drm.h"
31 #include "radeon_reg.h"
35 #include "r200_reg_safe.h"
37 #include "r100_track.h"
39 static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
44 if (vtx_fmt_0 & R200_VTX_Z0)
46 if (vtx_fmt_0 & R200_VTX_W0)
49 if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
50 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
51 if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
53 if (vtx_fmt_0 & R200_VTX_N0)
55 if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
57 if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
59 if (vtx_fmt_0 & R200_VTX_SHININESS_0)
61 if (vtx_fmt_0 & R200_VTX_SHININESS_1)
63 for (i = 0; i < 8; i++) {
64 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
67 case 1: vtx_size++; break;
68 case 2: vtx_size += 3; break;
69 case 3: vtx_size += 4; break;
72 if (vtx_fmt_0 & R200_VTX_XY1)
74 if (vtx_fmt_0 & R200_VTX_Z1)
76 if (vtx_fmt_0 & R200_VTX_W1)
78 if (vtx_fmt_0 & R200_VTX_N1)
83 int r200_copy_dma(struct radeon_device *rdev,
87 struct radeon_fence *fence)
94 /* radeon pitch is /64 */
95 size = num_pages << PAGE_SHIFT;
96 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
97 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
99 DRM_ERROR("radeon: moving bo (%d).\n", r);
102 /* Must wait for 2D idle & clean before DMA or hangs might happen */
103 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
104 radeon_ring_write(rdev, (1 << 16));
105 for (i = 0; i < num_loops; i++) {
107 if (cur_size > 0x1FFFFF) {
111 radeon_ring_write(rdev, PACKET0(0x720, 2));
112 radeon_ring_write(rdev, src_offset);
113 radeon_ring_write(rdev, dst_offset);
114 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
115 src_offset += cur_size;
116 dst_offset += cur_size;
118 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
119 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
121 r = radeon_fence_emit(rdev, fence);
123 radeon_ring_unlock_commit(rdev);
128 static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
130 int vtx_size, i, tex_size;
132 for (i = 0; i < 6; i++) {
133 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
136 vtx_size += tex_size;
141 int r200_packet0_check(struct radeon_cs_parser *p,
142 struct radeon_cs_packet *pkt,
143 unsigned idx, unsigned reg)
145 struct radeon_cs_reloc *reloc;
146 struct r100_cs_track *track;
147 volatile uint32_t *ib;
156 track = (struct r100_cs_track *)p->track;
157 idx_value = radeon_get_ib_value(p, idx);
159 case RADEON_CRTC_GUI_TRIG_VLINE:
160 r = r100_cs_packet_parse_vline(p);
162 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
164 r100_cs_dump_packet(p, pkt);
168 /* FIXME: only allow PACKET3 blit? easier to check for out of
170 case RADEON_DST_PITCH_OFFSET:
171 case RADEON_SRC_PITCH_OFFSET:
172 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
176 case RADEON_RB3D_DEPTHOFFSET:
177 r = r100_cs_packet_next_reloc(p, &reloc);
179 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
181 r100_cs_dump_packet(p, pkt);
184 track->zb.robj = reloc->robj;
185 track->zb.offset = idx_value;
186 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
188 case RADEON_RB3D_COLOROFFSET:
189 r = r100_cs_packet_next_reloc(p, &reloc);
191 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
193 r100_cs_dump_packet(p, pkt);
196 track->cb[0].robj = reloc->robj;
197 track->cb[0].offset = idx_value;
198 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
200 case R200_PP_TXOFFSET_0:
201 case R200_PP_TXOFFSET_1:
202 case R200_PP_TXOFFSET_2:
203 case R200_PP_TXOFFSET_3:
204 case R200_PP_TXOFFSET_4:
205 case R200_PP_TXOFFSET_5:
206 i = (reg - R200_PP_TXOFFSET_0) / 24;
207 r = r100_cs_packet_next_reloc(p, &reloc);
209 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
211 r100_cs_dump_packet(p, pkt);
214 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
215 track->textures[i].robj = reloc->robj;
217 case R200_PP_CUBIC_OFFSET_F1_0:
218 case R200_PP_CUBIC_OFFSET_F2_0:
219 case R200_PP_CUBIC_OFFSET_F3_0:
220 case R200_PP_CUBIC_OFFSET_F4_0:
221 case R200_PP_CUBIC_OFFSET_F5_0:
222 case R200_PP_CUBIC_OFFSET_F1_1:
223 case R200_PP_CUBIC_OFFSET_F2_1:
224 case R200_PP_CUBIC_OFFSET_F3_1:
225 case R200_PP_CUBIC_OFFSET_F4_1:
226 case R200_PP_CUBIC_OFFSET_F5_1:
227 case R200_PP_CUBIC_OFFSET_F1_2:
228 case R200_PP_CUBIC_OFFSET_F2_2:
229 case R200_PP_CUBIC_OFFSET_F3_2:
230 case R200_PP_CUBIC_OFFSET_F4_2:
231 case R200_PP_CUBIC_OFFSET_F5_2:
232 case R200_PP_CUBIC_OFFSET_F1_3:
233 case R200_PP_CUBIC_OFFSET_F2_3:
234 case R200_PP_CUBIC_OFFSET_F3_3:
235 case R200_PP_CUBIC_OFFSET_F4_3:
236 case R200_PP_CUBIC_OFFSET_F5_3:
237 case R200_PP_CUBIC_OFFSET_F1_4:
238 case R200_PP_CUBIC_OFFSET_F2_4:
239 case R200_PP_CUBIC_OFFSET_F3_4:
240 case R200_PP_CUBIC_OFFSET_F4_4:
241 case R200_PP_CUBIC_OFFSET_F5_4:
242 case R200_PP_CUBIC_OFFSET_F1_5:
243 case R200_PP_CUBIC_OFFSET_F2_5:
244 case R200_PP_CUBIC_OFFSET_F3_5:
245 case R200_PP_CUBIC_OFFSET_F4_5:
246 case R200_PP_CUBIC_OFFSET_F5_5:
247 i = (reg - R200_PP_TXOFFSET_0) / 24;
248 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
249 r = r100_cs_packet_next_reloc(p, &reloc);
251 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
253 r100_cs_dump_packet(p, pkt);
256 track->textures[i].cube_info[face - 1].offset = idx_value;
257 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
258 track->textures[i].cube_info[face - 1].robj = reloc->robj;
260 case RADEON_RE_WIDTH_HEIGHT:
261 track->maxy = ((idx_value >> 16) & 0x7FF);
263 case RADEON_RB3D_COLORPITCH:
264 r = r100_cs_packet_next_reloc(p, &reloc);
266 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
268 r100_cs_dump_packet(p, pkt);
272 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
273 tile_flags |= RADEON_COLOR_TILE_ENABLE;
274 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
275 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
277 tmp = idx_value & ~(0x7 << 16);
281 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
283 case RADEON_RB3D_DEPTHPITCH:
284 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
286 case RADEON_RB3D_CNTL:
287 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
293 track->cb[0].cpp = 1;
298 track->cb[0].cpp = 2;
301 track->cb[0].cpp = 4;
304 DRM_ERROR("Invalid color buffer format (%d) !\n",
305 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
308 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
309 DRM_ERROR("No support for depth xy offset in kms\n");
313 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
315 case RADEON_RB3D_ZSTENCILCNTL:
316 switch (idx_value & 0xf) {
332 case RADEON_RB3D_ZPASS_ADDR:
333 r = r100_cs_packet_next_reloc(p, &reloc);
335 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
337 r100_cs_dump_packet(p, pkt);
340 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
344 uint32_t temp = idx_value >> 4;
345 for (i = 0; i < track->num_texture; i++)
346 track->textures[i].enabled = !!(temp & (1 << i));
349 case RADEON_SE_VF_CNTL:
350 track->vap_vf_cntl = idx_value;
353 /* VAP_VF_MAX_VTX_INDX */
354 track->max_indx = idx_value & 0x00FFFFFFUL;
356 case R200_SE_VTX_FMT_0:
357 track->vtx_size = r200_get_vtx_size_0(idx_value);
359 case R200_SE_VTX_FMT_1:
360 track->vtx_size += r200_get_vtx_size_1(idx_value);
362 case R200_PP_TXSIZE_0:
363 case R200_PP_TXSIZE_1:
364 case R200_PP_TXSIZE_2:
365 case R200_PP_TXSIZE_3:
366 case R200_PP_TXSIZE_4:
367 case R200_PP_TXSIZE_5:
368 i = (reg - R200_PP_TXSIZE_0) / 32;
369 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
370 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
372 case R200_PP_TXPITCH_0:
373 case R200_PP_TXPITCH_1:
374 case R200_PP_TXPITCH_2:
375 case R200_PP_TXPITCH_3:
376 case R200_PP_TXPITCH_4:
377 case R200_PP_TXPITCH_5:
378 i = (reg - R200_PP_TXPITCH_0) / 32;
379 track->textures[i].pitch = idx_value + 32;
381 case R200_PP_TXFILTER_0:
382 case R200_PP_TXFILTER_1:
383 case R200_PP_TXFILTER_2:
384 case R200_PP_TXFILTER_3:
385 case R200_PP_TXFILTER_4:
386 case R200_PP_TXFILTER_5:
387 i = (reg - R200_PP_TXFILTER_0) / 32;
388 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
389 >> R200_MAX_MIP_LEVEL_SHIFT);
390 tmp = (idx_value >> 23) & 0x7;
391 if (tmp == 2 || tmp == 6)
392 track->textures[i].roundup_w = false;
393 tmp = (idx_value >> 27) & 0x7;
394 if (tmp == 2 || tmp == 6)
395 track->textures[i].roundup_h = false;
397 case R200_PP_TXMULTI_CTL_0:
398 case R200_PP_TXMULTI_CTL_1:
399 case R200_PP_TXMULTI_CTL_2:
400 case R200_PP_TXMULTI_CTL_3:
401 case R200_PP_TXMULTI_CTL_4:
402 case R200_PP_TXMULTI_CTL_5:
403 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
405 case R200_PP_TXFORMAT_X_0:
406 case R200_PP_TXFORMAT_X_1:
407 case R200_PP_TXFORMAT_X_2:
408 case R200_PP_TXFORMAT_X_3:
409 case R200_PP_TXFORMAT_X_4:
410 case R200_PP_TXFORMAT_X_5:
411 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
412 track->textures[i].txdepth = idx_value & 0x7;
413 tmp = (idx_value >> 16) & 0x3;
421 track->textures[i].tex_coord_type = 0;
425 track->textures[i].tex_coord_type = 2;
429 track->textures[i].tex_coord_type = 1;
433 case R200_PP_TXFORMAT_0:
434 case R200_PP_TXFORMAT_1:
435 case R200_PP_TXFORMAT_2:
436 case R200_PP_TXFORMAT_3:
437 case R200_PP_TXFORMAT_4:
438 case R200_PP_TXFORMAT_5:
439 i = (reg - R200_PP_TXFORMAT_0) / 32;
440 if (idx_value & R200_TXFORMAT_NON_POWER2) {
441 track->textures[i].use_pitch = 1;
443 track->textures[i].use_pitch = 0;
444 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
445 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
447 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
448 case R200_TXFORMAT_I8:
449 case R200_TXFORMAT_RGB332:
450 case R200_TXFORMAT_Y8:
451 track->textures[i].cpp = 1;
453 case R200_TXFORMAT_AI88:
454 case R200_TXFORMAT_ARGB1555:
455 case R200_TXFORMAT_RGB565:
456 case R200_TXFORMAT_ARGB4444:
457 case R200_TXFORMAT_VYUY422:
458 case R200_TXFORMAT_YVYU422:
459 case R200_TXFORMAT_LDVDU655:
460 case R200_TXFORMAT_DVDU88:
461 case R200_TXFORMAT_AVYU4444:
462 track->textures[i].cpp = 2;
464 case R200_TXFORMAT_ARGB8888:
465 case R200_TXFORMAT_RGBA8888:
466 case R200_TXFORMAT_ABGR8888:
467 case R200_TXFORMAT_BGR111110:
468 case R200_TXFORMAT_LDVDU8888:
469 track->textures[i].cpp = 4;
471 case R200_TXFORMAT_DXT1:
472 track->textures[i].cpp = 1;
473 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
475 case R200_TXFORMAT_DXT23:
476 case R200_TXFORMAT_DXT45:
477 track->textures[i].cpp = 1;
478 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
481 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
482 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
484 case R200_PP_CUBIC_FACES_0:
485 case R200_PP_CUBIC_FACES_1:
486 case R200_PP_CUBIC_FACES_2:
487 case R200_PP_CUBIC_FACES_3:
488 case R200_PP_CUBIC_FACES_4:
489 case R200_PP_CUBIC_FACES_5:
491 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
492 for (face = 0; face < 4; face++) {
493 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
494 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
498 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
505 void r200_set_safe_registers(struct radeon_device *rdev)
507 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
508 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);