2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_reg.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
37 #include "r300_reg_safe.h"
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
50 * rv370,rv380 PCIE GART
52 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
54 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
59 /* Workaround HW bug do flush 2 times */
60 for (i = 0; i < 2; i++) {
61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
69 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
73 if (i < 0 || i > rdev->gart.num_gpu_pages) {
76 addr = (lower_32_bits(addr) >> 8) |
77 ((upper_32_bits(addr) & 0xff) << 24) |
79 /* on x86 we want this to be CPU endian, on powerpc
80 * on powerpc without HW swappers, it'll get swapped on way
81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 writel(addr, ((void __iomem *)ptr) + (i * 4));
86 int rv370_pcie_gart_init(struct radeon_device *rdev)
90 if (rdev->gart.table.vram.robj) {
91 WARN(1, "RV370 PCIE GART already initialized.\n");
94 /* Initialize common gart structure */
95 r = radeon_gart_init(rdev);
98 r = rv370_debugfs_pcie_gart_info_init(rdev);
100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 return radeon_gart_table_vram_alloc(rdev);
107 int rv370_pcie_gart_enable(struct radeon_device *rdev)
113 if (rdev->gart.table.vram.robj == NULL) {
114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
117 r = radeon_gart_table_vram_pin(rdev);
120 radeon_gart_restore(rdev);
121 /* discard memory request outside of configured range */
122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129 table_addr = rdev->gart.table_addr;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131 /* FIXME: setup default page */
132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
135 WREG32_PCIE(0x18, 0);
136 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
137 tmp |= RADEON_PCIE_TX_GART_EN;
138 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
140 rv370_pcie_gart_tlb_flush(rdev);
141 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
142 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
143 rdev->gart.ready = true;
147 void rv370_pcie_gart_disable(struct radeon_device *rdev)
152 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
153 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
154 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
155 if (rdev->gart.table.vram.robj) {
156 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
157 if (likely(r == 0)) {
158 radeon_bo_kunmap(rdev->gart.table.vram.robj);
159 radeon_bo_unpin(rdev->gart.table.vram.robj);
160 radeon_bo_unreserve(rdev->gart.table.vram.robj);
165 void rv370_pcie_gart_fini(struct radeon_device *rdev)
167 rv370_pcie_gart_disable(rdev);
168 radeon_gart_table_vram_free(rdev);
169 radeon_gart_fini(rdev);
172 void r300_fence_ring_emit(struct radeon_device *rdev,
173 struct radeon_fence *fence)
175 /* Who ever call radeon_fence_emit should call ring_lock and ask
176 * for enough space (today caller are ib schedule and buffer move) */
177 /* Write SC register so SC & US assert idle */
178 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
179 radeon_ring_write(rdev, 0);
180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
181 radeon_ring_write(rdev, 0);
183 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
184 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_ZC_FLUSH);
187 /* Wait until IDLE & CLEAN */
188 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
189 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
190 RADEON_WAIT_2D_IDLECLEAN |
191 RADEON_WAIT_DMA_GUI_IDLE));
192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
194 RADEON_HDP_READ_BUFFER_INVALIDATE);
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
197 /* Emit fence sequence & fire IRQ */
198 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
199 radeon_ring_write(rdev, fence->seq);
200 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
201 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
204 void r300_ring_start(struct radeon_device *rdev)
206 unsigned gb_tile_config;
209 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
210 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
211 switch(rdev->num_gb_pipes) {
213 gb_tile_config |= R300_PIPE_COUNT_R300;
216 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
219 gb_tile_config |= R300_PIPE_COUNT_R420;
223 gb_tile_config |= R300_PIPE_COUNT_RV350;
227 r = radeon_ring_lock(rdev, 64);
231 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
232 radeon_ring_write(rdev,
233 RADEON_ISYNC_ANY2D_IDLE3D |
234 RADEON_ISYNC_ANY3D_IDLE2D |
235 RADEON_ISYNC_WAIT_IDLEGUI |
236 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
237 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
238 radeon_ring_write(rdev, gb_tile_config);
239 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
240 radeon_ring_write(rdev,
241 RADEON_WAIT_2D_IDLECLEAN |
242 RADEON_WAIT_3D_IDLECLEAN);
243 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
244 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
245 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
246 radeon_ring_write(rdev, 0);
247 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
250 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
253 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
254 radeon_ring_write(rdev,
255 RADEON_WAIT_2D_IDLECLEAN |
256 RADEON_WAIT_3D_IDLECLEAN);
257 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
258 radeon_ring_write(rdev, 0);
259 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
260 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
264 radeon_ring_write(rdev,
265 ((6 << R300_MS_X0_SHIFT) |
266 (6 << R300_MS_Y0_SHIFT) |
267 (6 << R300_MS_X1_SHIFT) |
268 (6 << R300_MS_Y1_SHIFT) |
269 (6 << R300_MS_X2_SHIFT) |
270 (6 << R300_MS_Y2_SHIFT) |
271 (6 << R300_MSBD0_Y_SHIFT) |
272 (6 << R300_MSBD0_X_SHIFT)));
273 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
274 radeon_ring_write(rdev,
275 ((6 << R300_MS_X3_SHIFT) |
276 (6 << R300_MS_Y3_SHIFT) |
277 (6 << R300_MS_X4_SHIFT) |
278 (6 << R300_MS_Y4_SHIFT) |
279 (6 << R300_MS_X5_SHIFT) |
280 (6 << R300_MS_Y5_SHIFT) |
281 (6 << R300_MSBD1_SHIFT)));
282 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
283 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
284 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
285 radeon_ring_write(rdev,
286 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
287 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
288 radeon_ring_write(rdev,
289 R300_GEOMETRY_ROUND_NEAREST |
290 R300_COLOR_ROUND_NEAREST);
291 radeon_ring_unlock_commit(rdev);
294 void r300_errata(struct radeon_device *rdev)
296 rdev->pll_errata = 0;
298 if (rdev->family == CHIP_R300 &&
299 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
300 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
304 int r300_mc_wait_for_idle(struct radeon_device *rdev)
309 for (i = 0; i < rdev->usec_timeout; i++) {
311 tmp = RREG32(RADEON_MC_STATUS);
312 if (tmp & R300_MC_IDLE) {
320 void r300_gpu_init(struct radeon_device *rdev)
322 uint32_t gb_tile_config, tmp;
324 r100_hdp_reset(rdev);
325 /* FIXME: rv380 one pipes ? */
326 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
328 rdev->num_gb_pipes = 2;
330 /* rv350,rv370,rv380 */
331 rdev->num_gb_pipes = 1;
333 rdev->num_z_pipes = 1;
334 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
335 switch (rdev->num_gb_pipes) {
337 gb_tile_config |= R300_PIPE_COUNT_R300;
340 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
343 gb_tile_config |= R300_PIPE_COUNT_R420;
347 gb_tile_config |= R300_PIPE_COUNT_RV350;
350 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
352 if (r100_gui_wait_for_idle(rdev)) {
353 printk(KERN_WARNING "Failed to wait GUI idle while "
354 "programming pipes. Bad things might happen.\n");
357 tmp = RREG32(R300_DST_PIPE_CONFIG);
358 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
360 WREG32(R300_RB2D_DSTCACHE_MODE,
361 R300_DC_AUTOFLUSH_ENABLE |
362 R300_DC_DC_DISABLE_IGNORE_PE);
364 if (r100_gui_wait_for_idle(rdev)) {
365 printk(KERN_WARNING "Failed to wait GUI idle while "
366 "programming pipes. Bad things might happen.\n");
368 if (r300_mc_wait_for_idle(rdev)) {
369 printk(KERN_WARNING "Failed to wait MC idle while "
370 "programming pipes. Bad things might happen.\n");
372 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
373 rdev->num_gb_pipes, rdev->num_z_pipes);
376 int r300_ga_reset(struct radeon_device *rdev)
382 reinit_cp = rdev->cp.ready;
383 rdev->cp.ready = false;
384 for (i = 0; i < rdev->usec_timeout; i++) {
385 WREG32(RADEON_CP_CSQ_MODE, 0);
386 WREG32(RADEON_CP_CSQ_CNTL, 0);
387 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
388 (void)RREG32(RADEON_RBBM_SOFT_RESET);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0);
391 /* Wait to prevent race in RBBM_STATUS */
393 tmp = RREG32(RADEON_RBBM_STATUS);
394 if (tmp & ((1 << 20) | (1 << 26))) {
395 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
396 /* GA still busy soft reset it */
397 WREG32(0x429C, 0x200);
398 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
399 WREG32(R300_RE_SCISSORS_TL, 0);
400 WREG32(R300_RE_SCISSORS_BR, 0);
403 /* Wait to prevent race in RBBM_STATUS */
405 tmp = RREG32(RADEON_RBBM_STATUS);
406 if (!(tmp & ((1 << 20) | (1 << 26)))) {
410 for (i = 0; i < rdev->usec_timeout; i++) {
411 tmp = RREG32(RADEON_RBBM_STATUS);
412 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
416 return r100_cp_init(rdev, rdev->cp.ring_size);
422 tmp = RREG32(RADEON_RBBM_STATUS);
423 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
427 int r300_gpu_reset(struct radeon_device *rdev)
431 /* reset order likely matter */
432 status = RREG32(RADEON_RBBM_STATUS);
434 r100_hdp_reset(rdev);
436 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
437 r100_rb2d_reset(rdev);
440 if (status & ((1 << 20) | (1 << 26))) {
444 status = RREG32(RADEON_RBBM_STATUS);
445 if (status & (1 << 16)) {
448 /* Check if GPU is idle */
449 status = RREG32(RADEON_RBBM_STATUS);
450 if (status & RADEON_RBBM_ACTIVE) {
451 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
454 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
460 * r300,r350,rv350,rv380 VRAM info
462 void r300_mc_init(struct radeon_device *rdev)
467 /* DDR for all card after R300 & IGP */
468 rdev->mc.vram_is_ddr = true;
469 tmp = RREG32(RADEON_MEM_CNTL);
470 tmp &= R300_MEM_NUM_CHANNELS_MASK;
472 case 0: rdev->mc.vram_width = 64; break;
473 case 1: rdev->mc.vram_width = 128; break;
474 case 2: rdev->mc.vram_width = 256; break;
475 default: rdev->mc.vram_width = 128; break;
477 r100_vram_init_sizes(rdev);
478 base = rdev->mc.aper_base;
479 if (rdev->flags & RADEON_IS_IGP)
480 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
481 radeon_vram_location(rdev, &rdev->mc, base);
482 if (!(rdev->flags & RADEON_IS_AGP))
483 radeon_gtt_location(rdev, &rdev->mc);
486 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
488 uint32_t link_width_cntl, mask;
490 if (rdev->flags & RADEON_IS_IGP)
493 if (!(rdev->flags & RADEON_IS_PCIE))
496 /* FIXME wait for idle */
500 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
503 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
506 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
509 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
512 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
515 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
519 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
523 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
525 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
526 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
529 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
530 RADEON_PCIE_LC_RECONFIG_NOW |
531 RADEON_PCIE_LC_RECONFIG_LATER |
532 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
533 link_width_cntl |= mask;
534 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
535 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
536 RADEON_PCIE_LC_RECONFIG_NOW));
538 /* wait for lane set to complete */
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
540 while (link_width_cntl == 0xffffffff)
541 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
545 int rv370_get_pcie_lanes(struct radeon_device *rdev)
549 if (rdev->flags & RADEON_IS_IGP)
552 if (!(rdev->flags & RADEON_IS_PCIE))
555 /* FIXME wait for idle */
557 if (rdev->family < CHIP_R600)
558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
560 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
563 case RADEON_PCIE_LC_LINK_WIDTH_X0:
565 case RADEON_PCIE_LC_LINK_WIDTH_X1:
567 case RADEON_PCIE_LC_LINK_WIDTH_X2:
569 case RADEON_PCIE_LC_LINK_WIDTH_X4:
571 case RADEON_PCIE_LC_LINK_WIDTH_X8:
573 case RADEON_PCIE_LC_LINK_WIDTH_X16:
579 #if defined(CONFIG_DEBUG_FS)
580 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
582 struct drm_info_node *node = (struct drm_info_node *) m->private;
583 struct drm_device *dev = node->minor->dev;
584 struct radeon_device *rdev = dev->dev_private;
587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
588 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
590 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
592 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
594 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
596 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
598 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
600 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
604 static struct drm_info_list rv370_pcie_gart_info_list[] = {
605 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
609 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
611 #if defined(CONFIG_DEBUG_FS)
612 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
618 static int r300_packet0_check(struct radeon_cs_parser *p,
619 struct radeon_cs_packet *pkt,
620 unsigned idx, unsigned reg)
622 struct radeon_cs_reloc *reloc;
623 struct r100_cs_track *track;
624 volatile uint32_t *ib;
625 uint32_t tmp, tile_flags = 0;
631 track = (struct r100_cs_track *)p->track;
632 idx_value = radeon_get_ib_value(p, idx);
635 case AVIVO_D1MODE_VLINE_START_END:
636 case RADEON_CRTC_GUI_TRIG_VLINE:
637 r = r100_cs_packet_parse_vline(p);
639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641 r100_cs_dump_packet(p, pkt);
645 case RADEON_DST_PITCH_OFFSET:
646 case RADEON_SRC_PITCH_OFFSET:
647 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
651 case R300_RB3D_COLOROFFSET0:
652 case R300_RB3D_COLOROFFSET1:
653 case R300_RB3D_COLOROFFSET2:
654 case R300_RB3D_COLOROFFSET3:
655 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
656 r = r100_cs_packet_next_reloc(p, &reloc);
658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
660 r100_cs_dump_packet(p, pkt);
663 track->cb[i].robj = reloc->robj;
664 track->cb[i].offset = idx_value;
665 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
667 case R300_ZB_DEPTHOFFSET:
668 r = r100_cs_packet_next_reloc(p, &reloc);
670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
672 r100_cs_dump_packet(p, pkt);
675 track->zb.robj = reloc->robj;
676 track->zb.offset = idx_value;
677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
679 case R300_TX_OFFSET_0:
680 case R300_TX_OFFSET_0+4:
681 case R300_TX_OFFSET_0+8:
682 case R300_TX_OFFSET_0+12:
683 case R300_TX_OFFSET_0+16:
684 case R300_TX_OFFSET_0+20:
685 case R300_TX_OFFSET_0+24:
686 case R300_TX_OFFSET_0+28:
687 case R300_TX_OFFSET_0+32:
688 case R300_TX_OFFSET_0+36:
689 case R300_TX_OFFSET_0+40:
690 case R300_TX_OFFSET_0+44:
691 case R300_TX_OFFSET_0+48:
692 case R300_TX_OFFSET_0+52:
693 case R300_TX_OFFSET_0+56:
694 case R300_TX_OFFSET_0+60:
695 i = (reg - R300_TX_OFFSET_0) >> 2;
696 r = r100_cs_packet_next_reloc(p, &reloc);
698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
700 r100_cs_dump_packet(p, pkt);
704 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
705 tile_flags |= R300_TXO_MACRO_TILE;
706 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
707 tile_flags |= R300_TXO_MICRO_TILE;
708 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
709 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
711 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
714 track->textures[i].robj = reloc->robj;
716 /* Tracked registers */
719 track->vap_vf_cntl = idx_value;
723 track->vtx_size = idx_value & 0x7F;
726 /* VAP_VF_MAX_VTX_INDX */
727 track->max_indx = idx_value & 0x00FFFFFFUL;
731 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
732 if (p->rdev->family < CHIP_RV515) {
738 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
744 /* RB3D_COLORPITCH0 */
745 /* RB3D_COLORPITCH1 */
746 /* RB3D_COLORPITCH2 */
747 /* RB3D_COLORPITCH3 */
748 r = r100_cs_packet_next_reloc(p, &reloc);
750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
752 r100_cs_dump_packet(p, pkt);
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
757 tile_flags |= R300_COLOR_TILE_ENABLE;
758 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
759 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
760 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
761 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
763 tmp = idx_value & ~(0x7 << 16);
767 i = (reg - 0x4E38) >> 2;
768 track->cb[i].pitch = idx_value & 0x3FFE;
769 switch (((idx_value >> 21) & 0xF)) {
773 track->cb[i].cpp = 1;
779 track->cb[i].cpp = 2;
782 track->cb[i].cpp = 4;
785 track->cb[i].cpp = 8;
788 track->cb[i].cpp = 16;
791 DRM_ERROR("Invalid color buffer format (%d) !\n",
792 ((idx_value >> 21) & 0xF));
799 track->z_enabled = true;
801 track->z_enabled = false;
806 switch ((idx_value & 0xF)) {
815 DRM_ERROR("Invalid z buffer format (%d) !\n",
822 r = r100_cs_packet_next_reloc(p, &reloc);
824 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
826 r100_cs_dump_packet(p, pkt);
830 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
831 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
832 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
833 tile_flags |= R300_DEPTHMICROTILE_TILED;
834 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
835 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
837 tmp = idx_value & ~(0x7 << 16);
841 track->zb.pitch = idx_value & 0x3FFC;
844 for (i = 0; i < 16; i++) {
847 enabled = !!(idx_value & (1 << i));
848 track->textures[i].enabled = enabled;
867 /* TX_FORMAT1_[0-15] */
868 i = (reg - 0x44C0) >> 2;
869 tmp = (idx_value >> 25) & 0x3;
870 track->textures[i].tex_coord_type = tmp;
871 switch ((idx_value & 0x1F)) {
872 case R300_TX_FORMAT_X8:
873 case R300_TX_FORMAT_Y4X4:
874 case R300_TX_FORMAT_Z3Y3X2:
875 track->textures[i].cpp = 1;
877 case R300_TX_FORMAT_X16:
878 case R300_TX_FORMAT_Y8X8:
879 case R300_TX_FORMAT_Z5Y6X5:
880 case R300_TX_FORMAT_Z6Y5X5:
881 case R300_TX_FORMAT_W4Z4Y4X4:
882 case R300_TX_FORMAT_W1Z5Y5X5:
883 case R300_TX_FORMAT_D3DMFT_CxV8U8:
884 case R300_TX_FORMAT_B8G8_B8G8:
885 case R300_TX_FORMAT_G8R8_G8B8:
886 track->textures[i].cpp = 2;
888 case R300_TX_FORMAT_Y16X16:
889 case R300_TX_FORMAT_Z11Y11X10:
890 case R300_TX_FORMAT_Z10Y11X11:
891 case R300_TX_FORMAT_W8Z8Y8X8:
892 case R300_TX_FORMAT_W2Z10Y10X10:
894 case R300_TX_FORMAT_FL_I32:
896 track->textures[i].cpp = 4;
898 case R300_TX_FORMAT_W16Z16Y16X16:
899 case R300_TX_FORMAT_FL_R16G16B16A16:
900 case R300_TX_FORMAT_FL_I32A32:
901 track->textures[i].cpp = 8;
903 case R300_TX_FORMAT_FL_R32G32B32A32:
904 track->textures[i].cpp = 16;
906 case R300_TX_FORMAT_DXT1:
907 track->textures[i].cpp = 1;
908 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
910 case R300_TX_FORMAT_ATI2N:
911 if (p->rdev->family < CHIP_R420) {
912 DRM_ERROR("Invalid texture format %u\n",
916 /* The same rules apply as for DXT3/5. */
918 case R300_TX_FORMAT_DXT3:
919 case R300_TX_FORMAT_DXT5:
920 track->textures[i].cpp = 1;
921 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
924 DRM_ERROR("Invalid texture format %u\n",
946 /* TX_FILTER0_[0-15] */
947 i = (reg - 0x4400) >> 2;
948 tmp = idx_value & 0x7;
949 if (tmp == 2 || tmp == 4 || tmp == 6) {
950 track->textures[i].roundup_w = false;
952 tmp = (idx_value >> 3) & 0x7;
953 if (tmp == 2 || tmp == 4 || tmp == 6) {
954 track->textures[i].roundup_h = false;
973 /* TX_FORMAT2_[0-15] */
974 i = (reg - 0x4500) >> 2;
975 tmp = idx_value & 0x3FFF;
976 track->textures[i].pitch = tmp + 1;
977 if (p->rdev->family >= CHIP_RV515) {
978 tmp = ((idx_value >> 15) & 1) << 11;
979 track->textures[i].width_11 = tmp;
980 tmp = ((idx_value >> 16) & 1) << 11;
981 track->textures[i].height_11 = tmp;
984 if (idx_value & (1 << 14)) {
985 /* The same rules apply as for DXT1. */
986 track->textures[i].compress_format =
987 R100_TRACK_COMP_DXT1;
989 } else if (idx_value & (1 << 14)) {
990 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1010 /* TX_FORMAT0_[0-15] */
1011 i = (reg - 0x4480) >> 2;
1012 tmp = idx_value & 0x7FF;
1013 track->textures[i].width = tmp + 1;
1014 tmp = (idx_value >> 11) & 0x7FF;
1015 track->textures[i].height = tmp + 1;
1016 tmp = (idx_value >> 26) & 0xF;
1017 track->textures[i].num_levels = tmp;
1018 tmp = idx_value & (1 << 31);
1019 track->textures[i].use_pitch = !!tmp;
1020 tmp = (idx_value >> 22) & 0xF;
1021 track->textures[i].txdepth = tmp;
1023 case R300_ZB_ZPASS_ADDR:
1024 r = r100_cs_packet_next_reloc(p, &reloc);
1026 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1028 r100_cs_dump_packet(p, pkt);
1031 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1034 /* RB3D_COLOR_CHANNEL_MASK */
1035 track->color_channel_mask = idx_value;
1039 track->fastfill = !!(idx_value & (1 << 2));
1042 /* RB3D_BLENDCNTL */
1043 track->blend_read_enable = !!(idx_value & (1 << 2));
1046 /* valid register only on RV530 */
1047 if (p->rdev->family == CHIP_RV530)
1049 /* fallthrough do not move */
1051 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1058 static int r300_packet3_check(struct radeon_cs_parser *p,
1059 struct radeon_cs_packet *pkt)
1061 struct radeon_cs_reloc *reloc;
1062 struct r100_cs_track *track;
1063 volatile uint32_t *ib;
1069 track = (struct r100_cs_track *)p->track;
1070 switch(pkt->opcode) {
1071 case PACKET3_3D_LOAD_VBPNTR:
1072 r = r100_packet3_load_vbpntr(p, pkt, idx);
1076 case PACKET3_INDX_BUFFER:
1077 r = r100_cs_packet_next_reloc(p, &reloc);
1079 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1080 r100_cs_dump_packet(p, pkt);
1083 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1084 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1090 case PACKET3_3D_DRAW_IMMD:
1091 /* Number of dwords is vtx_size * (num_vertices - 1)
1092 * PRIM_WALK must be equal to 3 vertex data in embedded
1094 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1095 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1098 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1099 track->immd_dwords = pkt->count - 1;
1100 r = r100_cs_track_check(p->rdev, track);
1105 case PACKET3_3D_DRAW_IMMD_2:
1106 /* Number of dwords is vtx_size * (num_vertices - 1)
1107 * PRIM_WALK must be equal to 3 vertex data in embedded
1109 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1110 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1113 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1114 track->immd_dwords = pkt->count;
1115 r = r100_cs_track_check(p->rdev, track);
1120 case PACKET3_3D_DRAW_VBUF:
1121 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1122 r = r100_cs_track_check(p->rdev, track);
1127 case PACKET3_3D_DRAW_VBUF_2:
1128 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1129 r = r100_cs_track_check(p->rdev, track);
1134 case PACKET3_3D_DRAW_INDX:
1135 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1136 r = r100_cs_track_check(p->rdev, track);
1141 case PACKET3_3D_DRAW_INDX_2:
1142 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1143 r = r100_cs_track_check(p->rdev, track);
1151 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1157 int r300_cs_parse(struct radeon_cs_parser *p)
1159 struct radeon_cs_packet pkt;
1160 struct r100_cs_track *track;
1163 track = kzalloc(sizeof(*track), GFP_KERNEL);
1164 r100_cs_track_clear(p->rdev, track);
1167 r = r100_cs_packet_parse(p, &pkt, p->idx);
1171 p->idx += pkt.count + 2;
1174 r = r100_cs_parse_packet0(p, &pkt,
1175 p->rdev->config.r300.reg_safe_bm,
1176 p->rdev->config.r300.reg_safe_bm_size,
1177 &r300_packet0_check);
1182 r = r300_packet3_check(p, &pkt);
1185 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1191 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1195 void r300_set_reg_safe(struct radeon_device *rdev)
1197 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1198 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1201 void r300_mc_program(struct radeon_device *rdev)
1203 struct r100_mc_save save;
1206 r = r100_debugfs_mc_info_init(rdev);
1208 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1211 /* Stops all mc clients */
1212 r100_mc_stop(rdev, &save);
1213 if (rdev->flags & RADEON_IS_AGP) {
1214 WREG32(R_00014C_MC_AGP_LOCATION,
1215 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1216 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1217 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1218 WREG32(R_00015C_AGP_BASE_2,
1219 upper_32_bits(rdev->mc.agp_base) & 0xff);
1221 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1222 WREG32(R_000170_AGP_BASE, 0);
1223 WREG32(R_00015C_AGP_BASE_2, 0);
1225 /* Wait for mc idle */
1226 if (r300_mc_wait_for_idle(rdev))
1227 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1228 /* Program MC, should be a 32bits limited address space */
1229 WREG32(R_000148_MC_FB_LOCATION,
1230 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1231 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1232 r100_mc_resume(rdev, &save);
1235 void r300_clock_startup(struct radeon_device *rdev)
1239 if (radeon_dynclks != -1 && radeon_dynclks)
1240 radeon_legacy_set_clock_gating(rdev, 1);
1241 /* We need to force on some of the block */
1242 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1243 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1244 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1245 tmp |= S_00000D_FORCE_VAP(1);
1246 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1249 static int r300_startup(struct radeon_device *rdev)
1253 /* set common regs */
1254 r100_set_common_regs(rdev);
1256 r300_mc_program(rdev);
1258 r300_clock_startup(rdev);
1259 /* Initialize GPU configuration (# pipes, ...) */
1260 r300_gpu_init(rdev);
1261 /* Initialize GART (initialize after TTM so we can allocate
1262 * memory through TTM but finalize after TTM) */
1263 if (rdev->flags & RADEON_IS_PCIE) {
1264 r = rv370_pcie_gart_enable(rdev);
1269 if (rdev->family == CHIP_R300 ||
1270 rdev->family == CHIP_R350 ||
1271 rdev->family == CHIP_RV350)
1272 r100_enable_bm(rdev);
1274 if (rdev->flags & RADEON_IS_PCI) {
1275 r = r100_pci_gart_enable(rdev);
1281 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1282 /* 1M ring buffer */
1283 r = r100_cp_init(rdev, 1024 * 1024);
1285 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1288 r = r100_wb_init(rdev);
1290 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1291 r = r100_ib_init(rdev);
1293 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1299 int r300_resume(struct radeon_device *rdev)
1301 /* Make sur GART are not working */
1302 if (rdev->flags & RADEON_IS_PCIE)
1303 rv370_pcie_gart_disable(rdev);
1304 if (rdev->flags & RADEON_IS_PCI)
1305 r100_pci_gart_disable(rdev);
1306 /* Resume clock before doing reset */
1307 r300_clock_startup(rdev);
1308 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1309 if (radeon_gpu_reset(rdev)) {
1310 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1311 RREG32(R_000E40_RBBM_STATUS),
1312 RREG32(R_0007C0_CP_STAT));
1315 radeon_combios_asic_init(rdev->ddev);
1316 /* Resume clock after posting */
1317 r300_clock_startup(rdev);
1318 /* Initialize surface registers */
1319 radeon_surface_init(rdev);
1320 return r300_startup(rdev);
1323 int r300_suspend(struct radeon_device *rdev)
1325 r100_cp_disable(rdev);
1326 r100_wb_disable(rdev);
1327 r100_irq_disable(rdev);
1328 if (rdev->flags & RADEON_IS_PCIE)
1329 rv370_pcie_gart_disable(rdev);
1330 if (rdev->flags & RADEON_IS_PCI)
1331 r100_pci_gart_disable(rdev);
1335 void r300_fini(struct radeon_device *rdev)
1340 radeon_gem_fini(rdev);
1341 if (rdev->flags & RADEON_IS_PCIE)
1342 rv370_pcie_gart_fini(rdev);
1343 if (rdev->flags & RADEON_IS_PCI)
1344 r100_pci_gart_fini(rdev);
1345 radeon_agp_fini(rdev);
1346 radeon_irq_kms_fini(rdev);
1347 radeon_fence_driver_fini(rdev);
1348 radeon_bo_fini(rdev);
1349 radeon_atombios_fini(rdev);
1354 int r300_init(struct radeon_device *rdev)
1359 r100_vga_render_disable(rdev);
1360 /* Initialize scratch registers */
1361 radeon_scratch_init(rdev);
1362 /* Initialize surface registers */
1363 radeon_surface_init(rdev);
1364 /* TODO: disable VGA need to use VGA request */
1366 if (!radeon_get_bios(rdev)) {
1367 if (ASIC_IS_AVIVO(rdev))
1370 if (rdev->is_atom_bios) {
1371 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1374 r = radeon_combios_init(rdev);
1378 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1379 if (radeon_gpu_reset(rdev)) {
1381 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1382 RREG32(R_000E40_RBBM_STATUS),
1383 RREG32(R_0007C0_CP_STAT));
1385 /* check if cards are posted or not */
1386 if (radeon_boot_test_post_card(rdev) == false)
1388 /* Set asic errata */
1390 /* Initialize clocks */
1391 radeon_get_clock_info(rdev->ddev);
1392 /* Initialize power management */
1393 radeon_pm_init(rdev);
1394 /* initialize AGP */
1395 if (rdev->flags & RADEON_IS_AGP) {
1396 r = radeon_agp_init(rdev);
1398 radeon_agp_disable(rdev);
1401 /* initialize memory controller */
1404 r = radeon_fence_driver_init(rdev);
1407 r = radeon_irq_kms_init(rdev);
1410 /* Memory manager */
1411 r = radeon_bo_init(rdev);
1414 if (rdev->flags & RADEON_IS_PCIE) {
1415 r = rv370_pcie_gart_init(rdev);
1419 if (rdev->flags & RADEON_IS_PCI) {
1420 r = r100_pci_gart_init(rdev);
1424 r300_set_reg_safe(rdev);
1425 rdev->accel_working = true;
1426 r = r300_startup(rdev);
1428 /* Somethings want wront with the accel init stop accel */
1429 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1433 radeon_irq_kms_fini(rdev);
1434 if (rdev->flags & RADEON_IS_PCIE)
1435 rv370_pcie_gart_fini(rdev);
1436 if (rdev->flags & RADEON_IS_PCI)
1437 r100_pci_gart_fini(rdev);
1438 radeon_agp_fini(rdev);
1439 rdev->accel_working = false;