2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
33 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
35 static int r520_mc_wait_for_idle(struct radeon_device *rdev)
40 for (i = 0; i < rdev->usec_timeout; i++) {
42 tmp = RREG32_MC(R520_MC_STATUS);
43 if (tmp & R520_MC_STATUS_IDLE) {
51 static void r520_gpu_init(struct radeon_device *rdev)
53 unsigned pipe_select_current, gb_pipe_select, tmp;
56 rv515_vga_render_disable(rdev);
58 * DST_PIPE_CONFIG 0x170C
59 * GB_TILE_CONFIG 0x4018
61 * GB_PIPE_SELECT 0x402C
62 * GB_PIPE_SELECT2 0x4124
64 * Z_PIPE_MASK 0x000000003
65 * GB_FIFO_SIZE2 0x4128
66 * SC_SFIFO_SIZE_SHIFT 0
67 * SC_SFIFO_SIZE_MASK 0x000000003
68 * SC_MFIFO_SIZE_SHIFT 2
69 * SC_MFIFO_SIZE_MASK 0x00000000C
70 * FG_SFIFO_SIZE_SHIFT 4
71 * FG_SFIFO_SIZE_MASK 0x000000030
72 * ZB_MFIFO_SIZE_SHIFT 6
73 * ZB_MFIFO_SIZE_MASK 0x0000000C0
77 /* workaround for RV530 */
78 if (rdev->family == CHIP_RV530) {
81 r420_pipes_init(rdev);
82 gb_pipe_select = RREG32(0x402C);
84 pipe_select_current = (tmp >> 2) & 3;
85 tmp = (1 << pipe_select_current) |
86 (((gb_pipe_select >> 8) & 0xF) << 4);
87 WREG32_PLL(0x000D, tmp);
88 if (r520_mc_wait_for_idle(rdev)) {
89 printk(KERN_WARNING "Failed to wait MC idle while "
90 "programming pipes. Bad things might happen.\n");
94 static void r520_vram_get_type(struct radeon_device *rdev)
98 rdev->mc.vram_width = 128;
99 rdev->mc.vram_is_ddr = true;
100 tmp = RREG32_MC(R520_MC_CNTL0);
101 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
103 rdev->mc.vram_width = 32;
106 rdev->mc.vram_width = 64;
109 rdev->mc.vram_width = 128;
112 rdev->mc.vram_width = 256;
115 rdev->mc.vram_width = 128;
118 if (tmp & R520_MC_CHANNEL_SIZE)
119 rdev->mc.vram_width *= 2;
122 void r520_vram_info(struct radeon_device *rdev)
126 r520_vram_get_type(rdev);
128 r100_vram_init_sizes(rdev);
129 /* FIXME: we should enforce default clock in case GPU is not in
132 a.full = rfixed_const(100);
133 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
134 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
137 void r520_mc_program(struct radeon_device *rdev)
139 struct rv515_mc_save save;
141 /* Stops all mc clients */
142 rv515_mc_stop(rdev, &save);
144 /* Wait for mc idle */
145 if (r520_mc_wait_for_idle(rdev))
146 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
147 /* Write VRAM size in case we are limiting it */
148 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
149 /* Program MC, should be a 32bits limited address space */
150 WREG32_MC(R_000004_MC_FB_LOCATION,
151 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
152 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
153 WREG32(R_000134_HDP_FB_LOCATION,
154 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
155 if (rdev->flags & RADEON_IS_AGP) {
156 WREG32_MC(R_000005_MC_AGP_LOCATION,
157 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
158 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
159 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
160 WREG32_MC(R_000007_AGP_BASE_2,
161 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
163 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
164 WREG32_MC(R_000006_AGP_BASE, 0);
165 WREG32_MC(R_000007_AGP_BASE_2, 0);
168 rv515_mc_resume(rdev, &save);
171 static int r520_startup(struct radeon_device *rdev)
175 r520_mc_program(rdev);
177 rv515_clock_startup(rdev);
178 /* Initialize GPU configuration (# pipes, ...) */
180 /* Initialize GART (initialize after TTM so we can allocate
181 * memory through TTM but finalize after TTM) */
182 if (rdev->flags & RADEON_IS_PCIE) {
183 r = rv370_pcie_gart_enable(rdev);
190 r = r100_cp_init(rdev, 1024 * 1024);
192 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
195 r = r100_wb_init(rdev);
197 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
198 r = r100_ib_init(rdev);
200 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
206 int r520_resume(struct radeon_device *rdev)
208 /* Make sur GART are not working */
209 if (rdev->flags & RADEON_IS_PCIE)
210 rv370_pcie_gart_disable(rdev);
211 /* Resume clock before doing reset */
212 rv515_clock_startup(rdev);
213 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
214 if (radeon_gpu_reset(rdev)) {
215 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
216 RREG32(R_000E40_RBBM_STATUS),
217 RREG32(R_0007C0_CP_STAT));
220 atom_asic_init(rdev->mode_info.atom_context);
221 /* Resume clock after posting */
222 rv515_clock_startup(rdev);
223 return r520_startup(rdev);
226 int r520_init(struct radeon_device *rdev)
230 /* Initialize scratch registers */
231 radeon_scratch_init(rdev);
232 /* Initialize surface registers */
233 radeon_surface_init(rdev);
234 /* TODO: disable VGA need to use VGA request */
236 if (!radeon_get_bios(rdev)) {
237 if (ASIC_IS_AVIVO(rdev))
240 if (rdev->is_atom_bios) {
241 r = radeon_atombios_init(rdev);
245 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
248 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
249 if (radeon_gpu_reset(rdev)) {
251 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
252 RREG32(R_000E40_RBBM_STATUS),
253 RREG32(R_0007C0_CP_STAT));
255 /* check if cards are posted or not */
256 if (radeon_boot_test_post_card(rdev) == false)
259 if (!radeon_card_posted(rdev) && rdev->bios) {
260 DRM_INFO("GPU not posted. posting now...\n");
261 atom_asic_init(rdev->mode_info.atom_context);
263 /* Initialize clocks */
264 radeon_get_clock_info(rdev->ddev);
265 /* Initialize power management */
266 radeon_pm_init(rdev);
267 /* Get vram informations */
268 r520_vram_info(rdev);
269 /* Initialize memory controller (also test AGP) */
270 r = r420_mc_init(rdev);
275 r = radeon_fence_driver_init(rdev);
278 r = radeon_irq_kms_init(rdev);
282 r = radeon_bo_init(rdev);
285 r = rv370_pcie_gart_init(rdev);
288 rv515_set_safe_registers(rdev);
289 rdev->accel_working = true;
290 r = r520_startup(rdev);
292 /* Somethings want wront with the accel init stop accel */
293 dev_err(rdev->dev, "Disabling GPU acceleration\n");
298 rv370_pcie_gart_fini(rdev);
299 radeon_agp_fini(rdev);
300 radeon_irq_kms_fini(rdev);
301 rdev->accel_working = false;