2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "radeon_asic.h"
34 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
36 static int r520_mc_wait_for_idle(struct radeon_device *rdev)
41 for (i = 0; i < rdev->usec_timeout; i++) {
43 tmp = RREG32_MC(R520_MC_STATUS);
44 if (tmp & R520_MC_STATUS_IDLE) {
52 static void r520_gpu_init(struct radeon_device *rdev)
54 unsigned pipe_select_current, gb_pipe_select, tmp;
57 rv515_vga_render_disable(rdev);
59 * DST_PIPE_CONFIG 0x170C
60 * GB_TILE_CONFIG 0x4018
62 * GB_PIPE_SELECT 0x402C
63 * GB_PIPE_SELECT2 0x4124
65 * Z_PIPE_MASK 0x000000003
66 * GB_FIFO_SIZE2 0x4128
67 * SC_SFIFO_SIZE_SHIFT 0
68 * SC_SFIFO_SIZE_MASK 0x000000003
69 * SC_MFIFO_SIZE_SHIFT 2
70 * SC_MFIFO_SIZE_MASK 0x00000000C
71 * FG_SFIFO_SIZE_SHIFT 4
72 * FG_SFIFO_SIZE_MASK 0x000000030
73 * ZB_MFIFO_SIZE_SHIFT 6
74 * ZB_MFIFO_SIZE_MASK 0x0000000C0
78 /* workaround for RV530 */
79 if (rdev->family == CHIP_RV530) {
82 r420_pipes_init(rdev);
83 gb_pipe_select = RREG32(0x402C);
85 pipe_select_current = (tmp >> 2) & 3;
86 tmp = (1 << pipe_select_current) |
87 (((gb_pipe_select >> 8) & 0xF) << 4);
88 WREG32_PLL(0x000D, tmp);
89 if (r520_mc_wait_for_idle(rdev)) {
90 printk(KERN_WARNING "Failed to wait MC idle while "
91 "programming pipes. Bad things might happen.\n");
95 static void r520_vram_get_type(struct radeon_device *rdev)
99 rdev->mc.vram_width = 128;
100 rdev->mc.vram_is_ddr = true;
101 tmp = RREG32_MC(R520_MC_CNTL0);
102 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
104 rdev->mc.vram_width = 32;
107 rdev->mc.vram_width = 64;
110 rdev->mc.vram_width = 128;
113 rdev->mc.vram_width = 256;
116 rdev->mc.vram_width = 128;
119 if (tmp & R520_MC_CHANNEL_SIZE)
120 rdev->mc.vram_width *= 2;
123 void r520_mc_init(struct radeon_device *rdev)
127 r520_vram_get_type(rdev);
128 r100_vram_init_sizes(rdev);
129 radeon_vram_location(rdev, &rdev->mc, 0);
130 if (!(rdev->flags & RADEON_IS_AGP))
131 radeon_gtt_location(rdev, &rdev->mc);
132 /* FIXME: we should enforce default clock in case GPU is not in
135 a.full = rfixed_const(100);
136 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
137 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
140 void r520_mc_program(struct radeon_device *rdev)
142 struct rv515_mc_save save;
144 /* Stops all mc clients */
145 rv515_mc_stop(rdev, &save);
147 /* Wait for mc idle */
148 if (r520_mc_wait_for_idle(rdev))
149 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
150 /* Write VRAM size in case we are limiting it */
151 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
152 /* Program MC, should be a 32bits limited address space */
153 WREG32_MC(R_000004_MC_FB_LOCATION,
154 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
155 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
156 WREG32(R_000134_HDP_FB_LOCATION,
157 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
158 if (rdev->flags & RADEON_IS_AGP) {
159 WREG32_MC(R_000005_MC_AGP_LOCATION,
160 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
161 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
162 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
163 WREG32_MC(R_000007_AGP_BASE_2,
164 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
166 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
167 WREG32_MC(R_000006_AGP_BASE, 0);
168 WREG32_MC(R_000007_AGP_BASE_2, 0);
171 rv515_mc_resume(rdev, &save);
174 static int r520_startup(struct radeon_device *rdev)
178 r520_mc_program(rdev);
180 rv515_clock_startup(rdev);
181 /* Initialize GPU configuration (# pipes, ...) */
183 /* Initialize GART (initialize after TTM so we can allocate
184 * memory through TTM but finalize after TTM) */
185 if (rdev->flags & RADEON_IS_PCIE) {
186 r = rv370_pcie_gart_enable(rdev);
192 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
194 r = r100_cp_init(rdev, 1024 * 1024);
196 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
199 r = r100_wb_init(rdev);
201 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
202 r = r100_ib_init(rdev);
204 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
210 int r520_resume(struct radeon_device *rdev)
212 /* Make sur GART are not working */
213 if (rdev->flags & RADEON_IS_PCIE)
214 rv370_pcie_gart_disable(rdev);
215 /* Resume clock before doing reset */
216 rv515_clock_startup(rdev);
217 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
218 if (radeon_gpu_reset(rdev)) {
219 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
220 RREG32(R_000E40_RBBM_STATUS),
221 RREG32(R_0007C0_CP_STAT));
224 atom_asic_init(rdev->mode_info.atom_context);
225 /* Resume clock after posting */
226 rv515_clock_startup(rdev);
227 /* Initialize surface registers */
228 radeon_surface_init(rdev);
229 return r520_startup(rdev);
232 int r520_init(struct radeon_device *rdev)
236 /* Initialize scratch registers */
237 radeon_scratch_init(rdev);
238 /* Initialize surface registers */
239 radeon_surface_init(rdev);
240 /* TODO: disable VGA need to use VGA request */
242 if (!radeon_get_bios(rdev)) {
243 if (ASIC_IS_AVIVO(rdev))
246 if (rdev->is_atom_bios) {
247 r = radeon_atombios_init(rdev);
251 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
254 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
255 if (radeon_gpu_reset(rdev)) {
257 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
258 RREG32(R_000E40_RBBM_STATUS),
259 RREG32(R_0007C0_CP_STAT));
261 /* check if cards are posted or not */
262 if (radeon_boot_test_post_card(rdev) == false)
265 if (!radeon_card_posted(rdev) && rdev->bios) {
266 DRM_INFO("GPU not posted. posting now...\n");
267 atom_asic_init(rdev->mode_info.atom_context);
269 /* Initialize clocks */
270 radeon_get_clock_info(rdev->ddev);
271 /* Initialize power management */
272 radeon_pm_init(rdev);
274 if (rdev->flags & RADEON_IS_AGP) {
275 r = radeon_agp_init(rdev);
277 radeon_agp_disable(rdev);
280 /* initialize memory controller */
284 r = radeon_fence_driver_init(rdev);
287 r = radeon_irq_kms_init(rdev);
291 r = radeon_bo_init(rdev);
294 r = rv370_pcie_gart_init(rdev);
297 rv515_set_safe_registers(rdev);
298 rdev->accel_working = true;
299 r = r520_startup(rdev);
301 /* Somethings want wront with the accel init stop accel */
302 dev_err(rdev->dev, "Disabling GPU acceleration\n");
306 radeon_irq_kms_fini(rdev);
307 rv370_pcie_gart_fini(rdev);
308 radeon_agp_fini(rdev);
309 rdev->accel_working = false;