drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  87 MODULE_FIRMWARE("radeon/PALM_me.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  89
  90 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  91
  92 /* r600,rv610,rv630,rv620,rv635,rv670 */
  93 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  94 void r600_gpu_init(struct radeon_device *rdev);
  95 void r600_fini(struct radeon_device *rdev);
  96 void r600_irq_disable(struct radeon_device *rdev);
  97
  98 /* get temperature in millidegrees */
  99 u32 rv6xx_get_temp(struct radeon_device *rdev)
 100 {
 101         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 102                 ASIC_T_SHIFT;
 103
 104         return temp * 1000;
 105 }
 106
 107 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 108 {
 109         int i;
 110
 111         rdev->pm.dynpm_can_upclock = true;
 112         rdev->pm.dynpm_can_downclock = true;
 113
 114         /* power state array is low to high, default is first */
 115         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 116                 int min_power_state_index = 0;
 117
 118                 if (rdev->pm.num_power_states > 2)
 119                         min_power_state_index = 1;
 120
 121                 switch (rdev->pm.dynpm_planned_action) {
 122                 case DYNPM_ACTION_MINIMUM:
 123                         rdev->pm.requested_power_state_index = min_power_state_index;
 124                         rdev->pm.requested_clock_mode_index = 0;
 125                         rdev->pm.dynpm_can_downclock = false;
 126                         break;
 127                 case DYNPM_ACTION_DOWNCLOCK:
 128                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 129                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 130                                 rdev->pm.dynpm_can_downclock = false;
 131                         } else {
 132                                 if (rdev->pm.active_crtc_count > 1) {
 133                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 134                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 135                                                         continue;
 136                                                 else if (i >= rdev->pm.current_power_state_index) {
 137                                                         rdev->pm.requested_power_state_index =
 138                                                                 rdev->pm.current_power_state_index;
 139                                                         break;
 140                                                 } else {
 141                                                         rdev->pm.requested_power_state_index = i;
 142                                                         break;
 143                                                 }
 144                                         }
 145                                 } else {
 146                                         if (rdev->pm.current_power_state_index == 0)
 147                                                 rdev->pm.requested_power_state_index =
 148                                                         rdev->pm.num_power_states - 1;
 149                                         else
 150                                                 rdev->pm.requested_power_state_index =
 151                                                         rdev->pm.current_power_state_index - 1;
 152                                 }
 153                         }
 154                         rdev->pm.requested_clock_mode_index = 0;
 155                         /* don't use the power state if crtcs are active and no display flag is set */
 156                         if ((rdev->pm.active_crtc_count > 0) &&
 157                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 159                              RADEON_PM_MODE_NO_DISPLAY)) {
 160                                 rdev->pm.requested_power_state_index++;
 161                         }
 162                         break;
 163                 case DYNPM_ACTION_UPCLOCK:
 164                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 165                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 166                                 rdev->pm.dynpm_can_upclock = false;
 167                         } else {
 168                                 if (rdev->pm.active_crtc_count > 1) {
 169                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 170                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 171                                                         continue;
 172                                                 else if (i <= rdev->pm.current_power_state_index) {
 173                                                         rdev->pm.requested_power_state_index =
 174                                                                 rdev->pm.current_power_state_index;
 175                                                         break;
 176                                                 } else {
 177                                                         rdev->pm.requested_power_state_index = i;
 178                                                         break;
 179                                                 }
 180                                         }
 181                                 } else
 182                                         rdev->pm.requested_power_state_index =
 183                                                 rdev->pm.current_power_state_index + 1;
 184                         }
 185                         rdev->pm.requested_clock_mode_index = 0;
 186                         break;
 187                 case DYNPM_ACTION_DEFAULT:
 188                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 189                         rdev->pm.requested_clock_mode_index = 0;
 190                         rdev->pm.dynpm_can_upclock = false;
 191                         break;
 192                 case DYNPM_ACTION_NONE:
 193                 default:
 194                         DRM_ERROR("Requested mode for not defined action\n");
 195                         return;
 196                 }
 197         } else {
 198                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 199                 /* for now just select the first power state and switch between clock modes */
 200                 /* power state array is low to high, default is first (0) */
 201                 if (rdev->pm.active_crtc_count > 1) {
 202                         rdev->pm.requested_power_state_index = -1;
 203                         /* start at 1 as we don't want the default mode */
 204                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 205                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 206                                         continue;
 207                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 208                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 209                                         rdev->pm.requested_power_state_index = i;
 210                                         break;
 211                                 }
 212                         }
 213                         /* if nothing selected, grab the default state. */
 214                         if (rdev->pm.requested_power_state_index == -1)
 215                                 rdev->pm.requested_power_state_index = 0;
 216                 } else
 217                         rdev->pm.requested_power_state_index = 1;
 218
 219                 switch (rdev->pm.dynpm_planned_action) {
 220                 case DYNPM_ACTION_MINIMUM:
 221                         rdev->pm.requested_clock_mode_index = 0;
 222                         rdev->pm.dynpm_can_downclock = false;
 223                         break;
 224                 case DYNPM_ACTION_DOWNCLOCK:
 225                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 226                                 if (rdev->pm.current_clock_mode_index == 0) {
 227                                         rdev->pm.requested_clock_mode_index = 0;
 228                                         rdev->pm.dynpm_can_downclock = false;
 229                                 } else
 230                                         rdev->pm.requested_clock_mode_index =
 231                                                 rdev->pm.current_clock_mode_index - 1;
 232                         } else {
 233                                 rdev->pm.requested_clock_mode_index = 0;
 234                                 rdev->pm.dynpm_can_downclock = false;
 235                         }
 236                         /* don't use the power state if crtcs are active and no display flag is set */
 237                         if ((rdev->pm.active_crtc_count > 0) &&
 238                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 239                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 240                              RADEON_PM_MODE_NO_DISPLAY)) {
 241                                 rdev->pm.requested_clock_mode_index++;
 242                         }
 243                         break;
 244                 case DYNPM_ACTION_UPCLOCK:
 245                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 246                                 if (rdev->pm.current_clock_mode_index ==
 247                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 248                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 249                                         rdev->pm.dynpm_can_upclock = false;
 250                                 } else
 251                                         rdev->pm.requested_clock_mode_index =
 252                                                 rdev->pm.current_clock_mode_index + 1;
 253                         } else {
 254                                 rdev->pm.requested_clock_mode_index =
 255                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 256                                 rdev->pm.dynpm_can_upclock = false;
 257                         }
 258                         break;
 259                 case DYNPM_ACTION_DEFAULT:
 260                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 261                         rdev->pm.requested_clock_mode_index = 0;
 262                         rdev->pm.dynpm_can_upclock = false;
 263                         break;
 264                 case DYNPM_ACTION_NONE:
 265                 default:
 266                         DRM_ERROR("Requested mode for not defined action\n");
 267                         return;
 268                 }
 269         }
 270
 271         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 272                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 273                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 274                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 275                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 276                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 277                   pcie_lanes);
 278 }
 279
 280 static int r600_pm_get_type_index(struct radeon_device *rdev,
 281                                   enum radeon_pm_state_type ps_type,
 282                                   int instance)
 283 {
 284         int i;
 285         int found_instance = -1;
 286
 287         for (i = 0; i < rdev->pm.num_power_states; i++) {
 288                 if (rdev->pm.power_state[i].type == ps_type) {
 289                         found_instance++;
 290                         if (found_instance == instance)
 291                                 return i;
 292                 }
 293         }
 294         /* return default if no match */
 295         return rdev->pm.default_power_state_index;
 296 }
 297
 298 void rs780_pm_init_profile(struct radeon_device *rdev)
 299 {
 300         if (rdev->pm.num_power_states == 2) {
 301                 /* default */
 302                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 303                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 304                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 305                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 306                 /* low sh */
 307                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 310                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 311                 /* mid sh */
 312                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 316                 /* high sh */
 317                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 319                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 321                 /* low mh */
 322                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 326                 /* mid mh */
 327                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 331                 /* high mh */
 332                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 334                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 336         } else if (rdev->pm.num_power_states == 3) {
 337                 /* default */
 338                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 339                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 340                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 341                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 342                 /* low sh */
 343                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 345                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 346                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 347                 /* mid sh */
 348                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 349                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 352                 /* high sh */
 353                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 355                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 357                 /* low mh */
 358                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 361                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 362                 /* mid mh */
 363                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 364                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 366                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 367                 /* high mh */
 368                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 369                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 370                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 372         } else {
 373                 /* default */
 374                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 375                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 376                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 378                 /* low sh */
 379                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 381                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 382                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 383                 /* mid sh */
 384                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 385                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 388                 /* high sh */
 389                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 390                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 391                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 393                 /* low mh */
 394                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 395                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 398                 /* mid mh */
 399                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 400                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 403                 /* high mh */
 404                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 405                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 406                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 408         }
 409 }
 410
 411 void r600_pm_init_profile(struct radeon_device *rdev)
 412 {
 413         if (rdev->family == CHIP_R600) {
 414                 /* XXX */
 415                 /* default */
 416                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 417                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 419                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 420                 /* low sh */
 421                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 422                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 424                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 425                 /* mid sh */
 426                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 427                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 429                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 430                 /* high sh */
 431                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 432                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 435                 /* low mh */
 436                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 437                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 439                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 440                 /* mid mh */
 441                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 442                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 444                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 445                 /* high mh */
 446                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 447                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 450         } else {
 451                 if (rdev->pm.num_power_states < 4) {
 452                         /* default */
 453                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 454                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 455                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 456                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 457                         /* low sh */
 458                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 459                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 461                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 462                         /* mid sh */
 463                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 464                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 466                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 467                         /* high sh */
 468                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 469                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 472                         /* low mh */
 473                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 474                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 476                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 477                         /* low mh */
 478                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 479                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 481                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 482                         /* high mh */
 483                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 484                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 487                 } else {
 488                         /* default */
 489                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 490                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 491                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 492                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 493                         /* low sh */
 494                         if (rdev->flags & RADEON_IS_MOBILITY) {
 495                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 496                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 497                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 498                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 499                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 501                         } else {
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 503                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 504                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 505                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 506                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 508                         }
 509                         /* mid sh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY) {
 511                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 512                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 513                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 514                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 515                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 517                         } else {
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 519                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 520                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 521                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 522                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 524                         }
 525                         /* high sh */
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 527                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 529                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 530                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 532                         /* low mh */
 533                         if (rdev->flags & RADEON_IS_MOBILITY) {
 534                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 535                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 536                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 537                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 538                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 540                         } else {
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 542                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 543                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 544                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 545                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 547                         }
 548                         /* mid mh */
 549                         if (rdev->flags & RADEON_IS_MOBILITY) {
 550                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 551                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 552                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 553                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 554                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 556                         } else {
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 558                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 559                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 560                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 561                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 563                         }
 564                         /* high mh */
 565                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 566                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 567                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 568                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 569                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 571                 }
 572         }
 573 }
 574
 575 void r600_pm_misc(struct radeon_device *rdev)
 576 {
 577         int req_ps_idx = rdev->pm.requested_power_state_index;
 578         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 579         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 580         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 581
 582         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 583                 if (voltage->voltage != rdev->pm.current_vddc) {
 584                         radeon_atom_set_voltage(rdev, voltage->voltage);
 585                         rdev->pm.current_vddc = voltage->voltage;
 586                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 587                 }
 588         }
 589 }
 590
 591 bool r600_gui_idle(struct radeon_device *rdev)
 592 {
 593         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 594                 return false;
 595         else
 596                 return true;
 597 }
 598
 599 /* hpd for digital panel detect/disconnect */
 600 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 601 {
 602         bool connected = false;
 603
 604         if (ASIC_IS_DCE3(rdev)) {
 605                 switch (hpd) {
 606                 case RADEON_HPD_1:
 607                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 608                                 connected = true;
 609                         break;
 610                 case RADEON_HPD_2:
 611                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 612                                 connected = true;
 613                         break;
 614                 case RADEON_HPD_3:
 615                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 616                                 connected = true;
 617                         break;
 618                 case RADEON_HPD_4:
 619                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 620                                 connected = true;
 621                         break;
 622                         /* DCE 3.2 */
 623                 case RADEON_HPD_5:
 624                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 625                                 connected = true;
 626                         break;
 627                 case RADEON_HPD_6:
 628                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 629                                 connected = true;
 630                         break;
 631                 default:
 632                         break;
 633                 }
 634         } else {
 635                 switch (hpd) {
 636                 case RADEON_HPD_1:
 637                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 638                                 connected = true;
 639                         break;
 640                 case RADEON_HPD_2:
 641                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 642                                 connected = true;
 643                         break;
 644                 case RADEON_HPD_3:
 645                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 646                                 connected = true;
 647                         break;
 648                 default:
 649                         break;
 650                 }
 651         }
 652         return connected;
 653 }
 654
 655 void r600_hpd_set_polarity(struct radeon_device *rdev,
 656                            enum radeon_hpd_id hpd)
 657 {
 658         u32 tmp;
 659         bool connected = r600_hpd_sense(rdev, hpd);
 660
 661         if (ASIC_IS_DCE3(rdev)) {
 662                 switch (hpd) {
 663                 case RADEON_HPD_1:
 664                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 665                         if (connected)
 666                                 tmp &= ~DC_HPDx_INT_POLARITY;
 667                         else
 668                                 tmp |= DC_HPDx_INT_POLARITY;
 669                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 670                         break;
 671                 case RADEON_HPD_2:
 672                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 673                         if (connected)
 674                                 tmp &= ~DC_HPDx_INT_POLARITY;
 675                         else
 676                                 tmp |= DC_HPDx_INT_POLARITY;
 677                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 678                         break;
 679                 case RADEON_HPD_3:
 680                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 681                         if (connected)
 682                                 tmp &= ~DC_HPDx_INT_POLARITY;
 683                         else
 684                                 tmp |= DC_HPDx_INT_POLARITY;
 685                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 686                         break;
 687                 case RADEON_HPD_4:
 688                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 689                         if (connected)
 690                                 tmp &= ~DC_HPDx_INT_POLARITY;
 691                         else
 692                                 tmp |= DC_HPDx_INT_POLARITY;
 693                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 694                         break;
 695                 case RADEON_HPD_5:
 696                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 697                         if (connected)
 698                                 tmp &= ~DC_HPDx_INT_POLARITY;
 699                         else
 700                                 tmp |= DC_HPDx_INT_POLARITY;
 701                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 702                         break;
 703                         /* DCE 3.2 */
 704                 case RADEON_HPD_6:
 705                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 706                         if (connected)
 707                                 tmp &= ~DC_HPDx_INT_POLARITY;
 708                         else
 709                                 tmp |= DC_HPDx_INT_POLARITY;
 710                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 711                         break;
 712                 default:
 713                         break;
 714                 }
 715         } else {
 716                 switch (hpd) {
 717                 case RADEON_HPD_1:
 718                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 719                         if (connected)
 720                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 721                         else
 722                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 723                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 724                         break;
 725                 case RADEON_HPD_2:
 726                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 727                         if (connected)
 728                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 729                         else
 730                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 731                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 732                         break;
 733                 case RADEON_HPD_3:
 734                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 735                         if (connected)
 736                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 737                         else
 738                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 739                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 740                         break;
 741                 default:
 742                         break;
 743                 }
 744         }
 745 }
 746
 747 void r600_hpd_init(struct radeon_device *rdev)
 748 {
 749         struct drm_device *dev = rdev->ddev;
 750         struct drm_connector *connector;
 751
 752         if (ASIC_IS_DCE3(rdev)) {
 753                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 754                 if (ASIC_IS_DCE32(rdev))
 755                         tmp |= DC_HPDx_EN;
 756
 757                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 758                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 759                         switch (radeon_connector->hpd.hpd) {
 760                         case RADEON_HPD_1:
 761                                 WREG32(DC_HPD1_CONTROL, tmp);
 762                                 rdev->irq.hpd[0] = true;
 763                                 break;
 764                         case RADEON_HPD_2:
 765                                 WREG32(DC_HPD2_CONTROL, tmp);
 766                                 rdev->irq.hpd[1] = true;
 767                                 break;
 768                         case RADEON_HPD_3:
 769                                 WREG32(DC_HPD3_CONTROL, tmp);
 770                                 rdev->irq.hpd[2] = true;
 771                                 break;
 772                         case RADEON_HPD_4:
 773                                 WREG32(DC_HPD4_CONTROL, tmp);
 774                                 rdev->irq.hpd[3] = true;
 775                                 break;
 776                                 /* DCE 3.2 */
 777                         case RADEON_HPD_5:
 778                                 WREG32(DC_HPD5_CONTROL, tmp);
 779                                 rdev->irq.hpd[4] = true;
 780                                 break;
 781                         case RADEON_HPD_6:
 782                                 WREG32(DC_HPD6_CONTROL, tmp);
 783                                 rdev->irq.hpd[5] = true;
 784                                 break;
 785                         default:
 786                                 break;
 787                         }
 788                 }
 789         } else {
 790                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 791                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 792                         switch (radeon_connector->hpd.hpd) {
 793                         case RADEON_HPD_1:
 794                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 795                                 rdev->irq.hpd[0] = true;
 796                                 break;
 797                         case RADEON_HPD_2:
 798                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 799                                 rdev->irq.hpd[1] = true;
 800                                 break;
 801                         case RADEON_HPD_3:
 802                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 803                                 rdev->irq.hpd[2] = true;
 804                                 break;
 805                         default:
 806                                 break;
 807                         }
 808                 }
 809         }
 810         if (rdev->irq.installed)
 811                 r600_irq_set(rdev);
 812 }
 813
 814 void r600_hpd_fini(struct radeon_device *rdev)
 815 {
 816         struct drm_device *dev = rdev->ddev;
 817         struct drm_connector *connector;
 818
 819         if (ASIC_IS_DCE3(rdev)) {
 820                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 821                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 822                         switch (radeon_connector->hpd.hpd) {
 823                         case RADEON_HPD_1:
 824                                 WREG32(DC_HPD1_CONTROL, 0);
 825                                 rdev->irq.hpd[0] = false;
 826                                 break;
 827                         case RADEON_HPD_2:
 828                                 WREG32(DC_HPD2_CONTROL, 0);
 829                                 rdev->irq.hpd[1] = false;
 830                                 break;
 831                         case RADEON_HPD_3:
 832                                 WREG32(DC_HPD3_CONTROL, 0);
 833                                 rdev->irq.hpd[2] = false;
 834                                 break;
 835                         case RADEON_HPD_4:
 836                                 WREG32(DC_HPD4_CONTROL, 0);
 837                                 rdev->irq.hpd[3] = false;
 838                                 break;
 839                                 /* DCE 3.2 */
 840                         case RADEON_HPD_5:
 841                                 WREG32(DC_HPD5_CONTROL, 0);
 842                                 rdev->irq.hpd[4] = false;
 843                                 break;
 844                         case RADEON_HPD_6:
 845                                 WREG32(DC_HPD6_CONTROL, 0);
 846                                 rdev->irq.hpd[5] = false;
 847                                 break;
 848                         default:
 849                                 break;
 850                         }
 851                 }
 852         } else {
 853                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 854                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 855                         switch (radeon_connector->hpd.hpd) {
 856                         case RADEON_HPD_1:
 857                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 858                                 rdev->irq.hpd[0] = false;
 859                                 break;
 860                         case RADEON_HPD_2:
 861                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 862                                 rdev->irq.hpd[1] = false;
 863                                 break;
 864                         case RADEON_HPD_3:
 865                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 866                                 rdev->irq.hpd[2] = false;
 867                                 break;
 868                         default:
 869                                 break;
 870                         }
 871                 }
 872         }
 873 }
 874
 875 /*
 876  * R600 PCIE GART
 877  */
 878 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 879 {
 880         unsigned i;
 881         u32 tmp;
 882
 883         /* flush hdp cache so updates hit vram */
 884         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
 885                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 886                 u32 tmp;
 887
 888                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 889                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 890                  */
 891                 WREG32(HDP_DEBUG1, 0);
 892                 tmp = readl((void __iomem *)ptr);
 893         } else
 894                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 895
 896         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 897         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 898         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 899         for (i = 0; i < rdev->usec_timeout; i++) {
 900                 /* read MC_STATUS */
 901                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 902                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 903                 if (tmp == 2) {
 904                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 905                         return;
 906                 }
 907                 if (tmp) {
 908                         return;
 909                 }
 910                 udelay(1);
 911         }
 912 }
 913
 914 int r600_pcie_gart_init(struct radeon_device *rdev)
 915 {
 916         int r;
 917
 918         if (rdev->gart.table.vram.robj) {
 919                 WARN(1, "R600 PCIE GART already initialized\n");
 920                 return 0;
 921         }
 922         /* Initialize common gart structure */
 923         r = radeon_gart_init(rdev);
 924         if (r)
 925                 return r;
 926         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 927         return radeon_gart_table_vram_alloc(rdev);
 928 }
 929
 930 int r600_pcie_gart_enable(struct radeon_device *rdev)
 931 {
 932         u32 tmp;
 933         int r, i;
 934
 935         if (rdev->gart.table.vram.robj == NULL) {
 936                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 937                 return -EINVAL;
 938         }
 939         r = radeon_gart_table_vram_pin(rdev);
 940         if (r)
 941                 return r;
 942         radeon_gart_restore(rdev);
 943
 944         /* Setup L2 cache */
 945         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 946                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 947                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 948         WREG32(VM_L2_CNTL2, 0);
 949         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 950         /* Setup TLB control */
 951         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 952                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 953                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 954                 ENABLE_WAIT_L2_QUERY;
 955         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 956         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 957         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 958         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 968         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 969         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 970         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 971         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 972         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 973                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 974         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 975                         (u32)(rdev->dummy_page.addr >> 12));
 976         for (i = 1; i < 7; i++)
 977                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 978
 979         r600_pcie_gart_tlb_flush(rdev);
 980         rdev->gart.ready = true;
 981         return 0;
 982 }
 983
 984 void r600_pcie_gart_disable(struct radeon_device *rdev)
 985 {
 986         u32 tmp;
 987         int i, r;
 988
 989         /* Disable all tables */
 990         for (i = 0; i < 7; i++)
 991                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 992
 993         /* Disable L2 cache */
 994         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 995                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 996         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 997         /* Setup L1 TLB control */
 998         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 999                 ENABLE_WAIT_L2_QUERY;
1000         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1001         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1014         if (rdev->gart.table.vram.robj) {
1015                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1016                 if (likely(r == 0)) {
1017                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1018                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1019                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1020                 }
1021         }
1022 }
1023
1024 void r600_pcie_gart_fini(struct radeon_device *rdev)
1025 {
1026         radeon_gart_fini(rdev);
1027         r600_pcie_gart_disable(rdev);
1028         radeon_gart_table_vram_free(rdev);
1029 }
1030
1031 void r600_agp_enable(struct radeon_device *rdev)
1032 {
1033         u32 tmp;
1034         int i;
1035
1036         /* Setup L2 cache */
1037         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1038                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1039                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1040         WREG32(VM_L2_CNTL2, 0);
1041         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1042         /* Setup TLB control */
1043         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1044                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1045                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1046                 ENABLE_WAIT_L2_QUERY;
1047         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1048         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1049         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1050         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1053         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1060         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1061         for (i = 0; i < 7; i++)
1062                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1063 }
1064
1065 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1066 {
1067         unsigned i;
1068         u32 tmp;
1069
1070         for (i = 0; i < rdev->usec_timeout; i++) {
1071                 /* read MC_STATUS */
1072                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1073                 if (!tmp)
1074                         return 0;
1075                 udelay(1);
1076         }
1077         return -1;
1078 }
1079
1080 static void r600_mc_program(struct radeon_device *rdev)
1081 {
1082         struct rv515_mc_save save;
1083         u32 tmp;
1084         int i, j;
1085
1086         /* Initialize HDP */
1087         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1088                 WREG32((0x2c14 + j), 0x00000000);
1089                 WREG32((0x2c18 + j), 0x00000000);
1090                 WREG32((0x2c1c + j), 0x00000000);
1091                 WREG32((0x2c20 + j), 0x00000000);
1092                 WREG32((0x2c24 + j), 0x00000000);
1093         }
1094         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1095
1096         rv515_mc_stop(rdev, &save);
1097         if (r600_mc_wait_for_idle(rdev)) {
1098                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1099         }
1100         /* Lockout access through VGA aperture (doesn't exist before R600) */
1101         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1102         /* Update configuration */
1103         if (rdev->flags & RADEON_IS_AGP) {
1104                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1105                         /* VRAM before AGP */
1106                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1107                                 rdev->mc.vram_start >> 12);
1108                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1109                                 rdev->mc.gtt_end >> 12);
1110                 } else {
1111                         /* VRAM after AGP */
1112                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1113                                 rdev->mc.gtt_start >> 12);
1114                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1115                                 rdev->mc.vram_end >> 12);
1116                 }
1117         } else {
1118                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1119                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1120         }
1121         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1122         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1123         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1124         WREG32(MC_VM_FB_LOCATION, tmp);
1125         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1126         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1127         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1128         if (rdev->flags & RADEON_IS_AGP) {
1129                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1130                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1131                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1132         } else {
1133                 WREG32(MC_VM_AGP_BASE, 0);
1134                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1135                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1136         }
1137         if (r600_mc_wait_for_idle(rdev)) {
1138                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1139         }
1140         rv515_mc_resume(rdev, &save);
1141         /* we need to own VRAM, so turn off the VGA renderer here
1142          * to stop it overwriting our objects */
1143         rv515_vga_render_disable(rdev);
1144 }
1145
1146 /**
1147  * r600_vram_gtt_location - try to find VRAM & GTT location
1148  * @rdev: radeon device structure holding all necessary informations
1149  * @mc: memory controller structure holding memory informations
1150  *
1151  * Function will place try to place VRAM at same place as in CPU (PCI)
1152  * address space as some GPU seems to have issue when we reprogram at
1153  * different address space.
1154  *
1155  * If there is not enough space to fit the unvisible VRAM after the
1156  * aperture then we limit the VRAM size to the aperture.
1157  *
1158  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1159  * them to be in one from GPU point of view so that we can program GPU to
1160  * catch access outside them (weird GPU policy see ??).
1161  *
1162  * This function will never fails, worst case are limiting VRAM or GTT.
1163  *
1164  * Note: GTT start, end, size should be initialized before calling this
1165  * function on AGP platform.
1166  */
1167 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1168 {
1169         u64 size_bf, size_af;
1170
1171         if (mc->mc_vram_size > 0xE0000000) {
1172                 /* leave room for at least 512M GTT */
1173                 dev_warn(rdev->dev, "limiting VRAM\n");
1174                 mc->real_vram_size = 0xE0000000;
1175                 mc->mc_vram_size = 0xE0000000;
1176         }
1177         if (rdev->flags & RADEON_IS_AGP) {
1178                 size_bf = mc->gtt_start;
1179                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1180                 if (size_bf > size_af) {
1181                         if (mc->mc_vram_size > size_bf) {
1182                                 dev_warn(rdev->dev, "limiting VRAM\n");
1183                                 mc->real_vram_size = size_bf;
1184                                 mc->mc_vram_size = size_bf;
1185                         }
1186                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1187                 } else {
1188                         if (mc->mc_vram_size > size_af) {
1189                                 dev_warn(rdev->dev, "limiting VRAM\n");
1190                                 mc->real_vram_size = size_af;
1191                                 mc->mc_vram_size = size_af;
1192                         }
1193                         mc->vram_start = mc->gtt_end;
1194                 }
1195                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1196                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1197                                 mc->mc_vram_size >> 20, mc->vram_start,
1198                                 mc->vram_end, mc->real_vram_size >> 20);
1199         } else {
1200                 u64 base = 0;
1201                 if (rdev->flags & RADEON_IS_IGP)
1202                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1203                 radeon_vram_location(rdev, &rdev->mc, base);
1204                 rdev->mc.gtt_base_align = 0;
1205                 radeon_gtt_location(rdev, mc);
1206         }
1207 }
1208
1209 int r600_mc_init(struct radeon_device *rdev)
1210 {
1211         u32 tmp;
1212         int chansize, numchan;
1213
1214         /* Get VRAM informations */
1215         rdev->mc.vram_is_ddr = true;
1216         tmp = RREG32(RAMCFG);
1217         if (tmp & CHANSIZE_OVERRIDE) {
1218                 chansize = 16;
1219         } else if (tmp & CHANSIZE_MASK) {
1220                 chansize = 64;
1221         } else {
1222                 chansize = 32;
1223         }
1224         tmp = RREG32(CHMAP);
1225         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1226         case 0:
1227         default:
1228                 numchan = 1;
1229                 break;
1230         case 1:
1231                 numchan = 2;
1232                 break;
1233         case 2:
1234                 numchan = 4;
1235                 break;
1236         case 3:
1237                 numchan = 8;
1238                 break;
1239         }
1240         rdev->mc.vram_width = numchan * chansize;
1241         /* Could aper size report 0 ? */
1242         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1243         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1244         /* Setup GPU memory space */
1245         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1246         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1247         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1248         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1249         r600_vram_gtt_location(rdev, &rdev->mc);
1250
1251         if (rdev->flags & RADEON_IS_IGP) {
1252                 rs690_pm_info(rdev);
1253                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1254         }
1255         radeon_update_bandwidth_info(rdev);
1256         return 0;
1257 }
1258
1259 /* We doesn't check that the GPU really needs a reset we simply do the
1260  * reset, it's up to the caller to determine if the GPU needs one. We
1261  * might add an helper function to check that.
1262  */
1263 int r600_gpu_soft_reset(struct radeon_device *rdev)
1264 {
1265         struct rv515_mc_save save;
1266         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1267                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1268                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1269                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1270                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1271                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1272                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1273                                 S_008010_GUI_ACTIVE(1);
1274         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1275                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1276                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1277                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1278                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1279                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1280                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1281                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1282         u32 tmp;
1283
1284         dev_info(rdev->dev, "GPU softreset \n");
1285         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1286                 RREG32(R_008010_GRBM_STATUS));
1287         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1288                 RREG32(R_008014_GRBM_STATUS2));
1289         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1290                 RREG32(R_000E50_SRBM_STATUS));
1291         rv515_mc_stop(rdev, &save);
1292         if (r600_mc_wait_for_idle(rdev)) {
1293                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1294         }
1295         /* Disable CP parsing/prefetching */
1296         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1297         /* Check if any of the rendering block is busy and reset it */
1298         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1299             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1300                 tmp = S_008020_SOFT_RESET_CR(1) |
1301                         S_008020_SOFT_RESET_DB(1) |
1302                         S_008020_SOFT_RESET_CB(1) |
1303                         S_008020_SOFT_RESET_PA(1) |
1304                         S_008020_SOFT_RESET_SC(1) |
1305                         S_008020_SOFT_RESET_SMX(1) |
1306                         S_008020_SOFT_RESET_SPI(1) |
1307                         S_008020_SOFT_RESET_SX(1) |
1308                         S_008020_SOFT_RESET_SH(1) |
1309                         S_008020_SOFT_RESET_TC(1) |
1310                         S_008020_SOFT_RESET_TA(1) |
1311                         S_008020_SOFT_RESET_VC(1) |
1312                         S_008020_SOFT_RESET_VGT(1);
1313                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1314                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1315                 RREG32(R_008020_GRBM_SOFT_RESET);
1316                 mdelay(15);
1317                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1318         }
1319         /* Reset CP (we always reset CP) */
1320         tmp = S_008020_SOFT_RESET_CP(1);
1321         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1322         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1323         RREG32(R_008020_GRBM_SOFT_RESET);
1324         mdelay(15);
1325         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1326         /* Wait a little for things to settle down */
1327         mdelay(1);
1328         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1329                 RREG32(R_008010_GRBM_STATUS));
1330         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1331                 RREG32(R_008014_GRBM_STATUS2));
1332         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1333                 RREG32(R_000E50_SRBM_STATUS));
1334         rv515_mc_resume(rdev, &save);
1335         return 0;
1336 }
1337
1338 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1339 {
1340         u32 srbm_status;
1341         u32 grbm_status;
1342         u32 grbm_status2;
1343         int r;
1344
1345         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1346         grbm_status = RREG32(R_008010_GRBM_STATUS);
1347         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1348         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1349                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1350                 return false;
1351         }
1352         /* force CP activities */
1353         r = radeon_ring_lock(rdev, 2);
1354         if (!r) {
1355                 /* PACKET2 NOP */
1356                 radeon_ring_write(rdev, 0x80000000);
1357                 radeon_ring_write(rdev, 0x80000000);
1358                 radeon_ring_unlock_commit(rdev);
1359         }
1360         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1361         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1362 }
1363
1364 int r600_asic_reset(struct radeon_device *rdev)
1365 {
1366         return r600_gpu_soft_reset(rdev);
1367 }
1368
1369 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1370                                              u32 num_backends,
1371                                              u32 backend_disable_mask)
1372 {
1373         u32 backend_map = 0;
1374         u32 enabled_backends_mask;
1375         u32 enabled_backends_count;
1376         u32 cur_pipe;
1377         u32 swizzle_pipe[R6XX_MAX_PIPES];
1378         u32 cur_backend;
1379         u32 i;
1380
1381         if (num_tile_pipes > R6XX_MAX_PIPES)
1382                 num_tile_pipes = R6XX_MAX_PIPES;
1383         if (num_tile_pipes < 1)
1384                 num_tile_pipes = 1;
1385         if (num_backends > R6XX_MAX_BACKENDS)
1386                 num_backends = R6XX_MAX_BACKENDS;
1387         if (num_backends < 1)
1388                 num_backends = 1;
1389
1390         enabled_backends_mask = 0;
1391         enabled_backends_count = 0;
1392         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1393                 if (((backend_disable_mask >> i) & 1) == 0) {
1394                         enabled_backends_mask |= (1 << i);
1395                         ++enabled_backends_count;
1396                 }
1397                 if (enabled_backends_count == num_backends)
1398                         break;
1399         }
1400
1401         if (enabled_backends_count == 0) {
1402                 enabled_backends_mask = 1;
1403                 enabled_backends_count = 1;
1404         }
1405
1406         if (enabled_backends_count != num_backends)
1407                 num_backends = enabled_backends_count;
1408
1409         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1410         switch (num_tile_pipes) {
1411         case 1:
1412                 swizzle_pipe[0] = 0;
1413                 break;
1414         case 2:
1415                 swizzle_pipe[0] = 0;
1416                 swizzle_pipe[1] = 1;
1417                 break;
1418         case 3:
1419                 swizzle_pipe[0] = 0;
1420                 swizzle_pipe[1] = 1;
1421                 swizzle_pipe[2] = 2;
1422                 break;
1423         case 4:
1424                 swizzle_pipe[0] = 0;
1425                 swizzle_pipe[1] = 1;
1426                 swizzle_pipe[2] = 2;
1427                 swizzle_pipe[3] = 3;
1428                 break;
1429         case 5:
1430                 swizzle_pipe[0] = 0;
1431                 swizzle_pipe[1] = 1;
1432                 swizzle_pipe[2] = 2;
1433                 swizzle_pipe[3] = 3;
1434                 swizzle_pipe[4] = 4;
1435                 break;
1436         case 6:
1437                 swizzle_pipe[0] = 0;
1438                 swizzle_pipe[1] = 2;
1439                 swizzle_pipe[2] = 4;
1440                 swizzle_pipe[3] = 5;
1441                 swizzle_pipe[4] = 1;
1442                 swizzle_pipe[5] = 3;
1443                 break;
1444         case 7:
1445                 swizzle_pipe[0] = 0;
1446                 swizzle_pipe[1] = 2;
1447                 swizzle_pipe[2] = 4;
1448                 swizzle_pipe[3] = 6;
1449                 swizzle_pipe[4] = 1;
1450                 swizzle_pipe[5] = 3;
1451                 swizzle_pipe[6] = 5;
1452                 break;
1453         case 8:
1454                 swizzle_pipe[0] = 0;
1455                 swizzle_pipe[1] = 2;
1456                 swizzle_pipe[2] = 4;
1457                 swizzle_pipe[3] = 6;
1458                 swizzle_pipe[4] = 1;
1459                 swizzle_pipe[5] = 3;
1460                 swizzle_pipe[6] = 5;
1461                 swizzle_pipe[7] = 7;
1462                 break;
1463         }
1464
1465         cur_backend = 0;
1466         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1467                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1468                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1469
1470                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1471
1472                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1473         }
1474
1475         return backend_map;
1476 }
1477
1478 int r600_count_pipe_bits(uint32_t val)
1479 {
1480         int i, ret = 0;
1481
1482         for (i = 0; i < 32; i++) {
1483                 ret += val & 1;
1484                 val >>= 1;
1485         }
1486         return ret;
1487 }
1488
1489 void r600_gpu_init(struct radeon_device *rdev)
1490 {
1491         u32 tiling_config;
1492         u32 ramcfg;
1493         u32 backend_map;
1494         u32 cc_rb_backend_disable;
1495         u32 cc_gc_shader_pipe_config;
1496         u32 tmp;
1497         int i, j;
1498         u32 sq_config;
1499         u32 sq_gpr_resource_mgmt_1 = 0;
1500         u32 sq_gpr_resource_mgmt_2 = 0;
1501         u32 sq_thread_resource_mgmt = 0;
1502         u32 sq_stack_resource_mgmt_1 = 0;
1503         u32 sq_stack_resource_mgmt_2 = 0;
1504
1505         /* FIXME: implement */
1506         switch (rdev->family) {
1507         case CHIP_R600:
1508                 rdev->config.r600.max_pipes = 4;
1509                 rdev->config.r600.max_tile_pipes = 8;
1510                 rdev->config.r600.max_simds = 4;
1511                 rdev->config.r600.max_backends = 4;
1512                 rdev->config.r600.max_gprs = 256;
1513                 rdev->config.r600.max_threads = 192;
1514                 rdev->config.r600.max_stack_entries = 256;
1515                 rdev->config.r600.max_hw_contexts = 8;
1516                 rdev->config.r600.max_gs_threads = 16;
1517                 rdev->config.r600.sx_max_export_size = 128;
1518                 rdev->config.r600.sx_max_export_pos_size = 16;
1519                 rdev->config.r600.sx_max_export_smx_size = 128;
1520                 rdev->config.r600.sq_num_cf_insts = 2;
1521                 break;
1522         case CHIP_RV630:
1523         case CHIP_RV635:
1524                 rdev->config.r600.max_pipes = 2;
1525                 rdev->config.r600.max_tile_pipes = 2;
1526                 rdev->config.r600.max_simds = 3;
1527                 rdev->config.r600.max_backends = 1;
1528                 rdev->config.r600.max_gprs = 128;
1529                 rdev->config.r600.max_threads = 192;
1530                 rdev->config.r600.max_stack_entries = 128;
1531                 rdev->config.r600.max_hw_contexts = 8;
1532                 rdev->config.r600.max_gs_threads = 4;
1533                 rdev->config.r600.sx_max_export_size = 128;
1534                 rdev->config.r600.sx_max_export_pos_size = 16;
1535                 rdev->config.r600.sx_max_export_smx_size = 128;
1536                 rdev->config.r600.sq_num_cf_insts = 2;
1537                 break;
1538         case CHIP_RV610:
1539         case CHIP_RV620:
1540         case CHIP_RS780:
1541         case CHIP_RS880:
1542                 rdev->config.r600.max_pipes = 1;
1543                 rdev->config.r600.max_tile_pipes = 1;
1544                 rdev->config.r600.max_simds = 2;
1545                 rdev->config.r600.max_backends = 1;
1546                 rdev->config.r600.max_gprs = 128;
1547                 rdev->config.r600.max_threads = 192;
1548                 rdev->config.r600.max_stack_entries = 128;
1549                 rdev->config.r600.max_hw_contexts = 4;
1550                 rdev->config.r600.max_gs_threads = 4;
1551                 rdev->config.r600.sx_max_export_size = 128;
1552                 rdev->config.r600.sx_max_export_pos_size = 16;
1553                 rdev->config.r600.sx_max_export_smx_size = 128;
1554                 rdev->config.r600.sq_num_cf_insts = 1;
1555                 break;
1556         case CHIP_RV670:
1557                 rdev->config.r600.max_pipes = 4;
1558                 rdev->config.r600.max_tile_pipes = 4;
1559                 rdev->config.r600.max_simds = 4;
1560                 rdev->config.r600.max_backends = 4;
1561                 rdev->config.r600.max_gprs = 192;
1562                 rdev->config.r600.max_threads = 192;
1563                 rdev->config.r600.max_stack_entries = 256;
1564                 rdev->config.r600.max_hw_contexts = 8;
1565                 rdev->config.r600.max_gs_threads = 16;
1566                 rdev->config.r600.sx_max_export_size = 128;
1567                 rdev->config.r600.sx_max_export_pos_size = 16;
1568                 rdev->config.r600.sx_max_export_smx_size = 128;
1569                 rdev->config.r600.sq_num_cf_insts = 2;
1570                 break;
1571         default:
1572                 break;
1573         }
1574
1575         /* Initialize HDP */
1576         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1577                 WREG32((0x2c14 + j), 0x00000000);
1578                 WREG32((0x2c18 + j), 0x00000000);
1579                 WREG32((0x2c1c + j), 0x00000000);
1580                 WREG32((0x2c20 + j), 0x00000000);
1581                 WREG32((0x2c24 + j), 0x00000000);
1582         }
1583
1584         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1585
1586         /* Setup tiling */
1587         tiling_config = 0;
1588         ramcfg = RREG32(RAMCFG);
1589         switch (rdev->config.r600.max_tile_pipes) {
1590         case 1:
1591                 tiling_config |= PIPE_TILING(0);
1592                 break;
1593         case 2:
1594                 tiling_config |= PIPE_TILING(1);
1595                 break;
1596         case 4:
1597                 tiling_config |= PIPE_TILING(2);
1598                 break;
1599         case 8:
1600                 tiling_config |= PIPE_TILING(3);
1601                 break;
1602         default:
1603                 break;
1604         }
1605         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1606         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1607         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1608         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1609         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1610                 rdev->config.r600.tiling_group_size = 512;
1611         else
1612                 rdev->config.r600.tiling_group_size = 256;
1613         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1614         if (tmp > 3) {
1615                 tiling_config |= ROW_TILING(3);
1616                 tiling_config |= SAMPLE_SPLIT(3);
1617         } else {
1618                 tiling_config |= ROW_TILING(tmp);
1619                 tiling_config |= SAMPLE_SPLIT(tmp);
1620         }
1621         tiling_config |= BANK_SWAPS(1);
1622
1623         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1624         cc_rb_backend_disable |=
1625                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1626
1627         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1628         cc_gc_shader_pipe_config |=
1629                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1630         cc_gc_shader_pipe_config |=
1631                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1632
1633         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1634                                                         (R6XX_MAX_BACKENDS -
1635                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1636                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1637                                                         (cc_rb_backend_disable >> 16));
1638         rdev->config.r600.tile_config = tiling_config;
1639         tiling_config |= BACKEND_MAP(backend_map);
1640         WREG32(GB_TILING_CONFIG, tiling_config);
1641         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1642         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1643
1644         /* Setup pipes */
1645         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1646         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1647         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1648
1649         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1650         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1651         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1652
1653         /* Setup some CP states */
1654         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1655         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1656
1657         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1658                              SYNC_WALKER | SYNC_ALIGNER));
1659         /* Setup various GPU states */
1660         if (rdev->family == CHIP_RV670)
1661                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1662
1663         tmp = RREG32(SX_DEBUG_1);
1664         tmp |= SMX_EVENT_RELEASE;
1665         if ((rdev->family > CHIP_R600))
1666                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1667         WREG32(SX_DEBUG_1, tmp);
1668
1669         if (((rdev->family) == CHIP_R600) ||
1670             ((rdev->family) == CHIP_RV630) ||
1671             ((rdev->family) == CHIP_RV610) ||
1672             ((rdev->family) == CHIP_RV620) ||
1673             ((rdev->family) == CHIP_RS780) ||
1674             ((rdev->family) == CHIP_RS880)) {
1675                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1676         } else {
1677                 WREG32(DB_DEBUG, 0);
1678         }
1679         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1680                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1681
1682         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1683         WREG32(VGT_NUM_INSTANCES, 0);
1684
1685         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1686         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1687
1688         tmp = RREG32(SQ_MS_FIFO_SIZES);
1689         if (((rdev->family) == CHIP_RV610) ||
1690             ((rdev->family) == CHIP_RV620) ||
1691             ((rdev->family) == CHIP_RS780) ||
1692             ((rdev->family) == CHIP_RS880)) {
1693                 tmp = (CACHE_FIFO_SIZE(0xa) |
1694                        FETCH_FIFO_HIWATER(0xa) |
1695                        DONE_FIFO_HIWATER(0xe0) |
1696                        ALU_UPDATE_FIFO_HIWATER(0x8));
1697         } else if (((rdev->family) == CHIP_R600) ||
1698                    ((rdev->family) == CHIP_RV630)) {
1699                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1700                 tmp |= DONE_FIFO_HIWATER(0x4);
1701         }
1702         WREG32(SQ_MS_FIFO_SIZES, tmp);
1703
1704         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1705          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1706          */
1707         sq_config = RREG32(SQ_CONFIG);
1708         sq_config &= ~(PS_PRIO(3) |
1709                        VS_PRIO(3) |
1710                        GS_PRIO(3) |
1711                        ES_PRIO(3));
1712         sq_config |= (DX9_CONSTS |
1713                       VC_ENABLE |
1714                       PS_PRIO(0) |
1715                       VS_PRIO(1) |
1716                       GS_PRIO(2) |
1717                       ES_PRIO(3));
1718
1719         if ((rdev->family) == CHIP_R600) {
1720                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1721                                           NUM_VS_GPRS(124) |
1722                                           NUM_CLAUSE_TEMP_GPRS(4));
1723                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1724                                           NUM_ES_GPRS(0));
1725                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1726                                            NUM_VS_THREADS(48) |
1727                                            NUM_GS_THREADS(4) |
1728                                            NUM_ES_THREADS(4));
1729                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1730                                             NUM_VS_STACK_ENTRIES(128));
1731                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1732                                             NUM_ES_STACK_ENTRIES(0));
1733         } else if (((rdev->family) == CHIP_RV610) ||
1734                    ((rdev->family) == CHIP_RV620) ||
1735                    ((rdev->family) == CHIP_RS780) ||
1736                    ((rdev->family) == CHIP_RS880)) {
1737                 /* no vertex cache */
1738                 sq_config &= ~VC_ENABLE;
1739
1740                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1741                                           NUM_VS_GPRS(44) |
1742                                           NUM_CLAUSE_TEMP_GPRS(2));
1743                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1744                                           NUM_ES_GPRS(17));
1745                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1746                                            NUM_VS_THREADS(78) |
1747                                            NUM_GS_THREADS(4) |
1748                                            NUM_ES_THREADS(31));
1749                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1750                                             NUM_VS_STACK_ENTRIES(40));
1751                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1752                                             NUM_ES_STACK_ENTRIES(16));
1753         } else if (((rdev->family) == CHIP_RV630) ||
1754                    ((rdev->family) == CHIP_RV635)) {
1755                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1756                                           NUM_VS_GPRS(44) |
1757                                           NUM_CLAUSE_TEMP_GPRS(2));
1758                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1759                                           NUM_ES_GPRS(18));
1760                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1761                                            NUM_VS_THREADS(78) |
1762                                            NUM_GS_THREADS(4) |
1763                                            NUM_ES_THREADS(31));
1764                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1765                                             NUM_VS_STACK_ENTRIES(40));
1766                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1767                                             NUM_ES_STACK_ENTRIES(16));
1768         } else if ((rdev->family) == CHIP_RV670) {
1769                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1770                                           NUM_VS_GPRS(44) |
1771                                           NUM_CLAUSE_TEMP_GPRS(2));
1772                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1773                                           NUM_ES_GPRS(17));
1774                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1775                                            NUM_VS_THREADS(78) |
1776                                            NUM_GS_THREADS(4) |
1777                                            NUM_ES_THREADS(31));
1778                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1779                                             NUM_VS_STACK_ENTRIES(64));
1780                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1781                                             NUM_ES_STACK_ENTRIES(64));
1782         }
1783
1784         WREG32(SQ_CONFIG, sq_config);
1785         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1786         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1787         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1788         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1789         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1790
1791         if (((rdev->family) == CHIP_RV610) ||
1792             ((rdev->family) == CHIP_RV620) ||
1793             ((rdev->family) == CHIP_RS780) ||
1794             ((rdev->family) == CHIP_RS880)) {
1795                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1796         } else {
1797                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1798         }
1799
1800         /* More default values. 2D/3D driver should adjust as needed */
1801         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1802                                          S1_X(0x4) | S1_Y(0xc)));
1803         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1804                                          S1_X(0x2) | S1_Y(0x2) |
1805                                          S2_X(0xa) | S2_Y(0x6) |
1806                                          S3_X(0x6) | S3_Y(0xa)));
1807         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1808                                              S1_X(0x4) | S1_Y(0xc) |
1809                                              S2_X(0x1) | S2_Y(0x6) |
1810                                              S3_X(0xa) | S3_Y(0xe)));
1811         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1812                                              S5_X(0x0) | S5_Y(0x0) |
1813                                              S6_X(0xb) | S6_Y(0x4) |
1814                                              S7_X(0x7) | S7_Y(0x8)));
1815
1816         WREG32(VGT_STRMOUT_EN, 0);
1817         tmp = rdev->config.r600.max_pipes * 16;
1818         switch (rdev->family) {
1819         case CHIP_RV610:
1820         case CHIP_RV620:
1821         case CHIP_RS780:
1822         case CHIP_RS880:
1823                 tmp += 32;
1824                 break;
1825         case CHIP_RV670:
1826                 tmp += 128;
1827                 break;
1828         default:
1829                 break;
1830         }
1831         if (tmp > 256) {
1832                 tmp = 256;
1833         }
1834         WREG32(VGT_ES_PER_GS, 128);
1835         WREG32(VGT_GS_PER_ES, tmp);
1836         WREG32(VGT_GS_PER_VS, 2);
1837         WREG32(VGT_GS_VERTEX_REUSE, 16);
1838
1839         /* more default values. 2D/3D driver should adjust as needed */
1840         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1841         WREG32(VGT_STRMOUT_EN, 0);
1842         WREG32(SX_MISC, 0);
1843         WREG32(PA_SC_MODE_CNTL, 0);
1844         WREG32(PA_SC_AA_CONFIG, 0);
1845         WREG32(PA_SC_LINE_STIPPLE, 0);
1846         WREG32(SPI_INPUT_Z, 0);
1847         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1848         WREG32(CB_COLOR7_FRAG, 0);
1849
1850         /* Clear render buffer base addresses */
1851         WREG32(CB_COLOR0_BASE, 0);
1852         WREG32(CB_COLOR1_BASE, 0);
1853         WREG32(CB_COLOR2_BASE, 0);
1854         WREG32(CB_COLOR3_BASE, 0);
1855         WREG32(CB_COLOR4_BASE, 0);
1856         WREG32(CB_COLOR5_BASE, 0);
1857         WREG32(CB_COLOR6_BASE, 0);
1858         WREG32(CB_COLOR7_BASE, 0);
1859         WREG32(CB_COLOR7_FRAG, 0);
1860
1861         switch (rdev->family) {
1862         case CHIP_RV610:
1863         case CHIP_RV620:
1864         case CHIP_RS780:
1865         case CHIP_RS880:
1866                 tmp = TC_L2_SIZE(8);
1867                 break;
1868         case CHIP_RV630:
1869         case CHIP_RV635:
1870                 tmp = TC_L2_SIZE(4);
1871                 break;
1872         case CHIP_R600:
1873                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1874                 break;
1875         default:
1876                 tmp = TC_L2_SIZE(0);
1877                 break;
1878         }
1879         WREG32(TC_CNTL, tmp);
1880
1881         tmp = RREG32(HDP_HOST_PATH_CNTL);
1882         WREG32(HDP_HOST_PATH_CNTL, tmp);
1883
1884         tmp = RREG32(ARB_POP);
1885         tmp |= ENABLE_TC128;
1886         WREG32(ARB_POP, tmp);
1887
1888         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1889         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1890                                NUM_CLIP_SEQ(3)));
1891         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1892 }
1893
1894
1895 /*
1896  * Indirect registers accessor
1897  */
1898 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1899 {
1900         u32 r;
1901
1902         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1903         (void)RREG32(PCIE_PORT_INDEX);
1904         r = RREG32(PCIE_PORT_DATA);
1905         return r;
1906 }
1907
1908 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1909 {
1910         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1911         (void)RREG32(PCIE_PORT_INDEX);
1912         WREG32(PCIE_PORT_DATA, (v));
1913         (void)RREG32(PCIE_PORT_DATA);
1914 }
1915
1916 /*
1917  * CP & Ring
1918  */
1919 void r600_cp_stop(struct radeon_device *rdev)
1920 {
1921         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1922         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1923         WREG32(SCRATCH_UMSK, 0);
1924 }
1925
1926 int r600_init_microcode(struct radeon_device *rdev)
1927 {
1928         struct platform_device *pdev;
1929         const char *chip_name;
1930         const char *rlc_chip_name;
1931         size_t pfp_req_size, me_req_size, rlc_req_size;
1932         char fw_name[30];
1933         int err;
1934
1935         DRM_DEBUG("\n");
1936
1937         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1938         err = IS_ERR(pdev);
1939         if (err) {
1940                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1941                 return -EINVAL;
1942         }
1943
1944         switch (rdev->family) {
1945         case CHIP_R600:
1946                 chip_name = "R600";
1947                 rlc_chip_name = "R600";
1948                 break;
1949         case CHIP_RV610:
1950                 chip_name = "RV610";
1951                 rlc_chip_name = "R600";
1952                 break;
1953         case CHIP_RV630:
1954                 chip_name = "RV630";
1955                 rlc_chip_name = "R600";
1956                 break;
1957         case CHIP_RV620:
1958                 chip_name = "RV620";
1959                 rlc_chip_name = "R600";
1960                 break;
1961         case CHIP_RV635:
1962                 chip_name = "RV635";
1963                 rlc_chip_name = "R600";
1964                 break;
1965         case CHIP_RV670:
1966                 chip_name = "RV670";
1967                 rlc_chip_name = "R600";
1968                 break;
1969         case CHIP_RS780:
1970         case CHIP_RS880:
1971                 chip_name = "RS780";
1972                 rlc_chip_name = "R600";
1973                 break;
1974         case CHIP_RV770:
1975                 chip_name = "RV770";
1976                 rlc_chip_name = "R700";
1977                 break;
1978         case CHIP_RV730:
1979         case CHIP_RV740:
1980                 chip_name = "RV730";
1981                 rlc_chip_name = "R700";
1982                 break;
1983         case CHIP_RV710:
1984                 chip_name = "RV710";
1985                 rlc_chip_name = "R700";
1986                 break;
1987         case CHIP_CEDAR:
1988                 chip_name = "CEDAR";
1989                 rlc_chip_name = "CEDAR";
1990                 break;
1991         case CHIP_REDWOOD:
1992                 chip_name = "REDWOOD";
1993                 rlc_chip_name = "REDWOOD";
1994                 break;
1995         case CHIP_JUNIPER:
1996                 chip_name = "JUNIPER";
1997                 rlc_chip_name = "JUNIPER";
1998                 break;
1999         case CHIP_CYPRESS:
2000         case CHIP_HEMLOCK:
2001                 chip_name = "CYPRESS";
2002                 rlc_chip_name = "CYPRESS";
2003                 break;
2004         case CHIP_PALM:
2005                 chip_name = "PALM";
2006                 rlc_chip_name = "SUMO";
2007                 break;
2008         default: BUG();
2009         }
2010
2011         if (rdev->family >= CHIP_CEDAR) {
2012                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2013                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2014                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2015         } else if (rdev->family >= CHIP_RV770) {
2016                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2017                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2018                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2019         } else {
2020                 pfp_req_size = PFP_UCODE_SIZE * 4;
2021                 me_req_size = PM4_UCODE_SIZE * 12;
2022                 rlc_req_size = RLC_UCODE_SIZE * 4;
2023         }
2024
2025         DRM_INFO("Loading %s Microcode\n", chip_name);
2026
2027         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2028         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2029         if (err)
2030                 goto out;
2031         if (rdev->pfp_fw->size != pfp_req_size) {
2032                 printk(KERN_ERR
2033                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2034                        rdev->pfp_fw->size, fw_name);
2035                 err = -EINVAL;
2036                 goto out;
2037         }
2038
2039         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2040         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2041         if (err)
2042                 goto out;
2043         if (rdev->me_fw->size != me_req_size) {
2044                 printk(KERN_ERR
2045                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2046                        rdev->me_fw->size, fw_name);
2047                 err = -EINVAL;
2048         }
2049
2050         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2051         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2052         if (err)
2053                 goto out;
2054         if (rdev->rlc_fw->size != rlc_req_size) {
2055                 printk(KERN_ERR
2056                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2057                        rdev->rlc_fw->size, fw_name);
2058                 err = -EINVAL;
2059         }
2060
2061 out:
2062         platform_device_unregister(pdev);
2063
2064         if (err) {
2065                 if (err != -EINVAL)
2066                         printk(KERN_ERR
2067                                "r600_cp: Failed to load firmware \"%s\"\n",
2068                                fw_name);
2069                 release_firmware(rdev->pfp_fw);
2070                 rdev->pfp_fw = NULL;
2071                 release_firmware(rdev->me_fw);
2072                 rdev->me_fw = NULL;
2073                 release_firmware(rdev->rlc_fw);
2074                 rdev->rlc_fw = NULL;
2075         }
2076         return err;
2077 }
2078
2079 static int r600_cp_load_microcode(struct radeon_device *rdev)
2080 {
2081         const __be32 *fw_data;
2082         int i;
2083
2084         if (!rdev->me_fw || !rdev->pfp_fw)
2085                 return -EINVAL;
2086
2087         r600_cp_stop(rdev);
2088
2089         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2090
2091         /* Reset cp */
2092         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2093         RREG32(GRBM_SOFT_RESET);
2094         mdelay(15);
2095         WREG32(GRBM_SOFT_RESET, 0);
2096
2097         WREG32(CP_ME_RAM_WADDR, 0);
2098
2099         fw_data = (const __be32 *)rdev->me_fw->data;
2100         WREG32(CP_ME_RAM_WADDR, 0);
2101         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2102                 WREG32(CP_ME_RAM_DATA,
2103                        be32_to_cpup(fw_data++));
2104
2105         fw_data = (const __be32 *)rdev->pfp_fw->data;
2106         WREG32(CP_PFP_UCODE_ADDR, 0);
2107         for (i = 0; i < PFP_UCODE_SIZE; i++)
2108                 WREG32(CP_PFP_UCODE_DATA,
2109                        be32_to_cpup(fw_data++));
2110
2111         WREG32(CP_PFP_UCODE_ADDR, 0);
2112         WREG32(CP_ME_RAM_WADDR, 0);
2113         WREG32(CP_ME_RAM_RADDR, 0);
2114         return 0;
2115 }
2116
2117 int r600_cp_start(struct radeon_device *rdev)
2118 {
2119         int r;
2120         uint32_t cp_me;
2121
2122         r = radeon_ring_lock(rdev, 7);
2123         if (r) {
2124                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2125                 return r;
2126         }
2127         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2128         radeon_ring_write(rdev, 0x1);
2129         if (rdev->family >= CHIP_RV770) {
2130                 radeon_ring_write(rdev, 0x0);
2131                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2132         } else {
2133                 radeon_ring_write(rdev, 0x3);
2134                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2135         }
2136         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2137         radeon_ring_write(rdev, 0);
2138         radeon_ring_write(rdev, 0);
2139         radeon_ring_unlock_commit(rdev);
2140
2141         cp_me = 0xff;
2142         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2143         return 0;
2144 }
2145
2146 int r600_cp_resume(struct radeon_device *rdev)
2147 {
2148         u32 tmp;
2149         u32 rb_bufsz;
2150         int r;
2151
2152         /* Reset cp */
2153         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2154         RREG32(GRBM_SOFT_RESET);
2155         mdelay(15);
2156         WREG32(GRBM_SOFT_RESET, 0);
2157
2158         /* Set ring buffer size */
2159         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2160         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2161 #ifdef __BIG_ENDIAN
2162         tmp |= BUF_SWAP_32BIT;
2163 #endif
2164         WREG32(CP_RB_CNTL, tmp);
2165         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2166
2167         /* Set the write pointer delay */
2168         WREG32(CP_RB_WPTR_DELAY, 0);
2169
2170         /* Initialize the ring buffer's read and write pointers */
2171         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2172         WREG32(CP_RB_RPTR_WR, 0);
2173         WREG32(CP_RB_WPTR, 0);
2174
2175         /* set the wb address whether it's enabled or not */
2176         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2177         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2178         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2179
2180         if (rdev->wb.enabled)
2181                 WREG32(SCRATCH_UMSK, 0xff);
2182         else {
2183                 tmp |= RB_NO_UPDATE;
2184                 WREG32(SCRATCH_UMSK, 0);
2185         }
2186
2187         mdelay(1);
2188         WREG32(CP_RB_CNTL, tmp);
2189
2190         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2191         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2192
2193         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2194         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2195
2196         r600_cp_start(rdev);
2197         rdev->cp.ready = true;
2198         r = radeon_ring_test(rdev);
2199         if (r) {
2200                 rdev->cp.ready = false;
2201                 return r;
2202         }
2203         return 0;
2204 }
2205
2206 void r600_cp_commit(struct radeon_device *rdev)
2207 {
2208         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2209         (void)RREG32(CP_RB_WPTR);
2210 }
2211
2212 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2213 {
2214         u32 rb_bufsz;
2215
2216         /* Align ring size */
2217         rb_bufsz = drm_order(ring_size / 8);
2218         ring_size = (1 << (rb_bufsz + 1)) * 4;
2219         rdev->cp.ring_size = ring_size;
2220         rdev->cp.align_mask = 16 - 1;
2221 }
2222
2223 void r600_cp_fini(struct radeon_device *rdev)
2224 {
2225         r600_cp_stop(rdev);
2226         radeon_ring_fini(rdev);
2227 }
2228
2229
2230 /*
2231  * GPU scratch registers helpers function.
2232  */
2233 void r600_scratch_init(struct radeon_device *rdev)
2234 {
2235         int i;
2236
2237         rdev->scratch.num_reg = 7;
2238         rdev->scratch.reg_base = SCRATCH_REG0;
2239         for (i = 0; i < rdev->scratch.num_reg; i++) {
2240                 rdev->scratch.free[i] = true;
2241                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2242         }
2243 }
2244
2245 int r600_ring_test(struct radeon_device *rdev)
2246 {
2247         uint32_t scratch;
2248         uint32_t tmp = 0;
2249         unsigned i;
2250         int r;
2251
2252         r = radeon_scratch_get(rdev, &scratch);
2253         if (r) {
2254                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2255                 return r;
2256         }
2257         WREG32(scratch, 0xCAFEDEAD);
2258         r = radeon_ring_lock(rdev, 3);
2259         if (r) {
2260                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2261                 radeon_scratch_free(rdev, scratch);
2262                 return r;
2263         }
2264         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2265         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2266         radeon_ring_write(rdev, 0xDEADBEEF);
2267         radeon_ring_unlock_commit(rdev);
2268         for (i = 0; i < rdev->usec_timeout; i++) {
2269                 tmp = RREG32(scratch);
2270                 if (tmp == 0xDEADBEEF)
2271                         break;
2272                 DRM_UDELAY(1);
2273         }
2274         if (i < rdev->usec_timeout) {
2275                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2276         } else {
2277                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2278                           scratch, tmp);
2279                 r = -EINVAL;
2280         }
2281         radeon_scratch_free(rdev, scratch);
2282         return r;
2283 }
2284
2285 void r600_fence_ring_emit(struct radeon_device *rdev,
2286                           struct radeon_fence *fence)
2287 {
2288         if (rdev->wb.use_event) {
2289                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2290                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2291                 /* EVENT_WRITE_EOP - flush caches, send int */
2292                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2293                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2294                 radeon_ring_write(rdev, addr & 0xffffffff);
2295                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2296                 radeon_ring_write(rdev, fence->seq);
2297                 radeon_ring_write(rdev, 0);
2298         } else {
2299                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2300                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2301                 /* wait for 3D idle clean */
2302                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2303                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2304                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2305                 /* Emit fence sequence & fire IRQ */
2306                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2307                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2308                 radeon_ring_write(rdev, fence->seq);
2309                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2310                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2311                 radeon_ring_write(rdev, RB_INT_STAT);
2312         }
2313 }
2314
2315 int r600_copy_blit(struct radeon_device *rdev,
2316                    uint64_t src_offset, uint64_t dst_offset,
2317                    unsigned num_pages, struct radeon_fence *fence)
2318 {
2319         int r;
2320
2321         mutex_lock(&rdev->r600_blit.mutex);
2322         rdev->r600_blit.vb_ib = NULL;
2323         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2324         if (r) {
2325                 if (rdev->r600_blit.vb_ib)
2326                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2327                 mutex_unlock(&rdev->r600_blit.mutex);
2328                 return r;
2329         }
2330         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2331         r600_blit_done_copy(rdev, fence);
2332         mutex_unlock(&rdev->r600_blit.mutex);
2333         return 0;
2334 }
2335
2336 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2337                          uint32_t tiling_flags, uint32_t pitch,
2338                          uint32_t offset, uint32_t obj_size)
2339 {
2340         /* FIXME: implement */
2341         return 0;
2342 }
2343
2344 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2345 {
2346         /* FIXME: implement */
2347 }
2348
2349
2350 bool r600_card_posted(struct radeon_device *rdev)
2351 {
2352         uint32_t reg;
2353
2354         /* first check CRTCs */
2355         reg = RREG32(D1CRTC_CONTROL) |
2356                 RREG32(D2CRTC_CONTROL);
2357         if (reg & CRTC_EN)
2358                 return true;
2359
2360         /* then check MEM_SIZE, in case the crtcs are off */
2361         if (RREG32(CONFIG_MEMSIZE))
2362                 return true;
2363
2364         return false;
2365 }
2366
2367 int r600_startup(struct radeon_device *rdev)
2368 {
2369         int r;
2370
2371         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2372                 r = r600_init_microcode(rdev);
2373                 if (r) {
2374                         DRM_ERROR("Failed to load firmware!\n");
2375                         return r;
2376                 }
2377         }
2378
2379         r600_mc_program(rdev);
2380         if (rdev->flags & RADEON_IS_AGP) {
2381                 r600_agp_enable(rdev);
2382         } else {
2383                 r = r600_pcie_gart_enable(rdev);
2384                 if (r)
2385                         return r;
2386         }
2387         r600_gpu_init(rdev);
2388         r = r600_blit_init(rdev);
2389         if (r) {
2390                 r600_blit_fini(rdev);
2391                 rdev->asic->copy = NULL;
2392                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2393         }
2394
2395         /* allocate wb buffer */
2396         r = radeon_wb_init(rdev);
2397         if (r)
2398                 return r;
2399
2400         /* Enable IRQ */
2401         r = r600_irq_init(rdev);
2402         if (r) {
2403                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2404                 radeon_irq_kms_fini(rdev);
2405                 return r;
2406         }
2407         r600_irq_set(rdev);
2408
2409         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2410         if (r)
2411                 return r;
2412         r = r600_cp_load_microcode(rdev);
2413         if (r)
2414                 return r;
2415         r = r600_cp_resume(rdev);
2416         if (r)
2417                 return r;
2418
2419         return 0;
2420 }
2421
2422 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2423 {
2424         uint32_t temp;
2425
2426         temp = RREG32(CONFIG_CNTL);
2427         if (state == false) {
2428                 temp &= ~(1<<0);
2429                 temp |= (1<<1);
2430         } else {
2431                 temp &= ~(1<<1);
2432         }
2433         WREG32(CONFIG_CNTL, temp);
2434 }
2435
2436 int r600_resume(struct radeon_device *rdev)
2437 {
2438         int r;
2439
2440         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2441          * posting will perform necessary task to bring back GPU into good
2442          * shape.
2443          */
2444         /* post card */
2445         atom_asic_init(rdev->mode_info.atom_context);
2446
2447         r = r600_startup(rdev);
2448         if (r) {
2449                 DRM_ERROR("r600 startup failed on resume\n");
2450                 return r;
2451         }
2452
2453         r = r600_ib_test(rdev);
2454         if (r) {
2455                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2456                 return r;
2457         }
2458
2459         r = r600_audio_init(rdev);
2460         if (r) {
2461                 DRM_ERROR("radeon: audio resume failed\n");
2462                 return r;
2463         }
2464
2465         return r;
2466 }
2467
2468 int r600_suspend(struct radeon_device *rdev)
2469 {
2470         int r;
2471
2472         r600_audio_fini(rdev);
2473         /* FIXME: we should wait for ring to be empty */
2474         r600_cp_stop(rdev);
2475         rdev->cp.ready = false;
2476         r600_irq_suspend(rdev);
2477         radeon_wb_disable(rdev);
2478         r600_pcie_gart_disable(rdev);
2479         /* unpin shaders bo */
2480         if (rdev->r600_blit.shader_obj) {
2481                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2482                 if (!r) {
2483                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2484                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2485                 }
2486         }
2487         return 0;
2488 }
2489
2490 /* Plan is to move initialization in that function and use
2491  * helper function so that radeon_device_init pretty much
2492  * do nothing more than calling asic specific function. This
2493  * should also allow to remove a bunch of callback function
2494  * like vram_info.
2495  */
2496 int r600_init(struct radeon_device *rdev)
2497 {
2498         int r;
2499
2500         r = radeon_dummy_page_init(rdev);
2501         if (r)
2502                 return r;
2503         if (r600_debugfs_mc_info_init(rdev)) {
2504                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2505         }
2506         /* This don't do much */
2507         r = radeon_gem_init(rdev);
2508         if (r)
2509                 return r;
2510         /* Read BIOS */
2511         if (!radeon_get_bios(rdev)) {
2512                 if (ASIC_IS_AVIVO(rdev))
2513                         return -EINVAL;
2514         }
2515         /* Must be an ATOMBIOS */
2516         if (!rdev->is_atom_bios) {
2517                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2518                 return -EINVAL;
2519         }
2520         r = radeon_atombios_init(rdev);
2521         if (r)
2522                 return r;
2523         /* Post card if necessary */
2524         if (!r600_card_posted(rdev)) {
2525                 if (!rdev->bios) {
2526                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2527                         return -EINVAL;
2528                 }
2529                 DRM_INFO("GPU not posted. posting now...\n");
2530                 atom_asic_init(rdev->mode_info.atom_context);
2531         }
2532         /* Initialize scratch registers */
2533         r600_scratch_init(rdev);
2534         /* Initialize surface registers */
2535         radeon_surface_init(rdev);
2536         /* Initialize clocks */
2537         radeon_get_clock_info(rdev->ddev);
2538         /* Fence driver */
2539         r = radeon_fence_driver_init(rdev);
2540         if (r)
2541                 return r;
2542         if (rdev->flags & RADEON_IS_AGP) {
2543                 r = radeon_agp_init(rdev);
2544                 if (r)
2545                         radeon_agp_disable(rdev);
2546         }
2547         r = r600_mc_init(rdev);
2548         if (r)
2549                 return r;
2550         /* Memory manager */
2551         r = radeon_bo_init(rdev);
2552         if (r)
2553                 return r;
2554
2555         r = radeon_irq_kms_init(rdev);
2556         if (r)
2557                 return r;
2558
2559         rdev->cp.ring_obj = NULL;
2560         r600_ring_init(rdev, 1024 * 1024);
2561
2562         rdev->ih.ring_obj = NULL;
2563         r600_ih_ring_init(rdev, 64 * 1024);
2564
2565         r = r600_pcie_gart_init(rdev);
2566         if (r)
2567                 return r;
2568
2569         rdev->accel_working = true;
2570         r = r600_startup(rdev);
2571         if (r) {
2572                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2573                 r600_cp_fini(rdev);
2574                 r600_irq_fini(rdev);
2575                 radeon_wb_fini(rdev);
2576                 radeon_irq_kms_fini(rdev);
2577                 r600_pcie_gart_fini(rdev);
2578                 rdev->accel_working = false;
2579         }
2580         if (rdev->accel_working) {
2581                 r = radeon_ib_pool_init(rdev);
2582                 if (r) {
2583                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2584                         rdev->accel_working = false;
2585                 } else {
2586                         r = r600_ib_test(rdev);
2587                         if (r) {
2588                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2589                                 rdev->accel_working = false;
2590                         }
2591                 }
2592         }
2593
2594         r = r600_audio_init(rdev);
2595         if (r)
2596                 return r; /* TODO error handling */
2597         return 0;
2598 }
2599
2600 void r600_fini(struct radeon_device *rdev)
2601 {
2602         r600_audio_fini(rdev);
2603         r600_blit_fini(rdev);
2604         r600_cp_fini(rdev);
2605         r600_irq_fini(rdev);
2606         radeon_wb_fini(rdev);
2607         radeon_irq_kms_fini(rdev);
2608         r600_pcie_gart_fini(rdev);
2609         radeon_agp_fini(rdev);
2610         radeon_gem_fini(rdev);
2611         radeon_fence_driver_fini(rdev);
2612         radeon_bo_fini(rdev);
2613         radeon_atombios_fini(rdev);
2614         kfree(rdev->bios);
2615         rdev->bios = NULL;
2616         radeon_dummy_page_fini(rdev);
2617 }
2618
2619
2620 /*
2621  * CS stuff
2622  */
2623 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2624 {
2625         /* FIXME: implement */
2626         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2627         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2628         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2629         radeon_ring_write(rdev, ib->length_dw);
2630 }
2631
2632 int r600_ib_test(struct radeon_device *rdev)
2633 {
2634         struct radeon_ib *ib;
2635         uint32_t scratch;
2636         uint32_t tmp = 0;
2637         unsigned i;
2638         int r;
2639
2640         r = radeon_scratch_get(rdev, &scratch);
2641         if (r) {
2642                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2643                 return r;
2644         }
2645         WREG32(scratch, 0xCAFEDEAD);
2646         r = radeon_ib_get(rdev, &ib);
2647         if (r) {
2648                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2649                 return r;
2650         }
2651         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2652         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2653         ib->ptr[2] = 0xDEADBEEF;
2654         ib->ptr[3] = PACKET2(0);
2655         ib->ptr[4] = PACKET2(0);
2656         ib->ptr[5] = PACKET2(0);
2657         ib->ptr[6] = PACKET2(0);
2658         ib->ptr[7] = PACKET2(0);
2659         ib->ptr[8] = PACKET2(0);
2660         ib->ptr[9] = PACKET2(0);
2661         ib->ptr[10] = PACKET2(0);
2662         ib->ptr[11] = PACKET2(0);
2663         ib->ptr[12] = PACKET2(0);
2664         ib->ptr[13] = PACKET2(0);
2665         ib->ptr[14] = PACKET2(0);
2666         ib->ptr[15] = PACKET2(0);
2667         ib->length_dw = 16;
2668         r = radeon_ib_schedule(rdev, ib);
2669         if (r) {
2670                 radeon_scratch_free(rdev, scratch);
2671                 radeon_ib_free(rdev, &ib);
2672                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2673                 return r;
2674         }
2675         r = radeon_fence_wait(ib->fence, false);
2676         if (r) {
2677                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2678                 return r;
2679         }
2680         for (i = 0; i < rdev->usec_timeout; i++) {
2681                 tmp = RREG32(scratch);
2682                 if (tmp == 0xDEADBEEF)
2683                         break;
2684                 DRM_UDELAY(1);
2685         }
2686         if (i < rdev->usec_timeout) {
2687                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2688         } else {
2689                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2690                           scratch, tmp);
2691                 r = -EINVAL;
2692         }
2693         radeon_scratch_free(rdev, scratch);
2694         radeon_ib_free(rdev, &ib);
2695         return r;
2696 }
2697
2698 /*
2699  * Interrupts
2700  *
2701  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2702  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2703  * writing to the ring and the GPU consuming, the GPU writes to the ring
2704  * and host consumes.  As the host irq handler processes interrupts, it
2705  * increments the rptr.  When the rptr catches up with the wptr, all the
2706  * current interrupts have been processed.
2707  */
2708
2709 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2710 {
2711         u32 rb_bufsz;
2712
2713         /* Align ring size */
2714         rb_bufsz = drm_order(ring_size / 4);
2715         ring_size = (1 << rb_bufsz) * 4;
2716         rdev->ih.ring_size = ring_size;
2717         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2718         rdev->ih.rptr = 0;
2719 }
2720
2721 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2722 {
2723         int r;
2724
2725         /* Allocate ring buffer */
2726         if (rdev->ih.ring_obj == NULL) {
2727                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2728                                      PAGE_SIZE, true,
2729                                      RADEON_GEM_DOMAIN_GTT,
2730                                      &rdev->ih.ring_obj);
2731                 if (r) {
2732                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2733                         return r;
2734                 }
2735                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2736                 if (unlikely(r != 0))
2737                         return r;
2738                 r = radeon_bo_pin(rdev->ih.ring_obj,
2739                                   RADEON_GEM_DOMAIN_GTT,
2740                                   &rdev->ih.gpu_addr);
2741                 if (r) {
2742                         radeon_bo_unreserve(rdev->ih.ring_obj);
2743                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2744                         return r;
2745                 }
2746                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2747                                    (void **)&rdev->ih.ring);
2748                 radeon_bo_unreserve(rdev->ih.ring_obj);
2749                 if (r) {
2750                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2751                         return r;
2752                 }
2753         }
2754         return 0;
2755 }
2756
2757 static void r600_ih_ring_fini(struct radeon_device *rdev)
2758 {
2759         int r;
2760         if (rdev->ih.ring_obj) {
2761                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2762                 if (likely(r == 0)) {
2763                         radeon_bo_kunmap(rdev->ih.ring_obj);
2764                         radeon_bo_unpin(rdev->ih.ring_obj);
2765                         radeon_bo_unreserve(rdev->ih.ring_obj);
2766                 }
2767                 radeon_bo_unref(&rdev->ih.ring_obj);
2768                 rdev->ih.ring = NULL;
2769                 rdev->ih.ring_obj = NULL;
2770         }
2771 }
2772
2773 void r600_rlc_stop(struct radeon_device *rdev)
2774 {
2775
2776         if ((rdev->family >= CHIP_RV770) &&
2777             (rdev->family <= CHIP_RV740)) {
2778                 /* r7xx asics need to soft reset RLC before halting */
2779                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2780                 RREG32(SRBM_SOFT_RESET);
2781                 udelay(15000);
2782                 WREG32(SRBM_SOFT_RESET, 0);
2783                 RREG32(SRBM_SOFT_RESET);
2784         }
2785
2786         WREG32(RLC_CNTL, 0);
2787 }
2788
2789 static void r600_rlc_start(struct radeon_device *rdev)
2790 {
2791         WREG32(RLC_CNTL, RLC_ENABLE);
2792 }
2793
2794 static int r600_rlc_init(struct radeon_device *rdev)
2795 {
2796         u32 i;
2797         const __be32 *fw_data;
2798
2799         if (!rdev->rlc_fw)
2800                 return -EINVAL;
2801
2802         r600_rlc_stop(rdev);
2803
2804         WREG32(RLC_HB_BASE, 0);
2805         WREG32(RLC_HB_CNTL, 0);
2806         WREG32(RLC_HB_RPTR, 0);
2807         WREG32(RLC_HB_WPTR, 0);
2808         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2809         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2810         WREG32(RLC_MC_CNTL, 0);
2811         WREG32(RLC_UCODE_CNTL, 0);
2812
2813         fw_data = (const __be32 *)rdev->rlc_fw->data;
2814         if (rdev->family >= CHIP_CEDAR) {
2815                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2816                         WREG32(RLC_UCODE_ADDR, i);
2817                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2818                 }
2819         } else if (rdev->family >= CHIP_RV770) {
2820                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2821                         WREG32(RLC_UCODE_ADDR, i);
2822                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2823                 }
2824         } else {
2825                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2826                         WREG32(RLC_UCODE_ADDR, i);
2827                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2828                 }
2829         }
2830         WREG32(RLC_UCODE_ADDR, 0);
2831
2832         r600_rlc_start(rdev);
2833
2834         return 0;
2835 }
2836
2837 static void r600_enable_interrupts(struct radeon_device *rdev)
2838 {
2839         u32 ih_cntl = RREG32(IH_CNTL);
2840         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2841
2842         ih_cntl |= ENABLE_INTR;
2843         ih_rb_cntl |= IH_RB_ENABLE;
2844         WREG32(IH_CNTL, ih_cntl);
2845         WREG32(IH_RB_CNTL, ih_rb_cntl);
2846         rdev->ih.enabled = true;
2847 }
2848
2849 void r600_disable_interrupts(struct radeon_device *rdev)
2850 {
2851         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2852         u32 ih_cntl = RREG32(IH_CNTL);
2853
2854         ih_rb_cntl &= ~IH_RB_ENABLE;
2855         ih_cntl &= ~ENABLE_INTR;
2856         WREG32(IH_RB_CNTL, ih_rb_cntl);
2857         WREG32(IH_CNTL, ih_cntl);
2858         /* set rptr, wptr to 0 */
2859         WREG32(IH_RB_RPTR, 0);
2860         WREG32(IH_RB_WPTR, 0);
2861         rdev->ih.enabled = false;
2862         rdev->ih.wptr = 0;
2863         rdev->ih.rptr = 0;
2864 }
2865
2866 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2867 {
2868         u32 tmp;
2869
2870         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2871         WREG32(GRBM_INT_CNTL, 0);
2872         WREG32(DxMODE_INT_MASK, 0);
2873         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2874         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2875         if (ASIC_IS_DCE3(rdev)) {
2876                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2877                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2878                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2879                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2880                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2881                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2882                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2883                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2884                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2885                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2886                 if (ASIC_IS_DCE32(rdev)) {
2887                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2888                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2889                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2890                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2891                 }
2892         } else {
2893                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2894                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2895                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2896                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2897                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2898                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2899                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2900                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2901         }
2902 }
2903
2904 int r600_irq_init(struct radeon_device *rdev)
2905 {
2906         int ret = 0;
2907         int rb_bufsz;
2908         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2909
2910         /* allocate ring */
2911         ret = r600_ih_ring_alloc(rdev);
2912         if (ret)
2913                 return ret;
2914
2915         /* disable irqs */
2916         r600_disable_interrupts(rdev);
2917
2918         /* init rlc */
2919         ret = r600_rlc_init(rdev);
2920         if (ret) {
2921                 r600_ih_ring_fini(rdev);
2922                 return ret;
2923         }
2924
2925         /* setup interrupt control */
2926         /* set dummy read address to ring address */
2927         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2928         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2929         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2930          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2931          */
2932         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2933         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2934         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2935         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2936
2937         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2938         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2939
2940         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2941                       IH_WPTR_OVERFLOW_CLEAR |
2942                       (rb_bufsz << 1));
2943
2944         if (rdev->wb.enabled)
2945                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2946
2947         /* set the writeback address whether it's enabled or not */
2948         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2949         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2950
2951         WREG32(IH_RB_CNTL, ih_rb_cntl);
2952
2953         /* set rptr, wptr to 0 */
2954         WREG32(IH_RB_RPTR, 0);
2955         WREG32(IH_RB_WPTR, 0);
2956
2957         /* Default settings for IH_CNTL (disabled at first) */
2958         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2959         /* RPTR_REARM only works if msi's are enabled */
2960         if (rdev->msi_enabled)
2961                 ih_cntl |= RPTR_REARM;
2962
2963 #ifdef __BIG_ENDIAN
2964         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2965 #endif
2966         WREG32(IH_CNTL, ih_cntl);
2967
2968         /* force the active interrupt state to all disabled */
2969         if (rdev->family >= CHIP_CEDAR)
2970                 evergreen_disable_interrupt_state(rdev);
2971         else
2972                 r600_disable_interrupt_state(rdev);
2973
2974         /* enable irqs */
2975         r600_enable_interrupts(rdev);
2976
2977         return ret;
2978 }
2979
2980 void r600_irq_suspend(struct radeon_device *rdev)
2981 {
2982         r600_irq_disable(rdev);
2983         r600_rlc_stop(rdev);
2984 }
2985
2986 void r600_irq_fini(struct radeon_device *rdev)
2987 {
2988         r600_irq_suspend(rdev);
2989         r600_ih_ring_fini(rdev);
2990 }
2991
2992 int r600_irq_set(struct radeon_device *rdev)
2993 {
2994         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2995         u32 mode_int = 0;
2996         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2997         u32 grbm_int_cntl = 0;
2998         u32 hdmi1, hdmi2;
2999         u32 d1grph = 0, d2grph = 0;
3000
3001         if (!rdev->irq.installed) {
3002                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3003                 return -EINVAL;
3004         }
3005         /* don't enable anything if the ih is disabled */
3006         if (!rdev->ih.enabled) {
3007                 r600_disable_interrupts(rdev);
3008                 /* force the active interrupt state to all disabled */
3009                 r600_disable_interrupt_state(rdev);
3010                 return 0;
3011         }
3012
3013         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3014         if (ASIC_IS_DCE3(rdev)) {
3015                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3016                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3017                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3018                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3019                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3020                 if (ASIC_IS_DCE32(rdev)) {
3021                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3022                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3023                 }
3024         } else {
3025                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3026                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3027                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029         }
3030
3031         if (rdev->irq.sw_int) {
3032                 DRM_DEBUG("r600_irq_set: sw int\n");
3033                 cp_int_cntl |= RB_INT_ENABLE;
3034                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3035         }
3036         if (rdev->irq.crtc_vblank_int[0] ||
3037             rdev->irq.pflip[0]) {
3038                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3039                 mode_int |= D1MODE_VBLANK_INT_MASK;
3040         }
3041         if (rdev->irq.crtc_vblank_int[1] ||
3042             rdev->irq.pflip[1]) {
3043                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3044                 mode_int |= D2MODE_VBLANK_INT_MASK;
3045         }
3046         if (rdev->irq.hpd[0]) {
3047                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3048                 hpd1 |= DC_HPDx_INT_EN;
3049         }
3050         if (rdev->irq.hpd[1]) {
3051                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3052                 hpd2 |= DC_HPDx_INT_EN;
3053         }
3054         if (rdev->irq.hpd[2]) {
3055                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3056                 hpd3 |= DC_HPDx_INT_EN;
3057         }
3058         if (rdev->irq.hpd[3]) {
3059                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3060                 hpd4 |= DC_HPDx_INT_EN;
3061         }
3062         if (rdev->irq.hpd[4]) {
3063                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3064                 hpd5 |= DC_HPDx_INT_EN;
3065         }
3066         if (rdev->irq.hpd[5]) {
3067                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3068                 hpd6 |= DC_HPDx_INT_EN;
3069         }
3070         if (rdev->irq.hdmi[0]) {
3071                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3072                 hdmi1 |= R600_HDMI_INT_EN;
3073         }
3074         if (rdev->irq.hdmi[1]) {
3075                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3076                 hdmi2 |= R600_HDMI_INT_EN;
3077         }
3078         if (rdev->irq.gui_idle) {
3079                 DRM_DEBUG("gui idle\n");
3080                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3081         }
3082
3083         WREG32(CP_INT_CNTL, cp_int_cntl);
3084         WREG32(DxMODE_INT_MASK, mode_int);
3085         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3086         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3087         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3088         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3089         if (ASIC_IS_DCE3(rdev)) {
3090                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3091                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3092                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3093                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3094                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3095                 if (ASIC_IS_DCE32(rdev)) {
3096                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3097                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3098                 }
3099         } else {
3100                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3101                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3102                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3103                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3104         }
3105
3106         return 0;
3107 }
3108
3109 static inline void r600_irq_ack(struct radeon_device *rdev)
3110 {
3111         u32 tmp;
3112
3113         if (ASIC_IS_DCE3(rdev)) {
3114                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3115                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3116                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3117         } else {
3118                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3119                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3120                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3121         }
3122         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3123         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3124
3125         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3126                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3127         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3128                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3129         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3130                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3131         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3132                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3133         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3134                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3135         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3136                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3137         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3138                 if (ASIC_IS_DCE3(rdev)) {
3139                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3140                         tmp |= DC_HPDx_INT_ACK;
3141                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3142                 } else {
3143                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3144                         tmp |= DC_HPDx_INT_ACK;
3145                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3146                 }
3147         }
3148         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3149                 if (ASIC_IS_DCE3(rdev)) {
3150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3151                         tmp |= DC_HPDx_INT_ACK;
3152                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3153                 } else {
3154                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3155                         tmp |= DC_HPDx_INT_ACK;
3156                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3157                 }
3158         }
3159         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3160                 if (ASIC_IS_DCE3(rdev)) {
3161                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3162                         tmp |= DC_HPDx_INT_ACK;
3163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3164                 } else {
3165                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3166                         tmp |= DC_HPDx_INT_ACK;
3167                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3168                 }
3169         }
3170         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3171                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3172                 tmp |= DC_HPDx_INT_ACK;
3173                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3174         }
3175         if (ASIC_IS_DCE32(rdev)) {
3176                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3177                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3178                         tmp |= DC_HPDx_INT_ACK;
3179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3180                 }
3181                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3182                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3183                         tmp |= DC_HPDx_INT_ACK;
3184                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3185                 }
3186         }
3187         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3188                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3189         }
3190         if (ASIC_IS_DCE3(rdev)) {
3191                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3192                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3193                 }
3194         } else {
3195                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3196                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3197                 }
3198         }
3199 }
3200
3201 void r600_irq_disable(struct radeon_device *rdev)
3202 {
3203         r600_disable_interrupts(rdev);
3204         /* Wait and acknowledge irq */
3205         mdelay(1);
3206         r600_irq_ack(rdev);
3207         r600_disable_interrupt_state(rdev);
3208 }
3209
3210 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3211 {
3212         u32 wptr, tmp;
3213
3214         if (rdev->wb.enabled)
3215                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3216         else
3217                 wptr = RREG32(IH_RB_WPTR);
3218
3219         if (wptr & RB_OVERFLOW) {
3220                 /* When a ring buffer overflow happen start parsing interrupt
3221                  * from the last not overwritten vector (wptr + 16). Hopefully
3222                  * this should allow us to catchup.
3223                  */
3224                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3225                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3226                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3227                 tmp = RREG32(IH_RB_CNTL);
3228                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3229                 WREG32(IH_RB_CNTL, tmp);
3230         }
3231         return (wptr & rdev->ih.ptr_mask);
3232 }
3233
3234 /*        r600 IV Ring
3235  * Each IV ring entry is 128 bits:
3236  * [7:0]    - interrupt source id
3237  * [31:8]   - reserved
3238  * [59:32]  - interrupt source data
3239  * [127:60]  - reserved
3240  *
3241  * The basic interrupt vector entries
3242  * are decoded as follows:
3243  * src_id  src_data  description
3244  *      1         0  D1 Vblank
3245  *      1         1  D1 Vline
3246  *      5         0  D2 Vblank
3247  *      5         1  D2 Vline
3248  *     19         0  FP Hot plug detection A
3249  *     19         1  FP Hot plug detection B
3250  *     19         2  DAC A auto-detection
3251  *     19         3  DAC B auto-detection
3252  *     21         4  HDMI block A
3253  *     21         5  HDMI block B
3254  *    176         -  CP_INT RB
3255  *    177         -  CP_INT IB1
3256  *    178         -  CP_INT IB2
3257  *    181         -  EOP Interrupt
3258  *    233         -  GUI Idle
3259  *
3260  * Note, these are based on r600 and may need to be
3261  * adjusted or added to on newer asics
3262  */
3263
3264 int r600_irq_process(struct radeon_device *rdev)
3265 {
3266         u32 wptr = r600_get_ih_wptr(rdev);
3267         u32 rptr = rdev->ih.rptr;
3268         u32 src_id, src_data;
3269         u32 ring_index;
3270         unsigned long flags;
3271         bool queue_hotplug = false;
3272
3273         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3274         if (!rdev->ih.enabled)
3275                 return IRQ_NONE;
3276
3277         spin_lock_irqsave(&rdev->ih.lock, flags);
3278
3279         if (rptr == wptr) {
3280                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3281                 return IRQ_NONE;
3282         }
3283         if (rdev->shutdown) {
3284                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3285                 return IRQ_NONE;
3286         }
3287
3288 restart_ih:
3289         /* display interrupts */
3290         r600_irq_ack(rdev);
3291
3292         rdev->ih.wptr = wptr;
3293         while (rptr != wptr) {
3294                 /* wptr/rptr are in bytes! */
3295                 ring_index = rptr / 4;
3296                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3297                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3298
3299                 switch (src_id) {
3300                 case 1: /* D1 vblank/vline */
3301                         switch (src_data) {
3302                         case 0: /* D1 vblank */
3303                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3304                                         if (rdev->irq.crtc_vblank_int[0]) {
3305                                                 drm_handle_vblank(rdev->ddev, 0);
3306                                                 rdev->pm.vblank_sync = true;
3307                                                 wake_up(&rdev->irq.vblank_queue);
3308                                         }
3309                                         if (rdev->irq.pflip[0])
3310                                                 radeon_crtc_handle_flip(rdev, 0);
3311                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3312                                         DRM_DEBUG("IH: D1 vblank\n");
3313                                 }
3314                                 break;
3315                         case 1: /* D1 vline */
3316                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3317                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3318                                         DRM_DEBUG("IH: D1 vline\n");
3319                                 }
3320                                 break;
3321                         default:
3322                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3323                                 break;
3324                         }
3325                         break;
3326                 case 5: /* D2 vblank/vline */
3327                         switch (src_data) {
3328                         case 0: /* D2 vblank */
3329                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3330                                         if (rdev->irq.crtc_vblank_int[1]) {
3331                                                 drm_handle_vblank(rdev->ddev, 1);
3332                                                 rdev->pm.vblank_sync = true;
3333                                                 wake_up(&rdev->irq.vblank_queue);
3334                                         }
3335                                         if (rdev->irq.pflip[1])
3336                                                 radeon_crtc_handle_flip(rdev, 1);
3337                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3338                                         DRM_DEBUG("IH: D2 vblank\n");
3339                                 }
3340                                 break;
3341                         case 1: /* D1 vline */
3342                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3343                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3344                                         DRM_DEBUG("IH: D2 vline\n");
3345                                 }
3346                                 break;
3347                         default:
3348                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3349                                 break;
3350                         }
3351                         break;
3352                 case 19: /* HPD/DAC hotplug */
3353                         switch (src_data) {
3354                         case 0:
3355                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3356                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3357                                         queue_hotplug = true;
3358                                         DRM_DEBUG("IH: HPD1\n");
3359                                 }
3360                                 break;
3361                         case 1:
3362                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3363                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3364                                         queue_hotplug = true;
3365                                         DRM_DEBUG("IH: HPD2\n");
3366                                 }
3367                                 break;
3368                         case 4:
3369                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3370                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3371                                         queue_hotplug = true;
3372                                         DRM_DEBUG("IH: HPD3\n");
3373                                 }
3374                                 break;
3375                         case 5:
3376                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3377                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3378                                         queue_hotplug = true;
3379                                         DRM_DEBUG("IH: HPD4\n");
3380                                 }
3381                                 break;
3382                         case 10:
3383                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3384                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3385                                         queue_hotplug = true;
3386                                         DRM_DEBUG("IH: HPD5\n");
3387                                 }
3388                                 break;
3389                         case 12:
3390                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3391                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3392                                         queue_hotplug = true;
3393                                         DRM_DEBUG("IH: HPD6\n");
3394                                 }
3395                                 break;
3396                         default:
3397                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3398                                 break;
3399                         }
3400                         break;
3401                 case 21: /* HDMI */
3402                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3403                         r600_audio_schedule_polling(rdev);
3404                         break;
3405                 case 176: /* CP_INT in ring buffer */
3406                 case 177: /* CP_INT in IB1 */
3407                 case 178: /* CP_INT in IB2 */
3408                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3409                         radeon_fence_process(rdev);
3410                         break;
3411                 case 181: /* CP EOP event */
3412                         DRM_DEBUG("IH: CP EOP\n");
3413                         radeon_fence_process(rdev);
3414                         break;
3415                 case 233: /* GUI IDLE */
3416                         DRM_DEBUG("IH: CP EOP\n");
3417                         rdev->pm.gui_idle = true;
3418                         wake_up(&rdev->irq.idle_queue);
3419                         break;
3420                 default:
3421                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3422                         break;
3423                 }
3424
3425                 /* wptr/rptr are in bytes! */
3426                 rptr += 16;
3427                 rptr &= rdev->ih.ptr_mask;
3428         }
3429         /* make sure wptr hasn't changed while processing */
3430         wptr = r600_get_ih_wptr(rdev);
3431         if (wptr != rdev->ih.wptr)
3432                 goto restart_ih;
3433         if (queue_hotplug)
3434                 queue_work(rdev->wq, &rdev->hotplug_work);
3435         rdev->ih.rptr = rptr;
3436         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3437         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3438         return IRQ_HANDLED;
3439 }
3440
3441 /*
3442  * Debugfs info
3443  */
3444 #if defined(CONFIG_DEBUG_FS)
3445
3446 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3447 {
3448         struct drm_info_node *node = (struct drm_info_node *) m->private;
3449         struct drm_device *dev = node->minor->dev;
3450         struct radeon_device *rdev = dev->dev_private;
3451         unsigned count, i, j;
3452
3453         radeon_ring_free_size(rdev);
3454         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3455         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3456         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3457         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3458         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3459         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3460         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3461         seq_printf(m, "%u dwords in ring\n", count);
3462         i = rdev->cp.rptr;
3463         for (j = 0; j <= count; j++) {
3464                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3465                 i = (i + 1) & rdev->cp.ptr_mask;
3466         }
3467         return 0;
3468 }
3469
3470 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3471 {
3472         struct drm_info_node *node = (struct drm_info_node *) m->private;
3473         struct drm_device *dev = node->minor->dev;
3474         struct radeon_device *rdev = dev->dev_private;
3475
3476         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3477         DREG32_SYS(m, rdev, VM_L2_STATUS);
3478         return 0;
3479 }
3480
3481 static struct drm_info_list r600_mc_info_list[] = {
3482         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3483         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3484 };
3485 #endif
3486
3487 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3488 {
3489 #if defined(CONFIG_DEBUG_FS)
3490         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3491 #else
3492         return 0;
3493 #endif
3494 }
3495
3496 /**
3497  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3498  * rdev: radeon device structure
3499  * bo: buffer object struct which userspace is waiting for idle
3500  *
3501  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3502  * through ring buffer, this leads to corruption in rendering, see
3503  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3504  * directly perform HDP flush by writing register through MMIO.
3505  */
3506 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3507 {
3508         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3509          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
3510          */
3511         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3512             rdev->vram_scratch.ptr) {
3513                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3514                 u32 tmp;
3515
3516                 WREG32(HDP_DEBUG1, 0);
3517                 tmp = readl((void __iomem *)ptr);
3518         } else
3519                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3520 }