2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
34 #include "radeon_mode.h"
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
80 bool connected = false;
82 if (ASIC_IS_DCE3(rdev)) {
85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134 enum radeon_hpd_id hpd)
137 bool connected = r600_hpd_sense(rdev, hpd);
139 if (ASIC_IS_DCE3(rdev)) {
142 tmp = RREG32(DC_HPD1_INT_CONTROL);
144 tmp &= ~DC_HPDx_INT_POLARITY;
146 tmp |= DC_HPDx_INT_POLARITY;
147 WREG32(DC_HPD1_INT_CONTROL, tmp);
150 tmp = RREG32(DC_HPD2_INT_CONTROL);
152 tmp &= ~DC_HPDx_INT_POLARITY;
154 tmp |= DC_HPDx_INT_POLARITY;
155 WREG32(DC_HPD2_INT_CONTROL, tmp);
158 tmp = RREG32(DC_HPD3_INT_CONTROL);
160 tmp &= ~DC_HPDx_INT_POLARITY;
162 tmp |= DC_HPDx_INT_POLARITY;
163 WREG32(DC_HPD3_INT_CONTROL, tmp);
166 tmp = RREG32(DC_HPD4_INT_CONTROL);
168 tmp &= ~DC_HPDx_INT_POLARITY;
170 tmp |= DC_HPDx_INT_POLARITY;
171 WREG32(DC_HPD4_INT_CONTROL, tmp);
174 tmp = RREG32(DC_HPD5_INT_CONTROL);
176 tmp &= ~DC_HPDx_INT_POLARITY;
178 tmp |= DC_HPDx_INT_POLARITY;
179 WREG32(DC_HPD5_INT_CONTROL, tmp);
183 tmp = RREG32(DC_HPD6_INT_CONTROL);
185 tmp &= ~DC_HPDx_INT_POLARITY;
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD6_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
225 void r600_hpd_init(struct radeon_device *rdev)
227 struct drm_device *dev = rdev->ddev;
228 struct drm_connector *connector;
230 if (ASIC_IS_DCE3(rdev)) {
231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev))
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
239 WREG32(DC_HPD1_CONTROL, tmp);
240 rdev->irq.hpd[0] = true;
243 WREG32(DC_HPD2_CONTROL, tmp);
244 rdev->irq.hpd[1] = true;
247 WREG32(DC_HPD3_CONTROL, tmp);
248 rdev->irq.hpd[2] = true;
251 WREG32(DC_HPD4_CONTROL, tmp);
252 rdev->irq.hpd[3] = true;
256 WREG32(DC_HPD5_CONTROL, tmp);
257 rdev->irq.hpd[4] = true;
260 WREG32(DC_HPD6_CONTROL, tmp);
261 rdev->irq.hpd[5] = true;
268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270 switch (radeon_connector->hpd.hpd) {
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273 rdev->irq.hpd[0] = true;
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277 rdev->irq.hpd[1] = true;
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281 rdev->irq.hpd[2] = true;
288 if (rdev->irq.installed)
292 void r600_hpd_fini(struct radeon_device *rdev)
294 struct drm_device *dev = rdev->ddev;
295 struct drm_connector *connector;
297 if (ASIC_IS_DCE3(rdev)) {
298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300 switch (radeon_connector->hpd.hpd) {
302 WREG32(DC_HPD1_CONTROL, 0);
303 rdev->irq.hpd[0] = false;
306 WREG32(DC_HPD2_CONTROL, 0);
307 rdev->irq.hpd[1] = false;
310 WREG32(DC_HPD3_CONTROL, 0);
311 rdev->irq.hpd[2] = false;
314 WREG32(DC_HPD4_CONTROL, 0);
315 rdev->irq.hpd[3] = false;
319 WREG32(DC_HPD5_CONTROL, 0);
320 rdev->irq.hpd[4] = false;
323 WREG32(DC_HPD6_CONTROL, 0);
324 rdev->irq.hpd[5] = false;
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
335 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336 rdev->irq.hpd[0] = false;
339 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340 rdev->irq.hpd[1] = false;
343 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344 rdev->irq.hpd[2] = false;
356 int r600_gart_clear_page(struct radeon_device *rdev, int i)
358 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
361 if (i < 0 || i > rdev->gart.num_gpu_pages)
364 writeq(pte, ((void __iomem *)ptr) + (i * 8));
368 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
373 /* flush hdp cache so updates hit vram */
374 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
376 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
377 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
378 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
379 for (i = 0; i < rdev->usec_timeout; i++) {
381 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
382 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
384 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
394 int r600_pcie_gart_init(struct radeon_device *rdev)
398 if (rdev->gart.table.vram.robj) {
399 WARN(1, "R600 PCIE GART already initialized.\n");
402 /* Initialize common gart structure */
403 r = radeon_gart_init(rdev);
406 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
407 return radeon_gart_table_vram_alloc(rdev);
410 int r600_pcie_gart_enable(struct radeon_device *rdev)
415 if (rdev->gart.table.vram.robj == NULL) {
416 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
419 r = radeon_gart_table_vram_pin(rdev);
422 radeon_gart_restore(rdev);
425 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
426 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
427 EFFECTIVE_L2_QUEUE_SIZE(7));
428 WREG32(VM_L2_CNTL2, 0);
429 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
430 /* Setup TLB control */
431 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
432 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
433 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
434 ENABLE_WAIT_L2_QUERY;
435 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
436 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
437 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
438 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
439 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
440 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
441 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
442 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
443 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
444 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
445 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
446 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
447 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
448 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
449 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
450 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
451 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
452 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
453 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
454 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
455 (u32)(rdev->dummy_page.addr >> 12));
456 for (i = 1; i < 7; i++)
457 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
459 r600_pcie_gart_tlb_flush(rdev);
460 rdev->gart.ready = true;
464 void r600_pcie_gart_disable(struct radeon_device *rdev)
469 /* Disable all tables */
470 for (i = 0; i < 7; i++)
471 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
473 /* Disable L2 cache */
474 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
475 EFFECTIVE_L2_QUEUE_SIZE(7));
476 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
477 /* Setup L1 TLB control */
478 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
479 ENABLE_WAIT_L2_QUERY;
480 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
482 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
483 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
484 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
485 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
486 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
487 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
488 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
489 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
490 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
491 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
492 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
493 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
494 if (rdev->gart.table.vram.robj) {
495 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
496 if (likely(r == 0)) {
497 radeon_bo_kunmap(rdev->gart.table.vram.robj);
498 radeon_bo_unpin(rdev->gart.table.vram.robj);
499 radeon_bo_unreserve(rdev->gart.table.vram.robj);
504 void r600_pcie_gart_fini(struct radeon_device *rdev)
506 r600_pcie_gart_disable(rdev);
507 radeon_gart_table_vram_free(rdev);
508 radeon_gart_fini(rdev);
511 void r600_agp_enable(struct radeon_device *rdev)
517 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
518 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
519 EFFECTIVE_L2_QUEUE_SIZE(7));
520 WREG32(VM_L2_CNTL2, 0);
521 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
522 /* Setup TLB control */
523 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
524 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
525 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
526 ENABLE_WAIT_L2_QUERY;
527 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
528 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
529 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
530 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
531 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
532 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
533 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
534 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
535 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
536 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
537 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
538 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
539 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
540 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
541 for (i = 0; i < 7; i++)
542 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
545 int r600_mc_wait_for_idle(struct radeon_device *rdev)
550 for (i = 0; i < rdev->usec_timeout; i++) {
552 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
560 static void r600_mc_program(struct radeon_device *rdev)
562 struct rv515_mc_save save;
567 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
568 WREG32((0x2c14 + j), 0x00000000);
569 WREG32((0x2c18 + j), 0x00000000);
570 WREG32((0x2c1c + j), 0x00000000);
571 WREG32((0x2c20 + j), 0x00000000);
572 WREG32((0x2c24 + j), 0x00000000);
574 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
576 rv515_mc_stop(rdev, &save);
577 if (r600_mc_wait_for_idle(rdev)) {
578 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
580 /* Lockout access through VGA aperture (doesn't exist before R600) */
581 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
582 /* Update configuration */
583 if (rdev->flags & RADEON_IS_AGP) {
584 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
585 /* VRAM before AGP */
586 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
587 rdev->mc.vram_start >> 12);
588 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
589 rdev->mc.gtt_end >> 12);
592 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
593 rdev->mc.gtt_start >> 12);
594 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
595 rdev->mc.vram_end >> 12);
598 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
599 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
601 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
602 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
603 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
604 WREG32(MC_VM_FB_LOCATION, tmp);
605 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
606 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
607 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
608 if (rdev->flags & RADEON_IS_AGP) {
609 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
610 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
611 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
613 WREG32(MC_VM_AGP_BASE, 0);
614 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
615 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
617 if (r600_mc_wait_for_idle(rdev)) {
618 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
620 rv515_mc_resume(rdev, &save);
621 /* we need to own VRAM, so turn off the VGA renderer here
622 * to stop it overwriting our objects */
623 rv515_vga_render_disable(rdev);
626 int r600_mc_init(struct radeon_device *rdev)
630 int chansize, numchan;
632 /* Get VRAM informations */
633 rdev->mc.vram_is_ddr = true;
634 tmp = RREG32(RAMCFG);
635 if (tmp & CHANSIZE_OVERRIDE) {
637 } else if (tmp & CHANSIZE_MASK) {
643 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
658 rdev->mc.vram_width = numchan * chansize;
659 /* Could aper size report 0 ? */
660 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
661 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
662 /* Setup GPU memory space */
663 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
664 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
666 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
667 rdev->mc.mc_vram_size = rdev->mc.aper_size;
669 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
670 rdev->mc.real_vram_size = rdev->mc.aper_size;
672 if (rdev->flags & RADEON_IS_AGP) {
673 /* gtt_size is setup by radeon_agp_init */
674 rdev->mc.gtt_location = rdev->mc.agp_base;
675 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
676 /* Try to put vram before or after AGP because we
677 * we want SYSTEM_APERTURE to cover both VRAM and
678 * AGP so that GPU can catch out of VRAM/AGP access
680 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
681 /* Enought place before */
682 rdev->mc.vram_location = rdev->mc.gtt_location -
683 rdev->mc.mc_vram_size;
684 } else if (tmp > rdev->mc.mc_vram_size) {
685 /* Enought place after */
686 rdev->mc.vram_location = rdev->mc.gtt_location +
689 /* Try to setup VRAM then AGP might not
690 * not work on some card
692 rdev->mc.vram_location = 0x00000000UL;
693 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
696 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
697 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
699 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
700 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
701 /* Enough place after vram */
702 rdev->mc.gtt_location = tmp;
703 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
704 /* Enough place before vram */
705 rdev->mc.gtt_location = 0;
707 /* Not enough place after or before shrink
710 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
711 rdev->mc.gtt_location = 0;
712 rdev->mc.gtt_size = rdev->mc.vram_location;
714 rdev->mc.gtt_location = tmp;
715 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
718 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
720 rdev->mc.vram_start = rdev->mc.vram_location;
721 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
722 rdev->mc.gtt_start = rdev->mc.gtt_location;
723 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
724 /* FIXME: we should enforce default clock in case GPU is not in
727 a.full = rfixed_const(100);
728 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
729 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
731 if (rdev->flags & RADEON_IS_IGP)
732 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
737 /* We doesn't check that the GPU really needs a reset we simply do the
738 * reset, it's up to the caller to determine if the GPU needs one. We
739 * might add an helper function to check that.
741 int r600_gpu_soft_reset(struct radeon_device *rdev)
743 struct rv515_mc_save save;
744 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
745 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
746 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
747 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
748 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
749 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
750 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
751 S_008010_GUI_ACTIVE(1);
752 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
753 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
754 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
755 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
756 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
757 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
758 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
759 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
763 dev_info(rdev->dev, "GPU softreset \n");
764 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
765 RREG32(R_008010_GRBM_STATUS));
766 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
767 RREG32(R_008014_GRBM_STATUS2));
768 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
769 RREG32(R_000E50_SRBM_STATUS));
770 rv515_mc_stop(rdev, &save);
771 if (r600_mc_wait_for_idle(rdev)) {
772 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
774 /* Disable CP parsing/prefetching */
775 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
776 /* Check if any of the rendering block is busy and reset it */
777 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
778 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
779 tmp = S_008020_SOFT_RESET_CR(1) |
780 S_008020_SOFT_RESET_DB(1) |
781 S_008020_SOFT_RESET_CB(1) |
782 S_008020_SOFT_RESET_PA(1) |
783 S_008020_SOFT_RESET_SC(1) |
784 S_008020_SOFT_RESET_SMX(1) |
785 S_008020_SOFT_RESET_SPI(1) |
786 S_008020_SOFT_RESET_SX(1) |
787 S_008020_SOFT_RESET_SH(1) |
788 S_008020_SOFT_RESET_TC(1) |
789 S_008020_SOFT_RESET_TA(1) |
790 S_008020_SOFT_RESET_VC(1) |
791 S_008020_SOFT_RESET_VGT(1);
792 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
793 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
794 (void)RREG32(R_008020_GRBM_SOFT_RESET);
796 WREG32(R_008020_GRBM_SOFT_RESET, 0);
797 (void)RREG32(R_008020_GRBM_SOFT_RESET);
799 /* Reset CP (we always reset CP) */
800 tmp = S_008020_SOFT_RESET_CP(1);
801 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
802 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
803 (void)RREG32(R_008020_GRBM_SOFT_RESET);
805 WREG32(R_008020_GRBM_SOFT_RESET, 0);
806 (void)RREG32(R_008020_GRBM_SOFT_RESET);
807 /* Reset others GPU block if necessary */
808 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
809 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
810 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
811 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
812 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
813 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
814 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
816 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
820 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
822 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
824 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
825 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
826 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
827 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
828 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
829 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
830 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
831 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
832 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
833 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
836 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
837 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
838 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
839 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
841 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
842 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
843 /* Wait a little for things to settle down */
845 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
846 RREG32(R_008010_GRBM_STATUS));
847 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
848 RREG32(R_008014_GRBM_STATUS2));
849 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
850 RREG32(R_000E50_SRBM_STATUS));
851 /* After reset we need to reinit the asic as GPU often endup in an
854 atom_asic_init(rdev->mode_info.atom_context);
855 rv515_mc_resume(rdev, &save);
859 int r600_gpu_reset(struct radeon_device *rdev)
861 return r600_gpu_soft_reset(rdev);
864 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
866 u32 backend_disable_mask)
869 u32 enabled_backends_mask;
870 u32 enabled_backends_count;
872 u32 swizzle_pipe[R6XX_MAX_PIPES];
876 if (num_tile_pipes > R6XX_MAX_PIPES)
877 num_tile_pipes = R6XX_MAX_PIPES;
878 if (num_tile_pipes < 1)
880 if (num_backends > R6XX_MAX_BACKENDS)
881 num_backends = R6XX_MAX_BACKENDS;
882 if (num_backends < 1)
885 enabled_backends_mask = 0;
886 enabled_backends_count = 0;
887 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
888 if (((backend_disable_mask >> i) & 1) == 0) {
889 enabled_backends_mask |= (1 << i);
890 ++enabled_backends_count;
892 if (enabled_backends_count == num_backends)
896 if (enabled_backends_count == 0) {
897 enabled_backends_mask = 1;
898 enabled_backends_count = 1;
901 if (enabled_backends_count != num_backends)
902 num_backends = enabled_backends_count;
904 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
905 switch (num_tile_pipes) {
961 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
962 while (((1 << cur_backend) & enabled_backends_mask) == 0)
963 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
965 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
967 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
973 int r600_count_pipe_bits(uint32_t val)
977 for (i = 0; i < 32; i++) {
984 void r600_gpu_init(struct radeon_device *rdev)
991 u32 sq_gpr_resource_mgmt_1 = 0;
992 u32 sq_gpr_resource_mgmt_2 = 0;
993 u32 sq_thread_resource_mgmt = 0;
994 u32 sq_stack_resource_mgmt_1 = 0;
995 u32 sq_stack_resource_mgmt_2 = 0;
997 /* FIXME: implement */
998 switch (rdev->family) {
1000 rdev->config.r600.max_pipes = 4;
1001 rdev->config.r600.max_tile_pipes = 8;
1002 rdev->config.r600.max_simds = 4;
1003 rdev->config.r600.max_backends = 4;
1004 rdev->config.r600.max_gprs = 256;
1005 rdev->config.r600.max_threads = 192;
1006 rdev->config.r600.max_stack_entries = 256;
1007 rdev->config.r600.max_hw_contexts = 8;
1008 rdev->config.r600.max_gs_threads = 16;
1009 rdev->config.r600.sx_max_export_size = 128;
1010 rdev->config.r600.sx_max_export_pos_size = 16;
1011 rdev->config.r600.sx_max_export_smx_size = 128;
1012 rdev->config.r600.sq_num_cf_insts = 2;
1016 rdev->config.r600.max_pipes = 2;
1017 rdev->config.r600.max_tile_pipes = 2;
1018 rdev->config.r600.max_simds = 3;
1019 rdev->config.r600.max_backends = 1;
1020 rdev->config.r600.max_gprs = 128;
1021 rdev->config.r600.max_threads = 192;
1022 rdev->config.r600.max_stack_entries = 128;
1023 rdev->config.r600.max_hw_contexts = 8;
1024 rdev->config.r600.max_gs_threads = 4;
1025 rdev->config.r600.sx_max_export_size = 128;
1026 rdev->config.r600.sx_max_export_pos_size = 16;
1027 rdev->config.r600.sx_max_export_smx_size = 128;
1028 rdev->config.r600.sq_num_cf_insts = 2;
1034 rdev->config.r600.max_pipes = 1;
1035 rdev->config.r600.max_tile_pipes = 1;
1036 rdev->config.r600.max_simds = 2;
1037 rdev->config.r600.max_backends = 1;
1038 rdev->config.r600.max_gprs = 128;
1039 rdev->config.r600.max_threads = 192;
1040 rdev->config.r600.max_stack_entries = 128;
1041 rdev->config.r600.max_hw_contexts = 4;
1042 rdev->config.r600.max_gs_threads = 4;
1043 rdev->config.r600.sx_max_export_size = 128;
1044 rdev->config.r600.sx_max_export_pos_size = 16;
1045 rdev->config.r600.sx_max_export_smx_size = 128;
1046 rdev->config.r600.sq_num_cf_insts = 1;
1049 rdev->config.r600.max_pipes = 4;
1050 rdev->config.r600.max_tile_pipes = 4;
1051 rdev->config.r600.max_simds = 4;
1052 rdev->config.r600.max_backends = 4;
1053 rdev->config.r600.max_gprs = 192;
1054 rdev->config.r600.max_threads = 192;
1055 rdev->config.r600.max_stack_entries = 256;
1056 rdev->config.r600.max_hw_contexts = 8;
1057 rdev->config.r600.max_gs_threads = 16;
1058 rdev->config.r600.sx_max_export_size = 128;
1059 rdev->config.r600.sx_max_export_pos_size = 16;
1060 rdev->config.r600.sx_max_export_smx_size = 128;
1061 rdev->config.r600.sq_num_cf_insts = 2;
1067 /* Initialize HDP */
1068 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1069 WREG32((0x2c14 + j), 0x00000000);
1070 WREG32((0x2c18 + j), 0x00000000);
1071 WREG32((0x2c1c + j), 0x00000000);
1072 WREG32((0x2c20 + j), 0x00000000);
1073 WREG32((0x2c24 + j), 0x00000000);
1076 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1080 ramcfg = RREG32(RAMCFG);
1081 switch (rdev->config.r600.max_tile_pipes) {
1083 tiling_config |= PIPE_TILING(0);
1084 rdev->config.r600.tiling_npipes = 1;
1087 tiling_config |= PIPE_TILING(1);
1088 rdev->config.r600.tiling_npipes = 2;
1091 tiling_config |= PIPE_TILING(2);
1092 rdev->config.r600.tiling_npipes = 4;
1095 tiling_config |= PIPE_TILING(3);
1096 rdev->config.r600.tiling_npipes = 8;
1101 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1102 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1103 tiling_config |= GROUP_SIZE(0);
1104 rdev->config.r600.tiling_group_size = 256;
1105 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1107 tiling_config |= ROW_TILING(3);
1108 tiling_config |= SAMPLE_SPLIT(3);
1110 tiling_config |= ROW_TILING(tmp);
1111 tiling_config |= SAMPLE_SPLIT(tmp);
1113 tiling_config |= BANK_SWAPS(1);
1114 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1115 rdev->config.r600.max_backends,
1116 (0xff << rdev->config.r600.max_backends) & 0xff);
1117 tiling_config |= BACKEND_MAP(tmp);
1118 WREG32(GB_TILING_CONFIG, tiling_config);
1119 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1120 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1122 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1123 WREG32(CC_RB_BACKEND_DISABLE, tmp);
1126 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1127 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1128 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1129 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1131 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1132 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1133 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1135 /* Setup some CP states */
1136 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1137 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1139 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1140 SYNC_WALKER | SYNC_ALIGNER));
1141 /* Setup various GPU states */
1142 if (rdev->family == CHIP_RV670)
1143 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1145 tmp = RREG32(SX_DEBUG_1);
1146 tmp |= SMX_EVENT_RELEASE;
1147 if ((rdev->family > CHIP_R600))
1148 tmp |= ENABLE_NEW_SMX_ADDRESS;
1149 WREG32(SX_DEBUG_1, tmp);
1151 if (((rdev->family) == CHIP_R600) ||
1152 ((rdev->family) == CHIP_RV630) ||
1153 ((rdev->family) == CHIP_RV610) ||
1154 ((rdev->family) == CHIP_RV620) ||
1155 ((rdev->family) == CHIP_RS780) ||
1156 ((rdev->family) == CHIP_RS880)) {
1157 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1159 WREG32(DB_DEBUG, 0);
1161 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1162 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1164 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1165 WREG32(VGT_NUM_INSTANCES, 0);
1167 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1168 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1170 tmp = RREG32(SQ_MS_FIFO_SIZES);
1171 if (((rdev->family) == CHIP_RV610) ||
1172 ((rdev->family) == CHIP_RV620) ||
1173 ((rdev->family) == CHIP_RS780) ||
1174 ((rdev->family) == CHIP_RS880)) {
1175 tmp = (CACHE_FIFO_SIZE(0xa) |
1176 FETCH_FIFO_HIWATER(0xa) |
1177 DONE_FIFO_HIWATER(0xe0) |
1178 ALU_UPDATE_FIFO_HIWATER(0x8));
1179 } else if (((rdev->family) == CHIP_R600) ||
1180 ((rdev->family) == CHIP_RV630)) {
1181 tmp &= ~DONE_FIFO_HIWATER(0xff);
1182 tmp |= DONE_FIFO_HIWATER(0x4);
1184 WREG32(SQ_MS_FIFO_SIZES, tmp);
1186 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1187 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1189 sq_config = RREG32(SQ_CONFIG);
1190 sq_config &= ~(PS_PRIO(3) |
1194 sq_config |= (DX9_CONSTS |
1201 if ((rdev->family) == CHIP_R600) {
1202 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1204 NUM_CLAUSE_TEMP_GPRS(4));
1205 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1207 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1208 NUM_VS_THREADS(48) |
1211 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1212 NUM_VS_STACK_ENTRIES(128));
1213 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1214 NUM_ES_STACK_ENTRIES(0));
1215 } else if (((rdev->family) == CHIP_RV610) ||
1216 ((rdev->family) == CHIP_RV620) ||
1217 ((rdev->family) == CHIP_RS780) ||
1218 ((rdev->family) == CHIP_RS880)) {
1219 /* no vertex cache */
1220 sq_config &= ~VC_ENABLE;
1222 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1224 NUM_CLAUSE_TEMP_GPRS(2));
1225 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1227 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1228 NUM_VS_THREADS(78) |
1230 NUM_ES_THREADS(31));
1231 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1232 NUM_VS_STACK_ENTRIES(40));
1233 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1234 NUM_ES_STACK_ENTRIES(16));
1235 } else if (((rdev->family) == CHIP_RV630) ||
1236 ((rdev->family) == CHIP_RV635)) {
1237 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1239 NUM_CLAUSE_TEMP_GPRS(2));
1240 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1242 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1243 NUM_VS_THREADS(78) |
1245 NUM_ES_THREADS(31));
1246 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1247 NUM_VS_STACK_ENTRIES(40));
1248 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1249 NUM_ES_STACK_ENTRIES(16));
1250 } else if ((rdev->family) == CHIP_RV670) {
1251 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1253 NUM_CLAUSE_TEMP_GPRS(2));
1254 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1256 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1257 NUM_VS_THREADS(78) |
1259 NUM_ES_THREADS(31));
1260 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1261 NUM_VS_STACK_ENTRIES(64));
1262 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1263 NUM_ES_STACK_ENTRIES(64));
1266 WREG32(SQ_CONFIG, sq_config);
1267 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1268 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1269 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1270 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1271 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1273 if (((rdev->family) == CHIP_RV610) ||
1274 ((rdev->family) == CHIP_RV620) ||
1275 ((rdev->family) == CHIP_RS780) ||
1276 ((rdev->family) == CHIP_RS880)) {
1277 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1279 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1282 /* More default values. 2D/3D driver should adjust as needed */
1283 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1284 S1_X(0x4) | S1_Y(0xc)));
1285 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1286 S1_X(0x2) | S1_Y(0x2) |
1287 S2_X(0xa) | S2_Y(0x6) |
1288 S3_X(0x6) | S3_Y(0xa)));
1289 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1290 S1_X(0x4) | S1_Y(0xc) |
1291 S2_X(0x1) | S2_Y(0x6) |
1292 S3_X(0xa) | S3_Y(0xe)));
1293 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1294 S5_X(0x0) | S5_Y(0x0) |
1295 S6_X(0xb) | S6_Y(0x4) |
1296 S7_X(0x7) | S7_Y(0x8)));
1298 WREG32(VGT_STRMOUT_EN, 0);
1299 tmp = rdev->config.r600.max_pipes * 16;
1300 switch (rdev->family) {
1316 WREG32(VGT_ES_PER_GS, 128);
1317 WREG32(VGT_GS_PER_ES, tmp);
1318 WREG32(VGT_GS_PER_VS, 2);
1319 WREG32(VGT_GS_VERTEX_REUSE, 16);
1321 /* more default values. 2D/3D driver should adjust as needed */
1322 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1323 WREG32(VGT_STRMOUT_EN, 0);
1325 WREG32(PA_SC_MODE_CNTL, 0);
1326 WREG32(PA_SC_AA_CONFIG, 0);
1327 WREG32(PA_SC_LINE_STIPPLE, 0);
1328 WREG32(SPI_INPUT_Z, 0);
1329 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1330 WREG32(CB_COLOR7_FRAG, 0);
1332 /* Clear render buffer base addresses */
1333 WREG32(CB_COLOR0_BASE, 0);
1334 WREG32(CB_COLOR1_BASE, 0);
1335 WREG32(CB_COLOR2_BASE, 0);
1336 WREG32(CB_COLOR3_BASE, 0);
1337 WREG32(CB_COLOR4_BASE, 0);
1338 WREG32(CB_COLOR5_BASE, 0);
1339 WREG32(CB_COLOR6_BASE, 0);
1340 WREG32(CB_COLOR7_BASE, 0);
1341 WREG32(CB_COLOR7_FRAG, 0);
1343 switch (rdev->family) {
1348 tmp = TC_L2_SIZE(8);
1352 tmp = TC_L2_SIZE(4);
1355 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1358 tmp = TC_L2_SIZE(0);
1361 WREG32(TC_CNTL, tmp);
1363 tmp = RREG32(HDP_HOST_PATH_CNTL);
1364 WREG32(HDP_HOST_PATH_CNTL, tmp);
1366 tmp = RREG32(ARB_POP);
1367 tmp |= ENABLE_TC128;
1368 WREG32(ARB_POP, tmp);
1370 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1371 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1373 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1378 * Indirect registers accessor
1380 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1384 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1385 (void)RREG32(PCIE_PORT_INDEX);
1386 r = RREG32(PCIE_PORT_DATA);
1390 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1392 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1393 (void)RREG32(PCIE_PORT_INDEX);
1394 WREG32(PCIE_PORT_DATA, (v));
1395 (void)RREG32(PCIE_PORT_DATA);
1401 void r600_cp_stop(struct radeon_device *rdev)
1403 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1406 int r600_init_microcode(struct radeon_device *rdev)
1408 struct platform_device *pdev;
1409 const char *chip_name;
1410 const char *rlc_chip_name;
1411 size_t pfp_req_size, me_req_size, rlc_req_size;
1417 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1420 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1424 switch (rdev->family) {
1427 rlc_chip_name = "R600";
1430 chip_name = "RV610";
1431 rlc_chip_name = "R600";
1434 chip_name = "RV630";
1435 rlc_chip_name = "R600";
1438 chip_name = "RV620";
1439 rlc_chip_name = "R600";
1442 chip_name = "RV635";
1443 rlc_chip_name = "R600";
1446 chip_name = "RV670";
1447 rlc_chip_name = "R600";
1451 chip_name = "RS780";
1452 rlc_chip_name = "R600";
1455 chip_name = "RV770";
1456 rlc_chip_name = "R700";
1460 chip_name = "RV730";
1461 rlc_chip_name = "R700";
1464 chip_name = "RV710";
1465 rlc_chip_name = "R700";
1470 if (rdev->family >= CHIP_RV770) {
1471 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1472 me_req_size = R700_PM4_UCODE_SIZE * 4;
1473 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1475 pfp_req_size = PFP_UCODE_SIZE * 4;
1476 me_req_size = PM4_UCODE_SIZE * 12;
1477 rlc_req_size = RLC_UCODE_SIZE * 4;
1480 DRM_INFO("Loading %s Microcode\n", chip_name);
1482 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1483 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1486 if (rdev->pfp_fw->size != pfp_req_size) {
1488 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1489 rdev->pfp_fw->size, fw_name);
1494 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1495 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1498 if (rdev->me_fw->size != me_req_size) {
1500 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1501 rdev->me_fw->size, fw_name);
1505 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1506 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1509 if (rdev->rlc_fw->size != rlc_req_size) {
1511 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1512 rdev->rlc_fw->size, fw_name);
1517 platform_device_unregister(pdev);
1522 "r600_cp: Failed to load firmware \"%s\"\n",
1524 release_firmware(rdev->pfp_fw);
1525 rdev->pfp_fw = NULL;
1526 release_firmware(rdev->me_fw);
1528 release_firmware(rdev->rlc_fw);
1529 rdev->rlc_fw = NULL;
1534 static int r600_cp_load_microcode(struct radeon_device *rdev)
1536 const __be32 *fw_data;
1539 if (!rdev->me_fw || !rdev->pfp_fw)
1544 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1547 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1548 RREG32(GRBM_SOFT_RESET);
1550 WREG32(GRBM_SOFT_RESET, 0);
1552 WREG32(CP_ME_RAM_WADDR, 0);
1554 fw_data = (const __be32 *)rdev->me_fw->data;
1555 WREG32(CP_ME_RAM_WADDR, 0);
1556 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1557 WREG32(CP_ME_RAM_DATA,
1558 be32_to_cpup(fw_data++));
1560 fw_data = (const __be32 *)rdev->pfp_fw->data;
1561 WREG32(CP_PFP_UCODE_ADDR, 0);
1562 for (i = 0; i < PFP_UCODE_SIZE; i++)
1563 WREG32(CP_PFP_UCODE_DATA,
1564 be32_to_cpup(fw_data++));
1566 WREG32(CP_PFP_UCODE_ADDR, 0);
1567 WREG32(CP_ME_RAM_WADDR, 0);
1568 WREG32(CP_ME_RAM_RADDR, 0);
1572 int r600_cp_start(struct radeon_device *rdev)
1577 r = radeon_ring_lock(rdev, 7);
1579 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1582 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1583 radeon_ring_write(rdev, 0x1);
1584 if (rdev->family < CHIP_RV770) {
1585 radeon_ring_write(rdev, 0x3);
1586 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1588 radeon_ring_write(rdev, 0x0);
1589 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1591 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1592 radeon_ring_write(rdev, 0);
1593 radeon_ring_write(rdev, 0);
1594 radeon_ring_unlock_commit(rdev);
1597 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1601 int r600_cp_resume(struct radeon_device *rdev)
1608 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1609 RREG32(GRBM_SOFT_RESET);
1611 WREG32(GRBM_SOFT_RESET, 0);
1613 /* Set ring buffer size */
1614 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1615 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1617 tmp |= BUF_SWAP_32BIT;
1619 WREG32(CP_RB_CNTL, tmp);
1620 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1622 /* Set the write pointer delay */
1623 WREG32(CP_RB_WPTR_DELAY, 0);
1625 /* Initialize the ring buffer's read and write pointers */
1626 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1627 WREG32(CP_RB_RPTR_WR, 0);
1628 WREG32(CP_RB_WPTR, 0);
1629 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1630 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1632 WREG32(CP_RB_CNTL, tmp);
1634 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1635 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1637 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1638 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1640 r600_cp_start(rdev);
1641 rdev->cp.ready = true;
1642 r = radeon_ring_test(rdev);
1644 rdev->cp.ready = false;
1650 void r600_cp_commit(struct radeon_device *rdev)
1652 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1653 (void)RREG32(CP_RB_WPTR);
1656 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1660 /* Align ring size */
1661 rb_bufsz = drm_order(ring_size / 8);
1662 ring_size = (1 << (rb_bufsz + 1)) * 4;
1663 rdev->cp.ring_size = ring_size;
1664 rdev->cp.align_mask = 16 - 1;
1667 void r600_cp_fini(struct radeon_device *rdev)
1670 radeon_ring_fini(rdev);
1675 * GPU scratch registers helpers function.
1677 void r600_scratch_init(struct radeon_device *rdev)
1681 rdev->scratch.num_reg = 7;
1682 for (i = 0; i < rdev->scratch.num_reg; i++) {
1683 rdev->scratch.free[i] = true;
1684 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1688 int r600_ring_test(struct radeon_device *rdev)
1695 r = radeon_scratch_get(rdev, &scratch);
1697 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1700 WREG32(scratch, 0xCAFEDEAD);
1701 r = radeon_ring_lock(rdev, 3);
1703 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1704 radeon_scratch_free(rdev, scratch);
1707 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1708 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1709 radeon_ring_write(rdev, 0xDEADBEEF);
1710 radeon_ring_unlock_commit(rdev);
1711 for (i = 0; i < rdev->usec_timeout; i++) {
1712 tmp = RREG32(scratch);
1713 if (tmp == 0xDEADBEEF)
1717 if (i < rdev->usec_timeout) {
1718 DRM_INFO("ring test succeeded in %d usecs\n", i);
1720 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1724 radeon_scratch_free(rdev, scratch);
1728 void r600_wb_disable(struct radeon_device *rdev)
1732 WREG32(SCRATCH_UMSK, 0);
1733 if (rdev->wb.wb_obj) {
1734 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1735 if (unlikely(r != 0))
1737 radeon_bo_kunmap(rdev->wb.wb_obj);
1738 radeon_bo_unpin(rdev->wb.wb_obj);
1739 radeon_bo_unreserve(rdev->wb.wb_obj);
1743 void r600_wb_fini(struct radeon_device *rdev)
1745 r600_wb_disable(rdev);
1746 if (rdev->wb.wb_obj) {
1747 radeon_bo_unref(&rdev->wb.wb_obj);
1749 rdev->wb.wb_obj = NULL;
1753 int r600_wb_enable(struct radeon_device *rdev)
1757 if (rdev->wb.wb_obj == NULL) {
1758 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1759 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1761 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1764 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1765 if (unlikely(r != 0)) {
1769 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1770 &rdev->wb.gpu_addr);
1772 radeon_bo_unreserve(rdev->wb.wb_obj);
1773 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1777 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1778 radeon_bo_unreserve(rdev->wb.wb_obj);
1780 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1785 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1786 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1787 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1788 WREG32(SCRATCH_UMSK, 0xff);
1792 void r600_fence_ring_emit(struct radeon_device *rdev,
1793 struct radeon_fence *fence)
1795 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1797 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1798 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1799 /* wait for 3D idle clean */
1800 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1801 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1802 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1803 /* Emit fence sequence & fire IRQ */
1804 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1805 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1806 radeon_ring_write(rdev, fence->seq);
1807 radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1808 radeon_ring_write(rdev, 1);
1809 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1810 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1811 radeon_ring_write(rdev, RB_INT_STAT);
1814 int r600_copy_blit(struct radeon_device *rdev,
1815 uint64_t src_offset, uint64_t dst_offset,
1816 unsigned num_pages, struct radeon_fence *fence)
1820 mutex_lock(&rdev->r600_blit.mutex);
1821 rdev->r600_blit.vb_ib = NULL;
1822 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1824 if (rdev->r600_blit.vb_ib)
1825 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1826 mutex_unlock(&rdev->r600_blit.mutex);
1829 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1830 r600_blit_done_copy(rdev, fence);
1831 mutex_unlock(&rdev->r600_blit.mutex);
1835 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1836 uint32_t tiling_flags, uint32_t pitch,
1837 uint32_t offset, uint32_t obj_size)
1839 /* FIXME: implement */
1843 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1845 /* FIXME: implement */
1849 bool r600_card_posted(struct radeon_device *rdev)
1853 /* first check CRTCs */
1854 reg = RREG32(D1CRTC_CONTROL) |
1855 RREG32(D2CRTC_CONTROL);
1859 /* then check MEM_SIZE, in case the crtcs are off */
1860 if (RREG32(CONFIG_MEMSIZE))
1866 int r600_startup(struct radeon_device *rdev)
1870 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1871 r = r600_init_microcode(rdev);
1873 DRM_ERROR("Failed to load firmware!\n");
1878 r600_mc_program(rdev);
1879 if (rdev->flags & RADEON_IS_AGP) {
1880 r600_agp_enable(rdev);
1882 r = r600_pcie_gart_enable(rdev);
1886 r600_gpu_init(rdev);
1887 r = r600_blit_init(rdev);
1889 r600_blit_fini(rdev);
1890 rdev->asic->copy = NULL;
1891 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1893 /* pin copy shader into vram */
1894 if (rdev->r600_blit.shader_obj) {
1895 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1896 if (unlikely(r != 0))
1898 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1899 &rdev->r600_blit.shader_gpu_addr);
1900 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1902 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1907 r = r600_irq_init(rdev);
1909 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1910 radeon_irq_kms_fini(rdev);
1915 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1918 r = r600_cp_load_microcode(rdev);
1921 r = r600_cp_resume(rdev);
1924 /* write back buffer are not vital so don't worry about failure */
1925 r600_wb_enable(rdev);
1929 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1933 temp = RREG32(CONFIG_CNTL);
1934 if (state == false) {
1940 WREG32(CONFIG_CNTL, temp);
1943 int r600_resume(struct radeon_device *rdev)
1947 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1948 * posting will perform necessary task to bring back GPU into good
1952 atom_asic_init(rdev->mode_info.atom_context);
1953 /* Initialize clocks */
1954 r = radeon_clocks_init(rdev);
1959 r = r600_startup(rdev);
1961 DRM_ERROR("r600 startup failed on resume\n");
1965 r = r600_ib_test(rdev);
1967 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1973 int r600_suspend(struct radeon_device *rdev)
1977 /* FIXME: we should wait for ring to be empty */
1979 rdev->cp.ready = false;
1980 r600_irq_suspend(rdev);
1981 r600_wb_disable(rdev);
1982 r600_pcie_gart_disable(rdev);
1983 /* unpin shaders bo */
1984 if (rdev->r600_blit.shader_obj) {
1985 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1987 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1988 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1994 /* Plan is to move initialization in that function and use
1995 * helper function so that radeon_device_init pretty much
1996 * do nothing more than calling asic specific function. This
1997 * should also allow to remove a bunch of callback function
2000 int r600_init(struct radeon_device *rdev)
2004 r = radeon_dummy_page_init(rdev);
2007 if (r600_debugfs_mc_info_init(rdev)) {
2008 DRM_ERROR("Failed to register debugfs file for mc !\n");
2010 /* This don't do much */
2011 r = radeon_gem_init(rdev);
2015 if (!radeon_get_bios(rdev)) {
2016 if (ASIC_IS_AVIVO(rdev))
2019 /* Must be an ATOMBIOS */
2020 if (!rdev->is_atom_bios) {
2021 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2024 r = radeon_atombios_init(rdev);
2027 /* Post card if necessary */
2028 if (!r600_card_posted(rdev)) {
2030 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2033 DRM_INFO("GPU not posted. posting now...\n");
2034 atom_asic_init(rdev->mode_info.atom_context);
2036 /* Initialize scratch registers */
2037 r600_scratch_init(rdev);
2038 /* Initialize surface registers */
2039 radeon_surface_init(rdev);
2040 /* Initialize clocks */
2041 radeon_get_clock_info(rdev->ddev);
2042 r = radeon_clocks_init(rdev);
2045 /* Initialize power management */
2046 radeon_pm_init(rdev);
2048 r = radeon_fence_driver_init(rdev);
2051 if (rdev->flags & RADEON_IS_AGP) {
2052 r = radeon_agp_init(rdev);
2054 radeon_agp_disable(rdev);
2056 r = r600_mc_init(rdev);
2059 /* Memory manager */
2060 r = radeon_bo_init(rdev);
2064 r = radeon_irq_kms_init(rdev);
2068 rdev->cp.ring_obj = NULL;
2069 r600_ring_init(rdev, 1024 * 1024);
2071 rdev->ih.ring_obj = NULL;
2072 r600_ih_ring_init(rdev, 64 * 1024);
2074 r = r600_pcie_gart_init(rdev);
2078 rdev->accel_working = true;
2079 r = r600_startup(rdev);
2081 dev_err(rdev->dev, "disabling GPU acceleration\n");
2084 r600_irq_fini(rdev);
2085 radeon_irq_kms_fini(rdev);
2086 r600_pcie_gart_fini(rdev);
2087 rdev->accel_working = false;
2089 if (rdev->accel_working) {
2090 r = radeon_ib_pool_init(rdev);
2092 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2093 rdev->accel_working = false;
2095 r = r600_ib_test(rdev);
2097 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2098 rdev->accel_working = false;
2103 r = r600_audio_init(rdev);
2105 return r; /* TODO error handling */
2109 void r600_fini(struct radeon_device *rdev)
2111 r600_audio_fini(rdev);
2112 r600_blit_fini(rdev);
2115 r600_irq_fini(rdev);
2116 radeon_irq_kms_fini(rdev);
2117 r600_pcie_gart_fini(rdev);
2118 radeon_agp_fini(rdev);
2119 radeon_gem_fini(rdev);
2120 radeon_fence_driver_fini(rdev);
2121 radeon_clocks_fini(rdev);
2122 radeon_bo_fini(rdev);
2123 radeon_atombios_fini(rdev);
2126 radeon_dummy_page_fini(rdev);
2133 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2135 /* FIXME: implement */
2136 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2137 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2138 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2139 radeon_ring_write(rdev, ib->length_dw);
2142 int r600_ib_test(struct radeon_device *rdev)
2144 struct radeon_ib *ib;
2150 r = radeon_scratch_get(rdev, &scratch);
2152 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2155 WREG32(scratch, 0xCAFEDEAD);
2156 r = radeon_ib_get(rdev, &ib);
2158 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2161 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2162 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2163 ib->ptr[2] = 0xDEADBEEF;
2164 ib->ptr[3] = PACKET2(0);
2165 ib->ptr[4] = PACKET2(0);
2166 ib->ptr[5] = PACKET2(0);
2167 ib->ptr[6] = PACKET2(0);
2168 ib->ptr[7] = PACKET2(0);
2169 ib->ptr[8] = PACKET2(0);
2170 ib->ptr[9] = PACKET2(0);
2171 ib->ptr[10] = PACKET2(0);
2172 ib->ptr[11] = PACKET2(0);
2173 ib->ptr[12] = PACKET2(0);
2174 ib->ptr[13] = PACKET2(0);
2175 ib->ptr[14] = PACKET2(0);
2176 ib->ptr[15] = PACKET2(0);
2178 r = radeon_ib_schedule(rdev, ib);
2180 radeon_scratch_free(rdev, scratch);
2181 radeon_ib_free(rdev, &ib);
2182 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2185 r = radeon_fence_wait(ib->fence, false);
2187 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2190 for (i = 0; i < rdev->usec_timeout; i++) {
2191 tmp = RREG32(scratch);
2192 if (tmp == 0xDEADBEEF)
2196 if (i < rdev->usec_timeout) {
2197 DRM_INFO("ib test succeeded in %u usecs\n", i);
2199 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2203 radeon_scratch_free(rdev, scratch);
2204 radeon_ib_free(rdev, &ib);
2211 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2212 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2213 * writing to the ring and the GPU consuming, the GPU writes to the ring
2214 * and host consumes. As the host irq handler processes interrupts, it
2215 * increments the rptr. When the rptr catches up with the wptr, all the
2216 * current interrupts have been processed.
2219 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2223 /* Align ring size */
2224 rb_bufsz = drm_order(ring_size / 4);
2225 ring_size = (1 << rb_bufsz) * 4;
2226 rdev->ih.ring_size = ring_size;
2227 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2231 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2235 /* Allocate ring buffer */
2236 if (rdev->ih.ring_obj == NULL) {
2237 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2239 RADEON_GEM_DOMAIN_GTT,
2240 &rdev->ih.ring_obj);
2242 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2245 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2246 if (unlikely(r != 0))
2248 r = radeon_bo_pin(rdev->ih.ring_obj,
2249 RADEON_GEM_DOMAIN_GTT,
2250 &rdev->ih.gpu_addr);
2252 radeon_bo_unreserve(rdev->ih.ring_obj);
2253 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2256 r = radeon_bo_kmap(rdev->ih.ring_obj,
2257 (void **)&rdev->ih.ring);
2258 radeon_bo_unreserve(rdev->ih.ring_obj);
2260 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2267 static void r600_ih_ring_fini(struct radeon_device *rdev)
2270 if (rdev->ih.ring_obj) {
2271 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2272 if (likely(r == 0)) {
2273 radeon_bo_kunmap(rdev->ih.ring_obj);
2274 radeon_bo_unpin(rdev->ih.ring_obj);
2275 radeon_bo_unreserve(rdev->ih.ring_obj);
2277 radeon_bo_unref(&rdev->ih.ring_obj);
2278 rdev->ih.ring = NULL;
2279 rdev->ih.ring_obj = NULL;
2283 static void r600_rlc_stop(struct radeon_device *rdev)
2286 if (rdev->family >= CHIP_RV770) {
2287 /* r7xx asics need to soft reset RLC before halting */
2288 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2289 RREG32(SRBM_SOFT_RESET);
2291 WREG32(SRBM_SOFT_RESET, 0);
2292 RREG32(SRBM_SOFT_RESET);
2295 WREG32(RLC_CNTL, 0);
2298 static void r600_rlc_start(struct radeon_device *rdev)
2300 WREG32(RLC_CNTL, RLC_ENABLE);
2303 static int r600_rlc_init(struct radeon_device *rdev)
2306 const __be32 *fw_data;
2311 r600_rlc_stop(rdev);
2313 WREG32(RLC_HB_BASE, 0);
2314 WREG32(RLC_HB_CNTL, 0);
2315 WREG32(RLC_HB_RPTR, 0);
2316 WREG32(RLC_HB_WPTR, 0);
2317 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2318 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2319 WREG32(RLC_MC_CNTL, 0);
2320 WREG32(RLC_UCODE_CNTL, 0);
2322 fw_data = (const __be32 *)rdev->rlc_fw->data;
2323 if (rdev->family >= CHIP_RV770) {
2324 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2325 WREG32(RLC_UCODE_ADDR, i);
2326 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2329 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2330 WREG32(RLC_UCODE_ADDR, i);
2331 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2334 WREG32(RLC_UCODE_ADDR, 0);
2336 r600_rlc_start(rdev);
2341 static void r600_enable_interrupts(struct radeon_device *rdev)
2343 u32 ih_cntl = RREG32(IH_CNTL);
2344 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2346 ih_cntl |= ENABLE_INTR;
2347 ih_rb_cntl |= IH_RB_ENABLE;
2348 WREG32(IH_CNTL, ih_cntl);
2349 WREG32(IH_RB_CNTL, ih_rb_cntl);
2350 rdev->ih.enabled = true;
2353 static void r600_disable_interrupts(struct radeon_device *rdev)
2355 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2356 u32 ih_cntl = RREG32(IH_CNTL);
2358 ih_rb_cntl &= ~IH_RB_ENABLE;
2359 ih_cntl &= ~ENABLE_INTR;
2360 WREG32(IH_RB_CNTL, ih_rb_cntl);
2361 WREG32(IH_CNTL, ih_cntl);
2362 /* set rptr, wptr to 0 */
2363 WREG32(IH_RB_RPTR, 0);
2364 WREG32(IH_RB_WPTR, 0);
2365 rdev->ih.enabled = false;
2370 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2374 WREG32(CP_INT_CNTL, 0);
2375 WREG32(GRBM_INT_CNTL, 0);
2376 WREG32(DxMODE_INT_MASK, 0);
2377 if (ASIC_IS_DCE3(rdev)) {
2378 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2379 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2380 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2381 WREG32(DC_HPD1_INT_CONTROL, tmp);
2382 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383 WREG32(DC_HPD2_INT_CONTROL, tmp);
2384 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2385 WREG32(DC_HPD3_INT_CONTROL, tmp);
2386 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2387 WREG32(DC_HPD4_INT_CONTROL, tmp);
2388 if (ASIC_IS_DCE32(rdev)) {
2389 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2390 WREG32(DC_HPD5_INT_CONTROL, 0);
2391 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2392 WREG32(DC_HPD6_INT_CONTROL, 0);
2395 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2396 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2397 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2398 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2399 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2400 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2401 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2402 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2406 int r600_irq_init(struct radeon_device *rdev)
2410 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2413 ret = r600_ih_ring_alloc(rdev);
2418 r600_disable_interrupts(rdev);
2421 ret = r600_rlc_init(rdev);
2423 r600_ih_ring_fini(rdev);
2427 /* setup interrupt control */
2428 /* set dummy read address to ring address */
2429 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2430 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2431 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2432 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2434 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2435 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2436 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2437 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2439 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2440 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2442 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2443 IH_WPTR_OVERFLOW_CLEAR |
2445 /* WPTR writeback, not yet */
2446 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2447 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2448 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2450 WREG32(IH_RB_CNTL, ih_rb_cntl);
2452 /* set rptr, wptr to 0 */
2453 WREG32(IH_RB_RPTR, 0);
2454 WREG32(IH_RB_WPTR, 0);
2456 /* Default settings for IH_CNTL (disabled at first) */
2457 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2458 /* RPTR_REARM only works if msi's are enabled */
2459 if (rdev->msi_enabled)
2460 ih_cntl |= RPTR_REARM;
2463 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2465 WREG32(IH_CNTL, ih_cntl);
2467 /* force the active interrupt state to all disabled */
2468 r600_disable_interrupt_state(rdev);
2471 r600_enable_interrupts(rdev);
2476 void r600_irq_suspend(struct radeon_device *rdev)
2478 r600_disable_interrupts(rdev);
2479 r600_rlc_stop(rdev);
2482 void r600_irq_fini(struct radeon_device *rdev)
2484 r600_irq_suspend(rdev);
2485 r600_ih_ring_fini(rdev);
2488 int r600_irq_set(struct radeon_device *rdev)
2490 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2492 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2494 if (!rdev->irq.installed) {
2495 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2498 /* don't enable anything if the ih is disabled */
2499 if (!rdev->ih.enabled) {
2500 r600_disable_interrupts(rdev);
2501 /* force the active interrupt state to all disabled */
2502 r600_disable_interrupt_state(rdev);
2506 if (ASIC_IS_DCE3(rdev)) {
2507 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2508 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2510 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2511 if (ASIC_IS_DCE32(rdev)) {
2512 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2513 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2516 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2517 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2518 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2521 if (rdev->irq.sw_int) {
2522 DRM_DEBUG("r600_irq_set: sw int\n");
2523 cp_int_cntl |= RB_INT_ENABLE;
2525 if (rdev->irq.crtc_vblank_int[0]) {
2526 DRM_DEBUG("r600_irq_set: vblank 0\n");
2527 mode_int |= D1MODE_VBLANK_INT_MASK;
2529 if (rdev->irq.crtc_vblank_int[1]) {
2530 DRM_DEBUG("r600_irq_set: vblank 1\n");
2531 mode_int |= D2MODE_VBLANK_INT_MASK;
2533 if (rdev->irq.hpd[0]) {
2534 DRM_DEBUG("r600_irq_set: hpd 1\n");
2535 hpd1 |= DC_HPDx_INT_EN;
2537 if (rdev->irq.hpd[1]) {
2538 DRM_DEBUG("r600_irq_set: hpd 2\n");
2539 hpd2 |= DC_HPDx_INT_EN;
2541 if (rdev->irq.hpd[2]) {
2542 DRM_DEBUG("r600_irq_set: hpd 3\n");
2543 hpd3 |= DC_HPDx_INT_EN;
2545 if (rdev->irq.hpd[3]) {
2546 DRM_DEBUG("r600_irq_set: hpd 4\n");
2547 hpd4 |= DC_HPDx_INT_EN;
2549 if (rdev->irq.hpd[4]) {
2550 DRM_DEBUG("r600_irq_set: hpd 5\n");
2551 hpd5 |= DC_HPDx_INT_EN;
2553 if (rdev->irq.hpd[5]) {
2554 DRM_DEBUG("r600_irq_set: hpd 6\n");
2555 hpd6 |= DC_HPDx_INT_EN;
2558 WREG32(CP_INT_CNTL, cp_int_cntl);
2559 WREG32(DxMODE_INT_MASK, mode_int);
2560 if (ASIC_IS_DCE3(rdev)) {
2561 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2562 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2563 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2564 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2565 if (ASIC_IS_DCE32(rdev)) {
2566 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2567 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2570 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2571 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2572 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2578 static inline void r600_irq_ack(struct radeon_device *rdev,
2581 u32 *disp_int_cont2)
2585 if (ASIC_IS_DCE3(rdev)) {
2586 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2587 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2588 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2590 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2591 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2592 *disp_int_cont2 = 0;
2595 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2596 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2597 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2598 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2599 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2600 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2601 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2602 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2603 if (*disp_int & DC_HPD1_INTERRUPT) {
2604 if (ASIC_IS_DCE3(rdev)) {
2605 tmp = RREG32(DC_HPD1_INT_CONTROL);
2606 tmp |= DC_HPDx_INT_ACK;
2607 WREG32(DC_HPD1_INT_CONTROL, tmp);
2609 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2610 tmp |= DC_HPDx_INT_ACK;
2611 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2614 if (*disp_int & DC_HPD2_INTERRUPT) {
2615 if (ASIC_IS_DCE3(rdev)) {
2616 tmp = RREG32(DC_HPD2_INT_CONTROL);
2617 tmp |= DC_HPDx_INT_ACK;
2618 WREG32(DC_HPD2_INT_CONTROL, tmp);
2620 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2621 tmp |= DC_HPDx_INT_ACK;
2622 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2625 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2626 if (ASIC_IS_DCE3(rdev)) {
2627 tmp = RREG32(DC_HPD3_INT_CONTROL);
2628 tmp |= DC_HPDx_INT_ACK;
2629 WREG32(DC_HPD3_INT_CONTROL, tmp);
2631 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2632 tmp |= DC_HPDx_INT_ACK;
2633 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2636 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2637 tmp = RREG32(DC_HPD4_INT_CONTROL);
2638 tmp |= DC_HPDx_INT_ACK;
2639 WREG32(DC_HPD4_INT_CONTROL, tmp);
2641 if (ASIC_IS_DCE32(rdev)) {
2642 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2643 tmp = RREG32(DC_HPD5_INT_CONTROL);
2644 tmp |= DC_HPDx_INT_ACK;
2645 WREG32(DC_HPD5_INT_CONTROL, tmp);
2647 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2648 tmp = RREG32(DC_HPD5_INT_CONTROL);
2649 tmp |= DC_HPDx_INT_ACK;
2650 WREG32(DC_HPD6_INT_CONTROL, tmp);
2655 void r600_irq_disable(struct radeon_device *rdev)
2657 u32 disp_int, disp_int_cont, disp_int_cont2;
2659 r600_disable_interrupts(rdev);
2660 /* Wait and acknowledge irq */
2662 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2663 r600_disable_interrupt_state(rdev);
2666 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2670 /* XXX use writeback */
2671 wptr = RREG32(IH_RB_WPTR);
2673 if (wptr & RB_OVERFLOW) {
2674 /* When a ring buffer overflow happen start parsing interrupt
2675 * from the last not overwritten vector (wptr + 16). Hopefully
2676 * this should allow us to catchup.
2678 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2679 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2680 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2681 tmp = RREG32(IH_RB_CNTL);
2682 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2683 WREG32(IH_RB_CNTL, tmp);
2685 return (wptr & rdev->ih.ptr_mask);
2689 * Each IV ring entry is 128 bits:
2690 * [7:0] - interrupt source id
2692 * [59:32] - interrupt source data
2693 * [127:60] - reserved
2695 * The basic interrupt vector entries
2696 * are decoded as follows:
2697 * src_id src_data description
2702 * 19 0 FP Hot plug detection A
2703 * 19 1 FP Hot plug detection B
2704 * 19 2 DAC A auto-detection
2705 * 19 3 DAC B auto-detection
2709 * 181 - EOP Interrupt
2712 * Note, these are based on r600 and may need to be
2713 * adjusted or added to on newer asics
2716 int r600_irq_process(struct radeon_device *rdev)
2718 u32 wptr = r600_get_ih_wptr(rdev);
2719 u32 rptr = rdev->ih.rptr;
2720 u32 src_id, src_data;
2721 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2722 unsigned long flags;
2723 bool queue_hotplug = false;
2725 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2726 if (!rdev->ih.enabled)
2729 spin_lock_irqsave(&rdev->ih.lock, flags);
2732 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2735 if (rdev->shutdown) {
2736 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2741 /* display interrupts */
2742 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2744 rdev->ih.wptr = wptr;
2745 while (rptr != wptr) {
2746 /* wptr/rptr are in bytes! */
2747 ring_index = rptr / 4;
2748 src_id = rdev->ih.ring[ring_index] & 0xff;
2749 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2752 case 1: /* D1 vblank/vline */
2754 case 0: /* D1 vblank */
2755 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2756 drm_handle_vblank(rdev->ddev, 0);
2757 wake_up(&rdev->irq.vblank_queue);
2758 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2759 DRM_DEBUG("IH: D1 vblank\n");
2762 case 1: /* D1 vline */
2763 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2764 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2765 DRM_DEBUG("IH: D1 vline\n");
2769 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2773 case 5: /* D2 vblank/vline */
2775 case 0: /* D2 vblank */
2776 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2777 drm_handle_vblank(rdev->ddev, 1);
2778 wake_up(&rdev->irq.vblank_queue);
2779 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2780 DRM_DEBUG("IH: D2 vblank\n");
2783 case 1: /* D1 vline */
2784 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2785 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2786 DRM_DEBUG("IH: D2 vline\n");
2790 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2794 case 19: /* HPD/DAC hotplug */
2797 if (disp_int & DC_HPD1_INTERRUPT) {
2798 disp_int &= ~DC_HPD1_INTERRUPT;
2799 queue_hotplug = true;
2800 DRM_DEBUG("IH: HPD1\n");
2804 if (disp_int & DC_HPD2_INTERRUPT) {
2805 disp_int &= ~DC_HPD2_INTERRUPT;
2806 queue_hotplug = true;
2807 DRM_DEBUG("IH: HPD2\n");
2811 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2812 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2813 queue_hotplug = true;
2814 DRM_DEBUG("IH: HPD3\n");
2818 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2819 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2820 queue_hotplug = true;
2821 DRM_DEBUG("IH: HPD4\n");
2825 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2826 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2827 queue_hotplug = true;
2828 DRM_DEBUG("IH: HPD5\n");
2832 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2833 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2834 queue_hotplug = true;
2835 DRM_DEBUG("IH: HPD6\n");
2839 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2843 case 176: /* CP_INT in ring buffer */
2844 case 177: /* CP_INT in IB1 */
2845 case 178: /* CP_INT in IB2 */
2846 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2847 radeon_fence_process(rdev);
2849 case 181: /* CP EOP event */
2850 DRM_DEBUG("IH: CP EOP\n");
2853 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2857 /* wptr/rptr are in bytes! */
2859 rptr &= rdev->ih.ptr_mask;
2861 /* make sure wptr hasn't changed while processing */
2862 wptr = r600_get_ih_wptr(rdev);
2863 if (wptr != rdev->ih.wptr)
2866 queue_work(rdev->wq, &rdev->hotplug_work);
2867 rdev->ih.rptr = rptr;
2868 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2869 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2876 #if defined(CONFIG_DEBUG_FS)
2878 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2880 struct drm_info_node *node = (struct drm_info_node *) m->private;
2881 struct drm_device *dev = node->minor->dev;
2882 struct radeon_device *rdev = dev->dev_private;
2883 unsigned count, i, j;
2885 radeon_ring_free_size(rdev);
2886 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2887 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2888 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2889 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2890 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2891 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2892 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2893 seq_printf(m, "%u dwords in ring\n", count);
2895 for (j = 0; j <= count; j++) {
2896 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2897 i = (i + 1) & rdev->cp.ptr_mask;
2902 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2904 struct drm_info_node *node = (struct drm_info_node *) m->private;
2905 struct drm_device *dev = node->minor->dev;
2906 struct radeon_device *rdev = dev->dev_private;
2908 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2909 DREG32_SYS(m, rdev, VM_L2_STATUS);
2913 static struct drm_info_list r600_mc_info_list[] = {
2914 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2915 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2919 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2921 #if defined(CONFIG_DEBUG_FS)
2922 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2929 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2930 * rdev: radeon device structure
2931 * bo: buffer object struct which userspace is waiting for idle
2933 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2934 * through ring buffer, this leads to corruption in rendering, see
2935 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2936 * directly perform HDP flush by writing register through MMIO.
2938 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2940 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);