2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
34 #include "radeon_drm.h"
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
99 /* r600,rv610,rv630,rv620,rv635,rv670 */
100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
101 void r600_gpu_init(struct radeon_device *rdev);
102 void r600_fini(struct radeon_device *rdev);
103 void r600_irq_disable(struct radeon_device *rdev);
104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
106 /* get temperature in millidegrees */
107 int rv6xx_get_temp(struct radeon_device *rdev)
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
111 int actual_temp = temp & 0xff;
116 return actual_temp * 1000;
119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
137 rdev->pm.dynpm_can_downclock = false;
139 case DYNPM_ACTION_DOWNCLOCK:
140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
142 rdev->pm.dynpm_can_downclock = false;
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
153 rdev->pm.requested_power_state_index = i;
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
166 rdev->pm.requested_clock_mode_index = 0;
167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
175 case DYNPM_ACTION_UPCLOCK:
176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
178 rdev->pm.dynpm_can_upclock = false;
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
189 rdev->pm.requested_power_state_index = i;
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
197 rdev->pm.requested_clock_mode_index = 0;
199 case DYNPM_ACTION_DEFAULT:
200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
202 rdev->pm.dynpm_can_upclock = false;
204 case DYNPM_ACTION_NONE:
206 DRM_ERROR("Requested mode for not defined action\n");
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
229 rdev->pm.requested_power_state_index = 1;
231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
233 rdev->pm.requested_clock_mode_index = 0;
234 rdev->pm.dynpm_can_downclock = false;
236 case DYNPM_ACTION_DOWNCLOCK:
237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
240 rdev->pm.dynpm_can_downclock = false;
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
245 rdev->pm.requested_clock_mode_index = 0;
246 rdev->pm.dynpm_can_downclock = false;
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
256 case DYNPM_ACTION_UPCLOCK:
257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
261 rdev->pm.dynpm_can_upclock = false;
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
268 rdev->pm.dynpm_can_upclock = false;
271 case DYNPM_ACTION_DEFAULT:
272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
274 rdev->pm.dynpm_can_upclock = false;
276 case DYNPM_ACTION_NONE:
278 DRM_ERROR("Requested mode for not defined action\n");
283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
292 void rs780_pm_init_profile(struct radeon_device *rdev)
294 if (rdev->pm.num_power_states == 2) {
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
405 void r600_pm_init_profile(struct radeon_device *rdev)
409 if (rdev->family == CHIP_R600) {
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
447 if (rdev->pm.num_power_states < 4) {
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
533 void r600_pm_misc(struct radeon_device *rdev)
535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
544 if (voltage->voltage != rdev->pm.current_vddc) {
545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
546 rdev->pm.current_vddc = voltage->voltage;
547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
552 bool r600_gui_idle(struct radeon_device *rdev)
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
560 /* hpd for digital panel detect/disconnect */
561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
563 bool connected = false;
565 if (ASIC_IS_DCE3(rdev)) {
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
616 void r600_hpd_set_polarity(struct radeon_device *rdev,
617 enum radeon_hpd_id hpd)
620 bool connected = r600_hpd_sense(rdev, hpd);
622 if (ASIC_IS_DCE3(rdev)) {
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
627 tmp &= ~DC_HPDx_INT_POLARITY;
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
635 tmp &= ~DC_HPDx_INT_POLARITY;
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
643 tmp &= ~DC_HPDx_INT_POLARITY;
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
651 tmp &= ~DC_HPDx_INT_POLARITY;
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
659 tmp &= ~DC_HPDx_INT_POLARITY;
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
668 tmp &= ~DC_HPDx_INT_POLARITY;
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
708 void r600_hpd_init(struct radeon_device *rdev)
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
713 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
714 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
716 if (ASIC_IS_DCE3(rdev)) {
717 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
718 if (ASIC_IS_DCE32(rdev))
721 switch (radeon_connector->hpd.hpd) {
723 WREG32(DC_HPD1_CONTROL, tmp);
724 rdev->irq.hpd[0] = true;
727 WREG32(DC_HPD2_CONTROL, tmp);
728 rdev->irq.hpd[1] = true;
731 WREG32(DC_HPD3_CONTROL, tmp);
732 rdev->irq.hpd[2] = true;
735 WREG32(DC_HPD4_CONTROL, tmp);
736 rdev->irq.hpd[3] = true;
740 WREG32(DC_HPD5_CONTROL, tmp);
741 rdev->irq.hpd[4] = true;
744 WREG32(DC_HPD6_CONTROL, tmp);
745 rdev->irq.hpd[5] = true;
751 switch (radeon_connector->hpd.hpd) {
753 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
754 rdev->irq.hpd[0] = true;
757 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
758 rdev->irq.hpd[1] = true;
761 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
762 rdev->irq.hpd[2] = true;
768 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
770 if (rdev->irq.installed)
774 void r600_hpd_fini(struct radeon_device *rdev)
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
779 if (ASIC_IS_DCE3(rdev)) {
780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 switch (radeon_connector->hpd.hpd) {
784 WREG32(DC_HPD1_CONTROL, 0);
785 rdev->irq.hpd[0] = false;
788 WREG32(DC_HPD2_CONTROL, 0);
789 rdev->irq.hpd[1] = false;
792 WREG32(DC_HPD3_CONTROL, 0);
793 rdev->irq.hpd[2] = false;
796 WREG32(DC_HPD4_CONTROL, 0);
797 rdev->irq.hpd[3] = false;
801 WREG32(DC_HPD5_CONTROL, 0);
802 rdev->irq.hpd[4] = false;
805 WREG32(DC_HPD6_CONTROL, 0);
806 rdev->irq.hpd[5] = false;
813 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
814 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
815 switch (radeon_connector->hpd.hpd) {
817 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
818 rdev->irq.hpd[0] = false;
821 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
822 rdev->irq.hpd[1] = false;
825 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
826 rdev->irq.hpd[2] = false;
838 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
843 /* flush hdp cache so updates hit vram */
844 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
845 !(rdev->flags & RADEON_IS_AGP)) {
846 void __iomem *ptr = (void *)rdev->gart.ptr;
849 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
850 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
851 * This seems to cause problems on some AGP cards. Just use the old
854 WREG32(HDP_DEBUG1, 0);
855 tmp = readl((void __iomem *)ptr);
857 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
859 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
860 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
861 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
862 for (i = 0; i < rdev->usec_timeout; i++) {
864 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
865 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
867 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
877 int r600_pcie_gart_init(struct radeon_device *rdev)
881 if (rdev->gart.robj) {
882 WARN(1, "R600 PCIE GART already initialized\n");
885 /* Initialize common gart structure */
886 r = radeon_gart_init(rdev);
889 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
890 return radeon_gart_table_vram_alloc(rdev);
893 int r600_pcie_gart_enable(struct radeon_device *rdev)
898 if (rdev->gart.robj == NULL) {
899 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
902 r = radeon_gart_table_vram_pin(rdev);
905 radeon_gart_restore(rdev);
908 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
909 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
910 EFFECTIVE_L2_QUEUE_SIZE(7));
911 WREG32(VM_L2_CNTL2, 0);
912 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
913 /* Setup TLB control */
914 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
915 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
916 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
917 ENABLE_WAIT_L2_QUERY;
918 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
921 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
922 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
923 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
926 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
931 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
932 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
933 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
934 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
935 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
936 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
937 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
938 (u32)(rdev->dummy_page.addr >> 12));
939 for (i = 1; i < 7; i++)
940 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
942 r600_pcie_gart_tlb_flush(rdev);
943 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
944 (unsigned)(rdev->mc.gtt_size >> 20),
945 (unsigned long long)rdev->gart.table_addr);
946 rdev->gart.ready = true;
950 void r600_pcie_gart_disable(struct radeon_device *rdev)
955 /* Disable all tables */
956 for (i = 0; i < 7; i++)
957 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
959 /* Disable L2 cache */
960 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
961 EFFECTIVE_L2_QUEUE_SIZE(7));
962 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
963 /* Setup L1 TLB control */
964 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
965 ENABLE_WAIT_L2_QUERY;
966 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
980 radeon_gart_table_vram_unpin(rdev);
983 void r600_pcie_gart_fini(struct radeon_device *rdev)
985 radeon_gart_fini(rdev);
986 r600_pcie_gart_disable(rdev);
987 radeon_gart_table_vram_free(rdev);
990 void r600_agp_enable(struct radeon_device *rdev)
996 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
997 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
998 EFFECTIVE_L2_QUEUE_SIZE(7));
999 WREG32(VM_L2_CNTL2, 0);
1000 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1001 /* Setup TLB control */
1002 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1003 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1004 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1005 ENABLE_WAIT_L2_QUERY;
1006 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1020 for (i = 0; i < 7; i++)
1021 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1024 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1029 for (i = 0; i < rdev->usec_timeout; i++) {
1030 /* read MC_STATUS */
1031 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1039 static void r600_mc_program(struct radeon_device *rdev)
1041 struct rv515_mc_save save;
1045 /* Initialize HDP */
1046 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1047 WREG32((0x2c14 + j), 0x00000000);
1048 WREG32((0x2c18 + j), 0x00000000);
1049 WREG32((0x2c1c + j), 0x00000000);
1050 WREG32((0x2c20 + j), 0x00000000);
1051 WREG32((0x2c24 + j), 0x00000000);
1053 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1055 rv515_mc_stop(rdev, &save);
1056 if (r600_mc_wait_for_idle(rdev)) {
1057 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1059 /* Lockout access through VGA aperture (doesn't exist before R600) */
1060 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1061 /* Update configuration */
1062 if (rdev->flags & RADEON_IS_AGP) {
1063 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1064 /* VRAM before AGP */
1065 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1066 rdev->mc.vram_start >> 12);
1067 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1068 rdev->mc.gtt_end >> 12);
1070 /* VRAM after AGP */
1071 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1072 rdev->mc.gtt_start >> 12);
1073 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1074 rdev->mc.vram_end >> 12);
1077 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1078 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1080 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1081 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1082 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1083 WREG32(MC_VM_FB_LOCATION, tmp);
1084 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1085 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1086 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1087 if (rdev->flags & RADEON_IS_AGP) {
1088 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1089 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1090 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1092 WREG32(MC_VM_AGP_BASE, 0);
1093 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1094 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1096 if (r600_mc_wait_for_idle(rdev)) {
1097 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1099 rv515_mc_resume(rdev, &save);
1100 /* we need to own VRAM, so turn off the VGA renderer here
1101 * to stop it overwriting our objects */
1102 rv515_vga_render_disable(rdev);
1106 * r600_vram_gtt_location - try to find VRAM & GTT location
1107 * @rdev: radeon device structure holding all necessary informations
1108 * @mc: memory controller structure holding memory informations
1110 * Function will place try to place VRAM at same place as in CPU (PCI)
1111 * address space as some GPU seems to have issue when we reprogram at
1112 * different address space.
1114 * If there is not enough space to fit the unvisible VRAM after the
1115 * aperture then we limit the VRAM size to the aperture.
1117 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1118 * them to be in one from GPU point of view so that we can program GPU to
1119 * catch access outside them (weird GPU policy see ??).
1121 * This function will never fails, worst case are limiting VRAM or GTT.
1123 * Note: GTT start, end, size should be initialized before calling this
1124 * function on AGP platform.
1126 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1128 u64 size_bf, size_af;
1130 if (mc->mc_vram_size > 0xE0000000) {
1131 /* leave room for at least 512M GTT */
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = 0xE0000000;
1134 mc->mc_vram_size = 0xE0000000;
1136 if (rdev->flags & RADEON_IS_AGP) {
1137 size_bf = mc->gtt_start;
1138 size_af = 0xFFFFFFFF - mc->gtt_end;
1139 if (size_bf > size_af) {
1140 if (mc->mc_vram_size > size_bf) {
1141 dev_warn(rdev->dev, "limiting VRAM\n");
1142 mc->real_vram_size = size_bf;
1143 mc->mc_vram_size = size_bf;
1145 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1147 if (mc->mc_vram_size > size_af) {
1148 dev_warn(rdev->dev, "limiting VRAM\n");
1149 mc->real_vram_size = size_af;
1150 mc->mc_vram_size = size_af;
1152 mc->vram_start = mc->gtt_end + 1;
1154 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1155 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1156 mc->mc_vram_size >> 20, mc->vram_start,
1157 mc->vram_end, mc->real_vram_size >> 20);
1160 if (rdev->flags & RADEON_IS_IGP) {
1161 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1164 radeon_vram_location(rdev, &rdev->mc, base);
1165 rdev->mc.gtt_base_align = 0;
1166 radeon_gtt_location(rdev, mc);
1170 int r600_mc_init(struct radeon_device *rdev)
1173 int chansize, numchan;
1175 /* Get VRAM informations */
1176 rdev->mc.vram_is_ddr = true;
1177 tmp = RREG32(RAMCFG);
1178 if (tmp & CHANSIZE_OVERRIDE) {
1180 } else if (tmp & CHANSIZE_MASK) {
1185 tmp = RREG32(CHMAP);
1186 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1201 rdev->mc.vram_width = numchan * chansize;
1202 /* Could aper size report 0 ? */
1203 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1204 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1205 /* Setup GPU memory space */
1206 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1207 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1208 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1209 r600_vram_gtt_location(rdev, &rdev->mc);
1211 if (rdev->flags & RADEON_IS_IGP) {
1212 rs690_pm_info(rdev);
1213 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1215 radeon_update_bandwidth_info(rdev);
1219 int r600_vram_scratch_init(struct radeon_device *rdev)
1223 if (rdev->vram_scratch.robj == NULL) {
1224 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1225 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1226 &rdev->vram_scratch.robj);
1232 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1233 if (unlikely(r != 0))
1235 r = radeon_bo_pin(rdev->vram_scratch.robj,
1236 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1238 radeon_bo_unreserve(rdev->vram_scratch.robj);
1241 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1242 (void **)&rdev->vram_scratch.ptr);
1244 radeon_bo_unpin(rdev->vram_scratch.robj);
1245 radeon_bo_unreserve(rdev->vram_scratch.robj);
1250 void r600_vram_scratch_fini(struct radeon_device *rdev)
1254 if (rdev->vram_scratch.robj == NULL) {
1257 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1258 if (likely(r == 0)) {
1259 radeon_bo_kunmap(rdev->vram_scratch.robj);
1260 radeon_bo_unpin(rdev->vram_scratch.robj);
1261 radeon_bo_unreserve(rdev->vram_scratch.robj);
1263 radeon_bo_unref(&rdev->vram_scratch.robj);
1266 /* We doesn't check that the GPU really needs a reset we simply do the
1267 * reset, it's up to the caller to determine if the GPU needs one. We
1268 * might add an helper function to check that.
1270 int r600_gpu_soft_reset(struct radeon_device *rdev)
1272 struct rv515_mc_save save;
1273 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1274 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1275 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1276 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1277 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1278 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1279 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1280 S_008010_GUI_ACTIVE(1);
1281 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1282 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1283 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1284 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1285 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1286 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1287 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1288 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1291 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1294 dev_info(rdev->dev, "GPU softreset \n");
1295 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1296 RREG32(R_008010_GRBM_STATUS));
1297 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1298 RREG32(R_008014_GRBM_STATUS2));
1299 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1300 RREG32(R_000E50_SRBM_STATUS));
1301 rv515_mc_stop(rdev, &save);
1302 if (r600_mc_wait_for_idle(rdev)) {
1303 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1305 /* Disable CP parsing/prefetching */
1306 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1307 /* Check if any of the rendering block is busy and reset it */
1308 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1309 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1310 tmp = S_008020_SOFT_RESET_CR(1) |
1311 S_008020_SOFT_RESET_DB(1) |
1312 S_008020_SOFT_RESET_CB(1) |
1313 S_008020_SOFT_RESET_PA(1) |
1314 S_008020_SOFT_RESET_SC(1) |
1315 S_008020_SOFT_RESET_SMX(1) |
1316 S_008020_SOFT_RESET_SPI(1) |
1317 S_008020_SOFT_RESET_SX(1) |
1318 S_008020_SOFT_RESET_SH(1) |
1319 S_008020_SOFT_RESET_TC(1) |
1320 S_008020_SOFT_RESET_TA(1) |
1321 S_008020_SOFT_RESET_VC(1) |
1322 S_008020_SOFT_RESET_VGT(1);
1323 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1324 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1325 RREG32(R_008020_GRBM_SOFT_RESET);
1327 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1329 /* Reset CP (we always reset CP) */
1330 tmp = S_008020_SOFT_RESET_CP(1);
1331 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1332 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1333 RREG32(R_008020_GRBM_SOFT_RESET);
1335 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1336 /* Wait a little for things to settle down */
1338 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1339 RREG32(R_008010_GRBM_STATUS));
1340 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1341 RREG32(R_008014_GRBM_STATUS2));
1342 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1343 RREG32(R_000E50_SRBM_STATUS));
1344 rv515_mc_resume(rdev, &save);
1348 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1353 struct r100_gpu_lockup *lockup;
1356 if (rdev->family >= CHIP_RV770)
1357 lockup = &rdev->config.rv770.lockup;
1359 lockup = &rdev->config.r600.lockup;
1361 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1362 grbm_status = RREG32(R_008010_GRBM_STATUS);
1363 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1364 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1365 r100_gpu_lockup_update(lockup, ring);
1368 /* force CP activities */
1369 r = radeon_ring_lock(rdev, ring, 2);
1372 radeon_ring_write(ring, 0x80000000);
1373 radeon_ring_write(ring, 0x80000000);
1374 radeon_ring_unlock_commit(rdev, ring);
1376 ring->rptr = RREG32(ring->rptr_reg);
1377 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
1380 int r600_asic_reset(struct radeon_device *rdev)
1382 return r600_gpu_soft_reset(rdev);
1385 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1387 u32 backend_disable_mask)
1389 u32 backend_map = 0;
1390 u32 enabled_backends_mask;
1391 u32 enabled_backends_count;
1393 u32 swizzle_pipe[R6XX_MAX_PIPES];
1397 if (num_tile_pipes > R6XX_MAX_PIPES)
1398 num_tile_pipes = R6XX_MAX_PIPES;
1399 if (num_tile_pipes < 1)
1401 if (num_backends > R6XX_MAX_BACKENDS)
1402 num_backends = R6XX_MAX_BACKENDS;
1403 if (num_backends < 1)
1406 enabled_backends_mask = 0;
1407 enabled_backends_count = 0;
1408 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1409 if (((backend_disable_mask >> i) & 1) == 0) {
1410 enabled_backends_mask |= (1 << i);
1411 ++enabled_backends_count;
1413 if (enabled_backends_count == num_backends)
1417 if (enabled_backends_count == 0) {
1418 enabled_backends_mask = 1;
1419 enabled_backends_count = 1;
1422 if (enabled_backends_count != num_backends)
1423 num_backends = enabled_backends_count;
1425 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1426 switch (num_tile_pipes) {
1428 swizzle_pipe[0] = 0;
1431 swizzle_pipe[0] = 0;
1432 swizzle_pipe[1] = 1;
1435 swizzle_pipe[0] = 0;
1436 swizzle_pipe[1] = 1;
1437 swizzle_pipe[2] = 2;
1440 swizzle_pipe[0] = 0;
1441 swizzle_pipe[1] = 1;
1442 swizzle_pipe[2] = 2;
1443 swizzle_pipe[3] = 3;
1446 swizzle_pipe[0] = 0;
1447 swizzle_pipe[1] = 1;
1448 swizzle_pipe[2] = 2;
1449 swizzle_pipe[3] = 3;
1450 swizzle_pipe[4] = 4;
1453 swizzle_pipe[0] = 0;
1454 swizzle_pipe[1] = 2;
1455 swizzle_pipe[2] = 4;
1456 swizzle_pipe[3] = 5;
1457 swizzle_pipe[4] = 1;
1458 swizzle_pipe[5] = 3;
1461 swizzle_pipe[0] = 0;
1462 swizzle_pipe[1] = 2;
1463 swizzle_pipe[2] = 4;
1464 swizzle_pipe[3] = 6;
1465 swizzle_pipe[4] = 1;
1466 swizzle_pipe[5] = 3;
1467 swizzle_pipe[6] = 5;
1470 swizzle_pipe[0] = 0;
1471 swizzle_pipe[1] = 2;
1472 swizzle_pipe[2] = 4;
1473 swizzle_pipe[3] = 6;
1474 swizzle_pipe[4] = 1;
1475 swizzle_pipe[5] = 3;
1476 swizzle_pipe[6] = 5;
1477 swizzle_pipe[7] = 7;
1482 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1483 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1484 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1486 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1488 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1494 int r600_count_pipe_bits(uint32_t val)
1498 for (i = 0; i < 32; i++) {
1505 void r600_gpu_init(struct radeon_device *rdev)
1510 u32 cc_rb_backend_disable;
1511 u32 cc_gc_shader_pipe_config;
1515 u32 sq_gpr_resource_mgmt_1 = 0;
1516 u32 sq_gpr_resource_mgmt_2 = 0;
1517 u32 sq_thread_resource_mgmt = 0;
1518 u32 sq_stack_resource_mgmt_1 = 0;
1519 u32 sq_stack_resource_mgmt_2 = 0;
1521 /* FIXME: implement */
1522 switch (rdev->family) {
1524 rdev->config.r600.max_pipes = 4;
1525 rdev->config.r600.max_tile_pipes = 8;
1526 rdev->config.r600.max_simds = 4;
1527 rdev->config.r600.max_backends = 4;
1528 rdev->config.r600.max_gprs = 256;
1529 rdev->config.r600.max_threads = 192;
1530 rdev->config.r600.max_stack_entries = 256;
1531 rdev->config.r600.max_hw_contexts = 8;
1532 rdev->config.r600.max_gs_threads = 16;
1533 rdev->config.r600.sx_max_export_size = 128;
1534 rdev->config.r600.sx_max_export_pos_size = 16;
1535 rdev->config.r600.sx_max_export_smx_size = 128;
1536 rdev->config.r600.sq_num_cf_insts = 2;
1540 rdev->config.r600.max_pipes = 2;
1541 rdev->config.r600.max_tile_pipes = 2;
1542 rdev->config.r600.max_simds = 3;
1543 rdev->config.r600.max_backends = 1;
1544 rdev->config.r600.max_gprs = 128;
1545 rdev->config.r600.max_threads = 192;
1546 rdev->config.r600.max_stack_entries = 128;
1547 rdev->config.r600.max_hw_contexts = 8;
1548 rdev->config.r600.max_gs_threads = 4;
1549 rdev->config.r600.sx_max_export_size = 128;
1550 rdev->config.r600.sx_max_export_pos_size = 16;
1551 rdev->config.r600.sx_max_export_smx_size = 128;
1552 rdev->config.r600.sq_num_cf_insts = 2;
1558 rdev->config.r600.max_pipes = 1;
1559 rdev->config.r600.max_tile_pipes = 1;
1560 rdev->config.r600.max_simds = 2;
1561 rdev->config.r600.max_backends = 1;
1562 rdev->config.r600.max_gprs = 128;
1563 rdev->config.r600.max_threads = 192;
1564 rdev->config.r600.max_stack_entries = 128;
1565 rdev->config.r600.max_hw_contexts = 4;
1566 rdev->config.r600.max_gs_threads = 4;
1567 rdev->config.r600.sx_max_export_size = 128;
1568 rdev->config.r600.sx_max_export_pos_size = 16;
1569 rdev->config.r600.sx_max_export_smx_size = 128;
1570 rdev->config.r600.sq_num_cf_insts = 1;
1573 rdev->config.r600.max_pipes = 4;
1574 rdev->config.r600.max_tile_pipes = 4;
1575 rdev->config.r600.max_simds = 4;
1576 rdev->config.r600.max_backends = 4;
1577 rdev->config.r600.max_gprs = 192;
1578 rdev->config.r600.max_threads = 192;
1579 rdev->config.r600.max_stack_entries = 256;
1580 rdev->config.r600.max_hw_contexts = 8;
1581 rdev->config.r600.max_gs_threads = 16;
1582 rdev->config.r600.sx_max_export_size = 128;
1583 rdev->config.r600.sx_max_export_pos_size = 16;
1584 rdev->config.r600.sx_max_export_smx_size = 128;
1585 rdev->config.r600.sq_num_cf_insts = 2;
1591 /* Initialize HDP */
1592 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1593 WREG32((0x2c14 + j), 0x00000000);
1594 WREG32((0x2c18 + j), 0x00000000);
1595 WREG32((0x2c1c + j), 0x00000000);
1596 WREG32((0x2c20 + j), 0x00000000);
1597 WREG32((0x2c24 + j), 0x00000000);
1600 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1604 ramcfg = RREG32(RAMCFG);
1605 switch (rdev->config.r600.max_tile_pipes) {
1607 tiling_config |= PIPE_TILING(0);
1610 tiling_config |= PIPE_TILING(1);
1613 tiling_config |= PIPE_TILING(2);
1616 tiling_config |= PIPE_TILING(3);
1621 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1622 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1623 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1624 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1625 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1626 rdev->config.r600.tiling_group_size = 512;
1628 rdev->config.r600.tiling_group_size = 256;
1629 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1631 tiling_config |= ROW_TILING(3);
1632 tiling_config |= SAMPLE_SPLIT(3);
1634 tiling_config |= ROW_TILING(tmp);
1635 tiling_config |= SAMPLE_SPLIT(tmp);
1637 tiling_config |= BANK_SWAPS(1);
1639 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1640 cc_rb_backend_disable |=
1641 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1643 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1644 cc_gc_shader_pipe_config |=
1645 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1646 cc_gc_shader_pipe_config |=
1647 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1649 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1650 (R6XX_MAX_BACKENDS -
1651 r600_count_pipe_bits((cc_rb_backend_disable &
1652 R6XX_MAX_BACKENDS_MASK) >> 16)),
1653 (cc_rb_backend_disable >> 16));
1654 rdev->config.r600.tile_config = tiling_config;
1655 rdev->config.r600.backend_map = backend_map;
1656 tiling_config |= BACKEND_MAP(backend_map);
1657 WREG32(GB_TILING_CONFIG, tiling_config);
1658 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1659 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1662 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1663 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1664 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1666 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1667 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1668 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1670 /* Setup some CP states */
1671 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1672 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1674 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1675 SYNC_WALKER | SYNC_ALIGNER));
1676 /* Setup various GPU states */
1677 if (rdev->family == CHIP_RV670)
1678 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1680 tmp = RREG32(SX_DEBUG_1);
1681 tmp |= SMX_EVENT_RELEASE;
1682 if ((rdev->family > CHIP_R600))
1683 tmp |= ENABLE_NEW_SMX_ADDRESS;
1684 WREG32(SX_DEBUG_1, tmp);
1686 if (((rdev->family) == CHIP_R600) ||
1687 ((rdev->family) == CHIP_RV630) ||
1688 ((rdev->family) == CHIP_RV610) ||
1689 ((rdev->family) == CHIP_RV620) ||
1690 ((rdev->family) == CHIP_RS780) ||
1691 ((rdev->family) == CHIP_RS880)) {
1692 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1694 WREG32(DB_DEBUG, 0);
1696 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1697 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1699 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1700 WREG32(VGT_NUM_INSTANCES, 0);
1702 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1703 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1705 tmp = RREG32(SQ_MS_FIFO_SIZES);
1706 if (((rdev->family) == CHIP_RV610) ||
1707 ((rdev->family) == CHIP_RV620) ||
1708 ((rdev->family) == CHIP_RS780) ||
1709 ((rdev->family) == CHIP_RS880)) {
1710 tmp = (CACHE_FIFO_SIZE(0xa) |
1711 FETCH_FIFO_HIWATER(0xa) |
1712 DONE_FIFO_HIWATER(0xe0) |
1713 ALU_UPDATE_FIFO_HIWATER(0x8));
1714 } else if (((rdev->family) == CHIP_R600) ||
1715 ((rdev->family) == CHIP_RV630)) {
1716 tmp &= ~DONE_FIFO_HIWATER(0xff);
1717 tmp |= DONE_FIFO_HIWATER(0x4);
1719 WREG32(SQ_MS_FIFO_SIZES, tmp);
1721 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1722 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1724 sq_config = RREG32(SQ_CONFIG);
1725 sq_config &= ~(PS_PRIO(3) |
1729 sq_config |= (DX9_CONSTS |
1736 if ((rdev->family) == CHIP_R600) {
1737 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1739 NUM_CLAUSE_TEMP_GPRS(4));
1740 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1742 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1743 NUM_VS_THREADS(48) |
1746 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1747 NUM_VS_STACK_ENTRIES(128));
1748 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1749 NUM_ES_STACK_ENTRIES(0));
1750 } else if (((rdev->family) == CHIP_RV610) ||
1751 ((rdev->family) == CHIP_RV620) ||
1752 ((rdev->family) == CHIP_RS780) ||
1753 ((rdev->family) == CHIP_RS880)) {
1754 /* no vertex cache */
1755 sq_config &= ~VC_ENABLE;
1757 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1759 NUM_CLAUSE_TEMP_GPRS(2));
1760 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1762 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1763 NUM_VS_THREADS(78) |
1765 NUM_ES_THREADS(31));
1766 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1767 NUM_VS_STACK_ENTRIES(40));
1768 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1769 NUM_ES_STACK_ENTRIES(16));
1770 } else if (((rdev->family) == CHIP_RV630) ||
1771 ((rdev->family) == CHIP_RV635)) {
1772 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1774 NUM_CLAUSE_TEMP_GPRS(2));
1775 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1777 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1778 NUM_VS_THREADS(78) |
1780 NUM_ES_THREADS(31));
1781 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1782 NUM_VS_STACK_ENTRIES(40));
1783 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1784 NUM_ES_STACK_ENTRIES(16));
1785 } else if ((rdev->family) == CHIP_RV670) {
1786 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1788 NUM_CLAUSE_TEMP_GPRS(2));
1789 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1791 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1792 NUM_VS_THREADS(78) |
1794 NUM_ES_THREADS(31));
1795 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1796 NUM_VS_STACK_ENTRIES(64));
1797 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1798 NUM_ES_STACK_ENTRIES(64));
1801 WREG32(SQ_CONFIG, sq_config);
1802 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1803 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1804 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1805 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1806 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1808 if (((rdev->family) == CHIP_RV610) ||
1809 ((rdev->family) == CHIP_RV620) ||
1810 ((rdev->family) == CHIP_RS780) ||
1811 ((rdev->family) == CHIP_RS880)) {
1812 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1814 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1817 /* More default values. 2D/3D driver should adjust as needed */
1818 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1819 S1_X(0x4) | S1_Y(0xc)));
1820 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1821 S1_X(0x2) | S1_Y(0x2) |
1822 S2_X(0xa) | S2_Y(0x6) |
1823 S3_X(0x6) | S3_Y(0xa)));
1824 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1825 S1_X(0x4) | S1_Y(0xc) |
1826 S2_X(0x1) | S2_Y(0x6) |
1827 S3_X(0xa) | S3_Y(0xe)));
1828 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1829 S5_X(0x0) | S5_Y(0x0) |
1830 S6_X(0xb) | S6_Y(0x4) |
1831 S7_X(0x7) | S7_Y(0x8)));
1833 WREG32(VGT_STRMOUT_EN, 0);
1834 tmp = rdev->config.r600.max_pipes * 16;
1835 switch (rdev->family) {
1851 WREG32(VGT_ES_PER_GS, 128);
1852 WREG32(VGT_GS_PER_ES, tmp);
1853 WREG32(VGT_GS_PER_VS, 2);
1854 WREG32(VGT_GS_VERTEX_REUSE, 16);
1856 /* more default values. 2D/3D driver should adjust as needed */
1857 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1858 WREG32(VGT_STRMOUT_EN, 0);
1860 WREG32(PA_SC_MODE_CNTL, 0);
1861 WREG32(PA_SC_AA_CONFIG, 0);
1862 WREG32(PA_SC_LINE_STIPPLE, 0);
1863 WREG32(SPI_INPUT_Z, 0);
1864 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1865 WREG32(CB_COLOR7_FRAG, 0);
1867 /* Clear render buffer base addresses */
1868 WREG32(CB_COLOR0_BASE, 0);
1869 WREG32(CB_COLOR1_BASE, 0);
1870 WREG32(CB_COLOR2_BASE, 0);
1871 WREG32(CB_COLOR3_BASE, 0);
1872 WREG32(CB_COLOR4_BASE, 0);
1873 WREG32(CB_COLOR5_BASE, 0);
1874 WREG32(CB_COLOR6_BASE, 0);
1875 WREG32(CB_COLOR7_BASE, 0);
1876 WREG32(CB_COLOR7_FRAG, 0);
1878 switch (rdev->family) {
1883 tmp = TC_L2_SIZE(8);
1887 tmp = TC_L2_SIZE(4);
1890 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1893 tmp = TC_L2_SIZE(0);
1896 WREG32(TC_CNTL, tmp);
1898 tmp = RREG32(HDP_HOST_PATH_CNTL);
1899 WREG32(HDP_HOST_PATH_CNTL, tmp);
1901 tmp = RREG32(ARB_POP);
1902 tmp |= ENABLE_TC128;
1903 WREG32(ARB_POP, tmp);
1905 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1906 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1908 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1913 * Indirect registers accessor
1915 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1919 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1920 (void)RREG32(PCIE_PORT_INDEX);
1921 r = RREG32(PCIE_PORT_DATA);
1925 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1927 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1928 (void)RREG32(PCIE_PORT_INDEX);
1929 WREG32(PCIE_PORT_DATA, (v));
1930 (void)RREG32(PCIE_PORT_DATA);
1936 void r600_cp_stop(struct radeon_device *rdev)
1938 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1939 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1940 WREG32(SCRATCH_UMSK, 0);
1943 int r600_init_microcode(struct radeon_device *rdev)
1945 struct platform_device *pdev;
1946 const char *chip_name;
1947 const char *rlc_chip_name;
1948 size_t pfp_req_size, me_req_size, rlc_req_size;
1954 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1957 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1961 switch (rdev->family) {
1964 rlc_chip_name = "R600";
1967 chip_name = "RV610";
1968 rlc_chip_name = "R600";
1971 chip_name = "RV630";
1972 rlc_chip_name = "R600";
1975 chip_name = "RV620";
1976 rlc_chip_name = "R600";
1979 chip_name = "RV635";
1980 rlc_chip_name = "R600";
1983 chip_name = "RV670";
1984 rlc_chip_name = "R600";
1988 chip_name = "RS780";
1989 rlc_chip_name = "R600";
1992 chip_name = "RV770";
1993 rlc_chip_name = "R700";
1997 chip_name = "RV730";
1998 rlc_chip_name = "R700";
2001 chip_name = "RV710";
2002 rlc_chip_name = "R700";
2005 chip_name = "CEDAR";
2006 rlc_chip_name = "CEDAR";
2009 chip_name = "REDWOOD";
2010 rlc_chip_name = "REDWOOD";
2013 chip_name = "JUNIPER";
2014 rlc_chip_name = "JUNIPER";
2018 chip_name = "CYPRESS";
2019 rlc_chip_name = "CYPRESS";
2023 rlc_chip_name = "SUMO";
2027 rlc_chip_name = "SUMO";
2030 chip_name = "SUMO2";
2031 rlc_chip_name = "SUMO";
2036 if (rdev->family >= CHIP_CEDAR) {
2037 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2038 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2039 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2040 } else if (rdev->family >= CHIP_RV770) {
2041 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2042 me_req_size = R700_PM4_UCODE_SIZE * 4;
2043 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2045 pfp_req_size = PFP_UCODE_SIZE * 4;
2046 me_req_size = PM4_UCODE_SIZE * 12;
2047 rlc_req_size = RLC_UCODE_SIZE * 4;
2050 DRM_INFO("Loading %s Microcode\n", chip_name);
2052 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2053 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2056 if (rdev->pfp_fw->size != pfp_req_size) {
2058 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2059 rdev->pfp_fw->size, fw_name);
2064 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2065 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2068 if (rdev->me_fw->size != me_req_size) {
2070 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2071 rdev->me_fw->size, fw_name);
2075 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2076 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2079 if (rdev->rlc_fw->size != rlc_req_size) {
2081 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2082 rdev->rlc_fw->size, fw_name);
2087 platform_device_unregister(pdev);
2092 "r600_cp: Failed to load firmware \"%s\"\n",
2094 release_firmware(rdev->pfp_fw);
2095 rdev->pfp_fw = NULL;
2096 release_firmware(rdev->me_fw);
2098 release_firmware(rdev->rlc_fw);
2099 rdev->rlc_fw = NULL;
2104 static int r600_cp_load_microcode(struct radeon_device *rdev)
2106 const __be32 *fw_data;
2109 if (!rdev->me_fw || !rdev->pfp_fw)
2118 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2121 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2122 RREG32(GRBM_SOFT_RESET);
2124 WREG32(GRBM_SOFT_RESET, 0);
2126 WREG32(CP_ME_RAM_WADDR, 0);
2128 fw_data = (const __be32 *)rdev->me_fw->data;
2129 WREG32(CP_ME_RAM_WADDR, 0);
2130 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2131 WREG32(CP_ME_RAM_DATA,
2132 be32_to_cpup(fw_data++));
2134 fw_data = (const __be32 *)rdev->pfp_fw->data;
2135 WREG32(CP_PFP_UCODE_ADDR, 0);
2136 for (i = 0; i < PFP_UCODE_SIZE; i++)
2137 WREG32(CP_PFP_UCODE_DATA,
2138 be32_to_cpup(fw_data++));
2140 WREG32(CP_PFP_UCODE_ADDR, 0);
2141 WREG32(CP_ME_RAM_WADDR, 0);
2142 WREG32(CP_ME_RAM_RADDR, 0);
2146 int r600_cp_start(struct radeon_device *rdev)
2148 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2152 r = radeon_ring_lock(rdev, ring, 7);
2154 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2157 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2158 radeon_ring_write(ring, 0x1);
2159 if (rdev->family >= CHIP_RV770) {
2160 radeon_ring_write(ring, 0x0);
2161 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2163 radeon_ring_write(ring, 0x3);
2164 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2166 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2167 radeon_ring_write(ring, 0);
2168 radeon_ring_write(ring, 0);
2169 radeon_ring_unlock_commit(rdev, ring);
2172 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2176 int r600_cp_resume(struct radeon_device *rdev)
2178 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2184 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2185 RREG32(GRBM_SOFT_RESET);
2187 WREG32(GRBM_SOFT_RESET, 0);
2189 /* Set ring buffer size */
2190 rb_bufsz = drm_order(ring->ring_size / 8);
2191 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2193 tmp |= BUF_SWAP_32BIT;
2195 WREG32(CP_RB_CNTL, tmp);
2196 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2198 /* Set the write pointer delay */
2199 WREG32(CP_RB_WPTR_DELAY, 0);
2201 /* Initialize the ring buffer's read and write pointers */
2202 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2203 WREG32(CP_RB_RPTR_WR, 0);
2205 WREG32(CP_RB_WPTR, ring->wptr);
2207 /* set the wb address whether it's enabled or not */
2208 WREG32(CP_RB_RPTR_ADDR,
2209 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2210 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2211 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2213 if (rdev->wb.enabled)
2214 WREG32(SCRATCH_UMSK, 0xff);
2216 tmp |= RB_NO_UPDATE;
2217 WREG32(SCRATCH_UMSK, 0);
2221 WREG32(CP_RB_CNTL, tmp);
2223 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2224 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2226 ring->rptr = RREG32(CP_RB_RPTR);
2228 r600_cp_start(rdev);
2230 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2232 ring->ready = false;
2238 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2242 /* Align ring size */
2243 rb_bufsz = drm_order(ring_size / 8);
2244 ring_size = (1 << (rb_bufsz + 1)) * 4;
2245 ring->ring_size = ring_size;
2246 ring->align_mask = 16 - 1;
2249 void r600_cp_fini(struct radeon_device *rdev)
2252 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2257 * GPU scratch registers helpers function.
2259 void r600_scratch_init(struct radeon_device *rdev)
2263 rdev->scratch.num_reg = 7;
2264 rdev->scratch.reg_base = SCRATCH_REG0;
2265 for (i = 0; i < rdev->scratch.num_reg; i++) {
2266 rdev->scratch.free[i] = true;
2267 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2271 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2275 unsigned i, ridx = radeon_ring_index(rdev, ring);
2278 r = radeon_scratch_get(rdev, &scratch);
2280 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2283 WREG32(scratch, 0xCAFEDEAD);
2284 r = radeon_ring_lock(rdev, ring, 3);
2286 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
2287 radeon_scratch_free(rdev, scratch);
2290 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2291 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2292 radeon_ring_write(ring, 0xDEADBEEF);
2293 radeon_ring_unlock_commit(rdev, ring);
2294 for (i = 0; i < rdev->usec_timeout; i++) {
2295 tmp = RREG32(scratch);
2296 if (tmp == 0xDEADBEEF)
2300 if (i < rdev->usec_timeout) {
2301 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
2303 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2304 ridx, scratch, tmp);
2307 radeon_scratch_free(rdev, scratch);
2311 void r600_fence_ring_emit(struct radeon_device *rdev,
2312 struct radeon_fence *fence)
2314 struct radeon_ring *ring = &rdev->ring[fence->ring];
2316 if (rdev->wb.use_event) {
2317 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2318 /* flush read cache over gart */
2319 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2320 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2321 PACKET3_VC_ACTION_ENA |
2322 PACKET3_SH_ACTION_ENA);
2323 radeon_ring_write(ring, 0xFFFFFFFF);
2324 radeon_ring_write(ring, 0);
2325 radeon_ring_write(ring, 10); /* poll interval */
2326 /* EVENT_WRITE_EOP - flush caches, send int */
2327 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2328 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2329 radeon_ring_write(ring, addr & 0xffffffff);
2330 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2331 radeon_ring_write(ring, fence->seq);
2332 radeon_ring_write(ring, 0);
2334 /* flush read cache over gart */
2335 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2336 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2337 PACKET3_VC_ACTION_ENA |
2338 PACKET3_SH_ACTION_ENA);
2339 radeon_ring_write(ring, 0xFFFFFFFF);
2340 radeon_ring_write(ring, 0);
2341 radeon_ring_write(ring, 10); /* poll interval */
2342 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2343 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2344 /* wait for 3D idle clean */
2345 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2346 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2347 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2348 /* Emit fence sequence & fire IRQ */
2349 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2350 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2351 radeon_ring_write(ring, fence->seq);
2352 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2353 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2354 radeon_ring_write(ring, RB_INT_STAT);
2358 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2359 struct radeon_ring *ring,
2360 struct radeon_semaphore *semaphore,
2363 uint64_t addr = semaphore->gpu_addr;
2364 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2366 if (rdev->family < CHIP_CAYMAN)
2367 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2369 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2370 radeon_ring_write(ring, addr & 0xffffffff);
2371 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2374 int r600_copy_blit(struct radeon_device *rdev,
2375 uint64_t src_offset,
2376 uint64_t dst_offset,
2377 unsigned num_gpu_pages,
2378 struct radeon_fence *fence)
2382 mutex_lock(&rdev->r600_blit.mutex);
2383 rdev->r600_blit.vb_ib = NULL;
2384 r = r600_blit_prepare_copy(rdev, num_gpu_pages);
2386 if (rdev->r600_blit.vb_ib)
2387 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2388 mutex_unlock(&rdev->r600_blit.mutex);
2391 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages);
2392 r600_blit_done_copy(rdev, fence);
2393 mutex_unlock(&rdev->r600_blit.mutex);
2397 void r600_blit_suspend(struct radeon_device *rdev)
2401 /* unpin shaders bo */
2402 if (rdev->r600_blit.shader_obj) {
2403 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2405 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2406 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2411 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2412 uint32_t tiling_flags, uint32_t pitch,
2413 uint32_t offset, uint32_t obj_size)
2415 /* FIXME: implement */
2419 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2421 /* FIXME: implement */
2424 int r600_startup(struct radeon_device *rdev)
2426 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2429 /* enable pcie gen2 link */
2430 r600_pcie_gen2_enable(rdev);
2432 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2433 r = r600_init_microcode(rdev);
2435 DRM_ERROR("Failed to load firmware!\n");
2440 r = r600_vram_scratch_init(rdev);
2444 r600_mc_program(rdev);
2445 if (rdev->flags & RADEON_IS_AGP) {
2446 r600_agp_enable(rdev);
2448 r = r600_pcie_gart_enable(rdev);
2452 r600_gpu_init(rdev);
2453 r = r600_blit_init(rdev);
2455 r600_blit_fini(rdev);
2456 rdev->asic->copy.copy = NULL;
2457 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2460 /* allocate wb buffer */
2461 r = radeon_wb_init(rdev);
2465 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2467 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2472 r = r600_irq_init(rdev);
2474 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2475 radeon_irq_kms_fini(rdev);
2480 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2481 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2482 0, 0xfffff, RADEON_CP_PACKET2);
2486 r = r600_cp_load_microcode(rdev);
2489 r = r600_cp_resume(rdev);
2493 r = radeon_ib_pool_start(rdev);
2497 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2499 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2500 rdev->accel_working = false;
2507 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2511 temp = RREG32(CONFIG_CNTL);
2512 if (state == false) {
2518 WREG32(CONFIG_CNTL, temp);
2521 int r600_resume(struct radeon_device *rdev)
2525 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2526 * posting will perform necessary task to bring back GPU into good
2530 atom_asic_init(rdev->mode_info.atom_context);
2532 rdev->accel_working = true;
2533 r = r600_startup(rdev);
2535 DRM_ERROR("r600 startup failed on resume\n");
2536 rdev->accel_working = false;
2540 r = r600_audio_init(rdev);
2542 DRM_ERROR("radeon: audio resume failed\n");
2549 int r600_suspend(struct radeon_device *rdev)
2551 r600_audio_fini(rdev);
2552 radeon_ib_pool_suspend(rdev);
2553 r600_blit_suspend(rdev);
2554 /* FIXME: we should wait for ring to be empty */
2556 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2557 r600_irq_suspend(rdev);
2558 radeon_wb_disable(rdev);
2559 r600_pcie_gart_disable(rdev);
2564 /* Plan is to move initialization in that function and use
2565 * helper function so that radeon_device_init pretty much
2566 * do nothing more than calling asic specific function. This
2567 * should also allow to remove a bunch of callback function
2570 int r600_init(struct radeon_device *rdev)
2574 if (r600_debugfs_mc_info_init(rdev)) {
2575 DRM_ERROR("Failed to register debugfs file for mc !\n");
2577 /* This don't do much */
2578 r = radeon_gem_init(rdev);
2582 if (!radeon_get_bios(rdev)) {
2583 if (ASIC_IS_AVIVO(rdev))
2586 /* Must be an ATOMBIOS */
2587 if (!rdev->is_atom_bios) {
2588 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2591 r = radeon_atombios_init(rdev);
2594 /* Post card if necessary */
2595 if (!radeon_card_posted(rdev)) {
2597 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2600 DRM_INFO("GPU not posted. posting now...\n");
2601 atom_asic_init(rdev->mode_info.atom_context);
2603 /* Initialize scratch registers */
2604 r600_scratch_init(rdev);
2605 /* Initialize surface registers */
2606 radeon_surface_init(rdev);
2607 /* Initialize clocks */
2608 radeon_get_clock_info(rdev->ddev);
2610 r = radeon_fence_driver_init(rdev);
2613 if (rdev->flags & RADEON_IS_AGP) {
2614 r = radeon_agp_init(rdev);
2616 radeon_agp_disable(rdev);
2618 r = r600_mc_init(rdev);
2621 /* Memory manager */
2622 r = radeon_bo_init(rdev);
2626 r = radeon_irq_kms_init(rdev);
2630 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2631 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2633 rdev->ih.ring_obj = NULL;
2634 r600_ih_ring_init(rdev, 64 * 1024);
2636 r = r600_pcie_gart_init(rdev);
2640 r = radeon_ib_pool_init(rdev);
2641 rdev->accel_working = true;
2643 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2644 rdev->accel_working = false;
2647 r = r600_startup(rdev);
2649 dev_err(rdev->dev, "disabling GPU acceleration\n");
2651 r600_irq_fini(rdev);
2652 radeon_wb_fini(rdev);
2654 radeon_irq_kms_fini(rdev);
2655 r600_pcie_gart_fini(rdev);
2656 rdev->accel_working = false;
2659 r = r600_audio_init(rdev);
2661 return r; /* TODO error handling */
2665 void r600_fini(struct radeon_device *rdev)
2667 r600_audio_fini(rdev);
2668 r600_blit_fini(rdev);
2670 r600_irq_fini(rdev);
2671 radeon_wb_fini(rdev);
2673 radeon_irq_kms_fini(rdev);
2674 r600_pcie_gart_fini(rdev);
2675 r600_vram_scratch_fini(rdev);
2676 radeon_agp_fini(rdev);
2677 radeon_gem_fini(rdev);
2678 radeon_semaphore_driver_fini(rdev);
2679 radeon_fence_driver_fini(rdev);
2680 radeon_bo_fini(rdev);
2681 radeon_atombios_fini(rdev);
2690 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2692 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
2694 /* FIXME: implement */
2695 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2696 radeon_ring_write(ring,
2700 (ib->gpu_addr & 0xFFFFFFFC));
2701 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2702 radeon_ring_write(ring, ib->length_dw);
2705 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2707 struct radeon_ib *ib;
2712 int ring_index = radeon_ring_index(rdev, ring);
2714 r = radeon_scratch_get(rdev, &scratch);
2716 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2719 WREG32(scratch, 0xCAFEDEAD);
2720 r = radeon_ib_get(rdev, ring_index, &ib, 256);
2722 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2725 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2726 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2727 ib->ptr[2] = 0xDEADBEEF;
2729 r = radeon_ib_schedule(rdev, ib);
2731 radeon_scratch_free(rdev, scratch);
2732 radeon_ib_free(rdev, &ib);
2733 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2736 r = radeon_fence_wait(ib->fence, false);
2738 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2741 for (i = 0; i < rdev->usec_timeout; i++) {
2742 tmp = RREG32(scratch);
2743 if (tmp == 0xDEADBEEF)
2747 if (i < rdev->usec_timeout) {
2748 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i);
2750 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2754 radeon_scratch_free(rdev, scratch);
2755 radeon_ib_free(rdev, &ib);
2762 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2763 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2764 * writing to the ring and the GPU consuming, the GPU writes to the ring
2765 * and host consumes. As the host irq handler processes interrupts, it
2766 * increments the rptr. When the rptr catches up with the wptr, all the
2767 * current interrupts have been processed.
2770 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2774 /* Align ring size */
2775 rb_bufsz = drm_order(ring_size / 4);
2776 ring_size = (1 << rb_bufsz) * 4;
2777 rdev->ih.ring_size = ring_size;
2778 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2782 int r600_ih_ring_alloc(struct radeon_device *rdev)
2786 /* Allocate ring buffer */
2787 if (rdev->ih.ring_obj == NULL) {
2788 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2790 RADEON_GEM_DOMAIN_GTT,
2791 &rdev->ih.ring_obj);
2793 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2796 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2797 if (unlikely(r != 0))
2799 r = radeon_bo_pin(rdev->ih.ring_obj,
2800 RADEON_GEM_DOMAIN_GTT,
2801 &rdev->ih.gpu_addr);
2803 radeon_bo_unreserve(rdev->ih.ring_obj);
2804 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2807 r = radeon_bo_kmap(rdev->ih.ring_obj,
2808 (void **)&rdev->ih.ring);
2809 radeon_bo_unreserve(rdev->ih.ring_obj);
2811 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2818 void r600_ih_ring_fini(struct radeon_device *rdev)
2821 if (rdev->ih.ring_obj) {
2822 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2823 if (likely(r == 0)) {
2824 radeon_bo_kunmap(rdev->ih.ring_obj);
2825 radeon_bo_unpin(rdev->ih.ring_obj);
2826 radeon_bo_unreserve(rdev->ih.ring_obj);
2828 radeon_bo_unref(&rdev->ih.ring_obj);
2829 rdev->ih.ring = NULL;
2830 rdev->ih.ring_obj = NULL;
2834 void r600_rlc_stop(struct radeon_device *rdev)
2837 if ((rdev->family >= CHIP_RV770) &&
2838 (rdev->family <= CHIP_RV740)) {
2839 /* r7xx asics need to soft reset RLC before halting */
2840 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2841 RREG32(SRBM_SOFT_RESET);
2843 WREG32(SRBM_SOFT_RESET, 0);
2844 RREG32(SRBM_SOFT_RESET);
2847 WREG32(RLC_CNTL, 0);
2850 static void r600_rlc_start(struct radeon_device *rdev)
2852 WREG32(RLC_CNTL, RLC_ENABLE);
2855 static int r600_rlc_init(struct radeon_device *rdev)
2858 const __be32 *fw_data;
2863 r600_rlc_stop(rdev);
2865 WREG32(RLC_HB_CNTL, 0);
2867 if (rdev->family == CHIP_ARUBA) {
2868 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
2869 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
2871 if (rdev->family <= CHIP_CAYMAN) {
2872 WREG32(RLC_HB_BASE, 0);
2873 WREG32(RLC_HB_RPTR, 0);
2874 WREG32(RLC_HB_WPTR, 0);
2876 if (rdev->family <= CHIP_CAICOS) {
2877 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2878 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2880 WREG32(RLC_MC_CNTL, 0);
2881 WREG32(RLC_UCODE_CNTL, 0);
2883 fw_data = (const __be32 *)rdev->rlc_fw->data;
2884 if (rdev->family >= CHIP_ARUBA) {
2885 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
2886 WREG32(RLC_UCODE_ADDR, i);
2887 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2889 } else if (rdev->family >= CHIP_CAYMAN) {
2890 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2891 WREG32(RLC_UCODE_ADDR, i);
2892 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2894 } else if (rdev->family >= CHIP_CEDAR) {
2895 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2896 WREG32(RLC_UCODE_ADDR, i);
2897 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2899 } else if (rdev->family >= CHIP_RV770) {
2900 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2901 WREG32(RLC_UCODE_ADDR, i);
2902 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2905 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2906 WREG32(RLC_UCODE_ADDR, i);
2907 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2910 WREG32(RLC_UCODE_ADDR, 0);
2912 r600_rlc_start(rdev);
2917 static void r600_enable_interrupts(struct radeon_device *rdev)
2919 u32 ih_cntl = RREG32(IH_CNTL);
2920 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2922 ih_cntl |= ENABLE_INTR;
2923 ih_rb_cntl |= IH_RB_ENABLE;
2924 WREG32(IH_CNTL, ih_cntl);
2925 WREG32(IH_RB_CNTL, ih_rb_cntl);
2926 rdev->ih.enabled = true;
2929 void r600_disable_interrupts(struct radeon_device *rdev)
2931 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2932 u32 ih_cntl = RREG32(IH_CNTL);
2934 ih_rb_cntl &= ~IH_RB_ENABLE;
2935 ih_cntl &= ~ENABLE_INTR;
2936 WREG32(IH_RB_CNTL, ih_rb_cntl);
2937 WREG32(IH_CNTL, ih_cntl);
2938 /* set rptr, wptr to 0 */
2939 WREG32(IH_RB_RPTR, 0);
2940 WREG32(IH_RB_WPTR, 0);
2941 rdev->ih.enabled = false;
2946 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2950 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2951 WREG32(GRBM_INT_CNTL, 0);
2952 WREG32(DxMODE_INT_MASK, 0);
2953 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2954 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2955 if (ASIC_IS_DCE3(rdev)) {
2956 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2957 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2958 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2959 WREG32(DC_HPD1_INT_CONTROL, tmp);
2960 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2961 WREG32(DC_HPD2_INT_CONTROL, tmp);
2962 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2963 WREG32(DC_HPD3_INT_CONTROL, tmp);
2964 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2965 WREG32(DC_HPD4_INT_CONTROL, tmp);
2966 if (ASIC_IS_DCE32(rdev)) {
2967 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2968 WREG32(DC_HPD5_INT_CONTROL, tmp);
2969 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2970 WREG32(DC_HPD6_INT_CONTROL, tmp);
2973 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2974 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2975 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2976 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2977 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2978 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2979 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2980 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2984 int r600_irq_init(struct radeon_device *rdev)
2988 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2991 ret = r600_ih_ring_alloc(rdev);
2996 r600_disable_interrupts(rdev);
2999 ret = r600_rlc_init(rdev);
3001 r600_ih_ring_fini(rdev);
3005 /* setup interrupt control */
3006 /* set dummy read address to ring address */
3007 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3008 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3009 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3010 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3012 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3013 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3014 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3015 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3017 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3018 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3020 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3021 IH_WPTR_OVERFLOW_CLEAR |
3024 if (rdev->wb.enabled)
3025 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3027 /* set the writeback address whether it's enabled or not */
3028 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3029 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3031 WREG32(IH_RB_CNTL, ih_rb_cntl);
3033 /* set rptr, wptr to 0 */
3034 WREG32(IH_RB_RPTR, 0);
3035 WREG32(IH_RB_WPTR, 0);
3037 /* Default settings for IH_CNTL (disabled at first) */
3038 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3039 /* RPTR_REARM only works if msi's are enabled */
3040 if (rdev->msi_enabled)
3041 ih_cntl |= RPTR_REARM;
3042 WREG32(IH_CNTL, ih_cntl);
3044 /* force the active interrupt state to all disabled */
3045 if (rdev->family >= CHIP_CEDAR)
3046 evergreen_disable_interrupt_state(rdev);
3048 r600_disable_interrupt_state(rdev);
3051 r600_enable_interrupts(rdev);
3056 void r600_irq_suspend(struct radeon_device *rdev)
3058 r600_irq_disable(rdev);
3059 r600_rlc_stop(rdev);
3062 void r600_irq_fini(struct radeon_device *rdev)
3064 r600_irq_suspend(rdev);
3065 r600_ih_ring_fini(rdev);
3068 int r600_irq_set(struct radeon_device *rdev)
3070 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3072 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3073 u32 grbm_int_cntl = 0;
3075 u32 d1grph = 0, d2grph = 0;
3077 if (!rdev->irq.installed) {
3078 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3081 /* don't enable anything if the ih is disabled */
3082 if (!rdev->ih.enabled) {
3083 r600_disable_interrupts(rdev);
3084 /* force the active interrupt state to all disabled */
3085 r600_disable_interrupt_state(rdev);
3089 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3090 if (ASIC_IS_DCE3(rdev)) {
3091 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3092 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3093 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3094 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3095 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3096 if (ASIC_IS_DCE32(rdev)) {
3097 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3098 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3101 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3102 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3103 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3104 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3107 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3108 DRM_DEBUG("r600_irq_set: sw int\n");
3109 cp_int_cntl |= RB_INT_ENABLE;
3110 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3112 if (rdev->irq.crtc_vblank_int[0] ||
3113 rdev->irq.pflip[0]) {
3114 DRM_DEBUG("r600_irq_set: vblank 0\n");
3115 mode_int |= D1MODE_VBLANK_INT_MASK;
3117 if (rdev->irq.crtc_vblank_int[1] ||
3118 rdev->irq.pflip[1]) {
3119 DRM_DEBUG("r600_irq_set: vblank 1\n");
3120 mode_int |= D2MODE_VBLANK_INT_MASK;
3122 if (rdev->irq.hpd[0]) {
3123 DRM_DEBUG("r600_irq_set: hpd 1\n");
3124 hpd1 |= DC_HPDx_INT_EN;
3126 if (rdev->irq.hpd[1]) {
3127 DRM_DEBUG("r600_irq_set: hpd 2\n");
3128 hpd2 |= DC_HPDx_INT_EN;
3130 if (rdev->irq.hpd[2]) {
3131 DRM_DEBUG("r600_irq_set: hpd 3\n");
3132 hpd3 |= DC_HPDx_INT_EN;
3134 if (rdev->irq.hpd[3]) {
3135 DRM_DEBUG("r600_irq_set: hpd 4\n");
3136 hpd4 |= DC_HPDx_INT_EN;
3138 if (rdev->irq.hpd[4]) {
3139 DRM_DEBUG("r600_irq_set: hpd 5\n");
3140 hpd5 |= DC_HPDx_INT_EN;
3142 if (rdev->irq.hpd[5]) {
3143 DRM_DEBUG("r600_irq_set: hpd 6\n");
3144 hpd6 |= DC_HPDx_INT_EN;
3146 if (rdev->irq.hdmi[0]) {
3147 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3148 hdmi1 |= R600_HDMI_INT_EN;
3150 if (rdev->irq.hdmi[1]) {
3151 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3152 hdmi2 |= R600_HDMI_INT_EN;
3154 if (rdev->irq.gui_idle) {
3155 DRM_DEBUG("gui idle\n");
3156 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3159 WREG32(CP_INT_CNTL, cp_int_cntl);
3160 WREG32(DxMODE_INT_MASK, mode_int);
3161 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3162 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3163 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3164 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3165 if (ASIC_IS_DCE3(rdev)) {
3166 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3167 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3168 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3169 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3170 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3171 if (ASIC_IS_DCE32(rdev)) {
3172 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3173 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3176 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3177 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3178 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3179 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3185 static void r600_irq_ack(struct radeon_device *rdev)
3189 if (ASIC_IS_DCE3(rdev)) {
3190 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3191 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3192 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3194 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3195 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3196 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3198 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3199 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3201 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3202 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3203 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3204 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3205 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3206 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3207 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3208 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3209 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3210 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3211 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3212 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3213 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3214 if (ASIC_IS_DCE3(rdev)) {
3215 tmp = RREG32(DC_HPD1_INT_CONTROL);
3216 tmp |= DC_HPDx_INT_ACK;
3217 WREG32(DC_HPD1_INT_CONTROL, tmp);
3219 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3220 tmp |= DC_HPDx_INT_ACK;
3221 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3224 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3225 if (ASIC_IS_DCE3(rdev)) {
3226 tmp = RREG32(DC_HPD2_INT_CONTROL);
3227 tmp |= DC_HPDx_INT_ACK;
3228 WREG32(DC_HPD2_INT_CONTROL, tmp);
3230 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3231 tmp |= DC_HPDx_INT_ACK;
3232 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3235 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3236 if (ASIC_IS_DCE3(rdev)) {
3237 tmp = RREG32(DC_HPD3_INT_CONTROL);
3238 tmp |= DC_HPDx_INT_ACK;
3239 WREG32(DC_HPD3_INT_CONTROL, tmp);
3241 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3242 tmp |= DC_HPDx_INT_ACK;
3243 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3246 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3247 tmp = RREG32(DC_HPD4_INT_CONTROL);
3248 tmp |= DC_HPDx_INT_ACK;
3249 WREG32(DC_HPD4_INT_CONTROL, tmp);
3251 if (ASIC_IS_DCE32(rdev)) {
3252 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3253 tmp = RREG32(DC_HPD5_INT_CONTROL);
3254 tmp |= DC_HPDx_INT_ACK;
3255 WREG32(DC_HPD5_INT_CONTROL, tmp);
3257 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3258 tmp = RREG32(DC_HPD5_INT_CONTROL);
3259 tmp |= DC_HPDx_INT_ACK;
3260 WREG32(DC_HPD6_INT_CONTROL, tmp);
3263 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3264 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3266 if (ASIC_IS_DCE3(rdev)) {
3267 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3268 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3271 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3272 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3277 void r600_irq_disable(struct radeon_device *rdev)
3279 r600_disable_interrupts(rdev);
3280 /* Wait and acknowledge irq */
3283 r600_disable_interrupt_state(rdev);
3286 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3290 if (rdev->wb.enabled)
3291 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3293 wptr = RREG32(IH_RB_WPTR);
3295 if (wptr & RB_OVERFLOW) {
3296 /* When a ring buffer overflow happen start parsing interrupt
3297 * from the last not overwritten vector (wptr + 16). Hopefully
3298 * this should allow us to catchup.
3300 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3301 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3302 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3303 tmp = RREG32(IH_RB_CNTL);
3304 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3305 WREG32(IH_RB_CNTL, tmp);
3307 return (wptr & rdev->ih.ptr_mask);
3311 * Each IV ring entry is 128 bits:
3312 * [7:0] - interrupt source id
3314 * [59:32] - interrupt source data
3315 * [127:60] - reserved
3317 * The basic interrupt vector entries
3318 * are decoded as follows:
3319 * src_id src_data description
3324 * 19 0 FP Hot plug detection A
3325 * 19 1 FP Hot plug detection B
3326 * 19 2 DAC A auto-detection
3327 * 19 3 DAC B auto-detection
3333 * 181 - EOP Interrupt
3336 * Note, these are based on r600 and may need to be
3337 * adjusted or added to on newer asics
3340 int r600_irq_process(struct radeon_device *rdev)
3344 u32 src_id, src_data;
3346 unsigned long flags;
3347 bool queue_hotplug = false;
3349 if (!rdev->ih.enabled || rdev->shutdown)
3352 /* No MSIs, need a dummy read to flush PCI DMAs */
3353 if (!rdev->msi_enabled)
3356 wptr = r600_get_ih_wptr(rdev);
3357 rptr = rdev->ih.rptr;
3358 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3360 spin_lock_irqsave(&rdev->ih.lock, flags);
3363 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3368 /* Order reading of wptr vs. reading of IH ring data */
3371 /* display interrupts */
3374 rdev->ih.wptr = wptr;
3375 while (rptr != wptr) {
3376 /* wptr/rptr are in bytes! */
3377 ring_index = rptr / 4;
3378 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3379 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3382 case 1: /* D1 vblank/vline */
3384 case 0: /* D1 vblank */
3385 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3386 if (rdev->irq.crtc_vblank_int[0]) {
3387 drm_handle_vblank(rdev->ddev, 0);
3388 rdev->pm.vblank_sync = true;
3389 wake_up(&rdev->irq.vblank_queue);
3391 if (rdev->irq.pflip[0])
3392 radeon_crtc_handle_flip(rdev, 0);
3393 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3394 DRM_DEBUG("IH: D1 vblank\n");
3397 case 1: /* D1 vline */
3398 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3399 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3400 DRM_DEBUG("IH: D1 vline\n");
3404 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3408 case 5: /* D2 vblank/vline */
3410 case 0: /* D2 vblank */
3411 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3412 if (rdev->irq.crtc_vblank_int[1]) {
3413 drm_handle_vblank(rdev->ddev, 1);
3414 rdev->pm.vblank_sync = true;
3415 wake_up(&rdev->irq.vblank_queue);
3417 if (rdev->irq.pflip[1])
3418 radeon_crtc_handle_flip(rdev, 1);
3419 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3420 DRM_DEBUG("IH: D2 vblank\n");
3423 case 1: /* D1 vline */
3424 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3425 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3426 DRM_DEBUG("IH: D2 vline\n");
3430 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3434 case 19: /* HPD/DAC hotplug */
3437 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3438 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3439 queue_hotplug = true;
3440 DRM_DEBUG("IH: HPD1\n");
3444 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3445 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3446 queue_hotplug = true;
3447 DRM_DEBUG("IH: HPD2\n");
3451 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3452 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3453 queue_hotplug = true;
3454 DRM_DEBUG("IH: HPD3\n");
3458 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3459 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3460 queue_hotplug = true;
3461 DRM_DEBUG("IH: HPD4\n");
3465 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3466 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3467 queue_hotplug = true;
3468 DRM_DEBUG("IH: HPD5\n");
3472 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3473 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3474 queue_hotplug = true;
3475 DRM_DEBUG("IH: HPD6\n");
3479 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3484 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3485 r600_audio_schedule_polling(rdev);
3487 case 176: /* CP_INT in ring buffer */
3488 case 177: /* CP_INT in IB1 */
3489 case 178: /* CP_INT in IB2 */
3490 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3491 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3493 case 181: /* CP EOP event */
3494 DRM_DEBUG("IH: CP EOP\n");
3495 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3497 case 233: /* GUI IDLE */
3498 DRM_DEBUG("IH: GUI idle\n");
3499 rdev->pm.gui_idle = true;
3500 wake_up(&rdev->irq.idle_queue);
3503 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3507 /* wptr/rptr are in bytes! */
3509 rptr &= rdev->ih.ptr_mask;
3511 /* make sure wptr hasn't changed while processing */
3512 wptr = r600_get_ih_wptr(rdev);
3513 if (wptr != rdev->ih.wptr)
3516 schedule_work(&rdev->hotplug_work);
3517 rdev->ih.rptr = rptr;
3518 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3519 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3526 #if defined(CONFIG_DEBUG_FS)
3528 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3530 struct drm_info_node *node = (struct drm_info_node *) m->private;
3531 struct drm_device *dev = node->minor->dev;
3532 struct radeon_device *rdev = dev->dev_private;
3534 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3535 DREG32_SYS(m, rdev, VM_L2_STATUS);
3539 static struct drm_info_list r600_mc_info_list[] = {
3540 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3544 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3546 #if defined(CONFIG_DEBUG_FS)
3547 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3554 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3555 * rdev: radeon device structure
3556 * bo: buffer object struct which userspace is waiting for idle
3558 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3559 * through ring buffer, this leads to corruption in rendering, see
3560 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3561 * directly perform HDP flush by writing register through MMIO.
3563 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3565 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3566 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3567 * This seems to cause problems on some AGP cards. Just use the old
3570 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3571 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3572 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3575 WREG32(HDP_DEBUG1, 0);
3576 tmp = readl((void __iomem *)ptr);
3578 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3581 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3583 u32 link_width_cntl, mask, target_reg;
3585 if (rdev->flags & RADEON_IS_IGP)
3588 if (!(rdev->flags & RADEON_IS_PCIE))
3591 /* x2 cards have a special sequence */
3592 if (ASIC_IS_X2(rdev))
3595 /* FIXME wait for idle */
3599 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3602 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3605 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3608 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3611 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3614 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3618 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3622 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3624 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3625 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3628 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3631 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3632 RADEON_PCIE_LC_RECONFIG_NOW |
3633 R600_PCIE_LC_RENEGOTIATE_EN |
3634 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3635 link_width_cntl |= mask;
3637 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3639 /* some northbridges can renegotiate the link rather than requiring
3640 * a complete re-config.
3641 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3643 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3644 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3646 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3648 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3649 RADEON_PCIE_LC_RECONFIG_NOW));
3651 if (rdev->family >= CHIP_RV770)
3652 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3654 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3656 /* wait for lane set to complete */
3657 link_width_cntl = RREG32(target_reg);
3658 while (link_width_cntl == 0xffffffff)
3659 link_width_cntl = RREG32(target_reg);
3663 int r600_get_pcie_lanes(struct radeon_device *rdev)
3665 u32 link_width_cntl;
3667 if (rdev->flags & RADEON_IS_IGP)
3670 if (!(rdev->flags & RADEON_IS_PCIE))
3673 /* x2 cards have a special sequence */
3674 if (ASIC_IS_X2(rdev))
3677 /* FIXME wait for idle */
3679 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3681 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3682 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3684 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3686 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3688 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3690 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3692 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3698 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3700 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3703 if (radeon_pcie_gen2 == 0)
3706 if (rdev->flags & RADEON_IS_IGP)
3709 if (!(rdev->flags & RADEON_IS_PCIE))
3712 /* x2 cards have a special sequence */
3713 if (ASIC_IS_X2(rdev))
3716 /* only RV6xx+ chips are supported */
3717 if (rdev->family <= CHIP_R600)
3720 /* 55 nm r6xx asics */
3721 if ((rdev->family == CHIP_RV670) ||
3722 (rdev->family == CHIP_RV620) ||
3723 (rdev->family == CHIP_RV635)) {
3724 /* advertise upconfig capability */
3725 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3726 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3727 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3728 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3729 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3730 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3731 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3732 LC_RECONFIG_ARC_MISSING_ESCAPE);
3733 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3734 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3736 link_width_cntl |= LC_UPCONFIGURE_DIS;
3737 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3741 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3742 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3743 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3745 /* 55 nm r6xx asics */
3746 if ((rdev->family == CHIP_RV670) ||
3747 (rdev->family == CHIP_RV620) ||
3748 (rdev->family == CHIP_RV635)) {
3749 WREG32(MM_CFGREGS_CNTL, 0x8);
3750 link_cntl2 = RREG32(0x4088);
3751 WREG32(MM_CFGREGS_CNTL, 0);
3752 /* not supported yet */
3753 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3757 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3758 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3759 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3760 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3761 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3762 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3764 tmp = RREG32(0x541c);
3765 WREG32(0x541c, tmp | 0x8);
3766 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3767 link_cntl2 = RREG16(0x4088);
3768 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3770 WREG16(0x4088, link_cntl2);
3771 WREG32(MM_CFGREGS_CNTL, 0);
3773 if ((rdev->family == CHIP_RV670) ||
3774 (rdev->family == CHIP_RV620) ||
3775 (rdev->family == CHIP_RV635)) {
3776 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3777 training_cntl &= ~LC_POINT_7_PLUS_EN;
3778 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3780 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3781 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3782 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3785 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3786 speed_cntl |= LC_GEN2_EN_STRAP;
3787 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3790 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3791 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3793 link_width_cntl |= LC_UPCONFIGURE_DIS;
3795 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3796 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);