2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
89 /* r600,rv610,rv630,rv620,rv635,rv670 */
90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
91 void r600_gpu_init(struct radeon_device *rdev);
92 void r600_fini(struct radeon_device *rdev);
93 void r600_irq_disable(struct radeon_device *rdev);
95 void r600_get_power_state(struct radeon_device *rdev,
96 enum radeon_pm_action action)
100 rdev->pm.can_upclock = true;
101 rdev->pm.can_downclock = true;
103 /* power state array is low to high, default is first */
104 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
105 int min_power_state_index = 0;
107 if (rdev->pm.num_power_states > 2)
108 min_power_state_index = 1;
111 case PM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = min_power_state_index;
113 rdev->pm.requested_clock_mode_index = 0;
114 rdev->pm.can_downclock = false;
116 case PM_ACTION_DOWNCLOCK:
117 if (rdev->pm.current_power_state_index == min_power_state_index) {
118 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
119 rdev->pm.can_downclock = false;
121 if (rdev->pm.active_crtc_count > 1) {
122 for (i = 0; i < rdev->pm.num_power_states; i++) {
123 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
125 else if (i >= rdev->pm.current_power_state_index) {
126 rdev->pm.requested_power_state_index =
127 rdev->pm.current_power_state_index;
130 rdev->pm.requested_power_state_index = i;
135 rdev->pm.requested_power_state_index =
136 rdev->pm.current_power_state_index - 1;
138 rdev->pm.requested_clock_mode_index = 0;
140 case PM_ACTION_UPCLOCK:
141 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
142 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
143 rdev->pm.can_upclock = false;
145 if (rdev->pm.active_crtc_count > 1) {
146 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
147 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
149 else if (i <= rdev->pm.current_power_state_index) {
150 rdev->pm.requested_power_state_index =
151 rdev->pm.current_power_state_index;
154 rdev->pm.requested_power_state_index = i;
159 rdev->pm.requested_power_state_index =
160 rdev->pm.current_power_state_index + 1;
162 rdev->pm.requested_clock_mode_index = 0;
164 case PM_ACTION_DEFAULT:
165 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
166 rdev->pm.requested_clock_mode_index = 0;
167 rdev->pm.can_upclock = false;
171 DRM_ERROR("Requested mode for not defined action\n");
175 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
176 /* for now just select the first power state and switch between clock modes */
177 /* power state array is low to high, default is first (0) */
178 if (rdev->pm.active_crtc_count > 1) {
179 rdev->pm.requested_power_state_index = -1;
180 /* start at 1 as we don't want the default mode */
181 for (i = 1; i < rdev->pm.num_power_states; i++) {
182 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
184 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
185 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
186 rdev->pm.requested_power_state_index = i;
190 /* if nothing selected, grab the default state. */
191 if (rdev->pm.requested_power_state_index == -1)
192 rdev->pm.requested_power_state_index = 0;
194 rdev->pm.requested_power_state_index = 1;
197 case PM_ACTION_MINIMUM:
198 rdev->pm.requested_clock_mode_index = 0;
199 rdev->pm.can_downclock = false;
201 case PM_ACTION_DOWNCLOCK:
202 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
203 if (rdev->pm.current_clock_mode_index == 0) {
204 rdev->pm.requested_clock_mode_index = 0;
205 rdev->pm.can_downclock = false;
207 rdev->pm.requested_clock_mode_index =
208 rdev->pm.current_clock_mode_index - 1;
210 rdev->pm.requested_clock_mode_index = 0;
211 rdev->pm.can_downclock = false;
214 case PM_ACTION_UPCLOCK:
215 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
216 if (rdev->pm.current_clock_mode_index ==
217 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
218 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
219 rdev->pm.can_upclock = false;
221 rdev->pm.requested_clock_mode_index =
222 rdev->pm.current_clock_mode_index + 1;
224 rdev->pm.requested_clock_mode_index =
225 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
226 rdev->pm.can_upclock = false;
229 case PM_ACTION_DEFAULT:
230 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
231 rdev->pm.requested_clock_mode_index = 0;
232 rdev->pm.can_upclock = false;
236 DRM_ERROR("Requested mode for not defined action\n");
241 DRM_INFO("Requested: e: %d m: %d p: %d\n",
242 rdev->pm.power_state[rdev->pm.requested_power_state_index].
243 clock_info[rdev->pm.requested_clock_mode_index].sclk,
244 rdev->pm.power_state[rdev->pm.requested_power_state_index].
245 clock_info[rdev->pm.requested_clock_mode_index].mclk,
246 rdev->pm.power_state[rdev->pm.requested_power_state_index].
250 void r600_set_power_state(struct radeon_device *rdev, bool static_switch)
254 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
255 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
258 if (radeon_gui_idle(rdev)) {
260 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
261 clock_info[rdev->pm.requested_clock_mode_index].sclk;
262 if (sclk > rdev->clock.default_sclk)
263 sclk = rdev->clock.default_sclk;
265 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
266 clock_info[rdev->pm.requested_clock_mode_index].mclk;
267 if (mclk > rdev->clock.default_mclk)
268 mclk = rdev->clock.default_mclk;
270 /* voltage, pcie lanes, etc.*/
271 radeon_pm_misc(rdev);
274 radeon_pm_prepare(rdev);
275 /* set engine clock */
276 if (sclk != rdev->pm.current_sclk) {
277 radeon_set_engine_clock(rdev, sclk);
278 rdev->pm.current_sclk = sclk;
279 DRM_INFO("Setting: e: %d\n", sclk);
282 /* set memory clock */
283 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
284 radeon_set_memory_clock(rdev, mclk);
285 rdev->pm.current_mclk = mclk;
286 DRM_INFO("Setting: m: %d\n", mclk);
289 radeon_pm_finish(rdev);
291 /* set engine clock */
292 if (sclk != rdev->pm.current_sclk) {
293 radeon_sync_with_vblank(rdev);
294 radeon_pm_debug_check_in_vbl(rdev, false);
295 radeon_set_engine_clock(rdev, sclk);
296 radeon_pm_debug_check_in_vbl(rdev, true);
297 rdev->pm.current_sclk = sclk;
298 DRM_INFO("Setting: e: %d\n", sclk);
302 /* set memory clock */
303 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
304 radeon_sync_with_vblank(rdev);
305 radeon_pm_debug_check_in_vbl(rdev, false);
306 radeon_pm_prepare(rdev);
307 radeon_set_memory_clock(rdev, mclk);
308 radeon_pm_finish(rdev);
309 radeon_pm_debug_check_in_vbl(rdev, true);
310 rdev->pm.current_mclk = mclk;
311 DRM_INFO("Setting: m: %d\n", mclk);
316 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
317 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
319 DRM_INFO("GUI not idle!!!\n");
322 void r600_pm_misc(struct radeon_device *rdev)
327 bool r600_gui_idle(struct radeon_device *rdev)
329 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
335 /* hpd for digital panel detect/disconnect */
336 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
338 bool connected = false;
340 if (ASIC_IS_DCE3(rdev)) {
343 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
347 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
351 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
355 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
360 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
364 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
373 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
377 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
381 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
391 void r600_hpd_set_polarity(struct radeon_device *rdev,
392 enum radeon_hpd_id hpd)
395 bool connected = r600_hpd_sense(rdev, hpd);
397 if (ASIC_IS_DCE3(rdev)) {
400 tmp = RREG32(DC_HPD1_INT_CONTROL);
402 tmp &= ~DC_HPDx_INT_POLARITY;
404 tmp |= DC_HPDx_INT_POLARITY;
405 WREG32(DC_HPD1_INT_CONTROL, tmp);
408 tmp = RREG32(DC_HPD2_INT_CONTROL);
410 tmp &= ~DC_HPDx_INT_POLARITY;
412 tmp |= DC_HPDx_INT_POLARITY;
413 WREG32(DC_HPD2_INT_CONTROL, tmp);
416 tmp = RREG32(DC_HPD3_INT_CONTROL);
418 tmp &= ~DC_HPDx_INT_POLARITY;
420 tmp |= DC_HPDx_INT_POLARITY;
421 WREG32(DC_HPD3_INT_CONTROL, tmp);
424 tmp = RREG32(DC_HPD4_INT_CONTROL);
426 tmp &= ~DC_HPDx_INT_POLARITY;
428 tmp |= DC_HPDx_INT_POLARITY;
429 WREG32(DC_HPD4_INT_CONTROL, tmp);
432 tmp = RREG32(DC_HPD5_INT_CONTROL);
434 tmp &= ~DC_HPDx_INT_POLARITY;
436 tmp |= DC_HPDx_INT_POLARITY;
437 WREG32(DC_HPD5_INT_CONTROL, tmp);
441 tmp = RREG32(DC_HPD6_INT_CONTROL);
443 tmp &= ~DC_HPDx_INT_POLARITY;
445 tmp |= DC_HPDx_INT_POLARITY;
446 WREG32(DC_HPD6_INT_CONTROL, tmp);
454 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
456 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
458 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
459 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
462 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
464 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
466 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
467 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
470 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
472 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
474 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
475 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
483 void r600_hpd_init(struct radeon_device *rdev)
485 struct drm_device *dev = rdev->ddev;
486 struct drm_connector *connector;
488 if (ASIC_IS_DCE3(rdev)) {
489 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
490 if (ASIC_IS_DCE32(rdev))
493 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
494 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
495 switch (radeon_connector->hpd.hpd) {
497 WREG32(DC_HPD1_CONTROL, tmp);
498 rdev->irq.hpd[0] = true;
501 WREG32(DC_HPD2_CONTROL, tmp);
502 rdev->irq.hpd[1] = true;
505 WREG32(DC_HPD3_CONTROL, tmp);
506 rdev->irq.hpd[2] = true;
509 WREG32(DC_HPD4_CONTROL, tmp);
510 rdev->irq.hpd[3] = true;
514 WREG32(DC_HPD5_CONTROL, tmp);
515 rdev->irq.hpd[4] = true;
518 WREG32(DC_HPD6_CONTROL, tmp);
519 rdev->irq.hpd[5] = true;
526 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
527 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
528 switch (radeon_connector->hpd.hpd) {
530 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
531 rdev->irq.hpd[0] = true;
534 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
535 rdev->irq.hpd[1] = true;
538 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
539 rdev->irq.hpd[2] = true;
546 if (rdev->irq.installed)
550 void r600_hpd_fini(struct radeon_device *rdev)
552 struct drm_device *dev = rdev->ddev;
553 struct drm_connector *connector;
555 if (ASIC_IS_DCE3(rdev)) {
556 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
557 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
558 switch (radeon_connector->hpd.hpd) {
560 WREG32(DC_HPD1_CONTROL, 0);
561 rdev->irq.hpd[0] = false;
564 WREG32(DC_HPD2_CONTROL, 0);
565 rdev->irq.hpd[1] = false;
568 WREG32(DC_HPD3_CONTROL, 0);
569 rdev->irq.hpd[2] = false;
572 WREG32(DC_HPD4_CONTROL, 0);
573 rdev->irq.hpd[3] = false;
577 WREG32(DC_HPD5_CONTROL, 0);
578 rdev->irq.hpd[4] = false;
581 WREG32(DC_HPD6_CONTROL, 0);
582 rdev->irq.hpd[5] = false;
589 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
590 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
591 switch (radeon_connector->hpd.hpd) {
593 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
594 rdev->irq.hpd[0] = false;
597 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
598 rdev->irq.hpd[1] = false;
601 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
602 rdev->irq.hpd[2] = false;
614 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
619 /* flush hdp cache so updates hit vram */
620 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
622 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
623 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
624 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
625 for (i = 0; i < rdev->usec_timeout; i++) {
627 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
628 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
630 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
640 int r600_pcie_gart_init(struct radeon_device *rdev)
644 if (rdev->gart.table.vram.robj) {
645 WARN(1, "R600 PCIE GART already initialized.\n");
648 /* Initialize common gart structure */
649 r = radeon_gart_init(rdev);
652 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
653 return radeon_gart_table_vram_alloc(rdev);
656 int r600_pcie_gart_enable(struct radeon_device *rdev)
661 if (rdev->gart.table.vram.robj == NULL) {
662 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
665 r = radeon_gart_table_vram_pin(rdev);
668 radeon_gart_restore(rdev);
671 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
672 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
673 EFFECTIVE_L2_QUEUE_SIZE(7));
674 WREG32(VM_L2_CNTL2, 0);
675 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
676 /* Setup TLB control */
677 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
678 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
679 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
680 ENABLE_WAIT_L2_QUERY;
681 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
682 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
683 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
684 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
685 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
686 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
687 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
688 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
689 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
690 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
691 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
692 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
693 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
694 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
695 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
696 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
697 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
698 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
699 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
700 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
701 (u32)(rdev->dummy_page.addr >> 12));
702 for (i = 1; i < 7; i++)
703 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
705 r600_pcie_gart_tlb_flush(rdev);
706 rdev->gart.ready = true;
710 void r600_pcie_gart_disable(struct radeon_device *rdev)
715 /* Disable all tables */
716 for (i = 0; i < 7; i++)
717 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
719 /* Disable L2 cache */
720 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
721 EFFECTIVE_L2_QUEUE_SIZE(7));
722 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
723 /* Setup L1 TLB control */
724 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
725 ENABLE_WAIT_L2_QUERY;
726 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
727 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
728 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
729 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
730 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
731 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
732 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
733 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
734 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
735 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
736 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
737 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
738 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
739 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
740 if (rdev->gart.table.vram.robj) {
741 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
742 if (likely(r == 0)) {
743 radeon_bo_kunmap(rdev->gart.table.vram.robj);
744 radeon_bo_unpin(rdev->gart.table.vram.robj);
745 radeon_bo_unreserve(rdev->gart.table.vram.robj);
750 void r600_pcie_gart_fini(struct radeon_device *rdev)
752 radeon_gart_fini(rdev);
753 r600_pcie_gart_disable(rdev);
754 radeon_gart_table_vram_free(rdev);
757 void r600_agp_enable(struct radeon_device *rdev)
763 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
764 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
765 EFFECTIVE_L2_QUEUE_SIZE(7));
766 WREG32(VM_L2_CNTL2, 0);
767 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
768 /* Setup TLB control */
769 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
770 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
771 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
772 ENABLE_WAIT_L2_QUERY;
773 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
774 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
775 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
776 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
777 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
778 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
779 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
780 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
781 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
782 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
783 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
784 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
785 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
786 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
787 for (i = 0; i < 7; i++)
788 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
791 int r600_mc_wait_for_idle(struct radeon_device *rdev)
796 for (i = 0; i < rdev->usec_timeout; i++) {
798 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
806 static void r600_mc_program(struct radeon_device *rdev)
808 struct rv515_mc_save save;
813 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
814 WREG32((0x2c14 + j), 0x00000000);
815 WREG32((0x2c18 + j), 0x00000000);
816 WREG32((0x2c1c + j), 0x00000000);
817 WREG32((0x2c20 + j), 0x00000000);
818 WREG32((0x2c24 + j), 0x00000000);
820 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
822 rv515_mc_stop(rdev, &save);
823 if (r600_mc_wait_for_idle(rdev)) {
824 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
826 /* Lockout access through VGA aperture (doesn't exist before R600) */
827 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
828 /* Update configuration */
829 if (rdev->flags & RADEON_IS_AGP) {
830 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
831 /* VRAM before AGP */
832 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
833 rdev->mc.vram_start >> 12);
834 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
835 rdev->mc.gtt_end >> 12);
838 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
839 rdev->mc.gtt_start >> 12);
840 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
841 rdev->mc.vram_end >> 12);
844 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
845 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
847 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
848 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
849 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
850 WREG32(MC_VM_FB_LOCATION, tmp);
851 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
852 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
853 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
854 if (rdev->flags & RADEON_IS_AGP) {
855 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
856 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
857 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
859 WREG32(MC_VM_AGP_BASE, 0);
860 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
861 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
863 if (r600_mc_wait_for_idle(rdev)) {
864 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
866 rv515_mc_resume(rdev, &save);
867 /* we need to own VRAM, so turn off the VGA renderer here
868 * to stop it overwriting our objects */
869 rv515_vga_render_disable(rdev);
873 * r600_vram_gtt_location - try to find VRAM & GTT location
874 * @rdev: radeon device structure holding all necessary informations
875 * @mc: memory controller structure holding memory informations
877 * Function will place try to place VRAM at same place as in CPU (PCI)
878 * address space as some GPU seems to have issue when we reprogram at
879 * different address space.
881 * If there is not enough space to fit the unvisible VRAM after the
882 * aperture then we limit the VRAM size to the aperture.
884 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
885 * them to be in one from GPU point of view so that we can program GPU to
886 * catch access outside them (weird GPU policy see ??).
888 * This function will never fails, worst case are limiting VRAM or GTT.
890 * Note: GTT start, end, size should be initialized before calling this
891 * function on AGP platform.
893 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
895 u64 size_bf, size_af;
897 if (mc->mc_vram_size > 0xE0000000) {
898 /* leave room for at least 512M GTT */
899 dev_warn(rdev->dev, "limiting VRAM\n");
900 mc->real_vram_size = 0xE0000000;
901 mc->mc_vram_size = 0xE0000000;
903 if (rdev->flags & RADEON_IS_AGP) {
904 size_bf = mc->gtt_start;
905 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
906 if (size_bf > size_af) {
907 if (mc->mc_vram_size > size_bf) {
908 dev_warn(rdev->dev, "limiting VRAM\n");
909 mc->real_vram_size = size_bf;
910 mc->mc_vram_size = size_bf;
912 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
914 if (mc->mc_vram_size > size_af) {
915 dev_warn(rdev->dev, "limiting VRAM\n");
916 mc->real_vram_size = size_af;
917 mc->mc_vram_size = size_af;
919 mc->vram_start = mc->gtt_end;
921 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
922 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
923 mc->mc_vram_size >> 20, mc->vram_start,
924 mc->vram_end, mc->real_vram_size >> 20);
927 if (rdev->flags & RADEON_IS_IGP)
928 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
929 radeon_vram_location(rdev, &rdev->mc, base);
930 radeon_gtt_location(rdev, mc);
934 int r600_mc_init(struct radeon_device *rdev)
937 int chansize, numchan;
939 /* Get VRAM informations */
940 rdev->mc.vram_is_ddr = true;
941 tmp = RREG32(RAMCFG);
942 if (tmp & CHANSIZE_OVERRIDE) {
944 } else if (tmp & CHANSIZE_MASK) {
950 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
965 rdev->mc.vram_width = numchan * chansize;
966 /* Could aper size report 0 ? */
967 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
968 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
969 /* Setup GPU memory space */
970 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
971 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
972 rdev->mc.visible_vram_size = rdev->mc.aper_size;
973 r600_vram_gtt_location(rdev, &rdev->mc);
975 if (rdev->flags & RADEON_IS_IGP)
976 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
977 radeon_update_bandwidth_info(rdev);
981 /* We doesn't check that the GPU really needs a reset we simply do the
982 * reset, it's up to the caller to determine if the GPU needs one. We
983 * might add an helper function to check that.
985 int r600_gpu_soft_reset(struct radeon_device *rdev)
987 struct rv515_mc_save save;
988 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
989 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
990 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
991 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
992 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
993 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
994 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
995 S_008010_GUI_ACTIVE(1);
996 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
997 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
998 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
999 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1000 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1001 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1002 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1003 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1006 dev_info(rdev->dev, "GPU softreset \n");
1007 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1008 RREG32(R_008010_GRBM_STATUS));
1009 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1010 RREG32(R_008014_GRBM_STATUS2));
1011 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1012 RREG32(R_000E50_SRBM_STATUS));
1013 rv515_mc_stop(rdev, &save);
1014 if (r600_mc_wait_for_idle(rdev)) {
1015 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1017 /* Disable CP parsing/prefetching */
1018 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1019 /* Check if any of the rendering block is busy and reset it */
1020 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1021 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1022 tmp = S_008020_SOFT_RESET_CR(1) |
1023 S_008020_SOFT_RESET_DB(1) |
1024 S_008020_SOFT_RESET_CB(1) |
1025 S_008020_SOFT_RESET_PA(1) |
1026 S_008020_SOFT_RESET_SC(1) |
1027 S_008020_SOFT_RESET_SMX(1) |
1028 S_008020_SOFT_RESET_SPI(1) |
1029 S_008020_SOFT_RESET_SX(1) |
1030 S_008020_SOFT_RESET_SH(1) |
1031 S_008020_SOFT_RESET_TC(1) |
1032 S_008020_SOFT_RESET_TA(1) |
1033 S_008020_SOFT_RESET_VC(1) |
1034 S_008020_SOFT_RESET_VGT(1);
1035 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1036 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1037 RREG32(R_008020_GRBM_SOFT_RESET);
1039 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1041 /* Reset CP (we always reset CP) */
1042 tmp = S_008020_SOFT_RESET_CP(1);
1043 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1044 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1045 RREG32(R_008020_GRBM_SOFT_RESET);
1047 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1048 /* Wait a little for things to settle down */
1050 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1051 RREG32(R_008010_GRBM_STATUS));
1052 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1053 RREG32(R_008014_GRBM_STATUS2));
1054 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1055 RREG32(R_000E50_SRBM_STATUS));
1056 rv515_mc_resume(rdev, &save);
1060 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1067 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1068 grbm_status = RREG32(R_008010_GRBM_STATUS);
1069 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1070 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1071 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1074 /* force CP activities */
1075 r = radeon_ring_lock(rdev, 2);
1078 radeon_ring_write(rdev, 0x80000000);
1079 radeon_ring_write(rdev, 0x80000000);
1080 radeon_ring_unlock_commit(rdev);
1082 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1083 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1086 int r600_asic_reset(struct radeon_device *rdev)
1088 return r600_gpu_soft_reset(rdev);
1091 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1093 u32 backend_disable_mask)
1095 u32 backend_map = 0;
1096 u32 enabled_backends_mask;
1097 u32 enabled_backends_count;
1099 u32 swizzle_pipe[R6XX_MAX_PIPES];
1103 if (num_tile_pipes > R6XX_MAX_PIPES)
1104 num_tile_pipes = R6XX_MAX_PIPES;
1105 if (num_tile_pipes < 1)
1107 if (num_backends > R6XX_MAX_BACKENDS)
1108 num_backends = R6XX_MAX_BACKENDS;
1109 if (num_backends < 1)
1112 enabled_backends_mask = 0;
1113 enabled_backends_count = 0;
1114 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1115 if (((backend_disable_mask >> i) & 1) == 0) {
1116 enabled_backends_mask |= (1 << i);
1117 ++enabled_backends_count;
1119 if (enabled_backends_count == num_backends)
1123 if (enabled_backends_count == 0) {
1124 enabled_backends_mask = 1;
1125 enabled_backends_count = 1;
1128 if (enabled_backends_count != num_backends)
1129 num_backends = enabled_backends_count;
1131 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1132 switch (num_tile_pipes) {
1134 swizzle_pipe[0] = 0;
1137 swizzle_pipe[0] = 0;
1138 swizzle_pipe[1] = 1;
1141 swizzle_pipe[0] = 0;
1142 swizzle_pipe[1] = 1;
1143 swizzle_pipe[2] = 2;
1146 swizzle_pipe[0] = 0;
1147 swizzle_pipe[1] = 1;
1148 swizzle_pipe[2] = 2;
1149 swizzle_pipe[3] = 3;
1152 swizzle_pipe[0] = 0;
1153 swizzle_pipe[1] = 1;
1154 swizzle_pipe[2] = 2;
1155 swizzle_pipe[3] = 3;
1156 swizzle_pipe[4] = 4;
1159 swizzle_pipe[0] = 0;
1160 swizzle_pipe[1] = 2;
1161 swizzle_pipe[2] = 4;
1162 swizzle_pipe[3] = 5;
1163 swizzle_pipe[4] = 1;
1164 swizzle_pipe[5] = 3;
1167 swizzle_pipe[0] = 0;
1168 swizzle_pipe[1] = 2;
1169 swizzle_pipe[2] = 4;
1170 swizzle_pipe[3] = 6;
1171 swizzle_pipe[4] = 1;
1172 swizzle_pipe[5] = 3;
1173 swizzle_pipe[6] = 5;
1176 swizzle_pipe[0] = 0;
1177 swizzle_pipe[1] = 2;
1178 swizzle_pipe[2] = 4;
1179 swizzle_pipe[3] = 6;
1180 swizzle_pipe[4] = 1;
1181 swizzle_pipe[5] = 3;
1182 swizzle_pipe[6] = 5;
1183 swizzle_pipe[7] = 7;
1188 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1189 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1190 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1192 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1194 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1200 int r600_count_pipe_bits(uint32_t val)
1204 for (i = 0; i < 32; i++) {
1211 void r600_gpu_init(struct radeon_device *rdev)
1216 u32 cc_rb_backend_disable;
1217 u32 cc_gc_shader_pipe_config;
1221 u32 sq_gpr_resource_mgmt_1 = 0;
1222 u32 sq_gpr_resource_mgmt_2 = 0;
1223 u32 sq_thread_resource_mgmt = 0;
1224 u32 sq_stack_resource_mgmt_1 = 0;
1225 u32 sq_stack_resource_mgmt_2 = 0;
1227 /* FIXME: implement */
1228 switch (rdev->family) {
1230 rdev->config.r600.max_pipes = 4;
1231 rdev->config.r600.max_tile_pipes = 8;
1232 rdev->config.r600.max_simds = 4;
1233 rdev->config.r600.max_backends = 4;
1234 rdev->config.r600.max_gprs = 256;
1235 rdev->config.r600.max_threads = 192;
1236 rdev->config.r600.max_stack_entries = 256;
1237 rdev->config.r600.max_hw_contexts = 8;
1238 rdev->config.r600.max_gs_threads = 16;
1239 rdev->config.r600.sx_max_export_size = 128;
1240 rdev->config.r600.sx_max_export_pos_size = 16;
1241 rdev->config.r600.sx_max_export_smx_size = 128;
1242 rdev->config.r600.sq_num_cf_insts = 2;
1246 rdev->config.r600.max_pipes = 2;
1247 rdev->config.r600.max_tile_pipes = 2;
1248 rdev->config.r600.max_simds = 3;
1249 rdev->config.r600.max_backends = 1;
1250 rdev->config.r600.max_gprs = 128;
1251 rdev->config.r600.max_threads = 192;
1252 rdev->config.r600.max_stack_entries = 128;
1253 rdev->config.r600.max_hw_contexts = 8;
1254 rdev->config.r600.max_gs_threads = 4;
1255 rdev->config.r600.sx_max_export_size = 128;
1256 rdev->config.r600.sx_max_export_pos_size = 16;
1257 rdev->config.r600.sx_max_export_smx_size = 128;
1258 rdev->config.r600.sq_num_cf_insts = 2;
1264 rdev->config.r600.max_pipes = 1;
1265 rdev->config.r600.max_tile_pipes = 1;
1266 rdev->config.r600.max_simds = 2;
1267 rdev->config.r600.max_backends = 1;
1268 rdev->config.r600.max_gprs = 128;
1269 rdev->config.r600.max_threads = 192;
1270 rdev->config.r600.max_stack_entries = 128;
1271 rdev->config.r600.max_hw_contexts = 4;
1272 rdev->config.r600.max_gs_threads = 4;
1273 rdev->config.r600.sx_max_export_size = 128;
1274 rdev->config.r600.sx_max_export_pos_size = 16;
1275 rdev->config.r600.sx_max_export_smx_size = 128;
1276 rdev->config.r600.sq_num_cf_insts = 1;
1279 rdev->config.r600.max_pipes = 4;
1280 rdev->config.r600.max_tile_pipes = 4;
1281 rdev->config.r600.max_simds = 4;
1282 rdev->config.r600.max_backends = 4;
1283 rdev->config.r600.max_gprs = 192;
1284 rdev->config.r600.max_threads = 192;
1285 rdev->config.r600.max_stack_entries = 256;
1286 rdev->config.r600.max_hw_contexts = 8;
1287 rdev->config.r600.max_gs_threads = 16;
1288 rdev->config.r600.sx_max_export_size = 128;
1289 rdev->config.r600.sx_max_export_pos_size = 16;
1290 rdev->config.r600.sx_max_export_smx_size = 128;
1291 rdev->config.r600.sq_num_cf_insts = 2;
1297 /* Initialize HDP */
1298 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1299 WREG32((0x2c14 + j), 0x00000000);
1300 WREG32((0x2c18 + j), 0x00000000);
1301 WREG32((0x2c1c + j), 0x00000000);
1302 WREG32((0x2c20 + j), 0x00000000);
1303 WREG32((0x2c24 + j), 0x00000000);
1306 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1310 ramcfg = RREG32(RAMCFG);
1311 switch (rdev->config.r600.max_tile_pipes) {
1313 tiling_config |= PIPE_TILING(0);
1316 tiling_config |= PIPE_TILING(1);
1319 tiling_config |= PIPE_TILING(2);
1322 tiling_config |= PIPE_TILING(3);
1327 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1328 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1329 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1330 tiling_config |= GROUP_SIZE(0);
1331 rdev->config.r600.tiling_group_size = 256;
1332 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1334 tiling_config |= ROW_TILING(3);
1335 tiling_config |= SAMPLE_SPLIT(3);
1337 tiling_config |= ROW_TILING(tmp);
1338 tiling_config |= SAMPLE_SPLIT(tmp);
1340 tiling_config |= BANK_SWAPS(1);
1342 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1343 cc_rb_backend_disable |=
1344 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1346 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1347 cc_gc_shader_pipe_config |=
1348 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1349 cc_gc_shader_pipe_config |=
1350 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1352 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1353 (R6XX_MAX_BACKENDS -
1354 r600_count_pipe_bits((cc_rb_backend_disable &
1355 R6XX_MAX_BACKENDS_MASK) >> 16)),
1356 (cc_rb_backend_disable >> 16));
1358 tiling_config |= BACKEND_MAP(backend_map);
1359 WREG32(GB_TILING_CONFIG, tiling_config);
1360 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1361 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1364 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1365 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1366 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1368 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1369 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1370 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1372 /* Setup some CP states */
1373 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1374 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1376 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1377 SYNC_WALKER | SYNC_ALIGNER));
1378 /* Setup various GPU states */
1379 if (rdev->family == CHIP_RV670)
1380 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1382 tmp = RREG32(SX_DEBUG_1);
1383 tmp |= SMX_EVENT_RELEASE;
1384 if ((rdev->family > CHIP_R600))
1385 tmp |= ENABLE_NEW_SMX_ADDRESS;
1386 WREG32(SX_DEBUG_1, tmp);
1388 if (((rdev->family) == CHIP_R600) ||
1389 ((rdev->family) == CHIP_RV630) ||
1390 ((rdev->family) == CHIP_RV610) ||
1391 ((rdev->family) == CHIP_RV620) ||
1392 ((rdev->family) == CHIP_RS780) ||
1393 ((rdev->family) == CHIP_RS880)) {
1394 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1396 WREG32(DB_DEBUG, 0);
1398 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1399 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1401 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1402 WREG32(VGT_NUM_INSTANCES, 0);
1404 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1405 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1407 tmp = RREG32(SQ_MS_FIFO_SIZES);
1408 if (((rdev->family) == CHIP_RV610) ||
1409 ((rdev->family) == CHIP_RV620) ||
1410 ((rdev->family) == CHIP_RS780) ||
1411 ((rdev->family) == CHIP_RS880)) {
1412 tmp = (CACHE_FIFO_SIZE(0xa) |
1413 FETCH_FIFO_HIWATER(0xa) |
1414 DONE_FIFO_HIWATER(0xe0) |
1415 ALU_UPDATE_FIFO_HIWATER(0x8));
1416 } else if (((rdev->family) == CHIP_R600) ||
1417 ((rdev->family) == CHIP_RV630)) {
1418 tmp &= ~DONE_FIFO_HIWATER(0xff);
1419 tmp |= DONE_FIFO_HIWATER(0x4);
1421 WREG32(SQ_MS_FIFO_SIZES, tmp);
1423 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1424 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1426 sq_config = RREG32(SQ_CONFIG);
1427 sq_config &= ~(PS_PRIO(3) |
1431 sq_config |= (DX9_CONSTS |
1438 if ((rdev->family) == CHIP_R600) {
1439 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1441 NUM_CLAUSE_TEMP_GPRS(4));
1442 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1444 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1445 NUM_VS_THREADS(48) |
1448 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1449 NUM_VS_STACK_ENTRIES(128));
1450 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1451 NUM_ES_STACK_ENTRIES(0));
1452 } else if (((rdev->family) == CHIP_RV610) ||
1453 ((rdev->family) == CHIP_RV620) ||
1454 ((rdev->family) == CHIP_RS780) ||
1455 ((rdev->family) == CHIP_RS880)) {
1456 /* no vertex cache */
1457 sq_config &= ~VC_ENABLE;
1459 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1461 NUM_CLAUSE_TEMP_GPRS(2));
1462 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1464 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1465 NUM_VS_THREADS(78) |
1467 NUM_ES_THREADS(31));
1468 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1469 NUM_VS_STACK_ENTRIES(40));
1470 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1471 NUM_ES_STACK_ENTRIES(16));
1472 } else if (((rdev->family) == CHIP_RV630) ||
1473 ((rdev->family) == CHIP_RV635)) {
1474 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1476 NUM_CLAUSE_TEMP_GPRS(2));
1477 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1479 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1480 NUM_VS_THREADS(78) |
1482 NUM_ES_THREADS(31));
1483 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1484 NUM_VS_STACK_ENTRIES(40));
1485 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1486 NUM_ES_STACK_ENTRIES(16));
1487 } else if ((rdev->family) == CHIP_RV670) {
1488 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1490 NUM_CLAUSE_TEMP_GPRS(2));
1491 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1493 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1494 NUM_VS_THREADS(78) |
1496 NUM_ES_THREADS(31));
1497 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1498 NUM_VS_STACK_ENTRIES(64));
1499 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1500 NUM_ES_STACK_ENTRIES(64));
1503 WREG32(SQ_CONFIG, sq_config);
1504 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1505 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1506 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1507 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1508 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1510 if (((rdev->family) == CHIP_RV610) ||
1511 ((rdev->family) == CHIP_RV620) ||
1512 ((rdev->family) == CHIP_RS780) ||
1513 ((rdev->family) == CHIP_RS880)) {
1514 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1516 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1519 /* More default values. 2D/3D driver should adjust as needed */
1520 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1521 S1_X(0x4) | S1_Y(0xc)));
1522 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1523 S1_X(0x2) | S1_Y(0x2) |
1524 S2_X(0xa) | S2_Y(0x6) |
1525 S3_X(0x6) | S3_Y(0xa)));
1526 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1527 S1_X(0x4) | S1_Y(0xc) |
1528 S2_X(0x1) | S2_Y(0x6) |
1529 S3_X(0xa) | S3_Y(0xe)));
1530 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1531 S5_X(0x0) | S5_Y(0x0) |
1532 S6_X(0xb) | S6_Y(0x4) |
1533 S7_X(0x7) | S7_Y(0x8)));
1535 WREG32(VGT_STRMOUT_EN, 0);
1536 tmp = rdev->config.r600.max_pipes * 16;
1537 switch (rdev->family) {
1553 WREG32(VGT_ES_PER_GS, 128);
1554 WREG32(VGT_GS_PER_ES, tmp);
1555 WREG32(VGT_GS_PER_VS, 2);
1556 WREG32(VGT_GS_VERTEX_REUSE, 16);
1558 /* more default values. 2D/3D driver should adjust as needed */
1559 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1560 WREG32(VGT_STRMOUT_EN, 0);
1562 WREG32(PA_SC_MODE_CNTL, 0);
1563 WREG32(PA_SC_AA_CONFIG, 0);
1564 WREG32(PA_SC_LINE_STIPPLE, 0);
1565 WREG32(SPI_INPUT_Z, 0);
1566 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1567 WREG32(CB_COLOR7_FRAG, 0);
1569 /* Clear render buffer base addresses */
1570 WREG32(CB_COLOR0_BASE, 0);
1571 WREG32(CB_COLOR1_BASE, 0);
1572 WREG32(CB_COLOR2_BASE, 0);
1573 WREG32(CB_COLOR3_BASE, 0);
1574 WREG32(CB_COLOR4_BASE, 0);
1575 WREG32(CB_COLOR5_BASE, 0);
1576 WREG32(CB_COLOR6_BASE, 0);
1577 WREG32(CB_COLOR7_BASE, 0);
1578 WREG32(CB_COLOR7_FRAG, 0);
1580 switch (rdev->family) {
1585 tmp = TC_L2_SIZE(8);
1589 tmp = TC_L2_SIZE(4);
1592 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1595 tmp = TC_L2_SIZE(0);
1598 WREG32(TC_CNTL, tmp);
1600 tmp = RREG32(HDP_HOST_PATH_CNTL);
1601 WREG32(HDP_HOST_PATH_CNTL, tmp);
1603 tmp = RREG32(ARB_POP);
1604 tmp |= ENABLE_TC128;
1605 WREG32(ARB_POP, tmp);
1607 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1608 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1610 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1615 * Indirect registers accessor
1617 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1621 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1622 (void)RREG32(PCIE_PORT_INDEX);
1623 r = RREG32(PCIE_PORT_DATA);
1627 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1629 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1630 (void)RREG32(PCIE_PORT_INDEX);
1631 WREG32(PCIE_PORT_DATA, (v));
1632 (void)RREG32(PCIE_PORT_DATA);
1638 void r600_cp_stop(struct radeon_device *rdev)
1640 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1643 int r600_init_microcode(struct radeon_device *rdev)
1645 struct platform_device *pdev;
1646 const char *chip_name;
1647 const char *rlc_chip_name;
1648 size_t pfp_req_size, me_req_size, rlc_req_size;
1654 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1657 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1661 switch (rdev->family) {
1664 rlc_chip_name = "R600";
1667 chip_name = "RV610";
1668 rlc_chip_name = "R600";
1671 chip_name = "RV630";
1672 rlc_chip_name = "R600";
1675 chip_name = "RV620";
1676 rlc_chip_name = "R600";
1679 chip_name = "RV635";
1680 rlc_chip_name = "R600";
1683 chip_name = "RV670";
1684 rlc_chip_name = "R600";
1688 chip_name = "RS780";
1689 rlc_chip_name = "R600";
1692 chip_name = "RV770";
1693 rlc_chip_name = "R700";
1697 chip_name = "RV730";
1698 rlc_chip_name = "R700";
1701 chip_name = "RV710";
1702 rlc_chip_name = "R700";
1705 chip_name = "CEDAR";
1706 rlc_chip_name = "CEDAR";
1709 chip_name = "REDWOOD";
1710 rlc_chip_name = "REDWOOD";
1713 chip_name = "JUNIPER";
1714 rlc_chip_name = "JUNIPER";
1718 chip_name = "CYPRESS";
1719 rlc_chip_name = "CYPRESS";
1724 if (rdev->family >= CHIP_CEDAR) {
1725 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1726 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1727 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1728 } else if (rdev->family >= CHIP_RV770) {
1729 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1730 me_req_size = R700_PM4_UCODE_SIZE * 4;
1731 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1733 pfp_req_size = PFP_UCODE_SIZE * 4;
1734 me_req_size = PM4_UCODE_SIZE * 12;
1735 rlc_req_size = RLC_UCODE_SIZE * 4;
1738 DRM_INFO("Loading %s Microcode\n", chip_name);
1740 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1741 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1744 if (rdev->pfp_fw->size != pfp_req_size) {
1746 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1747 rdev->pfp_fw->size, fw_name);
1752 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1753 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1756 if (rdev->me_fw->size != me_req_size) {
1758 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1759 rdev->me_fw->size, fw_name);
1763 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1764 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1767 if (rdev->rlc_fw->size != rlc_req_size) {
1769 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1770 rdev->rlc_fw->size, fw_name);
1775 platform_device_unregister(pdev);
1780 "r600_cp: Failed to load firmware \"%s\"\n",
1782 release_firmware(rdev->pfp_fw);
1783 rdev->pfp_fw = NULL;
1784 release_firmware(rdev->me_fw);
1786 release_firmware(rdev->rlc_fw);
1787 rdev->rlc_fw = NULL;
1792 static int r600_cp_load_microcode(struct radeon_device *rdev)
1794 const __be32 *fw_data;
1797 if (!rdev->me_fw || !rdev->pfp_fw)
1802 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1805 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1806 RREG32(GRBM_SOFT_RESET);
1808 WREG32(GRBM_SOFT_RESET, 0);
1810 WREG32(CP_ME_RAM_WADDR, 0);
1812 fw_data = (const __be32 *)rdev->me_fw->data;
1813 WREG32(CP_ME_RAM_WADDR, 0);
1814 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1815 WREG32(CP_ME_RAM_DATA,
1816 be32_to_cpup(fw_data++));
1818 fw_data = (const __be32 *)rdev->pfp_fw->data;
1819 WREG32(CP_PFP_UCODE_ADDR, 0);
1820 for (i = 0; i < PFP_UCODE_SIZE; i++)
1821 WREG32(CP_PFP_UCODE_DATA,
1822 be32_to_cpup(fw_data++));
1824 WREG32(CP_PFP_UCODE_ADDR, 0);
1825 WREG32(CP_ME_RAM_WADDR, 0);
1826 WREG32(CP_ME_RAM_RADDR, 0);
1830 int r600_cp_start(struct radeon_device *rdev)
1835 r = radeon_ring_lock(rdev, 7);
1837 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1840 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1841 radeon_ring_write(rdev, 0x1);
1842 if (rdev->family >= CHIP_CEDAR) {
1843 radeon_ring_write(rdev, 0x0);
1844 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1845 } else if (rdev->family >= CHIP_RV770) {
1846 radeon_ring_write(rdev, 0x0);
1847 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1849 radeon_ring_write(rdev, 0x3);
1850 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1852 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1853 radeon_ring_write(rdev, 0);
1854 radeon_ring_write(rdev, 0);
1855 radeon_ring_unlock_commit(rdev);
1858 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1862 int r600_cp_resume(struct radeon_device *rdev)
1869 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1870 RREG32(GRBM_SOFT_RESET);
1872 WREG32(GRBM_SOFT_RESET, 0);
1874 /* Set ring buffer size */
1875 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1876 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1878 tmp |= BUF_SWAP_32BIT;
1880 WREG32(CP_RB_CNTL, tmp);
1881 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1883 /* Set the write pointer delay */
1884 WREG32(CP_RB_WPTR_DELAY, 0);
1886 /* Initialize the ring buffer's read and write pointers */
1887 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1888 WREG32(CP_RB_RPTR_WR, 0);
1889 WREG32(CP_RB_WPTR, 0);
1890 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1891 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1893 WREG32(CP_RB_CNTL, tmp);
1895 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1896 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1898 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1899 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1901 r600_cp_start(rdev);
1902 rdev->cp.ready = true;
1903 r = radeon_ring_test(rdev);
1905 rdev->cp.ready = false;
1911 void r600_cp_commit(struct radeon_device *rdev)
1913 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1914 (void)RREG32(CP_RB_WPTR);
1917 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1921 /* Align ring size */
1922 rb_bufsz = drm_order(ring_size / 8);
1923 ring_size = (1 << (rb_bufsz + 1)) * 4;
1924 rdev->cp.ring_size = ring_size;
1925 rdev->cp.align_mask = 16 - 1;
1928 void r600_cp_fini(struct radeon_device *rdev)
1931 radeon_ring_fini(rdev);
1936 * GPU scratch registers helpers function.
1938 void r600_scratch_init(struct radeon_device *rdev)
1942 rdev->scratch.num_reg = 7;
1943 for (i = 0; i < rdev->scratch.num_reg; i++) {
1944 rdev->scratch.free[i] = true;
1945 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1949 int r600_ring_test(struct radeon_device *rdev)
1956 r = radeon_scratch_get(rdev, &scratch);
1958 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1961 WREG32(scratch, 0xCAFEDEAD);
1962 r = radeon_ring_lock(rdev, 3);
1964 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1965 radeon_scratch_free(rdev, scratch);
1968 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1969 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1970 radeon_ring_write(rdev, 0xDEADBEEF);
1971 radeon_ring_unlock_commit(rdev);
1972 for (i = 0; i < rdev->usec_timeout; i++) {
1973 tmp = RREG32(scratch);
1974 if (tmp == 0xDEADBEEF)
1978 if (i < rdev->usec_timeout) {
1979 DRM_INFO("ring test succeeded in %d usecs\n", i);
1981 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1985 radeon_scratch_free(rdev, scratch);
1989 void r600_wb_disable(struct radeon_device *rdev)
1993 WREG32(SCRATCH_UMSK, 0);
1994 if (rdev->wb.wb_obj) {
1995 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1996 if (unlikely(r != 0))
1998 radeon_bo_kunmap(rdev->wb.wb_obj);
1999 radeon_bo_unpin(rdev->wb.wb_obj);
2000 radeon_bo_unreserve(rdev->wb.wb_obj);
2004 void r600_wb_fini(struct radeon_device *rdev)
2006 r600_wb_disable(rdev);
2007 if (rdev->wb.wb_obj) {
2008 radeon_bo_unref(&rdev->wb.wb_obj);
2010 rdev->wb.wb_obj = NULL;
2014 int r600_wb_enable(struct radeon_device *rdev)
2018 if (rdev->wb.wb_obj == NULL) {
2019 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2020 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2022 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2025 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2026 if (unlikely(r != 0)) {
2030 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2031 &rdev->wb.gpu_addr);
2033 radeon_bo_unreserve(rdev->wb.wb_obj);
2034 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2038 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2039 radeon_bo_unreserve(rdev->wb.wb_obj);
2041 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2046 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2047 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2048 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2049 WREG32(SCRATCH_UMSK, 0xff);
2053 void r600_fence_ring_emit(struct radeon_device *rdev,
2054 struct radeon_fence *fence)
2056 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
2058 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2059 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2060 /* wait for 3D idle clean */
2061 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2062 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2063 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2064 /* Emit fence sequence & fire IRQ */
2065 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2066 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2067 radeon_ring_write(rdev, fence->seq);
2068 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2069 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2070 radeon_ring_write(rdev, RB_INT_STAT);
2073 int r600_copy_blit(struct radeon_device *rdev,
2074 uint64_t src_offset, uint64_t dst_offset,
2075 unsigned num_pages, struct radeon_fence *fence)
2079 mutex_lock(&rdev->r600_blit.mutex);
2080 rdev->r600_blit.vb_ib = NULL;
2081 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2083 if (rdev->r600_blit.vb_ib)
2084 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2085 mutex_unlock(&rdev->r600_blit.mutex);
2088 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2089 r600_blit_done_copy(rdev, fence);
2090 mutex_unlock(&rdev->r600_blit.mutex);
2094 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2095 uint32_t tiling_flags, uint32_t pitch,
2096 uint32_t offset, uint32_t obj_size)
2098 /* FIXME: implement */
2102 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2104 /* FIXME: implement */
2108 bool r600_card_posted(struct radeon_device *rdev)
2112 /* first check CRTCs */
2113 reg = RREG32(D1CRTC_CONTROL) |
2114 RREG32(D2CRTC_CONTROL);
2118 /* then check MEM_SIZE, in case the crtcs are off */
2119 if (RREG32(CONFIG_MEMSIZE))
2125 int r600_startup(struct radeon_device *rdev)
2129 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2130 r = r600_init_microcode(rdev);
2132 DRM_ERROR("Failed to load firmware!\n");
2137 r600_mc_program(rdev);
2138 if (rdev->flags & RADEON_IS_AGP) {
2139 r600_agp_enable(rdev);
2141 r = r600_pcie_gart_enable(rdev);
2145 r600_gpu_init(rdev);
2146 r = r600_blit_init(rdev);
2148 r600_blit_fini(rdev);
2149 rdev->asic->copy = NULL;
2150 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2152 /* pin copy shader into vram */
2153 if (rdev->r600_blit.shader_obj) {
2154 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2155 if (unlikely(r != 0))
2157 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2158 &rdev->r600_blit.shader_gpu_addr);
2159 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2161 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2166 r = r600_irq_init(rdev);
2168 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2169 radeon_irq_kms_fini(rdev);
2174 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2177 r = r600_cp_load_microcode(rdev);
2180 r = r600_cp_resume(rdev);
2183 /* write back buffer are not vital so don't worry about failure */
2184 r600_wb_enable(rdev);
2188 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2192 temp = RREG32(CONFIG_CNTL);
2193 if (state == false) {
2199 WREG32(CONFIG_CNTL, temp);
2202 int r600_resume(struct radeon_device *rdev)
2206 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2207 * posting will perform necessary task to bring back GPU into good
2211 atom_asic_init(rdev->mode_info.atom_context);
2212 /* Initialize clocks */
2213 r = radeon_clocks_init(rdev);
2218 r = r600_startup(rdev);
2220 DRM_ERROR("r600 startup failed on resume\n");
2224 r = r600_ib_test(rdev);
2226 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2230 r = r600_audio_init(rdev);
2232 DRM_ERROR("radeon: audio resume failed\n");
2239 int r600_suspend(struct radeon_device *rdev)
2243 r600_audio_fini(rdev);
2244 /* FIXME: we should wait for ring to be empty */
2246 rdev->cp.ready = false;
2247 r600_irq_suspend(rdev);
2248 r600_wb_disable(rdev);
2249 r600_pcie_gart_disable(rdev);
2250 /* unpin shaders bo */
2251 if (rdev->r600_blit.shader_obj) {
2252 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2254 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2255 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2261 /* Plan is to move initialization in that function and use
2262 * helper function so that radeon_device_init pretty much
2263 * do nothing more than calling asic specific function. This
2264 * should also allow to remove a bunch of callback function
2267 int r600_init(struct radeon_device *rdev)
2271 r = radeon_dummy_page_init(rdev);
2274 if (r600_debugfs_mc_info_init(rdev)) {
2275 DRM_ERROR("Failed to register debugfs file for mc !\n");
2277 /* This don't do much */
2278 r = radeon_gem_init(rdev);
2282 if (!radeon_get_bios(rdev)) {
2283 if (ASIC_IS_AVIVO(rdev))
2286 /* Must be an ATOMBIOS */
2287 if (!rdev->is_atom_bios) {
2288 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2291 r = radeon_atombios_init(rdev);
2294 /* Post card if necessary */
2295 if (!r600_card_posted(rdev)) {
2297 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2300 DRM_INFO("GPU not posted. posting now...\n");
2301 atom_asic_init(rdev->mode_info.atom_context);
2303 /* Initialize scratch registers */
2304 r600_scratch_init(rdev);
2305 /* Initialize surface registers */
2306 radeon_surface_init(rdev);
2307 /* Initialize clocks */
2308 radeon_get_clock_info(rdev->ddev);
2309 r = radeon_clocks_init(rdev);
2312 /* Initialize power management */
2313 radeon_pm_init(rdev);
2315 r = radeon_fence_driver_init(rdev);
2318 if (rdev->flags & RADEON_IS_AGP) {
2319 r = radeon_agp_init(rdev);
2321 radeon_agp_disable(rdev);
2323 r = r600_mc_init(rdev);
2326 /* Memory manager */
2327 r = radeon_bo_init(rdev);
2331 r = radeon_irq_kms_init(rdev);
2335 rdev->cp.ring_obj = NULL;
2336 r600_ring_init(rdev, 1024 * 1024);
2338 rdev->ih.ring_obj = NULL;
2339 r600_ih_ring_init(rdev, 64 * 1024);
2341 r = r600_pcie_gart_init(rdev);
2345 rdev->accel_working = true;
2346 r = r600_startup(rdev);
2348 dev_err(rdev->dev, "disabling GPU acceleration\n");
2351 r600_irq_fini(rdev);
2352 radeon_irq_kms_fini(rdev);
2353 r600_pcie_gart_fini(rdev);
2354 rdev->accel_working = false;
2356 if (rdev->accel_working) {
2357 r = radeon_ib_pool_init(rdev);
2359 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2360 rdev->accel_working = false;
2362 r = r600_ib_test(rdev);
2364 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2365 rdev->accel_working = false;
2370 r = r600_audio_init(rdev);
2372 return r; /* TODO error handling */
2376 void r600_fini(struct radeon_device *rdev)
2378 radeon_pm_fini(rdev);
2379 r600_audio_fini(rdev);
2380 r600_blit_fini(rdev);
2383 r600_irq_fini(rdev);
2384 radeon_irq_kms_fini(rdev);
2385 r600_pcie_gart_fini(rdev);
2386 radeon_agp_fini(rdev);
2387 radeon_gem_fini(rdev);
2388 radeon_fence_driver_fini(rdev);
2389 radeon_clocks_fini(rdev);
2390 radeon_bo_fini(rdev);
2391 radeon_atombios_fini(rdev);
2394 radeon_dummy_page_fini(rdev);
2401 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2403 /* FIXME: implement */
2404 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2405 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2406 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2407 radeon_ring_write(rdev, ib->length_dw);
2410 int r600_ib_test(struct radeon_device *rdev)
2412 struct radeon_ib *ib;
2418 r = radeon_scratch_get(rdev, &scratch);
2420 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2423 WREG32(scratch, 0xCAFEDEAD);
2424 r = radeon_ib_get(rdev, &ib);
2426 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2429 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2430 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2431 ib->ptr[2] = 0xDEADBEEF;
2432 ib->ptr[3] = PACKET2(0);
2433 ib->ptr[4] = PACKET2(0);
2434 ib->ptr[5] = PACKET2(0);
2435 ib->ptr[6] = PACKET2(0);
2436 ib->ptr[7] = PACKET2(0);
2437 ib->ptr[8] = PACKET2(0);
2438 ib->ptr[9] = PACKET2(0);
2439 ib->ptr[10] = PACKET2(0);
2440 ib->ptr[11] = PACKET2(0);
2441 ib->ptr[12] = PACKET2(0);
2442 ib->ptr[13] = PACKET2(0);
2443 ib->ptr[14] = PACKET2(0);
2444 ib->ptr[15] = PACKET2(0);
2446 r = radeon_ib_schedule(rdev, ib);
2448 radeon_scratch_free(rdev, scratch);
2449 radeon_ib_free(rdev, &ib);
2450 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2453 r = radeon_fence_wait(ib->fence, false);
2455 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2458 for (i = 0; i < rdev->usec_timeout; i++) {
2459 tmp = RREG32(scratch);
2460 if (tmp == 0xDEADBEEF)
2464 if (i < rdev->usec_timeout) {
2465 DRM_INFO("ib test succeeded in %u usecs\n", i);
2467 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2471 radeon_scratch_free(rdev, scratch);
2472 radeon_ib_free(rdev, &ib);
2479 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2480 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2481 * writing to the ring and the GPU consuming, the GPU writes to the ring
2482 * and host consumes. As the host irq handler processes interrupts, it
2483 * increments the rptr. When the rptr catches up with the wptr, all the
2484 * current interrupts have been processed.
2487 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2491 /* Align ring size */
2492 rb_bufsz = drm_order(ring_size / 4);
2493 ring_size = (1 << rb_bufsz) * 4;
2494 rdev->ih.ring_size = ring_size;
2495 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2499 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2503 /* Allocate ring buffer */
2504 if (rdev->ih.ring_obj == NULL) {
2505 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2507 RADEON_GEM_DOMAIN_GTT,
2508 &rdev->ih.ring_obj);
2510 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2513 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2514 if (unlikely(r != 0))
2516 r = radeon_bo_pin(rdev->ih.ring_obj,
2517 RADEON_GEM_DOMAIN_GTT,
2518 &rdev->ih.gpu_addr);
2520 radeon_bo_unreserve(rdev->ih.ring_obj);
2521 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2524 r = radeon_bo_kmap(rdev->ih.ring_obj,
2525 (void **)&rdev->ih.ring);
2526 radeon_bo_unreserve(rdev->ih.ring_obj);
2528 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2535 static void r600_ih_ring_fini(struct radeon_device *rdev)
2538 if (rdev->ih.ring_obj) {
2539 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2540 if (likely(r == 0)) {
2541 radeon_bo_kunmap(rdev->ih.ring_obj);
2542 radeon_bo_unpin(rdev->ih.ring_obj);
2543 radeon_bo_unreserve(rdev->ih.ring_obj);
2545 radeon_bo_unref(&rdev->ih.ring_obj);
2546 rdev->ih.ring = NULL;
2547 rdev->ih.ring_obj = NULL;
2551 void r600_rlc_stop(struct radeon_device *rdev)
2554 if ((rdev->family >= CHIP_RV770) &&
2555 (rdev->family <= CHIP_RV740)) {
2556 /* r7xx asics need to soft reset RLC before halting */
2557 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2558 RREG32(SRBM_SOFT_RESET);
2560 WREG32(SRBM_SOFT_RESET, 0);
2561 RREG32(SRBM_SOFT_RESET);
2564 WREG32(RLC_CNTL, 0);
2567 static void r600_rlc_start(struct radeon_device *rdev)
2569 WREG32(RLC_CNTL, RLC_ENABLE);
2572 static int r600_rlc_init(struct radeon_device *rdev)
2575 const __be32 *fw_data;
2580 r600_rlc_stop(rdev);
2582 WREG32(RLC_HB_BASE, 0);
2583 WREG32(RLC_HB_CNTL, 0);
2584 WREG32(RLC_HB_RPTR, 0);
2585 WREG32(RLC_HB_WPTR, 0);
2586 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2587 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2588 WREG32(RLC_MC_CNTL, 0);
2589 WREG32(RLC_UCODE_CNTL, 0);
2591 fw_data = (const __be32 *)rdev->rlc_fw->data;
2592 if (rdev->family >= CHIP_CEDAR) {
2593 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2594 WREG32(RLC_UCODE_ADDR, i);
2595 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2597 } else if (rdev->family >= CHIP_RV770) {
2598 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2599 WREG32(RLC_UCODE_ADDR, i);
2600 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2603 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2604 WREG32(RLC_UCODE_ADDR, i);
2605 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2608 WREG32(RLC_UCODE_ADDR, 0);
2610 r600_rlc_start(rdev);
2615 static void r600_enable_interrupts(struct radeon_device *rdev)
2617 u32 ih_cntl = RREG32(IH_CNTL);
2618 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2620 ih_cntl |= ENABLE_INTR;
2621 ih_rb_cntl |= IH_RB_ENABLE;
2622 WREG32(IH_CNTL, ih_cntl);
2623 WREG32(IH_RB_CNTL, ih_rb_cntl);
2624 rdev->ih.enabled = true;
2627 void r600_disable_interrupts(struct radeon_device *rdev)
2629 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2630 u32 ih_cntl = RREG32(IH_CNTL);
2632 ih_rb_cntl &= ~IH_RB_ENABLE;
2633 ih_cntl &= ~ENABLE_INTR;
2634 WREG32(IH_RB_CNTL, ih_rb_cntl);
2635 WREG32(IH_CNTL, ih_cntl);
2636 /* set rptr, wptr to 0 */
2637 WREG32(IH_RB_RPTR, 0);
2638 WREG32(IH_RB_WPTR, 0);
2639 rdev->ih.enabled = false;
2644 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2648 WREG32(CP_INT_CNTL, 0);
2649 WREG32(GRBM_INT_CNTL, 0);
2650 WREG32(DxMODE_INT_MASK, 0);
2651 if (ASIC_IS_DCE3(rdev)) {
2652 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2653 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2654 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2655 WREG32(DC_HPD1_INT_CONTROL, tmp);
2656 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2657 WREG32(DC_HPD2_INT_CONTROL, tmp);
2658 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2659 WREG32(DC_HPD3_INT_CONTROL, tmp);
2660 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2661 WREG32(DC_HPD4_INT_CONTROL, tmp);
2662 if (ASIC_IS_DCE32(rdev)) {
2663 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2664 WREG32(DC_HPD5_INT_CONTROL, tmp);
2665 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2666 WREG32(DC_HPD6_INT_CONTROL, tmp);
2669 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2670 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2671 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2672 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2673 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2674 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2675 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2676 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2680 int r600_irq_init(struct radeon_device *rdev)
2684 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2687 ret = r600_ih_ring_alloc(rdev);
2692 r600_disable_interrupts(rdev);
2695 ret = r600_rlc_init(rdev);
2697 r600_ih_ring_fini(rdev);
2701 /* setup interrupt control */
2702 /* set dummy read address to ring address */
2703 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2704 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2705 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2706 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2708 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2709 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2710 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2711 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2713 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2714 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2716 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2717 IH_WPTR_OVERFLOW_CLEAR |
2719 /* WPTR writeback, not yet */
2720 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2721 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2722 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2724 WREG32(IH_RB_CNTL, ih_rb_cntl);
2726 /* set rptr, wptr to 0 */
2727 WREG32(IH_RB_RPTR, 0);
2728 WREG32(IH_RB_WPTR, 0);
2730 /* Default settings for IH_CNTL (disabled at first) */
2731 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2732 /* RPTR_REARM only works if msi's are enabled */
2733 if (rdev->msi_enabled)
2734 ih_cntl |= RPTR_REARM;
2737 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2739 WREG32(IH_CNTL, ih_cntl);
2741 /* force the active interrupt state to all disabled */
2742 if (rdev->family >= CHIP_CEDAR)
2743 evergreen_disable_interrupt_state(rdev);
2745 r600_disable_interrupt_state(rdev);
2748 r600_enable_interrupts(rdev);
2753 void r600_irq_suspend(struct radeon_device *rdev)
2755 r600_irq_disable(rdev);
2756 r600_rlc_stop(rdev);
2759 void r600_irq_fini(struct radeon_device *rdev)
2761 r600_irq_suspend(rdev);
2762 r600_ih_ring_fini(rdev);
2765 int r600_irq_set(struct radeon_device *rdev)
2767 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2769 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2770 u32 grbm_int_cntl = 0;
2773 if (!rdev->irq.installed) {
2774 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2777 /* don't enable anything if the ih is disabled */
2778 if (!rdev->ih.enabled) {
2779 r600_disable_interrupts(rdev);
2780 /* force the active interrupt state to all disabled */
2781 r600_disable_interrupt_state(rdev);
2785 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2786 if (ASIC_IS_DCE3(rdev)) {
2787 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2788 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2789 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2790 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2791 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2792 if (ASIC_IS_DCE32(rdev)) {
2793 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2794 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2797 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
2798 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2799 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2800 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2803 if (rdev->irq.sw_int) {
2804 DRM_DEBUG("r600_irq_set: sw int\n");
2805 cp_int_cntl |= RB_INT_ENABLE;
2807 if (rdev->irq.crtc_vblank_int[0]) {
2808 DRM_DEBUG("r600_irq_set: vblank 0\n");
2809 mode_int |= D1MODE_VBLANK_INT_MASK;
2811 if (rdev->irq.crtc_vblank_int[1]) {
2812 DRM_DEBUG("r600_irq_set: vblank 1\n");
2813 mode_int |= D2MODE_VBLANK_INT_MASK;
2815 if (rdev->irq.hpd[0]) {
2816 DRM_DEBUG("r600_irq_set: hpd 1\n");
2817 hpd1 |= DC_HPDx_INT_EN;
2819 if (rdev->irq.hpd[1]) {
2820 DRM_DEBUG("r600_irq_set: hpd 2\n");
2821 hpd2 |= DC_HPDx_INT_EN;
2823 if (rdev->irq.hpd[2]) {
2824 DRM_DEBUG("r600_irq_set: hpd 3\n");
2825 hpd3 |= DC_HPDx_INT_EN;
2827 if (rdev->irq.hpd[3]) {
2828 DRM_DEBUG("r600_irq_set: hpd 4\n");
2829 hpd4 |= DC_HPDx_INT_EN;
2831 if (rdev->irq.hpd[4]) {
2832 DRM_DEBUG("r600_irq_set: hpd 5\n");
2833 hpd5 |= DC_HPDx_INT_EN;
2835 if (rdev->irq.hpd[5]) {
2836 DRM_DEBUG("r600_irq_set: hpd 6\n");
2837 hpd6 |= DC_HPDx_INT_EN;
2839 if (rdev->irq.hdmi[0]) {
2840 DRM_DEBUG("r600_irq_set: hdmi 1\n");
2841 hdmi1 |= R600_HDMI_INT_EN;
2843 if (rdev->irq.hdmi[1]) {
2844 DRM_DEBUG("r600_irq_set: hdmi 2\n");
2845 hdmi2 |= R600_HDMI_INT_EN;
2847 if (rdev->irq.gui_idle) {
2848 DRM_DEBUG("gui idle\n");
2849 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2852 WREG32(CP_INT_CNTL, cp_int_cntl);
2853 WREG32(DxMODE_INT_MASK, mode_int);
2854 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2855 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
2856 if (ASIC_IS_DCE3(rdev)) {
2857 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
2858 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2859 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2860 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2861 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2862 if (ASIC_IS_DCE32(rdev)) {
2863 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2864 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2867 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
2868 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2869 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2870 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2876 static inline void r600_irq_ack(struct radeon_device *rdev,
2879 u32 *disp_int_cont2)
2883 if (ASIC_IS_DCE3(rdev)) {
2884 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2885 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2886 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2888 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2889 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2890 *disp_int_cont2 = 0;
2893 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2894 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2895 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2896 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2897 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2898 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2899 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2900 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2901 if (*disp_int & DC_HPD1_INTERRUPT) {
2902 if (ASIC_IS_DCE3(rdev)) {
2903 tmp = RREG32(DC_HPD1_INT_CONTROL);
2904 tmp |= DC_HPDx_INT_ACK;
2905 WREG32(DC_HPD1_INT_CONTROL, tmp);
2907 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2908 tmp |= DC_HPDx_INT_ACK;
2909 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2912 if (*disp_int & DC_HPD2_INTERRUPT) {
2913 if (ASIC_IS_DCE3(rdev)) {
2914 tmp = RREG32(DC_HPD2_INT_CONTROL);
2915 tmp |= DC_HPDx_INT_ACK;
2916 WREG32(DC_HPD2_INT_CONTROL, tmp);
2918 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2919 tmp |= DC_HPDx_INT_ACK;
2920 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2923 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2924 if (ASIC_IS_DCE3(rdev)) {
2925 tmp = RREG32(DC_HPD3_INT_CONTROL);
2926 tmp |= DC_HPDx_INT_ACK;
2927 WREG32(DC_HPD3_INT_CONTROL, tmp);
2929 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2930 tmp |= DC_HPDx_INT_ACK;
2931 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2934 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2935 tmp = RREG32(DC_HPD4_INT_CONTROL);
2936 tmp |= DC_HPDx_INT_ACK;
2937 WREG32(DC_HPD4_INT_CONTROL, tmp);
2939 if (ASIC_IS_DCE32(rdev)) {
2940 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2941 tmp = RREG32(DC_HPD5_INT_CONTROL);
2942 tmp |= DC_HPDx_INT_ACK;
2943 WREG32(DC_HPD5_INT_CONTROL, tmp);
2945 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2946 tmp = RREG32(DC_HPD5_INT_CONTROL);
2947 tmp |= DC_HPDx_INT_ACK;
2948 WREG32(DC_HPD6_INT_CONTROL, tmp);
2951 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2952 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2954 if (ASIC_IS_DCE3(rdev)) {
2955 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2956 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2959 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
2960 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
2965 void r600_irq_disable(struct radeon_device *rdev)
2967 u32 disp_int, disp_int_cont, disp_int_cont2;
2969 r600_disable_interrupts(rdev);
2970 /* Wait and acknowledge irq */
2972 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2973 r600_disable_interrupt_state(rdev);
2976 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2980 /* XXX use writeback */
2981 wptr = RREG32(IH_RB_WPTR);
2983 if (wptr & RB_OVERFLOW) {
2984 /* When a ring buffer overflow happen start parsing interrupt
2985 * from the last not overwritten vector (wptr + 16). Hopefully
2986 * this should allow us to catchup.
2988 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2989 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2990 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2991 tmp = RREG32(IH_RB_CNTL);
2992 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2993 WREG32(IH_RB_CNTL, tmp);
2995 return (wptr & rdev->ih.ptr_mask);
2999 * Each IV ring entry is 128 bits:
3000 * [7:0] - interrupt source id
3002 * [59:32] - interrupt source data
3003 * [127:60] - reserved
3005 * The basic interrupt vector entries
3006 * are decoded as follows:
3007 * src_id src_data description
3012 * 19 0 FP Hot plug detection A
3013 * 19 1 FP Hot plug detection B
3014 * 19 2 DAC A auto-detection
3015 * 19 3 DAC B auto-detection
3021 * 181 - EOP Interrupt
3024 * Note, these are based on r600 and may need to be
3025 * adjusted or added to on newer asics
3028 int r600_irq_process(struct radeon_device *rdev)
3030 u32 wptr = r600_get_ih_wptr(rdev);
3031 u32 rptr = rdev->ih.rptr;
3032 u32 src_id, src_data;
3033 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3034 unsigned long flags;
3035 bool queue_hotplug = false;
3037 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3038 if (!rdev->ih.enabled)
3041 spin_lock_irqsave(&rdev->ih.lock, flags);
3044 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3047 if (rdev->shutdown) {
3048 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3053 /* display interrupts */
3054 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3056 rdev->ih.wptr = wptr;
3057 while (rptr != wptr) {
3058 /* wptr/rptr are in bytes! */
3059 ring_index = rptr / 4;
3060 src_id = rdev->ih.ring[ring_index] & 0xff;
3061 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3064 case 1: /* D1 vblank/vline */
3066 case 0: /* D1 vblank */
3067 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3068 drm_handle_vblank(rdev->ddev, 0);
3069 rdev->pm.vblank_sync = true;
3070 wake_up(&rdev->irq.vblank_queue);
3071 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3072 DRM_DEBUG("IH: D1 vblank\n");
3075 case 1: /* D1 vline */
3076 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3077 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3078 DRM_DEBUG("IH: D1 vline\n");
3082 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3086 case 5: /* D2 vblank/vline */
3088 case 0: /* D2 vblank */
3089 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3090 drm_handle_vblank(rdev->ddev, 1);
3091 rdev->pm.vblank_sync = true;
3092 wake_up(&rdev->irq.vblank_queue);
3093 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3094 DRM_DEBUG("IH: D2 vblank\n");
3097 case 1: /* D1 vline */
3098 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3099 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3100 DRM_DEBUG("IH: D2 vline\n");
3104 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3108 case 19: /* HPD/DAC hotplug */
3111 if (disp_int & DC_HPD1_INTERRUPT) {
3112 disp_int &= ~DC_HPD1_INTERRUPT;
3113 queue_hotplug = true;
3114 DRM_DEBUG("IH: HPD1\n");
3118 if (disp_int & DC_HPD2_INTERRUPT) {
3119 disp_int &= ~DC_HPD2_INTERRUPT;
3120 queue_hotplug = true;
3121 DRM_DEBUG("IH: HPD2\n");
3125 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3126 disp_int_cont &= ~DC_HPD3_INTERRUPT;
3127 queue_hotplug = true;
3128 DRM_DEBUG("IH: HPD3\n");
3132 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3133 disp_int_cont &= ~DC_HPD4_INTERRUPT;
3134 queue_hotplug = true;
3135 DRM_DEBUG("IH: HPD4\n");
3139 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3140 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3141 queue_hotplug = true;
3142 DRM_DEBUG("IH: HPD5\n");
3146 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3147 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3148 queue_hotplug = true;
3149 DRM_DEBUG("IH: HPD6\n");
3153 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3158 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3159 r600_audio_schedule_polling(rdev);
3161 case 176: /* CP_INT in ring buffer */
3162 case 177: /* CP_INT in IB1 */
3163 case 178: /* CP_INT in IB2 */
3164 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3165 radeon_fence_process(rdev);
3167 case 181: /* CP EOP event */
3168 DRM_DEBUG("IH: CP EOP\n");
3170 case 233: /* GUI IDLE */
3171 DRM_DEBUG("IH: CP EOP\n");
3172 rdev->pm.gui_idle = true;
3173 wake_up(&rdev->irq.idle_queue);
3176 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3180 /* wptr/rptr are in bytes! */
3182 rptr &= rdev->ih.ptr_mask;
3184 /* make sure wptr hasn't changed while processing */
3185 wptr = r600_get_ih_wptr(rdev);
3186 if (wptr != rdev->ih.wptr)
3189 queue_work(rdev->wq, &rdev->hotplug_work);
3190 rdev->ih.rptr = rptr;
3191 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3192 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3199 #if defined(CONFIG_DEBUG_FS)
3201 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3203 struct drm_info_node *node = (struct drm_info_node *) m->private;
3204 struct drm_device *dev = node->minor->dev;
3205 struct radeon_device *rdev = dev->dev_private;
3206 unsigned count, i, j;
3208 radeon_ring_free_size(rdev);
3209 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3210 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3211 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3212 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3213 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3214 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3215 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3216 seq_printf(m, "%u dwords in ring\n", count);
3218 for (j = 0; j <= count; j++) {
3219 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3220 i = (i + 1) & rdev->cp.ptr_mask;
3225 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3227 struct drm_info_node *node = (struct drm_info_node *) m->private;
3228 struct drm_device *dev = node->minor->dev;
3229 struct radeon_device *rdev = dev->dev_private;
3231 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3232 DREG32_SYS(m, rdev, VM_L2_STATUS);
3236 static struct drm_info_list r600_mc_info_list[] = {
3237 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3238 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3242 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3244 #if defined(CONFIG_DEBUG_FS)
3245 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3252 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3253 * rdev: radeon device structure
3254 * bo: buffer object struct which userspace is waiting for idle
3256 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3257 * through ring buffer, this leads to corruption in rendering, see
3258 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3259 * directly perform HDP flush by writing register through MMIO.
3261 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3263 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);