drivers/gpu/drm/radeon/r600_blit_kms.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  * Copyright 2009 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "drmP.h"
  27 #include "drm.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30
  31 #include "r600d.h"
  32 #include "r600_blit_shaders.h"
  33
  34 #define DI_PT_RECTLIST        0x11
  35 #define DI_INDEX_SIZE_16_BIT  0x0
  36 #define DI_SRC_SEL_AUTO_INDEX 0x2
  37
  38 #define FMT_8                 0x1
  39 #define FMT_5_6_5             0x8
  40 #define FMT_8_8_8_8           0x1a
  41 #define COLOR_8               0x1
  42 #define COLOR_5_6_5           0x8
  43 #define COLOR_8_8_8_8         0x1a
  44
  45 #define RECT_UNIT_H           32
  46 #define RECT_UNIT_W           (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
  47
  48 /* emits 21 on rv770+, 23 on r600 */
  49 static void
  50 set_render_target(struct radeon_device *rdev, int format,
  51                   int w, int h, u64 gpu_addr)
  52 {
  53         struct radeon_cp *cp = &rdev->cp;
  54         u32 cb_color_info;
  55         int pitch, slice;
  56
  57         h = ALIGN(h, 8);
  58         if (h < 8)
  59                 h = 8;
  60
  61         cb_color_info = CB_FORMAT(format) |
  62                 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
  63                 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
  64         pitch = (w / 8) - 1;
  65         slice = ((w * h) / 64) - 1;
  66
  67         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  68         radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  69         radeon_ring_write(cp, gpu_addr >> 8);
  70
  71         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
  72                 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
  73                 radeon_ring_write(cp, 2 << 0);
  74         }
  75
  76         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  77         radeon_ring_write(cp, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  78         radeon_ring_write(cp, (pitch << 0) | (slice << 10));
  79
  80         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  81         radeon_ring_write(cp, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  82         radeon_ring_write(cp, 0);
  83
  84         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  85         radeon_ring_write(cp, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  86         radeon_ring_write(cp, cb_color_info);
  87
  88         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  89         radeon_ring_write(cp, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  90         radeon_ring_write(cp, 0);
  91
  92         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  93         radeon_ring_write(cp, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  94         radeon_ring_write(cp, 0);
  95
  96         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
  97         radeon_ring_write(cp, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
  98         radeon_ring_write(cp, 0);
  99 }
 100
 101 /* emits 5dw */
 102 static void
 103 cp_set_surface_sync(struct radeon_device *rdev,
 104                     u32 sync_type, u32 size,
 105                     u64 mc_addr)
 106 {
 107         struct radeon_cp *cp = &rdev->cp;
 108         u32 cp_coher_size;
 109
 110         if (size == 0xffffffff)
 111                 cp_coher_size = 0xffffffff;
 112         else
 113                 cp_coher_size = ((size + 255) >> 8);
 114
 115         radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
 116         radeon_ring_write(cp, sync_type);
 117         radeon_ring_write(cp, cp_coher_size);
 118         radeon_ring_write(cp, mc_addr >> 8);
 119         radeon_ring_write(cp, 10); /* poll interval */
 120 }
 121
 122 /* emits 21dw + 1 surface sync = 26dw */
 123 static void
 124 set_shaders(struct radeon_device *rdev)
 125 {
 126         struct radeon_cp *cp = &rdev->cp;
 127         u64 gpu_addr;
 128         u32 sq_pgm_resources;
 129
 130         /* setup shader regs */
 131         sq_pgm_resources = (1 << 0);
 132
 133         /* VS */
 134         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 135         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 136         radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 137         radeon_ring_write(cp, gpu_addr >> 8);
 138
 139         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 140         radeon_ring_write(cp, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 141         radeon_ring_write(cp, sq_pgm_resources);
 142
 143         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 144         radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 145         radeon_ring_write(cp, 0);
 146
 147         /* PS */
 148         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 149         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 150         radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 151         radeon_ring_write(cp, gpu_addr >> 8);
 152
 153         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 154         radeon_ring_write(cp, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 155         radeon_ring_write(cp, sq_pgm_resources | (1 << 28));
 156
 157         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 158         radeon_ring_write(cp, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 159         radeon_ring_write(cp, 2);
 160
 161         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 162         radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 163         radeon_ring_write(cp, 0);
 164
 165         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 166         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 167 }
 168
 169 /* emits 9 + 1 sync (5) = 14*/
 170 static void
 171 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 172 {
 173         struct radeon_cp *cp = &rdev->cp;
 174         u32 sq_vtx_constant_word2;
 175
 176         sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
 177                 SQ_VTXC_STRIDE(16);
 178 #ifdef __BIG_ENDIAN
 179         sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 180 #endif
 181
 182         radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
 183         radeon_ring_write(cp, 0x460);
 184         radeon_ring_write(cp, gpu_addr & 0xffffffff);
 185         radeon_ring_write(cp, 48 - 1);
 186         radeon_ring_write(cp, sq_vtx_constant_word2);
 187         radeon_ring_write(cp, 1 << 0);
 188         radeon_ring_write(cp, 0);
 189         radeon_ring_write(cp, 0);
 190         radeon_ring_write(cp, SQ_TEX_VTX_VALID_BUFFER << 30);
 191
 192         if ((rdev->family == CHIP_RV610) ||
 193             (rdev->family == CHIP_RV620) ||
 194             (rdev->family == CHIP_RS780) ||
 195             (rdev->family == CHIP_RS880) ||
 196             (rdev->family == CHIP_RV710))
 197                 cp_set_surface_sync(rdev,
 198                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 199         else
 200                 cp_set_surface_sync(rdev,
 201                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 202 }
 203
 204 /* emits 9 */
 205 static void
 206 set_tex_resource(struct radeon_device *rdev,
 207                  int format, int w, int h, int pitch,
 208                  u64 gpu_addr, u32 size)
 209 {
 210         struct radeon_cp *cp = &rdev->cp;
 211         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 212
 213         if (h < 1)
 214                 h = 1;
 215
 216         sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
 217                 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
 218         sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
 219                 S_038000_TEX_WIDTH(w - 1);
 220
 221         sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
 222         sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
 223
 224         sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
 225                 S_038010_DST_SEL_X(SQ_SEL_X) |
 226                 S_038010_DST_SEL_Y(SQ_SEL_Y) |
 227                 S_038010_DST_SEL_Z(SQ_SEL_Z) |
 228                 S_038010_DST_SEL_W(SQ_SEL_W);
 229
 230         cp_set_surface_sync(rdev,
 231                             PACKET3_TC_ACTION_ENA, size, gpu_addr);
 232
 233         radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
 234         radeon_ring_write(cp, 0);
 235         radeon_ring_write(cp, sq_tex_resource_word0);
 236         radeon_ring_write(cp, sq_tex_resource_word1);
 237         radeon_ring_write(cp, gpu_addr >> 8);
 238         radeon_ring_write(cp, gpu_addr >> 8);
 239         radeon_ring_write(cp, sq_tex_resource_word4);
 240         radeon_ring_write(cp, 0);
 241         radeon_ring_write(cp, SQ_TEX_VTX_VALID_TEXTURE << 30);
 242 }
 243
 244 /* emits 12 */
 245 static void
 246 set_scissors(struct radeon_device *rdev, int x1, int y1,
 247              int x2, int y2)
 248 {
 249         struct radeon_cp *cp = &rdev->cp;
 250         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 251         radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 252         radeon_ring_write(cp, (x1 << 0) | (y1 << 16));
 253         radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 254
 255         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 256         radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 257         radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
 258         radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 259
 260         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 261         radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 262         radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
 263         radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 264 }
 265
 266 /* emits 10 */
 267 static void
 268 draw_auto(struct radeon_device *rdev)
 269 {
 270         struct radeon_cp *cp = &rdev->cp;
 271         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 272         radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 273         radeon_ring_write(cp, DI_PT_RECTLIST);
 274
 275         radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0));
 276         radeon_ring_write(cp,
 277 #ifdef __BIG_ENDIAN
 278                           (2 << 2) |
 279 #endif
 280                           DI_INDEX_SIZE_16_BIT);
 281
 282         radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0));
 283         radeon_ring_write(cp, 1);
 284
 285         radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 286         radeon_ring_write(cp, 3);
 287         radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX);
 288
 289 }
 290
 291 /* emits 14 */
 292 static void
 293 set_default_state(struct radeon_device *rdev)
 294 {
 295         struct radeon_cp *cp = &rdev->cp;
 296         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 297         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 298         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 299         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 300         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 301         u64 gpu_addr;
 302         int dwords;
 303
 304         switch (rdev->family) {
 305         case CHIP_R600:
 306                 num_ps_gprs = 192;
 307                 num_vs_gprs = 56;
 308                 num_temp_gprs = 4;
 309                 num_gs_gprs = 0;
 310                 num_es_gprs = 0;
 311                 num_ps_threads = 136;
 312                 num_vs_threads = 48;
 313                 num_gs_threads = 4;
 314                 num_es_threads = 4;
 315                 num_ps_stack_entries = 128;
 316                 num_vs_stack_entries = 128;
 317                 num_gs_stack_entries = 0;
 318                 num_es_stack_entries = 0;
 319                 break;
 320         case CHIP_RV630:
 321         case CHIP_RV635:
 322                 num_ps_gprs = 84;
 323                 num_vs_gprs = 36;
 324                 num_temp_gprs = 4;
 325                 num_gs_gprs = 0;
 326                 num_es_gprs = 0;
 327                 num_ps_threads = 144;
 328                 num_vs_threads = 40;
 329                 num_gs_threads = 4;
 330                 num_es_threads = 4;
 331                 num_ps_stack_entries = 40;
 332                 num_vs_stack_entries = 40;
 333                 num_gs_stack_entries = 32;
 334                 num_es_stack_entries = 16;
 335                 break;
 336         case CHIP_RV610:
 337         case CHIP_RV620:
 338         case CHIP_RS780:
 339         case CHIP_RS880:
 340         default:
 341                 num_ps_gprs = 84;
 342                 num_vs_gprs = 36;
 343                 num_temp_gprs = 4;
 344                 num_gs_gprs = 0;
 345                 num_es_gprs = 0;
 346                 num_ps_threads = 136;
 347                 num_vs_threads = 48;
 348                 num_gs_threads = 4;
 349                 num_es_threads = 4;
 350                 num_ps_stack_entries = 40;
 351                 num_vs_stack_entries = 40;
 352                 num_gs_stack_entries = 32;
 353                 num_es_stack_entries = 16;
 354                 break;
 355         case CHIP_RV670:
 356                 num_ps_gprs = 144;
 357                 num_vs_gprs = 40;
 358                 num_temp_gprs = 4;
 359                 num_gs_gprs = 0;
 360                 num_es_gprs = 0;
 361                 num_ps_threads = 136;
 362                 num_vs_threads = 48;
 363                 num_gs_threads = 4;
 364                 num_es_threads = 4;
 365                 num_ps_stack_entries = 40;
 366                 num_vs_stack_entries = 40;
 367                 num_gs_stack_entries = 32;
 368                 num_es_stack_entries = 16;
 369                 break;
 370         case CHIP_RV770:
 371                 num_ps_gprs = 192;
 372                 num_vs_gprs = 56;
 373                 num_temp_gprs = 4;
 374                 num_gs_gprs = 0;
 375                 num_es_gprs = 0;
 376                 num_ps_threads = 188;
 377                 num_vs_threads = 60;
 378                 num_gs_threads = 0;
 379                 num_es_threads = 0;
 380                 num_ps_stack_entries = 256;
 381                 num_vs_stack_entries = 256;
 382                 num_gs_stack_entries = 0;
 383                 num_es_stack_entries = 0;
 384                 break;
 385         case CHIP_RV730:
 386         case CHIP_RV740:
 387                 num_ps_gprs = 84;
 388                 num_vs_gprs = 36;
 389                 num_temp_gprs = 4;
 390                 num_gs_gprs = 0;
 391                 num_es_gprs = 0;
 392                 num_ps_threads = 188;
 393                 num_vs_threads = 60;
 394                 num_gs_threads = 0;
 395                 num_es_threads = 0;
 396                 num_ps_stack_entries = 128;
 397                 num_vs_stack_entries = 128;
 398                 num_gs_stack_entries = 0;
 399                 num_es_stack_entries = 0;
 400                 break;
 401         case CHIP_RV710:
 402                 num_ps_gprs = 192;
 403                 num_vs_gprs = 56;
 404                 num_temp_gprs = 4;
 405                 num_gs_gprs = 0;
 406                 num_es_gprs = 0;
 407                 num_ps_threads = 144;
 408                 num_vs_threads = 48;
 409                 num_gs_threads = 0;
 410                 num_es_threads = 0;
 411                 num_ps_stack_entries = 128;
 412                 num_vs_stack_entries = 128;
 413                 num_gs_stack_entries = 0;
 414                 num_es_stack_entries = 0;
 415                 break;
 416         }
 417
 418         if ((rdev->family == CHIP_RV610) ||
 419             (rdev->family == CHIP_RV620) ||
 420             (rdev->family == CHIP_RS780) ||
 421             (rdev->family == CHIP_RS880) ||
 422             (rdev->family == CHIP_RV710))
 423                 sq_config = 0;
 424         else
 425                 sq_config = VC_ENABLE;
 426
 427         sq_config |= (DX9_CONSTS |
 428                       ALU_INST_PREFER_VECTOR |
 429                       PS_PRIO(0) |
 430                       VS_PRIO(1) |
 431                       GS_PRIO(2) |
 432                       ES_PRIO(3));
 433
 434         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 435                                   NUM_VS_GPRS(num_vs_gprs) |
 436                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 437         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 438                                   NUM_ES_GPRS(num_es_gprs));
 439         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 440                                    NUM_VS_THREADS(num_vs_threads) |
 441                                    NUM_GS_THREADS(num_gs_threads) |
 442                                    NUM_ES_THREADS(num_es_threads));
 443         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 444                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 445         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 446                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 447
 448         /* emit an IB pointing at default state */
 449         dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
 450         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 451         radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 452         radeon_ring_write(cp,
 453 #ifdef __BIG_ENDIAN
 454                           (2 << 0) |
 455 #endif
 456                           (gpu_addr & 0xFFFFFFFC));
 457         radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF);
 458         radeon_ring_write(cp, dwords);
 459
 460         /* SQ config */
 461         radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 6));
 462         radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
 463         radeon_ring_write(cp, sq_config);
 464         radeon_ring_write(cp, sq_gpr_resource_mgmt_1);
 465         radeon_ring_write(cp, sq_gpr_resource_mgmt_2);
 466         radeon_ring_write(cp, sq_thread_resource_mgmt);
 467         radeon_ring_write(cp, sq_stack_resource_mgmt_1);
 468         radeon_ring_write(cp, sq_stack_resource_mgmt_2);
 469 }
 470
 471 static uint32_t i2f(uint32_t input)
 472 {
 473         u32 result, i, exponent, fraction;
 474
 475         if ((input & 0x3fff) == 0)
 476                 result = 0; /* 0 is a special case */
 477         else {
 478                 exponent = 140; /* exponent biased by 127; */
 479                 fraction = (input & 0x3fff) << 10; /* cheat and only
 480                                                       handle numbers below 2^^15 */
 481                 for (i = 0; i < 14; i++) {
 482                         if (fraction & 0x800000)
 483                                 break;
 484                         else {
 485                                 fraction = fraction << 1; /* keep
 486                                                              shifting left until top bit = 1 */
 487                                 exponent = exponent - 1;
 488                         }
 489                 }
 490                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 491                                                                     off top bit; assumed 1 */
 492         }
 493         return result;
 494 }
 495
 496 int r600_blit_init(struct radeon_device *rdev)
 497 {
 498         u32 obj_size;
 499         int i, r, dwords;
 500         void *ptr;
 501         u32 packet2s[16];
 502         int num_packet2s = 0;
 503
 504         rdev->r600_blit.primitives.set_render_target = set_render_target;
 505         rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
 506         rdev->r600_blit.primitives.set_shaders = set_shaders;
 507         rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
 508         rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
 509         rdev->r600_blit.primitives.set_scissors = set_scissors;
 510         rdev->r600_blit.primitives.draw_auto = draw_auto;
 511         rdev->r600_blit.primitives.set_default_state = set_default_state;
 512
 513         rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
 514         rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
 515         rdev->r600_blit.ring_size_common += 5; /* done copy */
 516         rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
 517
 518         rdev->r600_blit.ring_size_per_loop = 76;
 519         /* set_render_target emits 2 extra dwords on rv6xx */
 520         if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
 521                 rdev->r600_blit.ring_size_per_loop += 2;
 522
 523         rdev->r600_blit.max_dim = 8192;
 524
 525         /* pin copy shader into vram if already initialized */
 526         if (rdev->r600_blit.shader_obj)
 527                 goto done;
 528
 529         mutex_init(&rdev->r600_blit.mutex);
 530         rdev->r600_blit.state_offset = 0;
 531
 532         if (rdev->family >= CHIP_RV770)
 533                 rdev->r600_blit.state_len = r7xx_default_size;
 534         else
 535                 rdev->r600_blit.state_len = r6xx_default_size;
 536
 537         dwords = rdev->r600_blit.state_len;
 538         while (dwords & 0xf) {
 539                 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
 540                 dwords++;
 541         }
 542
 543         obj_size = dwords * 4;
 544         obj_size = ALIGN(obj_size, 256);
 545
 546         rdev->r600_blit.vs_offset = obj_size;
 547         obj_size += r6xx_vs_size * 4;
 548         obj_size = ALIGN(obj_size, 256);
 549
 550         rdev->r600_blit.ps_offset = obj_size;
 551         obj_size += r6xx_ps_size * 4;
 552         obj_size = ALIGN(obj_size, 256);
 553
 554         r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 555                                 &rdev->r600_blit.shader_obj);
 556         if (r) {
 557                 DRM_ERROR("r600 failed to allocate shader\n");
 558                 return r;
 559         }
 560
 561         DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
 562                   obj_size,
 563                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 564
 565         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 566         if (unlikely(r != 0))
 567                 return r;
 568         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 569         if (r) {
 570                 DRM_ERROR("failed to map blit object %d\n", r);
 571                 return r;
 572         }
 573         if (rdev->family >= CHIP_RV770)
 574                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 575                             r7xx_default_state, rdev->r600_blit.state_len * 4);
 576         else
 577                 memcpy_toio(ptr + rdev->r600_blit.state_offset,
 578                             r6xx_default_state, rdev->r600_blit.state_len * 4);
 579         if (num_packet2s)
 580                 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
 581                             packet2s, num_packet2s * 4);
 582         for (i = 0; i < r6xx_vs_size; i++)
 583                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
 584         for (i = 0; i < r6xx_ps_size; i++)
 585                 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
 586         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 587         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 588
 589 done:
 590         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 591         if (unlikely(r != 0))
 592                 return r;
 593         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 594                           &rdev->r600_blit.shader_gpu_addr);
 595         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 596         if (r) {
 597                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 598                 return r;
 599         }
 600         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 601         return 0;
 602 }
 603
 604 void r600_blit_fini(struct radeon_device *rdev)
 605 {
 606         int r;
 607
 608         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 609         if (rdev->r600_blit.shader_obj == NULL)
 610                 return;
 611         /* If we can't reserve the bo, unref should be enough to destroy
 612          * it when it becomes idle.
 613          */
 614         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 615         if (!r) {
 616                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 617                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 618         }
 619         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 620 }
 621
 622 static int r600_vb_ib_get(struct radeon_device *rdev)
 623 {
 624         int r;
 625         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->r600_blit.vb_ib);
 626         if (r) {
 627                 DRM_ERROR("failed to get IB for vertex buffer\n");
 628                 return r;
 629         }
 630
 631         rdev->r600_blit.vb_total = 64*1024;
 632         rdev->r600_blit.vb_used = 0;
 633         return 0;
 634 }
 635
 636 static void r600_vb_ib_put(struct radeon_device *rdev)
 637 {
 638         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 639         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 640 }
 641
 642 static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
 643                                       int *width, int *height, int max_dim)
 644 {
 645         unsigned max_pages;
 646         unsigned pages = num_gpu_pages;
 647         int w, h;
 648
 649         if (num_gpu_pages == 0) {
 650                 /* not supposed to be called with no pages, but just in case */
 651                 h = 0;
 652                 w = 0;
 653                 pages = 0;
 654                 WARN_ON(1);
 655         } else {
 656                 int rect_order = 2;
 657                 h = RECT_UNIT_H;
 658                 while (num_gpu_pages / rect_order) {
 659                         h *= 2;
 660                         rect_order *= 4;
 661                         if (h >= max_dim) {
 662                                 h = max_dim;
 663                                 break;
 664                         }
 665                 }
 666                 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
 667                 if (pages > max_pages)
 668                         pages = max_pages;
 669                 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
 670                 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
 671                 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
 672                 BUG_ON(pages == 0);
 673         }
 674
 675
 676         DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
 677
 678         /* return width and height only of the caller wants it */
 679         if (height)
 680                 *height = h;
 681         if (width)
 682                 *width = w;
 683
 684         return pages;
 685 }
 686
 687
 688 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
 689 {
 690         struct radeon_cp *cp = &rdev->cp;
 691         int r;
 692         int ring_size;
 693         int num_loops = 0;
 694         int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
 695
 696         r = r600_vb_ib_get(rdev);
 697         if (r)
 698                 return r;
 699
 700         /* num loops */
 701         while (num_gpu_pages) {
 702                 num_gpu_pages -=
 703                         r600_blit_create_rect(num_gpu_pages, NULL, NULL,
 704                                               rdev->r600_blit.max_dim);
 705                 num_loops++;
 706         }
 707
 708         /* calculate number of loops correctly */
 709         ring_size = num_loops * dwords_per_loop;
 710         ring_size += rdev->r600_blit.ring_size_common;
 711         r = radeon_ring_lock(rdev, cp, ring_size);
 712         if (r)
 713                 return r;
 714
 715         rdev->r600_blit.primitives.set_default_state(rdev);
 716         rdev->r600_blit.primitives.set_shaders(rdev);
 717         return 0;
 718 }
 719
 720 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 721 {
 722         int r;
 723
 724         if (rdev->r600_blit.vb_ib)
 725                 r600_vb_ib_put(rdev);
 726
 727         if (fence)
 728                 r = radeon_fence_emit(rdev, fence);
 729
 730         radeon_ring_unlock_commit(rdev, &rdev->cp);
 731 }
 732
 733 void r600_kms_blit_copy(struct radeon_device *rdev,
 734                         u64 src_gpu_addr, u64 dst_gpu_addr,
 735                         unsigned num_gpu_pages)
 736 {
 737         u64 vb_gpu_addr;
 738         u32 *vb;
 739
 740         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n",
 741                   src_gpu_addr, dst_gpu_addr,
 742                   num_gpu_pages, rdev->r600_blit.vb_used);
 743         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 744
 745         while (num_gpu_pages) {
 746                 int w, h;
 747                 unsigned size_in_bytes;
 748                 unsigned pages_per_loop =
 749                         r600_blit_create_rect(num_gpu_pages, &w, &h,
 750                                               rdev->r600_blit.max_dim);
 751
 752                 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
 753                 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
 754
 755                 if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 756                         WARN_ON(1);
 757                 }
 758
 759                 vb[0] = 0;
 760                 vb[1] = 0;
 761                 vb[2] = 0;
 762                 vb[3] = 0;
 763
 764                 vb[4] = 0;
 765                 vb[5] = i2f(h);
 766                 vb[6] = 0;
 767                 vb[7] = i2f(h);
 768
 769                 vb[8] = i2f(w);
 770                 vb[9] = i2f(h);
 771                 vb[10] = i2f(w);
 772                 vb[11] = i2f(h);
 773
 774                 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
 775                                                             w, h, w, src_gpu_addr, size_in_bytes);
 776                 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
 777                                                              w, h, dst_gpu_addr);
 778                 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
 779                 vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 780                 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
 781                 rdev->r600_blit.primitives.draw_auto(rdev);
 782                 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
 783                                     PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 784                                     size_in_bytes, dst_gpu_addr);
 785
 786                 vb += 12;
 787                 rdev->r600_blit.vb_used += 4*12;
 788                 src_gpu_addr += size_in_bytes;
 789                 dst_gpu_addr += size_in_bytes;
 790                 num_gpu_pages -= pages_per_loop;
 791         }
 792 }