2 * Copyright 2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
27 #include <linux/types.h>
28 #include <linux/kernel.h>
31 * R6xx+ cards need to use the 3D engine to blit data which requires
32 * quite a bit of hw state setup. Rather than pull the whole 3D driver
33 * (which normally generates the 3D state) into the DRM, we opt to use
34 * statically generated state tables. The regsiter state and shaders
35 * were hand generated to support blitting functionality. See the 3D
36 * driver or documentation for descriptions of the registers and
37 * shader instructions.
40 const u32 r6xx_default_state[] =
42 0xc0002400, /* START_3D_CMDBUF */
45 0xc0012800, /* CONTEXT_CONTROL */
51 0x00008000, /* WAIT_UNTIL */
55 0x07000003, /* TA_CNTL_AUX */
59 0x00000000, /* VC_ENHANCE */
63 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
67 0x82000000, /* DB_DEBUG */
71 0x01020204, /* DB_WATERMARKS */
75 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
79 0x00000000, /* SQ_VTX_START_INST_LOC */
83 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
95 0x00000000, /* DB_DEPTH_INFO */
99 0x00000000, /* DB_STENCIL_CLEAR */
103 0x00000000, /* DB_DEPTH_CLEAR */
107 0x00000000, /* DB_STENCILREFMASK */
111 0x00000000, /* DB_STENCILREFMASK_BF */
115 0x00000000, /* DB_DEPTH_CONTROL */
119 0x00000060, /* DB_RENDER_CONTROL */
123 0x00000040, /* DB_RENDER_OVERRIDE */
127 0x0000aa00, /* DB_ALPHA_TO_MASK */
131 0x00000000, /* SX_ALPHA_TEST_CONTROL */
135 0x00000000, /* SX_ALPHA_REF */
139 0x00000000, /* CB_BLEND_RED */
146 0x00000000, /* CB_FOG_RED */
152 0x01000000, /* CB_CLRCMP_CNTL */
159 0x3f800000, /* CB_CLEAR_RED */
166 0x0000000f, /* CB_TARGET_MASK */
170 0x00000000, /* PA_SC_WINDOW_OFFSET */
174 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
178 0x00000000, /* PA_SC_WINDOW_SCISSOR_TL */
210 0x00000000, /* PA_SC_EDGERULE */
214 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
218 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
222 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
227 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
422 0x00004010, /* PA_SC_MODE_CNTL */
426 0x00000000, /* PA_SC_LINE_CNTL */
430 0x00000000, /* PA_SC_AA_CONFIG */
434 0xffffffff, /* PA_SC_AA_MASK */
438 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
446 0x00000000, /* PA_SC_LINE_STIPPLE */
450 0x00000000, /* PA_SC_MPASS_PS_CNTL */
454 0x00000000, /* PA_CL_VPORT_0_XSCALE */
463 0x00000000, /* PA_CL_VS_OUT_CNTL */
467 0x00000000, /* PA_CL_NANINF_CNTL */
471 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
478 0x00000000, /* PA_SU_POINT_SIZE */
482 0x00000000, /* PA_SU_POINT_MINMAX */
486 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
490 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
494 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
498 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
502 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
506 0x00000008, /* PA_SU_LINE_CNTL */
510 0x0000002d, /* PA_SU_VTX_CNTL */
514 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
518 0x00000000, /* SPI_THREAD_GROUPING */
522 0x00000000, /* SPI_INPUT_Z */
526 0x00000000, /* SPI_FOG_CNTL */
530 0x00000000, /* SPI_FOG_FUNC_SCALE */
534 0x00000000, /* SPI_FOG_FUNC_BIAS */
538 0x00000000, /* SQ_PGM_START_FS */
542 0x00000000, /* SQ_PGM_RESOURCES_FS */
546 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
550 0x00000800, /* VGT_MAX_VTX_INDX */
554 0x00000000, /* VGT_MIN_VTX_INDX */
558 0x00000000, /* VGT_INDX_OFFSET */
562 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
566 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
570 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
574 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
578 0x00000000, /* VGT_GS_MODE */
582 0x00000000, /* VGT_HOS_CNTL */
586 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
590 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
594 0x00000000, /* VGT_HOS_REUSE_DEPTH */
598 0x00000000, /* VGT_GROUP_PRIM_TYPE */
602 0x00000000, /* VGT_GROUP_FIRST_DECR */
606 0x00000000, /* VGT_GROUP_DECR */
610 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
614 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
618 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
622 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
626 0x00000000, /* VGT_PRIMITIVEID_EN */
630 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
634 0x00000000, /* VGT_STRMOUT_EN */
638 0x00000000, /* VGT_REUSE_OFF */
642 0x00000000, /* VGT_VTX_CNT_EN */
646 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
650 0x00000100, /* PA_CL_VTE_CNTL */
654 0x00010000, /* PA_CL_CLIP_CNTL */
656 0xc0036e00, /* SET_SAMPLER */
664 0x0000000f, /* CB_SHADER_MASK */
668 0x00000001, /* CB_SHADER_CONTROL */
672 0x00cc0000, /* CB_COLOR_CONTROL */
676 0x00000244, /* PA_SU_SC_MODE_CNTL */
680 0x00000210, /* DB_SHADER_CNTL */
684 0x00000000, /* SPI_VS_OUT_CONFIG */
688 0x00000000, /* SPI_VS_OUT_ID_0 */
692 0x00000001, /* SPI_PS_IN_CONTROL_0 */
696 0x00000000, /* SPI_PS_IN_CONTROL_1 */
700 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
704 0x00000000, /* SPI_INTERP_CONTROL_0 */
707 const u32 r7xx_default_state[] =
709 0xc0012800, /* CONTEXT_CONTROL */
715 0x00008000, /* WAIT_UNTIL */
719 0x07000002, /* TA_CNTL_AUX */
723 0x00000000, /* VC_ENHANCE */
727 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
731 0x00000000, /* DB_DEBUG */
735 0x00420204, /* DB_WATERMARKS */
739 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
743 0x00000000, /* SQ_VTX_START_INST_LOC */
747 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
759 0x00000000, /* DB_DEPTH_INFO */
763 0x00000000, /* DB_STENCIL_CLEAR */
767 0x00000000, /* DB_DEPTH_CLEAR */
771 0x00000000, /* DB_STENCILREFMASK */
775 0x00000000, /* DB_STENCILREFMASK_BF */
779 0x00000000, /* DB_DEPTH_CONTROL */
783 0x00000060, /* DB_RENDER_CONTROL */
787 0x00000000, /* DB_RENDER_OVERRIDE */
791 0x0000aa00, /* DB_ALPHA_TO_MASK */
795 0x00000000, /* SX_ALPHA_TEST_CONTROL */
799 0x00000000, /* SX_ALPHA_REF */
803 0x00000000, /* CB_BLEND_RED */
809 0x0000030c, /* CB_CLRCMP_CNTL */
817 0x0000000f, /* CB_TARGET_MASK */
821 0x00000000, /* PA_SC_WINDOW_OFFSET */
825 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
829 0x00000000, /* PA_SC_WINDOW_SCISSOR_TL */
861 0xaaaaaaaa, /* PA_SC_EDGERULE */
865 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
869 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
873 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
1073 0x00514000, /* PA_SC_MODE_CNTL */
1077 0x00000000, /* PA_SC_LINE_CNTL */
1081 0x00000000, /* PA_SC_AA_CONFIG */
1085 0xffffffff, /* PA_SC_AA_MASK */
1089 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
1097 0x00000000, /* PA_SC_LINE_STIPPLE */
1101 0x00000000, /* PA_SC_MPASS_PS_CNTL */
1105 0x00000000, /* PA_CL_VPORT_0_XSCALE */
1114 0x00000000, /* PA_CL_VS_OUT_CNTL */
1118 0x00000000, /* PA_CL_NANINF_CNTL */
1122 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
1129 0x00000000, /* PA_SU_POINT_SIZE */
1133 0x00000000, /* PA_SU_POINT_MINMAX */
1137 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
1141 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
1145 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
1149 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
1153 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
1157 0x00000008, /* PA_SU_LINE_CNTL */
1161 0x0000002d, /* PA_SU_VTX_CNTL */
1165 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
1169 0x00000001, /* SPI_THREAD_GROUPING */
1173 0x00000000, /* SPI_INPUT_Z */
1177 0x00000000, /* SPI_FOG_CNTL */
1181 0x00000000, /* SPI_FOG_FUNC_SCALE */
1185 0x00000000, /* SPI_FOG_FUNC_BIAS */
1189 0x00000000, /* SQ_PGM_START_FS */
1193 0x00000000, /* SQ_PGM_RESOURCES_FS */
1197 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
1201 0x00000800, /* VGT_MAX_VTX_INDX */
1205 0x00000000, /* VGT_MIN_VTX_INDX */
1209 0x00000000, /* VGT_INDX_OFFSET */
1213 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
1217 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
1221 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
1225 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
1229 0x00000000, /* VGT_GS_MODE */
1233 0x00000000, /* VGT_HOS_CNTL */
1237 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
1241 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
1245 0x00000000, /* VGT_HOS_REUSE_DEPTH */
1249 0x00000000, /* VGT_GROUP_PRIM_TYPE */
1253 0x00000000, /* VGT_GROUP_FIRST_DECR */
1257 0x00000000, /* VGT_GROUP_DECR */
1261 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
1265 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
1269 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
1273 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
1277 0x00000000, /* VGT_PRIMITIVEID_EN */
1281 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
1285 0x00000000, /* VGT_STRMOUT_EN */
1289 0x00000000, /* VGT_REUSE_OFF */
1293 0x00000000, /* VGT_VTX_CNT_EN */
1297 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
1301 0x00000100, /* PA_CL_VTE_CNTL */
1305 0x00010000, /* PA_CL_CLIP_CNTL */
1307 0xc0036e00, /* SET_SAMPLER */
1315 0x0000000f, /* CB_SHADER_MASK */
1319 0x00000001, /* CB_SHADER_CONTROL */
1323 0x00cc0000, /* CB_COLOR_CONTROL */
1327 0x00000244, /* PA_SU_SC_MODE_CNTL */
1331 0x00000210, /* DB_SHADER_CNTL */
1335 0x00000000, /* SPI_VS_OUT_CONFIG */
1339 0x00000000, /* SPI_VS_OUT_ID_0 */
1343 0x00000001, /* SPI_PS_IN_CONTROL_0 */
1347 0x00000000, /* SPI_PS_IN_CONTROL_1 */
1351 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
1355 0x00000000, /* SPI_INTERP_CONTROL_0 */
1358 /* same for r6xx/r7xx */
1359 const u32 r6xx_vs[] =
1375 const u32 r6xx_ps[] =
1387 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
1388 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
1389 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
1390 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);