drivers/gpu/drm/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "radeon.h"
  31 #include "r600d.h"
  32 #include "r600_reg_safe.h"
  33
  34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  35                                         struct radeon_cs_reloc **cs_reloc);
  36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  37                                         struct radeon_cs_reloc **cs_reloc);
  38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  41
  42
  43 struct r600_cs_track {
  44         /* configuration we miror so that we use same code btw kms/ums */
  45         u32                     group_size;
  46         u32                     nbanks;
  47         u32                     npipes;
  48         /* value we track */
  49         u32                     sq_config;
  50         u32                     nsamples;
  51         u32                     cb_color_base_last[8];
  52         struct radeon_bo        *cb_color_bo[8];
  53         u64                     cb_color_bo_mc[8];
  54         u32                     cb_color_bo_offset[8];
  55         struct radeon_bo        *cb_color_frag_bo[8]; /* unused */
  56         struct radeon_bo        *cb_color_tile_bo[8]; /* unused */
  57         u32                     cb_color_info[8];
  58         u32                     cb_color_view[8];
  59         u32                     cb_color_size_idx[8]; /* unused */
  60         u32                     cb_target_mask;
  61         u32                     cb_shader_mask;  /* unused */
  62         u32                     cb_color_size[8];
  63         u32                     vgt_strmout_en;
  64         u32                     vgt_strmout_buffer_en;
  65         struct radeon_bo        *vgt_strmout_bo[4];
  66         u64                     vgt_strmout_bo_mc[4]; /* unused */
  67         u32                     vgt_strmout_bo_offset[4];
  68         u32                     vgt_strmout_size[4];
  69         u32                     db_depth_control;
  70         u32                     db_depth_info;
  71         u32                     db_depth_size_idx;
  72         u32                     db_depth_view;
  73         u32                     db_depth_size;
  74         u32                     db_offset;
  75         struct radeon_bo        *db_bo;
  76         u64                     db_bo_mc;
  77         bool                    sx_misc_kill_all_prims;
  78         bool                    cb_dirty;
  79         bool                    db_dirty;
  80         bool                    streamout_dirty;
  81 };
  82
  83 #define FMT_8_BIT(fmt, vc)   [fmt] = { 1, 1, 1, vc, CHIP_R600 }
  84 #define FMT_16_BIT(fmt, vc)  [fmt] = { 1, 1, 2, vc, CHIP_R600 }
  85 #define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 4,  0, CHIP_R600 }
  86 #define FMT_32_BIT(fmt, vc)  [fmt] = { 1, 1, 4, vc, CHIP_R600 }
  87 #define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 8,  0, CHIP_R600 }
  88 #define FMT_64_BIT(fmt, vc)  [fmt] = { 1, 1, 8, vc, CHIP_R600 }
  89 #define FMT_96_BIT(fmt)      [fmt] = { 1, 1, 12, 0, CHIP_R600 }
  90 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
  91
  92 struct gpu_formats {
  93         unsigned blockwidth;
  94         unsigned blockheight;
  95         unsigned blocksize;
  96         unsigned valid_color;
  97         enum radeon_family min_family;
  98 };
  99
 100 static const struct gpu_formats color_formats_table[] = {
 101         /* 8 bit */
 102         FMT_8_BIT(V_038004_COLOR_8, 1),
 103         FMT_8_BIT(V_038004_COLOR_4_4, 1),
 104         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
 105         FMT_8_BIT(V_038004_FMT_1, 0),
 106
 107         /* 16-bit */
 108         FMT_16_BIT(V_038004_COLOR_16, 1),
 109         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
 110         FMT_16_BIT(V_038004_COLOR_8_8, 1),
 111         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
 112         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
 113         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
 114         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
 115         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
 116
 117         /* 24-bit */
 118         FMT_24_BIT(V_038004_FMT_8_8_8),
 119
 120         /* 32-bit */
 121         FMT_32_BIT(V_038004_COLOR_32, 1),
 122         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
 123         FMT_32_BIT(V_038004_COLOR_16_16, 1),
 124         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
 125         FMT_32_BIT(V_038004_COLOR_8_24, 1),
 126         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
 127         FMT_32_BIT(V_038004_COLOR_24_8, 1),
 128         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
 129         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
 130         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
 131         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
 132         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
 133         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
 134         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
 135         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
 136         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
 137         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
 138         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
 139
 140         /* 48-bit */
 141         FMT_48_BIT(V_038004_FMT_16_16_16),
 142         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
 143
 144         /* 64-bit */
 145         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
 146         FMT_64_BIT(V_038004_COLOR_32_32, 1),
 147         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
 148         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
 149         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
 150
 151         FMT_96_BIT(V_038004_FMT_32_32_32),
 152         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
 153
 154         /* 128-bit */
 155         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
 156         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
 157
 158         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
 159         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
 160
 161         /* block compressed formats */
 162         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
 163         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
 164         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
 165         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
 166         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
 167         [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 168         [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 169
 170         /* The other Evergreen formats */
 171         [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
 172 };
 173
 174 bool r600_fmt_is_valid_color(u32 format)
 175 {
 176         if (format >= ARRAY_SIZE(color_formats_table))
 177                 return false;
 178
 179         if (color_formats_table[format].valid_color)
 180                 return true;
 181
 182         return false;
 183 }
 184
 185 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 186 {
 187         if (format >= ARRAY_SIZE(color_formats_table))
 188                 return false;
 189
 190         if (family < color_formats_table[format].min_family)
 191                 return false;
 192
 193         if (color_formats_table[format].blockwidth > 0)
 194                 return true;
 195
 196         return false;
 197 }
 198
 199 int r600_fmt_get_blocksize(u32 format)
 200 {
 201         if (format >= ARRAY_SIZE(color_formats_table))
 202                 return 0;
 203
 204         return color_formats_table[format].blocksize;
 205 }
 206
 207 int r600_fmt_get_nblocksx(u32 format, u32 w)
 208 {
 209         unsigned bw;
 210
 211         if (format >= ARRAY_SIZE(color_formats_table))
 212                 return 0;
 213
 214         bw = color_formats_table[format].blockwidth;
 215         if (bw == 0)
 216                 return 0;
 217
 218         return (w + bw - 1) / bw;
 219 }
 220
 221 int r600_fmt_get_nblocksy(u32 format, u32 h)
 222 {
 223         unsigned bh;
 224
 225         if (format >= ARRAY_SIZE(color_formats_table))
 226                 return 0;
 227
 228         bh = color_formats_table[format].blockheight;
 229         if (bh == 0)
 230                 return 0;
 231
 232         return (h + bh - 1) / bh;
 233 }
 234
 235 struct array_mode_checker {
 236         int array_mode;
 237         u32 group_size;
 238         u32 nbanks;
 239         u32 npipes;
 240         u32 nsamples;
 241         u32 blocksize;
 242 };
 243
 244 /* returns alignment in pixels for pitch/height/depth and bytes for base */
 245 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
 246                                                 u32 *pitch_align,
 247                                                 u32 *height_align,
 248                                                 u32 *depth_align,
 249                                                 u64 *base_align)
 250 {
 251         u32 tile_width = 8;
 252         u32 tile_height = 8;
 253         u32 macro_tile_width = values->nbanks;
 254         u32 macro_tile_height = values->npipes;
 255         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
 256         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
 257
 258         switch (values->array_mode) {
 259         case ARRAY_LINEAR_GENERAL:
 260                 /* technically tile_width/_height for pitch/height */
 261                 *pitch_align = 1; /* tile_width */
 262                 *height_align = 1; /* tile_height */
 263                 *depth_align = 1;
 264                 *base_align = 1;
 265                 break;
 266         case ARRAY_LINEAR_ALIGNED:
 267                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
 268                 *height_align = 1;
 269                 *depth_align = 1;
 270                 *base_align = values->group_size;
 271                 break;
 272         case ARRAY_1D_TILED_THIN1:
 273                 *pitch_align = max((u32)tile_width,
 274                                    (u32)(values->group_size /
 275                                          (tile_height * values->blocksize * values->nsamples)));
 276                 *height_align = tile_height;
 277                 *depth_align = 1;
 278                 *base_align = values->group_size;
 279                 break;
 280         case ARRAY_2D_TILED_THIN1:
 281                 *pitch_align = max((u32)macro_tile_width * tile_width,
 282                                 (u32)((values->group_size * values->nbanks) /
 283                                 (values->blocksize * values->nsamples * tile_width)));
 284                 *height_align = macro_tile_height * tile_height;
 285                 *depth_align = 1;
 286                 *base_align = max(macro_tile_bytes,
 287                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
 288                 break;
 289         default:
 290                 return -EINVAL;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static void r600_cs_track_init(struct r600_cs_track *track)
 297 {
 298         int i;
 299
 300         /* assume DX9 mode */
 301         track->sq_config = DX9_CONSTS;
 302         for (i = 0; i < 8; i++) {
 303                 track->cb_color_base_last[i] = 0;
 304                 track->cb_color_size[i] = 0;
 305                 track->cb_color_size_idx[i] = 0;
 306                 track->cb_color_info[i] = 0;
 307                 track->cb_color_view[i] = 0xFFFFFFFF;
 308                 track->cb_color_bo[i] = NULL;
 309                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 310                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
 311         }
 312         track->cb_target_mask = 0xFFFFFFFF;
 313         track->cb_shader_mask = 0xFFFFFFFF;
 314         track->cb_dirty = true;
 315         track->db_bo = NULL;
 316         track->db_bo_mc = 0xFFFFFFFF;
 317         /* assume the biggest format and that htile is enabled */
 318         track->db_depth_info = 7 | (1 << 25);
 319         track->db_depth_view = 0xFFFFC000;
 320         track->db_depth_size = 0xFFFFFFFF;
 321         track->db_depth_size_idx = 0;
 322         track->db_depth_control = 0xFFFFFFFF;
 323         track->db_dirty = true;
 324
 325         for (i = 0; i < 4; i++) {
 326                 track->vgt_strmout_size[i] = 0;
 327                 track->vgt_strmout_bo[i] = NULL;
 328                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 329                 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
 330         }
 331         track->streamout_dirty = true;
 332         track->sx_misc_kill_all_prims = false;
 333 }
 334
 335 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 336 {
 337         struct r600_cs_track *track = p->track;
 338         u32 slice_tile_max, size, tmp;
 339         u32 height, height_align, pitch, pitch_align, depth_align;
 340         u64 base_offset, base_align;
 341         struct array_mode_checker array_check;
 342         volatile u32 *ib = p->ib->ptr;
 343         unsigned array_mode;
 344         u32 format;
 345
 346         if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 347                 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
 348                 return -EINVAL;
 349         }
 350         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 351         format = G_0280A0_FORMAT(track->cb_color_info[i]);
 352         if (!r600_fmt_is_valid_color(format)) {
 353                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 354                          __func__, __LINE__, format,
 355                         i, track->cb_color_info[i]);
 356                 return -EINVAL;
 357         }
 358         /* pitch in pixels */
 359         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
 360         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 361         slice_tile_max *= 64;
 362         height = slice_tile_max / pitch;
 363         if (height > 8192)
 364                 height = 8192;
 365         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 366
 367         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
 368         array_check.array_mode = array_mode;
 369         array_check.group_size = track->group_size;
 370         array_check.nbanks = track->nbanks;
 371         array_check.npipes = track->npipes;
 372         array_check.nsamples = track->nsamples;
 373         array_check.blocksize = r600_fmt_get_blocksize(format);
 374         if (r600_get_array_mode_alignment(&array_check,
 375                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 376                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 377                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 378                          track->cb_color_info[i]);
 379                 return -EINVAL;
 380         }
 381         switch (array_mode) {
 382         case V_0280A0_ARRAY_LINEAR_GENERAL:
 383                 break;
 384         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 385                 break;
 386         case V_0280A0_ARRAY_1D_TILED_THIN1:
 387                 /* avoid breaking userspace */
 388                 if (height > 7)
 389                         height &= ~0x7;
 390                 break;
 391         case V_0280A0_ARRAY_2D_TILED_THIN1:
 392                 break;
 393         default:
 394                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 395                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 396                         track->cb_color_info[i]);
 397                 return -EINVAL;
 398         }
 399
 400         if (!IS_ALIGNED(pitch, pitch_align)) {
 401                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
 402                          __func__, __LINE__, pitch, pitch_align, array_mode);
 403                 return -EINVAL;
 404         }
 405         if (!IS_ALIGNED(height, height_align)) {
 406                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
 407                          __func__, __LINE__, height, height_align, array_mode);
 408                 return -EINVAL;
 409         }
 410         if (!IS_ALIGNED(base_offset, base_align)) {
 411                 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
 412                          base_offset, base_align, array_mode);
 413                 return -EINVAL;
 414         }
 415
 416         /* check offset */
 417         tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
 418         switch (array_mode) {
 419         default:
 420         case V_0280A0_ARRAY_LINEAR_GENERAL:
 421         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 422                 tmp += track->cb_color_view[i] & 0xFF;
 423                 break;
 424         case V_0280A0_ARRAY_1D_TILED_THIN1:
 425         case V_0280A0_ARRAY_2D_TILED_THIN1:
 426                 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
 427                 break;
 428         }
 429         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 430                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 431                         /* the initial DDX does bad things with the CB size occasionally */
 432                         /* it rounds up height too far for slice tile max but the BO is smaller */
 433                         /* r600c,g also seem to flush at bad times in some apps resulting in
 434                          * bogus values here. So for linear just allow anything to avoid breaking
 435                          * broken userspace.
 436                          */
 437                 } else {
 438                         dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
 439                                  __func__, i, array_mode,
 440                                  track->cb_color_bo_offset[i], tmp,
 441                                  radeon_bo_size(track->cb_color_bo[i]),
 442                                  pitch, height, r600_fmt_get_nblocksx(format, pitch),
 443                                  r600_fmt_get_nblocksy(format, height),
 444                                  r600_fmt_get_blocksize(format));
 445                         return -EINVAL;
 446                 }
 447         }
 448         /* limit max tile */
 449         tmp = (height * pitch) >> 6;
 450         if (tmp < slice_tile_max)
 451                 slice_tile_max = tmp;
 452         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
 453                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 454         ib[track->cb_color_size_idx[i]] = tmp;
 455         return 0;
 456 }
 457
 458 static int r600_cs_track_check(struct radeon_cs_parser *p)
 459 {
 460         struct r600_cs_track *track = p->track;
 461         u32 tmp;
 462         int r, i;
 463         volatile u32 *ib = p->ib->ptr;
 464
 465         /* on legacy kernel we don't perform advanced check */
 466         if (p->rdev == NULL)
 467                 return 0;
 468
 469         /* check streamout */
 470         if (track->streamout_dirty && track->vgt_strmout_en) {
 471                 for (i = 0; i < 4; i++) {
 472                         if (track->vgt_strmout_buffer_en & (1 << i)) {
 473                                 if (track->vgt_strmout_bo[i]) {
 474                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 475                                                 (u64)track->vgt_strmout_size[i];
 476                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 477                                                 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
 478                                                           i, offset,
 479                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
 480                                                 return -EINVAL;
 481                                         }
 482                                 } else {
 483                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
 484                                         return -EINVAL;
 485                                 }
 486                         }
 487                 }
 488                 track->streamout_dirty = false;
 489         }
 490
 491         if (track->sx_misc_kill_all_prims)
 492                 return 0;
 493
 494         /* check that we have a cb for each enabled target, we don't check
 495          * shader_mask because it seems mesa isn't always setting it :(
 496          */
 497         if (track->cb_dirty) {
 498                 tmp = track->cb_target_mask;
 499                 for (i = 0; i < 8; i++) {
 500                         if ((tmp >> (i * 4)) & 0xF) {
 501                                 /* at least one component is enabled */
 502                                 if (track->cb_color_bo[i] == NULL) {
 503                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 504                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 505                                         return -EINVAL;
 506                                 }
 507                                 /* perform rewrite of CB_COLOR[0-7]_SIZE */
 508                                 r = r600_cs_track_validate_cb(p, i);
 509                                 if (r)
 510                                         return r;
 511                         }
 512                 }
 513                 track->cb_dirty = false;
 514         }
 515
 516         if (track->db_dirty) {
 517                 /* Check depth buffer */
 518                 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 519                         G_028800_Z_ENABLE(track->db_depth_control)) {
 520                         u32 nviews, bpe, ntiles, size, slice_tile_max;
 521                         u32 height, height_align, pitch, pitch_align, depth_align;
 522                         u64 base_offset, base_align;
 523                         struct array_mode_checker array_check;
 524                         int array_mode;
 525
 526                         if (track->db_bo == NULL) {
 527                                 dev_warn(p->dev, "z/stencil with no depth buffer\n");
 528                                 return -EINVAL;
 529                         }
 530                         if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 531                                 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
 532                                 return -EINVAL;
 533                         }
 534                         switch (G_028010_FORMAT(track->db_depth_info)) {
 535                         case V_028010_DEPTH_16:
 536                                 bpe = 2;
 537                                 break;
 538                         case V_028010_DEPTH_X8_24:
 539                         case V_028010_DEPTH_8_24:
 540                         case V_028010_DEPTH_X8_24_FLOAT:
 541                         case V_028010_DEPTH_8_24_FLOAT:
 542                         case V_028010_DEPTH_32_FLOAT:
 543                                 bpe = 4;
 544                                 break;
 545                         case V_028010_DEPTH_X24_8_32_FLOAT:
 546                                 bpe = 8;
 547                                 break;
 548                         default:
 549                                 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 550                                 return -EINVAL;
 551                         }
 552                         if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 553                                 if (!track->db_depth_size_idx) {
 554                                         dev_warn(p->dev, "z/stencil buffer size not set\n");
 555                                         return -EINVAL;
 556                                 }
 557                                 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 558                                 tmp = (tmp / bpe) >> 6;
 559                                 if (!tmp) {
 560                                         dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 561                                                         track->db_depth_size, bpe, track->db_offset,
 562                                                         radeon_bo_size(track->db_bo));
 563                                         return -EINVAL;
 564                                 }
 565                                 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 566                         } else {
 567                                 size = radeon_bo_size(track->db_bo);
 568                                 /* pitch in pixels */
 569                                 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
 570                                 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 571                                 slice_tile_max *= 64;
 572                                 height = slice_tile_max / pitch;
 573                                 if (height > 8192)
 574                                         height = 8192;
 575                                 base_offset = track->db_bo_mc + track->db_offset;
 576                                 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
 577                                 array_check.array_mode = array_mode;
 578                                 array_check.group_size = track->group_size;
 579                                 array_check.nbanks = track->nbanks;
 580                                 array_check.npipes = track->npipes;
 581                                 array_check.nsamples = track->nsamples;
 582                                 array_check.blocksize = bpe;
 583                                 if (r600_get_array_mode_alignment(&array_check,
 584                                                                   &pitch_align, &height_align, &depth_align, &base_align)) {
 585                                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 586                                                  G_028010_ARRAY_MODE(track->db_depth_info),
 587                                                  track->db_depth_info);
 588                                         return -EINVAL;
 589                                 }
 590                                 switch (array_mode) {
 591                                 case V_028010_ARRAY_1D_TILED_THIN1:
 592                                         /* don't break userspace */
 593                                         height &= ~0x7;
 594                                         break;
 595                                 case V_028010_ARRAY_2D_TILED_THIN1:
 596                                         break;
 597                                 default:
 598                                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 599                                                  G_028010_ARRAY_MODE(track->db_depth_info),
 600                                                  track->db_depth_info);
 601                                         return -EINVAL;
 602                                 }
 603
 604                                 if (!IS_ALIGNED(pitch, pitch_align)) {
 605                                         dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
 606                                                  __func__, __LINE__, pitch, pitch_align, array_mode);
 607                                         return -EINVAL;
 608                                 }
 609                                 if (!IS_ALIGNED(height, height_align)) {
 610                                         dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
 611                                                  __func__, __LINE__, height, height_align, array_mode);
 612                                         return -EINVAL;
 613                                 }
 614                                 if (!IS_ALIGNED(base_offset, base_align)) {
 615                                         dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
 616                                                  base_offset, base_align, array_mode);
 617                                         return -EINVAL;
 618                                 }
 619
 620                                 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 621                                 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 622                                 tmp = ntiles * bpe * 64 * nviews;
 623                                 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 624                                         dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
 625                                                  array_mode,
 626                                                  track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 627                                                  radeon_bo_size(track->db_bo));
 628                                         return -EINVAL;
 629                                 }
 630                         }
 631                 }
 632                 track->db_dirty = false;
 633         }
 634         return 0;
 635 }
 636
 637 /**
 638  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 639  * @parser:     parser structure holding parsing context.
 640  * @pkt:        where to store packet informations
 641  *
 642  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 643  * if packet is bigger than remaining ib size. or if packets is unknown.
 644  **/
 645 int r600_cs_packet_parse(struct radeon_cs_parser *p,
 646                         struct radeon_cs_packet *pkt,
 647                         unsigned idx)
 648 {
 649         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 650         uint32_t header;
 651
 652         if (idx >= ib_chunk->length_dw) {
 653                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 654                           idx, ib_chunk->length_dw);
 655                 return -EINVAL;
 656         }
 657         header = radeon_get_ib_value(p, idx);
 658         pkt->idx = idx;
 659         pkt->type = CP_PACKET_GET_TYPE(header);
 660         pkt->count = CP_PACKET_GET_COUNT(header);
 661         pkt->one_reg_wr = 0;
 662         switch (pkt->type) {
 663         case PACKET_TYPE0:
 664                 pkt->reg = CP_PACKET0_GET_REG(header);
 665                 break;
 666         case PACKET_TYPE3:
 667                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 668                 break;
 669         case PACKET_TYPE2:
 670                 pkt->count = -1;
 671                 break;
 672         default:
 673                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 674                 return -EINVAL;
 675         }
 676         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 677                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 678                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 679                 return -EINVAL;
 680         }
 681         return 0;
 682 }
 683
 684 /**
 685  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 686  * @parser:             parser structure holding parsing context.
 687  * @data:               pointer to relocation data
 688  * @offset_start:       starting offset
 689  * @offset_mask:        offset mask (to align start offset on)
 690  * @reloc:              reloc informations
 691  *
 692  * Check next packet is relocation packet3, do bo validation and compute
 693  * GPU offset using the provided start.
 694  **/
 695 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 696                                         struct radeon_cs_reloc **cs_reloc)
 697 {
 698         struct radeon_cs_chunk *relocs_chunk;
 699         struct radeon_cs_packet p3reloc;
 700         unsigned idx;
 701         int r;
 702
 703         if (p->chunk_relocs_idx == -1) {
 704                 DRM_ERROR("No relocation chunk !\n");
 705                 return -EINVAL;
 706         }
 707         *cs_reloc = NULL;
 708         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 709         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 710         if (r) {
 711                 return r;
 712         }
 713         p->idx += p3reloc.count + 2;
 714         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 715                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 716                           p3reloc.idx);
 717                 return -EINVAL;
 718         }
 719         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 720         if (idx >= relocs_chunk->length_dw) {
 721                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 722                           idx, relocs_chunk->length_dw);
 723                 return -EINVAL;
 724         }
 725         /* FIXME: we assume reloc size is 4 dwords */
 726         *cs_reloc = p->relocs_ptr[(idx / 4)];
 727         return 0;
 728 }
 729
 730 /**
 731  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 732  * @parser:             parser structure holding parsing context.
 733  * @data:               pointer to relocation data
 734  * @offset_start:       starting offset
 735  * @offset_mask:        offset mask (to align start offset on)
 736  * @reloc:              reloc informations
 737  *
 738  * Check next packet is relocation packet3, do bo validation and compute
 739  * GPU offset using the provided start.
 740  **/
 741 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 742                                         struct radeon_cs_reloc **cs_reloc)
 743 {
 744         struct radeon_cs_chunk *relocs_chunk;
 745         struct radeon_cs_packet p3reloc;
 746         unsigned idx;
 747         int r;
 748
 749         if (p->chunk_relocs_idx == -1) {
 750                 DRM_ERROR("No relocation chunk !\n");
 751                 return -EINVAL;
 752         }
 753         *cs_reloc = NULL;
 754         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 755         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 756         if (r) {
 757                 return r;
 758         }
 759         p->idx += p3reloc.count + 2;
 760         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 761                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 762                           p3reloc.idx);
 763                 return -EINVAL;
 764         }
 765         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 766         if (idx >= relocs_chunk->length_dw) {
 767                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 768                           idx, relocs_chunk->length_dw);
 769                 return -EINVAL;
 770         }
 771         *cs_reloc = p->relocs;
 772         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 773         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 774         return 0;
 775 }
 776
 777 /**
 778  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 779  * @parser:             parser structure holding parsing context.
 780  *
 781  * Check next packet is relocation packet3, do bo validation and compute
 782  * GPU offset using the provided start.
 783  **/
 784 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 785 {
 786         struct radeon_cs_packet p3reloc;
 787         int r;
 788
 789         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 790         if (r) {
 791                 return 0;
 792         }
 793         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 794                 return 0;
 795         }
 796         return 1;
 797 }
 798
 799 /**
 800  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 801  * @parser:             parser structure holding parsing context.
 802  *
 803  * Userspace sends a special sequence for VLINE waits.
 804  * PACKET0 - VLINE_START_END + value
 805  * PACKET3 - WAIT_REG_MEM poll vline status reg
 806  * RELOC (P3) - crtc_id in reloc.
 807  *
 808  * This function parses this and relocates the VLINE START END
 809  * and WAIT_REG_MEM packets to the correct crtc.
 810  * It also detects a switched off crtc and nulls out the
 811  * wait in that case.
 812  */
 813 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 814 {
 815         struct drm_mode_object *obj;
 816         struct drm_crtc *crtc;
 817         struct radeon_crtc *radeon_crtc;
 818         struct radeon_cs_packet p3reloc, wait_reg_mem;
 819         int crtc_id;
 820         int r;
 821         uint32_t header, h_idx, reg, wait_reg_mem_info;
 822         volatile uint32_t *ib;
 823
 824         ib = p->ib->ptr;
 825
 826         /* parse the WAIT_REG_MEM */
 827         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 828         if (r)
 829                 return r;
 830
 831         /* check its a WAIT_REG_MEM */
 832         if (wait_reg_mem.type != PACKET_TYPE3 ||
 833             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 834                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 835                 return -EINVAL;
 836         }
 837
 838         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 839         /* bit 4 is reg (0) or mem (1) */
 840         if (wait_reg_mem_info & 0x10) {
 841                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 842                 return -EINVAL;
 843         }
 844         /* waiting for value to be equal */
 845         if ((wait_reg_mem_info & 0x7) != 0x3) {
 846                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
 847                 return -EINVAL;
 848         }
 849         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
 850                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
 851                 return -EINVAL;
 852         }
 853
 854         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
 855                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
 856                 return -EINVAL;
 857         }
 858
 859         /* jump over the NOP */
 860         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
 861         if (r)
 862                 return r;
 863
 864         h_idx = p->idx - 2;
 865         p->idx += wait_reg_mem.count + 2;
 866         p->idx += p3reloc.count + 2;
 867
 868         header = radeon_get_ib_value(p, h_idx);
 869         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
 870         reg = CP_PACKET0_GET_REG(header);
 871
 872         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 873         if (!obj) {
 874                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 875                 return -EINVAL;
 876         }
 877         crtc = obj_to_crtc(obj);
 878         radeon_crtc = to_radeon_crtc(crtc);
 879         crtc_id = radeon_crtc->crtc_id;
 880
 881         if (!crtc->enabled) {
 882                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
 883                 ib[h_idx + 2] = PACKET2(0);
 884                 ib[h_idx + 3] = PACKET2(0);
 885                 ib[h_idx + 4] = PACKET2(0);
 886                 ib[h_idx + 5] = PACKET2(0);
 887                 ib[h_idx + 6] = PACKET2(0);
 888                 ib[h_idx + 7] = PACKET2(0);
 889                 ib[h_idx + 8] = PACKET2(0);
 890         } else if (crtc_id == 1) {
 891                 switch (reg) {
 892                 case AVIVO_D1MODE_VLINE_START_END:
 893                         header &= ~R600_CP_PACKET0_REG_MASK;
 894                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
 895                         break;
 896                 default:
 897                         DRM_ERROR("unknown crtc reloc\n");
 898                         return -EINVAL;
 899                 }
 900                 ib[h_idx] = header;
 901                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
 902         }
 903
 904         return 0;
 905 }
 906
 907 static int r600_packet0_check(struct radeon_cs_parser *p,
 908                                 struct radeon_cs_packet *pkt,
 909                                 unsigned idx, unsigned reg)
 910 {
 911         int r;
 912
 913         switch (reg) {
 914         case AVIVO_D1MODE_VLINE_START_END:
 915                 r = r600_cs_packet_parse_vline(p);
 916                 if (r) {
 917                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 918                                         idx, reg);
 919                         return r;
 920                 }
 921                 break;
 922         default:
 923                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
 924                        reg, idx);
 925                 return -EINVAL;
 926         }
 927         return 0;
 928 }
 929
 930 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
 931                                 struct radeon_cs_packet *pkt)
 932 {
 933         unsigned reg, i;
 934         unsigned idx;
 935         int r;
 936
 937         idx = pkt->idx + 1;
 938         reg = pkt->reg;
 939         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
 940                 r = r600_packet0_check(p, pkt, idx, reg);
 941                 if (r) {
 942                         return r;
 943                 }
 944         }
 945         return 0;
 946 }
 947
 948 /**
 949  * r600_cs_check_reg() - check if register is authorized or not
 950  * @parser: parser structure holding parsing context
 951  * @reg: register we are testing
 952  * @idx: index into the cs buffer
 953  *
 954  * This function will test against r600_reg_safe_bm and return 0
 955  * if register is safe. If register is not flag as safe this function
 956  * will test it against a list of register needind special handling.
 957  */
 958 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 959 {
 960         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
 961         struct radeon_cs_reloc *reloc;
 962         u32 m, i, tmp, *ib;
 963         int r;
 964
 965         i = (reg >> 7);
 966         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
 967                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
 968                 return -EINVAL;
 969         }
 970         m = 1 << ((reg >> 2) & 31);
 971         if (!(r600_reg_safe_bm[i] & m))
 972                 return 0;
 973         ib = p->ib->ptr;
 974         switch (reg) {
 975         /* force following reg to 0 in an attempt to disable out buffer
 976          * which will need us to better understand how it works to perform
 977          * security check on it (Jerome)
 978          */
 979         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
 980         case R_008C44_SQ_ESGS_RING_SIZE:
 981         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
 982         case R_008C54_SQ_ESTMP_RING_SIZE:
 983         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
 984         case R_008C74_SQ_FBUF_RING_SIZE:
 985         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
 986         case R_008C5C_SQ_GSTMP_RING_SIZE:
 987         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
 988         case R_008C4C_SQ_GSVS_RING_SIZE:
 989         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
 990         case R_008C6C_SQ_PSTMP_RING_SIZE:
 991         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
 992         case R_008C7C_SQ_REDUC_RING_SIZE:
 993         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
 994         case R_008C64_SQ_VSTMP_RING_SIZE:
 995         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
 996                 /* get value to populate the IB don't remove */
 997                 tmp =radeon_get_ib_value(p, idx);
 998                 ib[idx] = 0;
 999                 break;
1000         case SQ_CONFIG:
1001                 track->sq_config = radeon_get_ib_value(p, idx);
1002                 break;
1003         case R_028800_DB_DEPTH_CONTROL:
1004                 track->db_depth_control = radeon_get_ib_value(p, idx);
1005                 track->db_dirty = true;
1006                 break;
1007         case R_028010_DB_DEPTH_INFO:
1008                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1009                     r600_cs_packet_next_is_pkt3_nop(p)) {
1010                         r = r600_cs_packet_next_reloc(p, &reloc);
1011                         if (r) {
1012                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1013                                          "0x%04X\n", reg);
1014                                 return -EINVAL;
1015                         }
1016                         track->db_depth_info = radeon_get_ib_value(p, idx);
1017                         ib[idx] &= C_028010_ARRAY_MODE;
1018                         track->db_depth_info &= C_028010_ARRAY_MODE;
1019                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1020                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1021                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1022                         } else {
1023                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1024                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1025                         }
1026                 } else {
1027                         track->db_depth_info = radeon_get_ib_value(p, idx);
1028                 }
1029                 track->db_dirty = true;
1030                 break;
1031         case R_028004_DB_DEPTH_VIEW:
1032                 track->db_depth_view = radeon_get_ib_value(p, idx);
1033                 track->db_dirty = true;
1034                 break;
1035         case R_028000_DB_DEPTH_SIZE:
1036                 track->db_depth_size = radeon_get_ib_value(p, idx);
1037                 track->db_depth_size_idx = idx;
1038                 track->db_dirty = true;
1039                 break;
1040         case R_028AB0_VGT_STRMOUT_EN:
1041                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1042                 track->streamout_dirty = true;
1043                 break;
1044         case R_028B20_VGT_STRMOUT_BUFFER_EN:
1045                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1046                 track->streamout_dirty = true;
1047                 break;
1048         case VGT_STRMOUT_BUFFER_BASE_0:
1049         case VGT_STRMOUT_BUFFER_BASE_1:
1050         case VGT_STRMOUT_BUFFER_BASE_2:
1051         case VGT_STRMOUT_BUFFER_BASE_3:
1052                 r = r600_cs_packet_next_reloc(p, &reloc);
1053                 if (r) {
1054                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1055                                         "0x%04X\n", reg);
1056                         return -EINVAL;
1057                 }
1058                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1059                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1060                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1061                 track->vgt_strmout_bo[tmp] = reloc->robj;
1062                 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1063                 track->streamout_dirty = true;
1064                 break;
1065         case VGT_STRMOUT_BUFFER_SIZE_0:
1066         case VGT_STRMOUT_BUFFER_SIZE_1:
1067         case VGT_STRMOUT_BUFFER_SIZE_2:
1068         case VGT_STRMOUT_BUFFER_SIZE_3:
1069                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1070                 /* size in register is DWs, convert to bytes */
1071                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1072                 track->streamout_dirty = true;
1073                 break;
1074         case CP_COHER_BASE:
1075                 r = r600_cs_packet_next_reloc(p, &reloc);
1076                 if (r) {
1077                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1078                                         "0x%04X\n", reg);
1079                         return -EINVAL;
1080                 }
1081                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1082                 break;
1083         case R_028238_CB_TARGET_MASK:
1084                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1085                 track->cb_dirty = true;
1086                 break;
1087         case R_02823C_CB_SHADER_MASK:
1088                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1089                 break;
1090         case R_028C04_PA_SC_AA_CONFIG:
1091                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1092                 track->nsamples = 1 << tmp;
1093                 track->cb_dirty = true;
1094                 break;
1095         case R_0280A0_CB_COLOR0_INFO:
1096         case R_0280A4_CB_COLOR1_INFO:
1097         case R_0280A8_CB_COLOR2_INFO:
1098         case R_0280AC_CB_COLOR3_INFO:
1099         case R_0280B0_CB_COLOR4_INFO:
1100         case R_0280B4_CB_COLOR5_INFO:
1101         case R_0280B8_CB_COLOR6_INFO:
1102         case R_0280BC_CB_COLOR7_INFO:
1103                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1104                      r600_cs_packet_next_is_pkt3_nop(p)) {
1105                         r = r600_cs_packet_next_reloc(p, &reloc);
1106                         if (r) {
1107                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1108                                 return -EINVAL;
1109                         }
1110                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1111                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1112                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1113                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1114                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1115                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1116                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1117                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1118                         }
1119                 } else {
1120                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1121                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1122                 }
1123                 track->cb_dirty = true;
1124                 break;
1125         case R_028080_CB_COLOR0_VIEW:
1126         case R_028084_CB_COLOR1_VIEW:
1127         case R_028088_CB_COLOR2_VIEW:
1128         case R_02808C_CB_COLOR3_VIEW:
1129         case R_028090_CB_COLOR4_VIEW:
1130         case R_028094_CB_COLOR5_VIEW:
1131         case R_028098_CB_COLOR6_VIEW:
1132         case R_02809C_CB_COLOR7_VIEW:
1133                 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1134                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1135                 track->cb_dirty = true;
1136                 break;
1137         case R_028060_CB_COLOR0_SIZE:
1138         case R_028064_CB_COLOR1_SIZE:
1139         case R_028068_CB_COLOR2_SIZE:
1140         case R_02806C_CB_COLOR3_SIZE:
1141         case R_028070_CB_COLOR4_SIZE:
1142         case R_028074_CB_COLOR5_SIZE:
1143         case R_028078_CB_COLOR6_SIZE:
1144         case R_02807C_CB_COLOR7_SIZE:
1145                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1146                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1147                 track->cb_color_size_idx[tmp] = idx;
1148                 track->cb_dirty = true;
1149                 break;
1150                 /* This register were added late, there is userspace
1151                  * which does provide relocation for those but set
1152                  * 0 offset. In order to avoid breaking old userspace
1153                  * we detect this and set address to point to last
1154                  * CB_COLOR0_BASE, note that if userspace doesn't set
1155                  * CB_COLOR0_BASE before this register we will report
1156                  * error. Old userspace always set CB_COLOR0_BASE
1157                  * before any of this.
1158                  */
1159         case R_0280E0_CB_COLOR0_FRAG:
1160         case R_0280E4_CB_COLOR1_FRAG:
1161         case R_0280E8_CB_COLOR2_FRAG:
1162         case R_0280EC_CB_COLOR3_FRAG:
1163         case R_0280F0_CB_COLOR4_FRAG:
1164         case R_0280F4_CB_COLOR5_FRAG:
1165         case R_0280F8_CB_COLOR6_FRAG:
1166         case R_0280FC_CB_COLOR7_FRAG:
1167                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1168                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1169                         if (!track->cb_color_base_last[tmp]) {
1170                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1171                                 return -EINVAL;
1172                         }
1173                         ib[idx] = track->cb_color_base_last[tmp];
1174                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1175                 } else {
1176                         r = r600_cs_packet_next_reloc(p, &reloc);
1177                         if (r) {
1178                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1179                                 return -EINVAL;
1180                         }
1181                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1182                         track->cb_color_frag_bo[tmp] = reloc->robj;
1183                 }
1184                 break;
1185         case R_0280C0_CB_COLOR0_TILE:
1186         case R_0280C4_CB_COLOR1_TILE:
1187         case R_0280C8_CB_COLOR2_TILE:
1188         case R_0280CC_CB_COLOR3_TILE:
1189         case R_0280D0_CB_COLOR4_TILE:
1190         case R_0280D4_CB_COLOR5_TILE:
1191         case R_0280D8_CB_COLOR6_TILE:
1192         case R_0280DC_CB_COLOR7_TILE:
1193                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1194                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1195                         if (!track->cb_color_base_last[tmp]) {
1196                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1197                                 return -EINVAL;
1198                         }
1199                         ib[idx] = track->cb_color_base_last[tmp];
1200                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1201                 } else {
1202                         r = r600_cs_packet_next_reloc(p, &reloc);
1203                         if (r) {
1204                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1205                                 return -EINVAL;
1206                         }
1207                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1208                         track->cb_color_tile_bo[tmp] = reloc->robj;
1209                 }
1210                 break;
1211         case CB_COLOR0_BASE:
1212         case CB_COLOR1_BASE:
1213         case CB_COLOR2_BASE:
1214         case CB_COLOR3_BASE:
1215         case CB_COLOR4_BASE:
1216         case CB_COLOR5_BASE:
1217         case CB_COLOR6_BASE:
1218         case CB_COLOR7_BASE:
1219                 r = r600_cs_packet_next_reloc(p, &reloc);
1220                 if (r) {
1221                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1222                                         "0x%04X\n", reg);
1223                         return -EINVAL;
1224                 }
1225                 tmp = (reg - CB_COLOR0_BASE) / 4;
1226                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1227                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1228                 track->cb_color_base_last[tmp] = ib[idx];
1229                 track->cb_color_bo[tmp] = reloc->robj;
1230                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1231                 track->cb_dirty = true;
1232                 break;
1233         case DB_DEPTH_BASE:
1234                 r = r600_cs_packet_next_reloc(p, &reloc);
1235                 if (r) {
1236                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1237                                         "0x%04X\n", reg);
1238                         return -EINVAL;
1239                 }
1240                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1241                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1242                 track->db_bo = reloc->robj;
1243                 track->db_bo_mc = reloc->lobj.gpu_offset;
1244                 track->db_dirty = true;
1245                 break;
1246         case DB_HTILE_DATA_BASE:
1247         case SQ_PGM_START_FS:
1248         case SQ_PGM_START_ES:
1249         case SQ_PGM_START_VS:
1250         case SQ_PGM_START_GS:
1251         case SQ_PGM_START_PS:
1252         case SQ_ALU_CONST_CACHE_GS_0:
1253         case SQ_ALU_CONST_CACHE_GS_1:
1254         case SQ_ALU_CONST_CACHE_GS_2:
1255         case SQ_ALU_CONST_CACHE_GS_3:
1256         case SQ_ALU_CONST_CACHE_GS_4:
1257         case SQ_ALU_CONST_CACHE_GS_5:
1258         case SQ_ALU_CONST_CACHE_GS_6:
1259         case SQ_ALU_CONST_CACHE_GS_7:
1260         case SQ_ALU_CONST_CACHE_GS_8:
1261         case SQ_ALU_CONST_CACHE_GS_9:
1262         case SQ_ALU_CONST_CACHE_GS_10:
1263         case SQ_ALU_CONST_CACHE_GS_11:
1264         case SQ_ALU_CONST_CACHE_GS_12:
1265         case SQ_ALU_CONST_CACHE_GS_13:
1266         case SQ_ALU_CONST_CACHE_GS_14:
1267         case SQ_ALU_CONST_CACHE_GS_15:
1268         case SQ_ALU_CONST_CACHE_PS_0:
1269         case SQ_ALU_CONST_CACHE_PS_1:
1270         case SQ_ALU_CONST_CACHE_PS_2:
1271         case SQ_ALU_CONST_CACHE_PS_3:
1272         case SQ_ALU_CONST_CACHE_PS_4:
1273         case SQ_ALU_CONST_CACHE_PS_5:
1274         case SQ_ALU_CONST_CACHE_PS_6:
1275         case SQ_ALU_CONST_CACHE_PS_7:
1276         case SQ_ALU_CONST_CACHE_PS_8:
1277         case SQ_ALU_CONST_CACHE_PS_9:
1278         case SQ_ALU_CONST_CACHE_PS_10:
1279         case SQ_ALU_CONST_CACHE_PS_11:
1280         case SQ_ALU_CONST_CACHE_PS_12:
1281         case SQ_ALU_CONST_CACHE_PS_13:
1282         case SQ_ALU_CONST_CACHE_PS_14:
1283         case SQ_ALU_CONST_CACHE_PS_15:
1284         case SQ_ALU_CONST_CACHE_VS_0:
1285         case SQ_ALU_CONST_CACHE_VS_1:
1286         case SQ_ALU_CONST_CACHE_VS_2:
1287         case SQ_ALU_CONST_CACHE_VS_3:
1288         case SQ_ALU_CONST_CACHE_VS_4:
1289         case SQ_ALU_CONST_CACHE_VS_5:
1290         case SQ_ALU_CONST_CACHE_VS_6:
1291         case SQ_ALU_CONST_CACHE_VS_7:
1292         case SQ_ALU_CONST_CACHE_VS_8:
1293         case SQ_ALU_CONST_CACHE_VS_9:
1294         case SQ_ALU_CONST_CACHE_VS_10:
1295         case SQ_ALU_CONST_CACHE_VS_11:
1296         case SQ_ALU_CONST_CACHE_VS_12:
1297         case SQ_ALU_CONST_CACHE_VS_13:
1298         case SQ_ALU_CONST_CACHE_VS_14:
1299         case SQ_ALU_CONST_CACHE_VS_15:
1300                 r = r600_cs_packet_next_reloc(p, &reloc);
1301                 if (r) {
1302                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1303                                         "0x%04X\n", reg);
1304                         return -EINVAL;
1305                 }
1306                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1307                 break;
1308         case SX_MEMORY_EXPORT_BASE:
1309                 r = r600_cs_packet_next_reloc(p, &reloc);
1310                 if (r) {
1311                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1312                                         "0x%04X\n", reg);
1313                         return -EINVAL;
1314                 }
1315                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1316                 break;
1317         case SX_MISC:
1318                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1319                 break;
1320         default:
1321                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1322                 return -EINVAL;
1323         }
1324         return 0;
1325 }
1326
1327 unsigned r600_mip_minify(unsigned size, unsigned level)
1328 {
1329         unsigned val;
1330
1331         val = max(1U, size >> level);
1332         if (level > 0)
1333                 val = roundup_pow_of_two(val);
1334         return val;
1335 }
1336
1337 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1338                               unsigned w0, unsigned h0, unsigned d0, unsigned format,
1339                               unsigned block_align, unsigned height_align, unsigned base_align,
1340                               unsigned *l0_size, unsigned *mipmap_size)
1341 {
1342         unsigned offset, i, level;
1343         unsigned width, height, depth, size;
1344         unsigned blocksize;
1345         unsigned nbx, nby;
1346         unsigned nlevels = llevel - blevel + 1;
1347
1348         *l0_size = -1;
1349         blocksize = r600_fmt_get_blocksize(format);
1350
1351         w0 = r600_mip_minify(w0, 0);
1352         h0 = r600_mip_minify(h0, 0);
1353         d0 = r600_mip_minify(d0, 0);
1354         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1355                 width = r600_mip_minify(w0, i);
1356                 nbx = r600_fmt_get_nblocksx(format, width);
1357
1358                 nbx = round_up(nbx, block_align);
1359
1360                 height = r600_mip_minify(h0, i);
1361                 nby = r600_fmt_get_nblocksy(format, height);
1362                 nby = round_up(nby, height_align);
1363
1364                 depth = r600_mip_minify(d0, i);
1365
1366                 size = nbx * nby * blocksize;
1367                 if (nfaces)
1368                         size *= nfaces;
1369                 else
1370                         size *= depth;
1371
1372                 if (i == 0)
1373                         *l0_size = size;
1374
1375                 if (i == 0 || i == 1)
1376                         offset = round_up(offset, base_align);
1377
1378                 offset += size;
1379         }
1380         *mipmap_size = offset;
1381         if (llevel == 0)
1382                 *mipmap_size = *l0_size;
1383         if (!blevel)
1384                 *mipmap_size -= *l0_size;
1385 }
1386
1387 /**
1388  * r600_check_texture_resource() - check if register is authorized or not
1389  * @p: parser structure holding parsing context
1390  * @idx: index into the cs buffer
1391  * @texture: texture's bo structure
1392  * @mipmap: mipmap's bo structure
1393  *
1394  * This function will check that the resource has valid field and that
1395  * the texture and mipmap bo object are big enough to cover this resource.
1396  */
1397 static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1398                                               struct radeon_bo *texture,
1399                                               struct radeon_bo *mipmap,
1400                                               u64 base_offset,
1401                                               u64 mip_offset,
1402                                               u32 tiling_flags)
1403 {
1404         struct r600_cs_track *track = p->track;
1405         u32 nfaces, llevel, blevel, w0, h0, d0;
1406         u32 word0, word1, l0_size, mipmap_size, word2, word3;
1407         u32 height_align, pitch, pitch_align, depth_align;
1408         u32 array, barray, larray;
1409         u64 base_align;
1410         struct array_mode_checker array_check;
1411         u32 format;
1412
1413         /* on legacy kernel we don't perform advanced check */
1414         if (p->rdev == NULL)
1415                 return 0;
1416
1417         /* convert to bytes */
1418         base_offset <<= 8;
1419         mip_offset <<= 8;
1420
1421         word0 = radeon_get_ib_value(p, idx + 0);
1422         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1423                 if (tiling_flags & RADEON_TILING_MACRO)
1424                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1425                 else if (tiling_flags & RADEON_TILING_MICRO)
1426                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1427         }
1428         word1 = radeon_get_ib_value(p, idx + 1);
1429         w0 = G_038000_TEX_WIDTH(word0) + 1;
1430         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1431         d0 = G_038004_TEX_DEPTH(word1);
1432         nfaces = 1;
1433         array = 0;
1434         switch (G_038000_DIM(word0)) {
1435         case V_038000_SQ_TEX_DIM_1D:
1436         case V_038000_SQ_TEX_DIM_2D:
1437         case V_038000_SQ_TEX_DIM_3D:
1438                 break;
1439         case V_038000_SQ_TEX_DIM_CUBEMAP:
1440                 if (p->family >= CHIP_RV770)
1441                         nfaces = 8;
1442                 else
1443                         nfaces = 6;
1444                 break;
1445         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1446         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1447                 array = 1;
1448                 break;
1449         case V_038000_SQ_TEX_DIM_2D_MSAA:
1450         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1451         default:
1452                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1453                 return -EINVAL;
1454         }
1455         format = G_038004_DATA_FORMAT(word1);
1456         if (!r600_fmt_is_valid_texture(format, p->family)) {
1457                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1458                          __func__, __LINE__, format);
1459                 return -EINVAL;
1460         }
1461
1462         /* pitch in texels */
1463         pitch = (G_038000_PITCH(word0) + 1) * 8;
1464         array_check.array_mode = G_038000_TILE_MODE(word0);
1465         array_check.group_size = track->group_size;
1466         array_check.nbanks = track->nbanks;
1467         array_check.npipes = track->npipes;
1468         array_check.nsamples = 1;
1469         array_check.blocksize = r600_fmt_get_blocksize(format);
1470         if (r600_get_array_mode_alignment(&array_check,
1471                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1472                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1473                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1474                 return -EINVAL;
1475         }
1476
1477         /* XXX check height as well... */
1478
1479         if (!IS_ALIGNED(pitch, pitch_align)) {
1480                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1481                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1482                 return -EINVAL;
1483         }
1484         if (!IS_ALIGNED(base_offset, base_align)) {
1485                 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1486                          __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1487                 return -EINVAL;
1488         }
1489         if (!IS_ALIGNED(mip_offset, base_align)) {
1490                 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1491                          __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1492                 return -EINVAL;
1493         }
1494
1495         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1496         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1497
1498         word0 = radeon_get_ib_value(p, idx + 4);
1499         word1 = radeon_get_ib_value(p, idx + 5);
1500         blevel = G_038010_BASE_LEVEL(word0);
1501         llevel = G_038014_LAST_LEVEL(word1);
1502         if (blevel > llevel) {
1503                 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1504                          blevel, llevel);
1505         }
1506         if (array == 1) {
1507                 barray = G_038014_BASE_ARRAY(word1);
1508                 larray = G_038014_LAST_ARRAY(word1);
1509
1510                 nfaces = larray - barray + 1;
1511         }
1512         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1513                           pitch_align, height_align, base_align,
1514                           &l0_size, &mipmap_size);
1515         /* using get ib will give us the offset into the texture bo */
1516         if ((l0_size + word2) > radeon_bo_size(texture)) {
1517                 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1518                          w0, h0, pitch_align, height_align,
1519                          array_check.array_mode, format, word2,
1520                          l0_size, radeon_bo_size(texture));
1521                 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1522                 return -EINVAL;
1523         }
1524         /* using get ib will give us the offset into the mipmap bo */
1525         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1526         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1527                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1528                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1529         }
1530         return 0;
1531 }
1532
1533 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1534 {
1535         u32 m, i;
1536
1537         i = (reg >> 7);
1538         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1539                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1540                 return false;
1541         }
1542         m = 1 << ((reg >> 2) & 31);
1543         if (!(r600_reg_safe_bm[i] & m))
1544                 return true;
1545         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1546         return false;
1547 }
1548
1549 static int r600_packet3_check(struct radeon_cs_parser *p,
1550                                 struct radeon_cs_packet *pkt)
1551 {
1552         struct radeon_cs_reloc *reloc;
1553         struct r600_cs_track *track;
1554         volatile u32 *ib;
1555         unsigned idx;
1556         unsigned i;
1557         unsigned start_reg, end_reg, reg;
1558         int r;
1559         u32 idx_value;
1560
1561         track = (struct r600_cs_track *)p->track;
1562         ib = p->ib->ptr;
1563         idx = pkt->idx + 1;
1564         idx_value = radeon_get_ib_value(p, idx);
1565
1566         switch (pkt->opcode) {
1567         case PACKET3_SET_PREDICATION:
1568         {
1569                 int pred_op;
1570                 int tmp;
1571                 uint64_t offset;
1572
1573                 if (pkt->count != 1) {
1574                         DRM_ERROR("bad SET PREDICATION\n");
1575                         return -EINVAL;
1576                 }
1577
1578                 tmp = radeon_get_ib_value(p, idx + 1);
1579                 pred_op = (tmp >> 16) & 0x7;
1580
1581                 /* for the clear predicate operation */
1582                 if (pred_op == 0)
1583                         return 0;
1584
1585                 if (pred_op > 2) {
1586                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1587                         return -EINVAL;
1588                 }
1589
1590                 r = r600_cs_packet_next_reloc(p, &reloc);
1591                 if (r) {
1592                         DRM_ERROR("bad SET PREDICATION\n");
1593                         return -EINVAL;
1594                 }
1595
1596                 offset = reloc->lobj.gpu_offset +
1597                          (idx_value & 0xfffffff0) +
1598                          ((u64)(tmp & 0xff) << 32);
1599
1600                 ib[idx + 0] = offset;
1601                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1602         }
1603         break;
1604
1605         case PACKET3_START_3D_CMDBUF:
1606                 if (p->family >= CHIP_RV770 || pkt->count) {
1607                         DRM_ERROR("bad START_3D\n");
1608                         return -EINVAL;
1609                 }
1610                 break;
1611         case PACKET3_CONTEXT_CONTROL:
1612                 if (pkt->count != 1) {
1613                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1614                         return -EINVAL;
1615                 }
1616                 break;
1617         case PACKET3_INDEX_TYPE:
1618         case PACKET3_NUM_INSTANCES:
1619                 if (pkt->count) {
1620                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1621                         return -EINVAL;
1622                 }
1623                 break;
1624         case PACKET3_DRAW_INDEX:
1625         {
1626                 uint64_t offset;
1627                 if (pkt->count != 3) {
1628                         DRM_ERROR("bad DRAW_INDEX\n");
1629                         return -EINVAL;
1630                 }
1631                 r = r600_cs_packet_next_reloc(p, &reloc);
1632                 if (r) {
1633                         DRM_ERROR("bad DRAW_INDEX\n");
1634                         return -EINVAL;
1635                 }
1636
1637                 offset = reloc->lobj.gpu_offset +
1638                          idx_value +
1639                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1640
1641                 ib[idx+0] = offset;
1642                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1643
1644                 r = r600_cs_track_check(p);
1645                 if (r) {
1646                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1647                         return r;
1648                 }
1649                 break;
1650         }
1651         case PACKET3_DRAW_INDEX_AUTO:
1652                 if (pkt->count != 1) {
1653                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1654                         return -EINVAL;
1655                 }
1656                 r = r600_cs_track_check(p);
1657                 if (r) {
1658                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1659                         return r;
1660                 }
1661                 break;
1662         case PACKET3_DRAW_INDEX_IMMD_BE:
1663         case PACKET3_DRAW_INDEX_IMMD:
1664                 if (pkt->count < 2) {
1665                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1666                         return -EINVAL;
1667                 }
1668                 r = r600_cs_track_check(p);
1669                 if (r) {
1670                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1671                         return r;
1672                 }
1673                 break;
1674         case PACKET3_WAIT_REG_MEM:
1675                 if (pkt->count != 5) {
1676                         DRM_ERROR("bad WAIT_REG_MEM\n");
1677                         return -EINVAL;
1678                 }
1679                 /* bit 4 is reg (0) or mem (1) */
1680                 if (idx_value & 0x10) {
1681                         uint64_t offset;
1682
1683                         r = r600_cs_packet_next_reloc(p, &reloc);
1684                         if (r) {
1685                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1686                                 return -EINVAL;
1687                         }
1688
1689                         offset = reloc->lobj.gpu_offset +
1690                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1691                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1692
1693                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1694                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1695                 }
1696                 break;
1697         case PACKET3_SURFACE_SYNC:
1698                 if (pkt->count != 3) {
1699                         DRM_ERROR("bad SURFACE_SYNC\n");
1700                         return -EINVAL;
1701                 }
1702                 /* 0xffffffff/0x0 is flush all cache flag */
1703                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1704                     radeon_get_ib_value(p, idx + 2) != 0) {
1705                         r = r600_cs_packet_next_reloc(p, &reloc);
1706                         if (r) {
1707                                 DRM_ERROR("bad SURFACE_SYNC\n");
1708                                 return -EINVAL;
1709                         }
1710                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1711                 }
1712                 break;
1713         case PACKET3_EVENT_WRITE:
1714                 if (pkt->count != 2 && pkt->count != 0) {
1715                         DRM_ERROR("bad EVENT_WRITE\n");
1716                         return -EINVAL;
1717                 }
1718                 if (pkt->count) {
1719                         uint64_t offset;
1720
1721                         r = r600_cs_packet_next_reloc(p, &reloc);
1722                         if (r) {
1723                                 DRM_ERROR("bad EVENT_WRITE\n");
1724                                 return -EINVAL;
1725                         }
1726                         offset = reloc->lobj.gpu_offset +
1727                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1728                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1729
1730                         ib[idx+1] = offset & 0xfffffff8;
1731                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1732                 }
1733                 break;
1734         case PACKET3_EVENT_WRITE_EOP:
1735         {
1736                 uint64_t offset;
1737
1738                 if (pkt->count != 4) {
1739                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
1740                         return -EINVAL;
1741                 }
1742                 r = r600_cs_packet_next_reloc(p, &reloc);
1743                 if (r) {
1744                         DRM_ERROR("bad EVENT_WRITE\n");
1745                         return -EINVAL;
1746                 }
1747
1748                 offset = reloc->lobj.gpu_offset +
1749                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1750                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1751
1752                 ib[idx+1] = offset & 0xfffffffc;
1753                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1754                 break;
1755         }
1756         case PACKET3_SET_CONFIG_REG:
1757                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1758                 end_reg = 4 * pkt->count + start_reg - 4;
1759                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1760                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1761                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1762                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1763                         return -EINVAL;
1764                 }
1765                 for (i = 0; i < pkt->count; i++) {
1766                         reg = start_reg + (4 * i);
1767                         r = r600_cs_check_reg(p, reg, idx+1+i);
1768                         if (r)
1769                                 return r;
1770                 }
1771                 break;
1772         case PACKET3_SET_CONTEXT_REG:
1773                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1774                 end_reg = 4 * pkt->count + start_reg - 4;
1775                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1776                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1777                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1778                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1779                         return -EINVAL;
1780                 }
1781                 for (i = 0; i < pkt->count; i++) {
1782                         reg = start_reg + (4 * i);
1783                         r = r600_cs_check_reg(p, reg, idx+1+i);
1784                         if (r)
1785                                 return r;
1786                 }
1787                 break;
1788         case PACKET3_SET_RESOURCE:
1789                 if (pkt->count % 7) {
1790                         DRM_ERROR("bad SET_RESOURCE\n");
1791                         return -EINVAL;
1792                 }
1793                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1794                 end_reg = 4 * pkt->count + start_reg - 4;
1795                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1796                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
1797                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
1798                         DRM_ERROR("bad SET_RESOURCE\n");
1799                         return -EINVAL;
1800                 }
1801                 for (i = 0; i < (pkt->count / 7); i++) {
1802                         struct radeon_bo *texture, *mipmap;
1803                         u32 size, offset, base_offset, mip_offset;
1804
1805                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1806                         case SQ_TEX_VTX_VALID_TEXTURE:
1807                                 /* tex base */
1808                                 r = r600_cs_packet_next_reloc(p, &reloc);
1809                                 if (r) {
1810                                         DRM_ERROR("bad SET_RESOURCE\n");
1811                                         return -EINVAL;
1812                                 }
1813                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1814                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1815                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1816                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1817                                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1818                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1819                                 }
1820                                 texture = reloc->robj;
1821                                 /* tex mip base */
1822                                 r = r600_cs_packet_next_reloc(p, &reloc);
1823                                 if (r) {
1824                                         DRM_ERROR("bad SET_RESOURCE\n");
1825                                         return -EINVAL;
1826                                 }
1827                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1828                                 mipmap = reloc->robj;
1829                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
1830                                                                 texture, mipmap,
1831                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1832                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1833                                                                 reloc->lobj.tiling_flags);
1834                                 if (r)
1835                                         return r;
1836                                 ib[idx+1+(i*7)+2] += base_offset;
1837                                 ib[idx+1+(i*7)+3] += mip_offset;
1838                                 break;
1839                         case SQ_TEX_VTX_VALID_BUFFER:
1840                         {
1841                                 uint64_t offset64;
1842                                 /* vtx base */
1843                                 r = r600_cs_packet_next_reloc(p, &reloc);
1844                                 if (r) {
1845                                         DRM_ERROR("bad SET_RESOURCE\n");
1846                                         return -EINVAL;
1847                                 }
1848                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1849                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1850                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1851                                         /* force size to size of the buffer */
1852                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1853                                                  size + offset, radeon_bo_size(reloc->robj));
1854                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
1855                                 }
1856
1857                                 offset64 = reloc->lobj.gpu_offset + offset;
1858                                 ib[idx+1+(i*8)+0] = offset64;
1859                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
1860                                                     (upper_32_bits(offset64) & 0xff);
1861                                 break;
1862                         }
1863                         case SQ_TEX_VTX_INVALID_TEXTURE:
1864                         case SQ_TEX_VTX_INVALID_BUFFER:
1865                         default:
1866                                 DRM_ERROR("bad SET_RESOURCE\n");
1867                                 return -EINVAL;
1868                         }
1869                 }
1870                 break;
1871         case PACKET3_SET_ALU_CONST:
1872                 if (track->sq_config & DX9_CONSTS) {
1873                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1874                         end_reg = 4 * pkt->count + start_reg - 4;
1875                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1876                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1877                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1878                                 DRM_ERROR("bad SET_ALU_CONST\n");
1879                                 return -EINVAL;
1880                         }
1881                 }
1882                 break;
1883         case PACKET3_SET_BOOL_CONST:
1884                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1885                 end_reg = 4 * pkt->count + start_reg - 4;
1886                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1887                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1888                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1889                         DRM_ERROR("bad SET_BOOL_CONST\n");
1890                         return -EINVAL;
1891                 }
1892                 break;
1893         case PACKET3_SET_LOOP_CONST:
1894                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1895                 end_reg = 4 * pkt->count + start_reg - 4;
1896                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1897                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1898                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1899                         DRM_ERROR("bad SET_LOOP_CONST\n");
1900                         return -EINVAL;
1901                 }
1902                 break;
1903         case PACKET3_SET_CTL_CONST:
1904                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1905                 end_reg = 4 * pkt->count + start_reg - 4;
1906                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1907                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1908                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1909                         DRM_ERROR("bad SET_CTL_CONST\n");
1910                         return -EINVAL;
1911                 }
1912                 break;
1913         case PACKET3_SET_SAMPLER:
1914                 if (pkt->count % 3) {
1915                         DRM_ERROR("bad SET_SAMPLER\n");
1916                         return -EINVAL;
1917                 }
1918                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1919                 end_reg = 4 * pkt->count + start_reg - 4;
1920                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1921                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
1922                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
1923                         DRM_ERROR("bad SET_SAMPLER\n");
1924                         return -EINVAL;
1925                 }
1926                 break;
1927         case PACKET3_SURFACE_BASE_UPDATE:
1928                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1929                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1930                         return -EINVAL;
1931                 }
1932                 if (pkt->count) {
1933                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1934                         return -EINVAL;
1935                 }
1936                 break;
1937         case PACKET3_STRMOUT_BUFFER_UPDATE:
1938                 if (pkt->count != 4) {
1939                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
1940                         return -EINVAL;
1941                 }
1942                 /* Updating memory at DST_ADDRESS. */
1943                 if (idx_value & 0x1) {
1944                         u64 offset;
1945                         r = r600_cs_packet_next_reloc(p, &reloc);
1946                         if (r) {
1947                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
1948                                 return -EINVAL;
1949                         }
1950                         offset = radeon_get_ib_value(p, idx+1);
1951                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
1952                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
1953                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
1954                                           offset + 4, radeon_bo_size(reloc->robj));
1955                                 return -EINVAL;
1956                         }
1957                         offset += reloc->lobj.gpu_offset;
1958                         ib[idx+1] = offset;
1959                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1960                 }
1961                 /* Reading data from SRC_ADDRESS. */
1962                 if (((idx_value >> 1) & 0x3) == 2) {
1963                         u64 offset;
1964                         r = r600_cs_packet_next_reloc(p, &reloc);
1965                         if (r) {
1966                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
1967                                 return -EINVAL;
1968                         }
1969                         offset = radeon_get_ib_value(p, idx+3);
1970                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
1971                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
1972                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
1973                                           offset + 4, radeon_bo_size(reloc->robj));
1974                                 return -EINVAL;
1975                         }
1976                         offset += reloc->lobj.gpu_offset;
1977                         ib[idx+3] = offset;
1978                         ib[idx+4] = upper_32_bits(offset) & 0xff;
1979                 }
1980                 break;
1981         case PACKET3_COPY_DW:
1982                 if (pkt->count != 4) {
1983                         DRM_ERROR("bad COPY_DW (invalid count)\n");
1984                         return -EINVAL;
1985                 }
1986                 if (idx_value & 0x1) {
1987                         u64 offset;
1988                         /* SRC is memory. */
1989                         r = r600_cs_packet_next_reloc(p, &reloc);
1990                         if (r) {
1991                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
1992                                 return -EINVAL;
1993                         }
1994                         offset = radeon_get_ib_value(p, idx+1);
1995                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
1996                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
1997                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
1998                                           offset + 4, radeon_bo_size(reloc->robj));
1999                                 return -EINVAL;
2000                         }
2001                         offset += reloc->lobj.gpu_offset;
2002                         ib[idx+1] = offset;
2003                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2004                 } else {
2005                         /* SRC is a reg. */
2006                         reg = radeon_get_ib_value(p, idx+1) << 2;
2007                         if (!r600_is_safe_reg(p, reg, idx+1))
2008                                 return -EINVAL;
2009                 }
2010                 if (idx_value & 0x2) {
2011                         u64 offset;
2012                         /* DST is memory. */
2013                         r = r600_cs_packet_next_reloc(p, &reloc);
2014                         if (r) {
2015                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2016                                 return -EINVAL;
2017                         }
2018                         offset = radeon_get_ib_value(p, idx+3);
2019                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2020                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2021                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2022                                           offset + 4, radeon_bo_size(reloc->robj));
2023                                 return -EINVAL;
2024                         }
2025                         offset += reloc->lobj.gpu_offset;
2026                         ib[idx+3] = offset;
2027                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2028                 } else {
2029                         /* DST is a reg. */
2030                         reg = radeon_get_ib_value(p, idx+3) << 2;
2031                         if (!r600_is_safe_reg(p, reg, idx+3))
2032                                 return -EINVAL;
2033                 }
2034                 break;
2035         case PACKET3_NOP:
2036                 break;
2037         default:
2038                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2039                 return -EINVAL;
2040         }
2041         return 0;
2042 }
2043
2044 int r600_cs_parse(struct radeon_cs_parser *p)
2045 {
2046         struct radeon_cs_packet pkt;
2047         struct r600_cs_track *track;
2048         int r;
2049
2050         if (p->track == NULL) {
2051                 /* initialize tracker, we are in kms */
2052                 track = kzalloc(sizeof(*track), GFP_KERNEL);
2053                 if (track == NULL)
2054                         return -ENOMEM;
2055                 r600_cs_track_init(track);
2056                 if (p->rdev->family < CHIP_RV770) {
2057                         track->npipes = p->rdev->config.r600.tiling_npipes;
2058                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
2059                         track->group_size = p->rdev->config.r600.tiling_group_size;
2060                 } else if (p->rdev->family <= CHIP_RV740) {
2061                         track->npipes = p->rdev->config.rv770.tiling_npipes;
2062                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2063                         track->group_size = p->rdev->config.rv770.tiling_group_size;
2064                 }
2065                 p->track = track;
2066         }
2067         do {
2068                 r = r600_cs_packet_parse(p, &pkt, p->idx);
2069                 if (r) {
2070                         kfree(p->track);
2071                         p->track = NULL;
2072                         return r;
2073                 }
2074                 p->idx += pkt.count + 2;
2075                 switch (pkt.type) {
2076                 case PACKET_TYPE0:
2077                         r = r600_cs_parse_packet0(p, &pkt);
2078                         break;
2079                 case PACKET_TYPE2:
2080                         break;
2081                 case PACKET_TYPE3:
2082                         r = r600_packet3_check(p, &pkt);
2083                         break;
2084                 default:
2085                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2086                         kfree(p->track);
2087                         p->track = NULL;
2088                         return -EINVAL;
2089                 }
2090                 if (r) {
2091                         kfree(p->track);
2092                         p->track = NULL;
2093                         return r;
2094                 }
2095         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2096 #if 0
2097         for (r = 0; r < p->ib->length_dw; r++) {
2098                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
2099                 mdelay(1);
2100         }
2101 #endif
2102         kfree(p->track);
2103         p->track = NULL;
2104         return 0;
2105 }
2106
2107 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2108 {
2109         if (p->chunk_relocs_idx == -1) {
2110                 return 0;
2111         }
2112         p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2113         if (p->relocs == NULL) {
2114                 return -ENOMEM;
2115         }
2116         return 0;
2117 }
2118
2119 /**
2120  * cs_parser_fini() - clean parser states
2121  * @parser:     parser structure holding parsing context.
2122  * @error:      error number
2123  *
2124  * If error is set than unvalidate buffer, otherwise just free memory
2125  * used by parsing context.
2126  **/
2127 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2128 {
2129         unsigned i;
2130
2131         kfree(parser->relocs);
2132         for (i = 0; i < parser->nchunks; i++) {
2133                 kfree(parser->chunks[i].kdata);
2134                 kfree(parser->chunks[i].kpage[0]);
2135                 kfree(parser->chunks[i].kpage[1]);
2136         }
2137         kfree(parser->chunks);
2138         kfree(parser->chunks_array);
2139 }
2140
2141 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2142                         unsigned family, u32 *ib, int *l)
2143 {
2144         struct radeon_cs_parser parser;
2145         struct radeon_cs_chunk *ib_chunk;
2146         struct radeon_ib fake_ib;
2147         struct r600_cs_track *track;
2148         int r;
2149
2150         /* initialize tracker */
2151         track = kzalloc(sizeof(*track), GFP_KERNEL);
2152         if (track == NULL)
2153                 return -ENOMEM;
2154         r600_cs_track_init(track);
2155         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2156         /* initialize parser */
2157         memset(&parser, 0, sizeof(struct radeon_cs_parser));
2158         parser.filp = filp;
2159         parser.dev = &dev->pdev->dev;
2160         parser.rdev = NULL;
2161         parser.family = family;
2162         parser.ib = &fake_ib;
2163         parser.track = track;
2164         fake_ib.ptr = ib;
2165         r = radeon_cs_parser_init(&parser, data);
2166         if (r) {
2167                 DRM_ERROR("Failed to initialize parser !\n");
2168                 r600_cs_parser_fini(&parser, r);
2169                 return r;
2170         }
2171         r = r600_cs_parser_relocs_legacy(&parser);
2172         if (r) {
2173                 DRM_ERROR("Failed to parse relocation !\n");
2174                 r600_cs_parser_fini(&parser, r);
2175                 return r;
2176         }
2177         /* Copy the packet into the IB, the parser will read from the
2178          * input memory (cached) and write to the IB (which can be
2179          * uncached). */
2180         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2181         parser.ib->length_dw = ib_chunk->length_dw;
2182         *l = parser.ib->length_dw;
2183         r = r600_cs_parse(&parser);
2184         if (r) {
2185                 DRM_ERROR("Invalid command stream !\n");
2186                 r600_cs_parser_fini(&parser, r);
2187                 return r;
2188         }
2189         r = radeon_cs_finish_pages(&parser);
2190         if (r) {
2191                 DRM_ERROR("Invalid command stream !\n");
2192                 r600_cs_parser_fini(&parser, r);
2193                 return r;
2194         }
2195         r600_cs_parser_fini(&parser, r);
2196         return r;
2197 }
2198
2199 void r600_cs_legacy_init(void)
2200 {
2201         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2202 }