2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include "radeon_drm.h"
29 #include "radeon_asic.h"
35 enum r600_hdmi_color_format {
42 * IEC60958 status bits
44 enum r600_hdmi_iec_status_bits {
45 AUDIO_STATUS_DIG_ENABLE = 0x01,
46 AUDIO_STATUS_V = 0x02,
47 AUDIO_STATUS_VCFG = 0x04,
48 AUDIO_STATUS_EMPHASIS = 0x08,
49 AUDIO_STATUS_COPYRIGHT = 0x10,
50 AUDIO_STATUS_NONAUDIO = 0x20,
51 AUDIO_STATUS_PROFESSIONAL = 0x40,
52 AUDIO_STATUS_LEVEL = 0x80
68 /* 32kHz 44.1kHz 48kHz */
69 /* Clock N CTS N CTS N CTS */
70 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
71 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
72 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
73 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
74 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
75 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
76 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
77 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
78 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
79 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
80 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
84 * calculate CTS value if it's not found in the table
86 static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
89 *CTS = clock * N / (128 * freq) * 1000;
90 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
95 * update the N and CTS parameters for a given pixel clock rate
97 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
99 struct drm_device *dev = encoder->dev;
100 struct radeon_device *rdev = dev->dev_private;
101 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
106 for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
108 CTS = r600_hdmi_ACR[i].CTS_32kHz;
109 N = r600_hdmi_ACR[i].N_32kHz;
110 r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
111 WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
112 WREG32(offset+R600_HDMI_32kHz_N, N);
114 CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
115 N = r600_hdmi_ACR[i].N_44_1kHz;
116 r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
117 WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
118 WREG32(offset+R600_HDMI_44_1kHz_N, N);
120 CTS = r600_hdmi_ACR[i].CTS_48kHz;
121 N = r600_hdmi_ACR[i].N_48kHz;
122 r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
123 WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
124 WREG32(offset+R600_HDMI_48kHz_N, N);
128 * calculate the crc for a given info frame
130 static void r600_hdmi_infoframe_checksum(uint8_t packetType,
131 uint8_t versionNumber,
136 frame[0] = packetType + versionNumber + length;
137 for (i = 1; i <= length; i++)
138 frame[0] += frame[i];
139 frame[0] = 0x100 - frame[0];
143 * build a HDMI Video Info Frame
145 static void r600_hdmi_videoinfoframe(
146 struct drm_encoder *encoder,
147 enum r600_hdmi_color_format color_format,
148 int active_information_present,
149 uint8_t active_format_aspect_ratio,
150 uint8_t scan_information,
152 uint8_t ex_colorimetry,
153 uint8_t quantization,
155 uint8_t picture_aspect_ratio,
156 uint8_t video_format_identification,
157 uint8_t pixel_repetition,
158 uint8_t non_uniform_picture_scaling,
159 uint8_t bar_info_data_valid,
166 struct drm_device *dev = encoder->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
174 (scan_information & 0x3) |
175 ((bar_info_data_valid & 0x3) << 2) |
176 ((active_information_present & 0x1) << 4) |
177 ((color_format & 0x3) << 5);
179 (active_format_aspect_ratio & 0xF) |
180 ((picture_aspect_ratio & 0x3) << 4) |
181 ((colorimetry & 0x3) << 6);
183 (non_uniform_picture_scaling & 0x3) |
184 ((quantization & 0x3) << 2) |
185 ((ex_colorimetry & 0x7) << 4) |
187 frame[0x4] = (video_format_identification & 0x7F);
188 frame[0x5] = (pixel_repetition & 0xF);
189 frame[0x6] = (top_bar & 0xFF);
190 frame[0x7] = (top_bar >> 8);
191 frame[0x8] = (bottom_bar & 0xFF);
192 frame[0x9] = (bottom_bar >> 8);
193 frame[0xA] = (left_bar & 0xFF);
194 frame[0xB] = (left_bar >> 8);
195 frame[0xC] = (right_bar & 0xFF);
196 frame[0xD] = (right_bar >> 8);
198 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
199 /* Our header values (type, version, length) should be alright, Intel
200 * is using the same. Checksum function also seems to be OK, it works
201 * fine for audio infoframe. However calculated value is always lower
202 * by 2 in comparison to fglrx. It breaks displaying anything in case
203 * of TVs that strictly check the checksum. Hack it manually here to
204 * workaround this issue. */
207 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
208 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
209 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
210 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
211 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
212 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
213 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
214 frame[0xC] | (frame[0xD] << 8));
218 * build a Audio Info Frame
220 static void r600_hdmi_audioinfoframe(
221 struct drm_encoder *encoder,
222 uint8_t channel_count,
225 uint8_t sample_frequency,
227 uint8_t channel_allocation,
232 struct drm_device *dev = encoder->dev;
233 struct radeon_device *rdev = dev->dev_private;
234 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
239 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
240 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
242 frame[0x4] = channel_allocation;
243 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
250 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
252 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
253 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
254 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
255 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
259 * test if audio buffer is filled enough to start playing
261 static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
263 struct drm_device *dev = encoder->dev;
264 struct radeon_device *rdev = dev->dev_private;
265 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
267 return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
271 * have buffer status changed since last call?
273 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
275 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
278 if (!radeon_encoder->hdmi_enabled)
281 status = r600_hdmi_is_audio_buffer_filled(encoder);
282 result = radeon_encoder->hdmi_buffer_status != status;
283 radeon_encoder->hdmi_buffer_status = status;
289 * write the audio workaround status to the hardware
291 void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
293 struct drm_device *dev = encoder->dev;
294 struct radeon_device *rdev = dev->dev_private;
295 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
296 uint32_t offset = radeon_encoder->hdmi_offset;
298 if (!radeon_encoder->hdmi_enabled)
301 if (!radeon_encoder->hdmi_audio_workaround ||
302 r600_hdmi_is_audio_buffer_filled(encoder)) {
304 /* disable audio workaround */
305 WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);
308 /* enable audio workaround */
309 WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
315 * update the info frames with the data from the current display mode
317 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
319 struct drm_device *dev = encoder->dev;
320 struct radeon_device *rdev = dev->dev_private;
321 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
323 if (ASIC_IS_DCE5(rdev))
326 if (!to_radeon_encoder(encoder)->hdmi_enabled)
329 r600_audio_set_clock(encoder, mode->clock);
331 WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
332 WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
333 WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);
335 r600_hdmi_update_ACR(encoder, mode->clock);
337 WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);
339 WREG32(offset+R600_HDMI_VERSION, 0x202);
341 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
342 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
344 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
345 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
346 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
347 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
348 WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);
350 r600_hdmi_audio_workaround(encoder);
352 /* audio packets per line, does anyone know how to calc this ? */
353 WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
357 * update settings with current parameters from audio engine
359 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
361 struct drm_device *dev = encoder->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
365 int channels = r600_audio_channels(rdev);
366 int rate = r600_audio_rate(rdev);
367 int bps = r600_audio_bits_per_sample(rdev);
368 uint8_t status_bits = r600_audio_status_bits(rdev);
369 uint8_t category_code = r600_audio_category_code(rdev);
373 if (!to_radeon_encoder(encoder)->hdmi_enabled)
376 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
377 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
378 channels, rate, bps);
379 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
380 (int)status_bits, (int)category_code);
383 if (status_bits & AUDIO_STATUS_PROFESSIONAL)
385 if (status_bits & AUDIO_STATUS_NONAUDIO)
387 if (status_bits & AUDIO_STATUS_COPYRIGHT)
389 if (status_bits & AUDIO_STATUS_EMPHASIS)
392 iec |= category_code << 8;
395 case 32000: iec |= 0x3 << 24; break;
396 case 44100: iec |= 0x0 << 24; break;
397 case 88200: iec |= 0x8 << 24; break;
398 case 176400: iec |= 0xc << 24; break;
399 case 48000: iec |= 0x2 << 24; break;
400 case 96000: iec |= 0xa << 24; break;
401 case 192000: iec |= 0xe << 24; break;
404 WREG32(offset+R600_HDMI_IEC60958_1, iec);
408 case 16: iec |= 0x2; break;
409 case 20: iec |= 0x3; break;
410 case 24: iec |= 0xb; break;
412 if (status_bits & AUDIO_STATUS_V)
415 WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);
417 /* 0x021 or 0x031 sets the audio frame length */
418 WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
419 r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
421 r600_hdmi_audio_workaround(encoder);
424 static void r600_hdmi_assign_block(struct drm_encoder *encoder)
426 struct drm_device *dev = encoder->dev;
427 struct radeon_device *rdev = dev->dev_private;
428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
429 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
432 EVERGREEN_CRTC0_REGISTER_OFFSET,
433 EVERGREEN_CRTC1_REGISTER_OFFSET,
434 EVERGREEN_CRTC2_REGISTER_OFFSET,
435 EVERGREEN_CRTC3_REGISTER_OFFSET,
436 EVERGREEN_CRTC4_REGISTER_OFFSET,
437 EVERGREEN_CRTC5_REGISTER_OFFSET,
441 dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
445 if (ASIC_IS_DCE5(rdev)) {
447 } else if (ASIC_IS_DCE4(rdev)) {
448 if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) {
449 dev_err(rdev->dev, "Enabling HDMI on unknown dig\n");
452 radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BASE +
453 eg_offsets[dig->dig_encoder];
454 } else if (ASIC_IS_DCE3(rdev)) {
455 radeon_encoder->hdmi_offset = dig->dig_encoder ?
456 R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
457 } else if (rdev->family >= CHIP_R600) {
458 /* 2 routable blocks, but using dig_encoder should be fine */
459 radeon_encoder->hdmi_offset = dig->dig_encoder ?
460 R600_HDMI_BLOCK2 : R600_HDMI_BLOCK1;
461 } else if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
462 rdev->family == CHIP_RS740) {
463 /* Only 1 routable block */
464 radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
466 radeon_encoder->hdmi_enabled = true;
470 * enable the HDMI engine
472 void r600_hdmi_enable(struct drm_encoder *encoder)
474 struct drm_device *dev = encoder->dev;
475 struct radeon_device *rdev = dev->dev_private;
476 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
479 if (ASIC_IS_DCE5(rdev))
482 if (!radeon_encoder->hdmi_enabled) {
483 r600_hdmi_assign_block(encoder);
484 if (!radeon_encoder->hdmi_enabled) {
485 dev_warn(rdev->dev, "Could not find HDMI block for "
486 "0x%x encoder\n", radeon_encoder->encoder_id);
491 offset = radeon_encoder->hdmi_offset;
492 if (ASIC_IS_DCE5(rdev)) {
494 } else if (ASIC_IS_DCE4(rdev)) {
495 WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0x1, ~0x1);
496 } else if (ASIC_IS_DCE32(rdev)) {
497 WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0x1, ~0x1);
498 } else if (ASIC_IS_DCE3(rdev)) {
500 } else if (rdev->family >= CHIP_R600) {
501 switch (radeon_encoder->encoder_id) {
502 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
503 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
504 ~AVIVO_TMDSA_CNTL_HDMI_EN);
505 WREG32(offset + R600_HDMI_ENABLE, 0x101);
507 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
508 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
509 ~AVIVO_LVTMA_CNTL_HDMI_EN);
510 WREG32(offset + R600_HDMI_ENABLE, 0x105);
513 dev_err(rdev->dev, "Unknown HDMI output type\n");
518 if (rdev->irq.installed) {
519 /* if irq is available use it */
520 rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
521 radeon_irq_set(rdev);
524 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
525 radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
529 * disable the HDMI engine
531 void r600_hdmi_disable(struct drm_encoder *encoder)
533 struct drm_device *dev = encoder->dev;
534 struct radeon_device *rdev = dev->dev_private;
535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
538 if (ASIC_IS_DCE5(rdev))
541 offset = radeon_encoder->hdmi_offset;
542 if (!radeon_encoder->hdmi_enabled) {
543 dev_err(rdev->dev, "Disabling not enabled HDMI\n");
547 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
548 offset, radeon_encoder->encoder_id);
551 rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false;
552 radeon_irq_set(rdev);
555 if (ASIC_IS_DCE5(rdev)) {
557 } else if (ASIC_IS_DCE4(rdev)) {
558 WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0, ~0x1);
559 } else if (ASIC_IS_DCE32(rdev)) {
560 WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0, ~0x1);
561 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
562 switch (radeon_encoder->encoder_id) {
563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
564 WREG32_P(AVIVO_TMDSA_CNTL, 0,
565 ~AVIVO_TMDSA_CNTL_HDMI_EN);
566 WREG32(offset + R600_HDMI_ENABLE, 0);
568 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
569 WREG32_P(AVIVO_LVTMA_CNTL, 0,
570 ~AVIVO_LVTMA_CNTL_HDMI_EN);
571 WREG32(offset + R600_HDMI_ENABLE, 0);
574 dev_err(rdev->dev, "Unknown HDMI output type\n");
579 radeon_encoder->hdmi_enabled = false;
580 radeon_encoder->hdmi_offset = 0;