2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
26 #include <linux/hdmi.h>
28 #include <drm/radeon_drm.h>
30 #include "radeon_asic.h"
37 enum r600_hdmi_color_format {
44 * IEC60958 status bits
46 enum r600_hdmi_iec_status_bits {
47 AUDIO_STATUS_DIG_ENABLE = 0x01,
48 AUDIO_STATUS_V = 0x02,
49 AUDIO_STATUS_VCFG = 0x04,
50 AUDIO_STATUS_EMPHASIS = 0x08,
51 AUDIO_STATUS_COPYRIGHT = 0x10,
52 AUDIO_STATUS_NONAUDIO = 0x20,
53 AUDIO_STATUS_PROFESSIONAL = 0x40,
54 AUDIO_STATUS_LEVEL = 0x80
57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
58 /* 32kHz 44.1kHz 48kHz */
59 /* Clock N CTS N CTS N CTS */
60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
74 * calculate CTS value if it's not found in the table
76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
79 *CTS = clock * N / (128 * freq) * 1000;
80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
84 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
86 struct radeon_hdmi_acr res;
89 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
90 r600_hdmi_predefined_acr[i].clock != 0; i++)
92 res = r600_hdmi_predefined_acr[i];
94 /* In case some CTS are missing */
95 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
96 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
97 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
103 * update the N and CTS parameters for a given pixel clock rate
105 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
107 struct drm_device *dev = encoder->dev;
108 struct radeon_device *rdev = dev->dev_private;
109 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
112 uint32_t offset = dig->afmt->offset;
114 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
115 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
117 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
118 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
120 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
121 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
125 * build a HDMI Video Info Frame
127 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
128 void *buffer, size_t size)
130 struct drm_device *dev = encoder->dev;
131 struct radeon_device *rdev = dev->dev_private;
132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
134 uint32_t offset = dig->afmt->offset;
135 uint8_t *frame = buffer + 3;
136 uint8_t *header = buffer;
138 WREG32(HDMI0_AVI_INFO0 + offset,
139 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
140 WREG32(HDMI0_AVI_INFO1 + offset,
141 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
142 WREG32(HDMI0_AVI_INFO2 + offset,
143 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
144 WREG32(HDMI0_AVI_INFO3 + offset,
145 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
149 * build a Audio Info Frame
151 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
152 const void *buffer, size_t size)
154 struct drm_device *dev = encoder->dev;
155 struct radeon_device *rdev = dev->dev_private;
156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
157 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
158 uint32_t offset = dig->afmt->offset;
159 const u8 *frame = buffer + 3;
161 WREG32(HDMI0_AUDIO_INFO0 + offset,
162 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
163 WREG32(HDMI0_AUDIO_INFO1 + offset,
164 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
168 * test if audio buffer is filled enough to start playing
170 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
172 struct drm_device *dev = encoder->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
175 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
176 uint32_t offset = dig->afmt->offset;
178 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
182 * have buffer status changed since last call?
184 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
186 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
187 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
190 if (!dig->afmt || !dig->afmt->enabled)
193 status = r600_hdmi_is_audio_buffer_filled(encoder);
194 result = dig->afmt->last_buffer_filled_status != status;
195 dig->afmt->last_buffer_filled_status = status;
201 * write the audio workaround status to the hardware
203 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
205 struct drm_device *dev = encoder->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
208 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
209 uint32_t offset = dig->afmt->offset;
210 bool hdmi_audio_workaround = false; /* FIXME */
213 if (!hdmi_audio_workaround ||
214 r600_hdmi_is_audio_buffer_filled(encoder))
215 value = 0; /* disable workaround */
217 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
218 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
219 value, ~HDMI0_AUDIO_TEST_EN);
222 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
224 struct drm_device *dev = encoder->dev;
225 struct radeon_device *rdev = dev->dev_private;
226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
227 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
228 u32 base_rate = 24000;
229 u32 max_ratio = clock / base_rate;
231 u32 dto_modulo = clock;
235 if (!dig || !dig->afmt)
238 if (max_ratio >= 8) {
239 dto_phase = 192 * 1000;
241 } else if (max_ratio >= 4) {
242 dto_phase = 96 * 1000;
244 } else if (max_ratio >= 2) {
245 dto_phase = 48 * 1000;
248 dto_phase = 24 * 1000;
252 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
253 * doesn't matter which one you use. Just use the first one.
255 /* XXX two dtos; generally use dto0 for hdmi */
256 /* Express [24MHz / target pixel clock] as an exact rational
257 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
258 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
260 if (ASIC_IS_DCE3(rdev)) {
261 /* according to the reg specs, this should DCE3.2 only, but in
262 * practice it seems to cover DCE3.0 as well.
264 if (dig->dig_encoder == 0) {
265 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
266 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
267 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
268 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
269 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
270 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
272 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
273 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
274 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
275 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
276 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
277 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
280 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
281 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
282 AUDIO_DTO_MODULE(clock / 10));
287 * update the info frames with the data from the current display mode
289 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
291 struct drm_device *dev = encoder->dev;
292 struct radeon_device *rdev = dev->dev_private;
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
295 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
296 struct hdmi_avi_infoframe frame;
300 if (!dig || !dig->afmt)
303 /* Silent, r600_hdmi_enable will raise WARN for us */
304 if (!dig->afmt->enabled)
306 offset = dig->afmt->offset;
308 r600_audio_set_dto(encoder, mode->clock);
310 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
311 HDMI0_NULL_SEND); /* send null packets when required */
313 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
315 if (ASIC_IS_DCE32(rdev)) {
316 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
317 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
318 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
319 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
320 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
321 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
323 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
324 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
325 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
326 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
327 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
330 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
331 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
332 HDMI0_ACR_SOURCE); /* select SW CTS value */
334 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
335 HDMI0_NULL_SEND | /* send null packets when required */
336 HDMI0_GC_SEND | /* send general control packets */
337 HDMI0_GC_CONT); /* send general control packets every frame */
339 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
340 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
341 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
342 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
343 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
344 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
346 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
347 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
348 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
350 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
352 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
354 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
358 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
360 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
364 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
365 r600_hdmi_update_ACR(encoder, mode->clock);
367 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
368 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
369 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
370 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
371 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
373 r600_hdmi_audio_workaround(encoder);
377 * update settings with current parameters from audio engine
379 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
381 struct drm_device *dev = encoder->dev;
382 struct radeon_device *rdev = dev->dev_private;
383 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
384 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
385 struct r600_audio audio = r600_audio_status(rdev);
386 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
387 struct hdmi_audio_infoframe frame;
392 if (!dig->afmt || !dig->afmt->enabled)
394 offset = dig->afmt->offset;
396 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
397 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
398 audio.channels, audio.rate, audio.bits_per_sample);
399 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
400 (int)audio.status_bits, (int)audio.category_code);
403 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
405 if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
407 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
409 if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
412 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
414 switch (audio.rate) {
416 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
419 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
422 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
425 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
428 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
431 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
434 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
438 WREG32(HDMI0_60958_0 + offset, iec);
441 switch (audio.bits_per_sample) {
443 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
446 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
449 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
452 if (audio.status_bits & AUDIO_STATUS_V)
454 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
456 err = hdmi_audio_infoframe_init(&frame);
458 DRM_ERROR("failed to setup audio infoframe\n");
462 frame.channels = audio.channels;
464 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
466 DRM_ERROR("failed to pack audio infoframe\n");
470 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
471 r600_hdmi_audio_workaround(encoder);
475 * enable the HDMI engine
477 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
479 struct drm_device *dev = encoder->dev;
480 struct radeon_device *rdev = dev->dev_private;
481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
482 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
483 u32 hdmi = HDMI0_ERROR_ACK;
485 if (!dig || !dig->afmt)
488 /* Silent, r600_hdmi_enable will raise WARN for us */
489 if (enable && dig->afmt->enabled)
491 if (!enable && !dig->afmt->enabled)
494 /* Older chipsets require setting HDMI and routing manually */
495 if (!ASIC_IS_DCE3(rdev)) {
497 hdmi |= HDMI0_ENABLE;
498 switch (radeon_encoder->encoder_id) {
499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
501 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
502 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
504 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
507 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
509 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
510 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
512 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
515 case ENCODER_OBJECT_ID_INTERNAL_DDI:
517 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
518 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
520 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
525 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
528 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
529 radeon_encoder->encoder_id);
532 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
535 if (rdev->irq.installed) {
536 /* if irq is available use it */
537 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
539 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
541 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
544 dig->afmt->enabled = enable;
546 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
547 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);