2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
36 #define R6XX_MAX_SH_GPRS 256
37 #define R6XX_MAX_TEMP_GPRS 16
38 #define R6XX_MAX_SH_THREADS 256
39 #define R6XX_MAX_SH_STACK_ENTRIES 4096
40 #define R6XX_MAX_BACKENDS 8
41 #define R6XX_MAX_BACKENDS_MASK 0xff
42 #define R6XX_MAX_SIMDS 8
43 #define R6XX_MAX_SIMDS_MASK 0xff
44 #define R6XX_MAX_PIPES 8
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define PTE_VALID (1 << 0)
49 #define PTE_SYSTEM (1 << 1)
50 #define PTE_SNOOPED (1 << 2)
51 #define PTE_READABLE (1 << 5)
52 #define PTE_WRITEABLE (1 << 6)
55 #define ARRAY_LINEAR_GENERAL 0x00000000
56 #define ARRAY_LINEAR_ALIGNED 0x00000001
57 #define ARRAY_1D_TILED_THIN1 0x00000002
58 #define ARRAY_2D_TILED_THIN1 0x00000004
61 #define ARB_POP 0x2418
62 #define ENABLE_TC128 (1 << 30)
63 #define ARB_GDEC_RD_CNTL 0x246C
65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
66 #define CC_RB_BACKEND_DISABLE 0x98F4
67 #define BACKEND_DISABLE(x) ((x) << 16)
69 #define CB_COLOR0_BASE 0x28040
70 #define CB_COLOR1_BASE 0x28044
71 #define CB_COLOR2_BASE 0x28048
72 #define CB_COLOR3_BASE 0x2804C
73 #define CB_COLOR4_BASE 0x28050
74 #define CB_COLOR5_BASE 0x28054
75 #define CB_COLOR6_BASE 0x28058
76 #define CB_COLOR7_BASE 0x2805C
77 #define CB_COLOR7_FRAG 0x280FC
79 #define CB_COLOR0_SIZE 0x28060
80 #define CB_COLOR0_VIEW 0x28080
81 #define R_028080_CB_COLOR0_VIEW 0x028080
82 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
83 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
84 #define C_028080_SLICE_START 0xFFFFF800
85 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
86 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
87 #define C_028080_SLICE_MAX 0xFF001FFF
88 #define R_028084_CB_COLOR1_VIEW 0x028084
89 #define R_028088_CB_COLOR2_VIEW 0x028088
90 #define R_02808C_CB_COLOR3_VIEW 0x02808C
91 #define R_028090_CB_COLOR4_VIEW 0x028090
92 #define R_028094_CB_COLOR5_VIEW 0x028094
93 #define R_028098_CB_COLOR6_VIEW 0x028098
94 #define R_02809C_CB_COLOR7_VIEW 0x02809C
95 #define R_028100_CB_COLOR0_MASK 0x028100
96 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
97 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
98 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
99 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
100 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
101 #define C_028100_FMASK_TILE_MAX 0x00000FFF
102 #define R_028104_CB_COLOR1_MASK 0x028104
103 #define R_028108_CB_COLOR2_MASK 0x028108
104 #define R_02810C_CB_COLOR3_MASK 0x02810C
105 #define R_028110_CB_COLOR4_MASK 0x028110
106 #define R_028114_CB_COLOR5_MASK 0x028114
107 #define R_028118_CB_COLOR6_MASK 0x028118
108 #define R_02811C_CB_COLOR7_MASK 0x02811C
109 #define CB_COLOR0_INFO 0x280a0
110 # define CB_FORMAT(x) ((x) << 2)
111 # define CB_ARRAY_MODE(x) ((x) << 8)
112 # define CB_SOURCE_FORMAT(x) ((x) << 27)
113 # define CB_SF_EXPORT_FULL 0
114 # define CB_SF_EXPORT_NORM 1
115 #define CB_COLOR0_TILE 0x280c0
116 #define CB_COLOR0_FRAG 0x280e0
117 #define CB_COLOR0_MASK 0x28100
119 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
120 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
121 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
122 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
123 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
124 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
125 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
126 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
127 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
128 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
129 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
130 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
131 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
132 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
133 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
134 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
135 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
136 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
137 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
138 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
139 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
140 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
141 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
142 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
143 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
144 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
145 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
146 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
147 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
148 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
149 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
150 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
151 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
152 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
153 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
154 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
155 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
156 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
157 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
158 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
159 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
160 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
161 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
162 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
163 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
164 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
165 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
166 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
168 #define CONFIG_MEMSIZE 0x5428
169 #define CONFIG_CNTL 0x5424
170 #define CP_STALLED_STAT1 0x8674
171 #define CP_STALLED_STAT2 0x8678
172 #define CP_BUSY_STAT 0x867C
173 #define CP_STAT 0x8680
174 #define CP_COHER_BASE 0x85F8
175 #define CP_DEBUG 0xC1FC
176 #define R_0086D8_CP_ME_CNTL 0x86D8
177 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
178 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
179 #define CP_ME_RAM_DATA 0xC160
180 #define CP_ME_RAM_RADDR 0xC158
181 #define CP_ME_RAM_WADDR 0xC15C
182 #define CP_MEQ_THRESHOLDS 0x8764
183 #define MEQ_END(x) ((x) << 16)
184 #define ROQ_END(x) ((x) << 24)
185 #define CP_PERFMON_CNTL 0x87FC
186 #define CP_PFP_UCODE_ADDR 0xC150
187 #define CP_PFP_UCODE_DATA 0xC154
188 #define CP_QUEUE_THRESHOLDS 0x8760
189 #define ROQ_IB1_START(x) ((x) << 0)
190 #define ROQ_IB2_START(x) ((x) << 8)
191 #define CP_RB_BASE 0xC100
192 #define CP_RB_CNTL 0xC104
193 #define RB_BUFSZ(x) ((x) << 0)
194 #define RB_BLKSZ(x) ((x) << 8)
195 #define RB_NO_UPDATE (1 << 27)
196 #define RB_RPTR_WR_ENA (1 << 31)
197 #define BUF_SWAP_32BIT (2 << 16)
198 #define CP_RB_RPTR 0x8700
199 #define CP_RB_RPTR_ADDR 0xC10C
200 #define RB_RPTR_SWAP(x) ((x) << 0)
201 #define CP_RB_RPTR_ADDR_HI 0xC110
202 #define CP_RB_RPTR_WR 0xC108
203 #define CP_RB_WPTR 0xC114
204 #define CP_RB_WPTR_ADDR 0xC118
205 #define CP_RB_WPTR_ADDR_HI 0xC11C
206 #define CP_RB_WPTR_DELAY 0x8704
207 #define CP_ROQ_IB1_STAT 0x8784
208 #define CP_ROQ_IB2_STAT 0x8788
209 #define CP_SEM_WAIT_TIMER 0x85BC
211 #define DB_DEBUG 0x9830
212 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
213 #define DB_DEPTH_BASE 0x2800C
214 #define DB_HTILE_DATA_BASE 0x28014
215 #define DB_HTILE_SURFACE 0x28D24
216 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
217 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
218 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE
219 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
220 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
221 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
222 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
223 #define DB_WATERMARKS 0x9838
224 #define DEPTH_FREE(x) ((x) << 0)
225 #define DEPTH_FLUSH(x) ((x) << 5)
226 #define DEPTH_PENDING_FREE(x) ((x) << 15)
227 #define DEPTH_CACHELINE_FREE(x) ((x) << 20)
229 #define DCP_TILING_CONFIG 0x6CA0
230 #define PIPE_TILING(x) ((x) << 1)
231 #define BANK_TILING(x) ((x) << 4)
232 #define GROUP_SIZE(x) ((x) << 6)
233 #define ROW_TILING(x) ((x) << 8)
234 #define BANK_SWAPS(x) ((x) << 11)
235 #define SAMPLE_SPLIT(x) ((x) << 14)
236 #define BACKEND_MAP(x) ((x) << 16)
238 #define GB_TILING_CONFIG 0x98F0
239 #define PIPE_TILING__SHIFT 1
240 #define PIPE_TILING__MASK 0x0000000e
242 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
243 #define INACTIVE_QD_PIPES(x) ((x) << 8)
244 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
245 #define INACTIVE_SIMDS(x) ((x) << 16)
246 #define INACTIVE_SIMDS_MASK 0x00FF0000
248 #define SQ_CONFIG 0x8c00
249 # define VC_ENABLE (1 << 0)
250 # define EXPORT_SRC_C (1 << 1)
251 # define DX9_CONSTS (1 << 2)
252 # define ALU_INST_PREFER_VECTOR (1 << 3)
253 # define DX10_CLAMP (1 << 4)
254 # define CLAUSE_SEQ_PRIO(x) ((x) << 8)
255 # define PS_PRIO(x) ((x) << 24)
256 # define VS_PRIO(x) ((x) << 26)
257 # define GS_PRIO(x) ((x) << 28)
258 # define ES_PRIO(x) ((x) << 30)
259 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04
260 # define NUM_PS_GPRS(x) ((x) << 0)
261 # define NUM_VS_GPRS(x) ((x) << 16)
262 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
263 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08
264 # define NUM_GS_GPRS(x) ((x) << 0)
265 # define NUM_ES_GPRS(x) ((x) << 16)
266 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c
267 # define NUM_PS_THREADS(x) ((x) << 0)
268 # define NUM_VS_THREADS(x) ((x) << 8)
269 # define NUM_GS_THREADS(x) ((x) << 16)
270 # define NUM_ES_THREADS(x) ((x) << 24)
271 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10
272 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
273 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
274 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14
275 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
276 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
277 #define SQ_ESGS_RING_BASE 0x8c40
278 #define SQ_GSVS_RING_BASE 0x8c48
279 #define SQ_ESTMP_RING_BASE 0x8c50
280 #define SQ_GSTMP_RING_BASE 0x8c58
281 #define SQ_VSTMP_RING_BASE 0x8c60
282 #define SQ_PSTMP_RING_BASE 0x8c68
283 #define SQ_FBUF_RING_BASE 0x8c70
284 #define SQ_REDUC_RING_BASE 0x8c78
286 #define GRBM_CNTL 0x8000
287 # define GRBM_READ_TIMEOUT(x) ((x) << 0)
288 #define GRBM_STATUS 0x8010
289 #define CMDFIFO_AVAIL_MASK 0x0000001F
290 #define GUI_ACTIVE (1<<31)
291 #define GRBM_STATUS2 0x8014
292 #define GRBM_SOFT_RESET 0x8020
293 #define SOFT_RESET_CP (1<<0)
295 #define CG_THERMAL_STATUS 0x7F4
296 #define ASIC_T(x) ((x) << 0)
297 #define ASIC_T_MASK 0x1FF
298 #define ASIC_T_SHIFT 0
300 #define HDP_HOST_PATH_CNTL 0x2C00
301 #define HDP_NONSURFACE_BASE 0x2C04
302 #define HDP_NONSURFACE_INFO 0x2C08
303 #define HDP_NONSURFACE_SIZE 0x2C0C
304 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
305 #define HDP_TILING_CONFIG 0x2F3C
306 #define HDP_DEBUG1 0x2F34
308 #define MC_VM_AGP_TOP 0x2184
309 #define MC_VM_AGP_BOT 0x2188
310 #define MC_VM_AGP_BASE 0x218C
311 #define MC_VM_FB_LOCATION 0x2180
312 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
313 #define ENABLE_L1_TLB (1 << 0)
314 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
315 #define ENABLE_L1_STRICT_ORDERING (1 << 2)
316 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0
317 #define SYSTEM_ACCESS_MODE_SHIFT 6
318 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
319 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
320 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
321 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
322 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
323 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
324 #define ENABLE_SEMAPHORE_MODE (1 << 10)
325 #define ENABLE_WAIT_L2_QUERY (1 << 11)
326 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
327 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
328 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
329 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
330 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
331 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
332 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
333 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
334 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
335 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
336 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
337 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
338 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
339 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
340 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
341 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
342 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
343 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
344 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
345 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
346 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
347 #define LOGICAL_PAGE_NUMBER_SHIFT 0
348 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
349 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
351 #define PA_CL_ENHANCE 0x8A14
352 #define CLIP_VTX_REORDER_ENA (1 << 0)
353 #define NUM_CLIP_SEQ(x) ((x) << 1)
354 #define PA_SC_AA_CONFIG 0x28C04
355 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
356 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
357 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
358 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
359 #define S0_X(x) ((x) << 0)
360 #define S0_Y(x) ((x) << 4)
361 #define S1_X(x) ((x) << 8)
362 #define S1_Y(x) ((x) << 12)
363 #define S2_X(x) ((x) << 16)
364 #define S2_Y(x) ((x) << 20)
365 #define S3_X(x) ((x) << 24)
366 #define S3_Y(x) ((x) << 28)
367 #define S4_X(x) ((x) << 0)
368 #define S4_Y(x) ((x) << 4)
369 #define S5_X(x) ((x) << 8)
370 #define S5_Y(x) ((x) << 12)
371 #define S6_X(x) ((x) << 16)
372 #define S6_Y(x) ((x) << 20)
373 #define S7_X(x) ((x) << 24)
374 #define S7_Y(x) ((x) << 28)
375 #define PA_SC_CLIPRECT_RULE 0x2820c
376 #define PA_SC_ENHANCE 0x8BF0
377 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
378 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
379 #define PA_SC_LINE_STIPPLE 0x28A0C
380 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
381 #define PA_SC_MODE_CNTL 0x28A4C
382 #define PA_SC_MULTI_CHIP_CNTL 0x8B20
384 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
385 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
386 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
388 #define PCIE_PORT_INDEX 0x0038
389 #define PCIE_PORT_DATA 0x003C
392 #define NOOFCHAN_SHIFT 12
393 #define NOOFCHAN_MASK 0x00003000
395 #define RAMCFG 0x2408
396 #define NOOFBANK_SHIFT 0
397 #define NOOFBANK_MASK 0x00000001
398 #define NOOFRANK_SHIFT 1
399 #define NOOFRANK_MASK 0x00000002
400 #define NOOFROWS_SHIFT 2
401 #define NOOFROWS_MASK 0x0000001C
402 #define NOOFCOLS_SHIFT 5
403 #define NOOFCOLS_MASK 0x00000060
404 #define CHANSIZE_SHIFT 7
405 #define CHANSIZE_MASK 0x00000080
406 #define BURSTLENGTH_SHIFT 8
407 #define BURSTLENGTH_MASK 0x00000100
408 #define CHANSIZE_OVERRIDE (1 << 10)
410 #define SCRATCH_REG0 0x8500
411 #define SCRATCH_REG1 0x8504
412 #define SCRATCH_REG2 0x8508
413 #define SCRATCH_REG3 0x850C
414 #define SCRATCH_REG4 0x8510
415 #define SCRATCH_REG5 0x8514
416 #define SCRATCH_REG6 0x8518
417 #define SCRATCH_REG7 0x851C
418 #define SCRATCH_UMSK 0x8540
419 #define SCRATCH_ADDR 0x8544
421 #define SPI_CONFIG_CNTL 0x9100
422 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
423 #define DISABLE_INTERP_1 (1 << 5)
424 #define SPI_CONFIG_CNTL_1 0x913C
425 #define VTX_DONE_DELAY(x) ((x) << 0)
426 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
427 #define SPI_INPUT_Z 0x286D8
428 #define SPI_PS_IN_CONTROL_0 0x286CC
429 #define NUM_INTERP(x) ((x)<<0)
430 #define POSITION_ENA (1<<8)
431 #define POSITION_CENTROID (1<<9)
432 #define POSITION_ADDR(x) ((x)<<10)
433 #define PARAM_GEN(x) ((x)<<15)
434 #define PARAM_GEN_ADDR(x) ((x)<<19)
435 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
436 #define PERSP_GRADIENT_ENA (1<<28)
437 #define LINEAR_GRADIENT_ENA (1<<29)
438 #define POSITION_SAMPLE (1<<30)
439 #define BARYC_AT_SAMPLE_ENA (1<<31)
440 #define SPI_PS_IN_CONTROL_1 0x286D0
441 #define GEN_INDEX_PIX (1<<0)
442 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
443 #define FRONT_FACE_ENA (1<<8)
444 #define FRONT_FACE_CHAN(x) ((x)<<9)
445 #define FRONT_FACE_ALL_BITS (1<<11)
446 #define FRONT_FACE_ADDR(x) ((x)<<12)
447 #define FOG_ADDR(x) ((x)<<17)
448 #define FIXED_PT_POSITION_ENA (1<<24)
449 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
451 #define SQ_MS_FIFO_SIZES 0x8CF0
452 #define CACHE_FIFO_SIZE(x) ((x) << 0)
453 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
454 #define DONE_FIFO_HIWATER(x) ((x) << 16)
455 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
456 #define SQ_PGM_START_ES 0x28880
457 #define SQ_PGM_START_FS 0x28894
458 #define SQ_PGM_START_GS 0x2886C
459 #define SQ_PGM_START_PS 0x28840
460 #define SQ_PGM_RESOURCES_PS 0x28850
461 #define SQ_PGM_EXPORTS_PS 0x28854
462 #define SQ_PGM_CF_OFFSET_PS 0x288cc
463 #define SQ_PGM_START_VS 0x28858
464 #define SQ_PGM_RESOURCES_VS 0x28868
465 #define SQ_PGM_CF_OFFSET_VS 0x288d0
467 #define SQ_VTX_CONSTANT_WORD0_0 0x30000
468 #define SQ_VTX_CONSTANT_WORD1_0 0x30004
469 #define SQ_VTX_CONSTANT_WORD2_0 0x30008
470 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
471 # define SQ_VTXC_STRIDE(x) ((x) << 8)
472 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
473 # define SQ_ENDIAN_NONE 0
474 # define SQ_ENDIAN_8IN16 1
475 # define SQ_ENDIAN_8IN32 2
476 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c
477 #define SQ_VTX_CONSTANT_WORD6_0 0x38018
478 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
479 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
480 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
481 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
482 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
483 #define SQ_TEX_VTX_VALID_BUFFER 0x3
486 #define SX_MISC 0x28350
487 #define SX_MEMORY_EXPORT_BASE 0x9010
488 #define SX_DEBUG_1 0x9054
489 #define SMX_EVENT_RELEASE (1 << 0)
490 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
492 #define TA_CNTL_AUX 0x9508
493 #define DISABLE_CUBE_WRAP (1 << 0)
494 #define DISABLE_CUBE_ANISO (1 << 1)
495 #define SYNC_GRADIENT (1 << 24)
496 #define SYNC_WALKER (1 << 25)
497 #define SYNC_ALIGNER (1 << 26)
498 #define BILINEAR_PRECISION_6_BIT (0 << 31)
499 #define BILINEAR_PRECISION_8_BIT (1 << 31)
501 #define TC_CNTL 0x9608
502 #define TC_L2_SIZE(x) ((x)<<5)
503 #define L2_DISABLE_LATE_HIT (1<<9)
505 #define VC_ENHANCE 0x9714
507 #define VGT_CACHE_INVALIDATION 0x88C4
508 #define CACHE_INVALIDATION(x) ((x)<<0)
512 #define VGT_DMA_BASE 0x287E8
513 #define VGT_DMA_BASE_HI 0x287E4
514 #define VGT_ES_PER_GS 0x88CC
515 #define VGT_GS_PER_ES 0x88C8
516 #define VGT_GS_PER_VS 0x88E8
517 #define VGT_GS_VERTEX_REUSE 0x88D4
518 #define VGT_PRIMITIVE_TYPE 0x8958
519 #define VGT_NUM_INSTANCES 0x8974
520 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
521 #define DEALLOC_DIST_MASK 0x0000007F
522 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
523 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
524 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
525 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
526 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
527 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
528 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
529 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
530 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
531 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
532 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
533 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
534 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
535 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
536 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
537 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
538 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
539 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
540 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
541 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
543 #define VGT_STRMOUT_EN 0x28AB0
544 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
545 #define VTX_REUSE_DEPTH_MASK 0x000000FF
546 #define VGT_EVENT_INITIATOR 0x28a90
547 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
548 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
550 #define VM_CONTEXT0_CNTL 0x1410
551 #define ENABLE_CONTEXT (1 << 0)
552 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
553 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
554 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
555 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
556 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
557 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
558 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
559 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
560 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
561 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
562 #define RESPONSE_TYPE_MASK 0x000000F0
563 #define RESPONSE_TYPE_SHIFT 4
564 #define VM_L2_CNTL 0x1400
565 #define ENABLE_L2_CACHE (1 << 0)
566 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
567 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
568 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
569 #define VM_L2_CNTL2 0x1404
570 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
571 #define INVALIDATE_L2_CACHE (1 << 1)
572 #define VM_L2_CNTL3 0x1408
573 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
574 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
575 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
576 #define VM_L2_STATUS 0x140C
577 #define L2_BUSY (1 << 0)
579 #define WAIT_UNTIL 0x8040
580 #define WAIT_2D_IDLE_bit (1 << 14)
581 #define WAIT_3D_IDLE_bit (1 << 15)
582 #define WAIT_2D_IDLECLEAN_bit (1 << 16)
583 #define WAIT_3D_IDLECLEAN_bit (1 << 17)
585 #define IH_RB_CNTL 0x3e00
586 # define IH_RB_ENABLE (1 << 0)
587 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
588 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
589 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
590 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
591 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
592 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
593 #define IH_RB_BASE 0x3e04
594 #define IH_RB_RPTR 0x3e08
595 #define IH_RB_WPTR 0x3e0c
596 # define RB_OVERFLOW (1 << 0)
597 # define WPTR_OFFSET_MASK 0x3fffc
598 #define IH_RB_WPTR_ADDR_HI 0x3e10
599 #define IH_RB_WPTR_ADDR_LO 0x3e14
600 #define IH_CNTL 0x3e18
601 # define ENABLE_INTR (1 << 0)
602 # define IH_MC_SWAP(x) ((x) << 1)
603 # define IH_MC_SWAP_NONE 0
604 # define IH_MC_SWAP_16BIT 1
605 # define IH_MC_SWAP_32BIT 2
606 # define IH_MC_SWAP_64BIT 3
607 # define RPTR_REARM (1 << 4)
608 # define MC_WRREQ_CREDIT(x) ((x) << 15)
609 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
611 #define RLC_CNTL 0x3f00
612 # define RLC_ENABLE (1 << 0)
613 #define RLC_HB_BASE 0x3f10
614 #define RLC_HB_CNTL 0x3f0c
615 #define RLC_HB_RPTR 0x3f20
616 #define RLC_HB_WPTR 0x3f1c
617 #define RLC_HB_WPTR_LSB_ADDR 0x3f14
618 #define RLC_HB_WPTR_MSB_ADDR 0x3f18
619 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
620 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
621 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
622 #define RLC_MC_CNTL 0x3f44
623 #define RLC_UCODE_CNTL 0x3f48
624 #define RLC_UCODE_ADDR 0x3f2c
625 #define RLC_UCODE_DATA 0x3f30
628 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
629 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
631 #define SRBM_SOFT_RESET 0xe60
632 # define SOFT_RESET_RLC (1 << 13)
634 #define CP_INT_CNTL 0xc124
635 # define CNTX_BUSY_INT_ENABLE (1 << 19)
636 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
637 # define SCRATCH_INT_ENABLE (1 << 25)
638 # define TIME_STAMP_INT_ENABLE (1 << 26)
639 # define IB2_INT_ENABLE (1 << 29)
640 # define IB1_INT_ENABLE (1 << 30)
641 # define RB_INT_ENABLE (1 << 31)
642 #define CP_INT_STATUS 0xc128
643 # define SCRATCH_INT_STAT (1 << 25)
644 # define TIME_STAMP_INT_STAT (1 << 26)
645 # define IB2_INT_STAT (1 << 29)
646 # define IB1_INT_STAT (1 << 30)
647 # define RB_INT_STAT (1 << 31)
649 #define GRBM_INT_CNTL 0x8060
650 # define RDERR_INT_ENABLE (1 << 0)
651 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
652 # define GUI_IDLE_INT_ENABLE (1 << 19)
654 #define INTERRUPT_CNTL 0x5468
655 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
656 # define IH_DUMMY_RD_EN (1 << 1)
657 # define IH_REQ_NONSNOOP_EN (1 << 3)
658 # define GEN_IH_INT_EN (1 << 8)
659 #define INTERRUPT_CNTL2 0x546c
661 #define D1MODE_VBLANK_STATUS 0x6534
662 #define D2MODE_VBLANK_STATUS 0x6d34
663 # define DxMODE_VBLANK_OCCURRED (1 << 0)
664 # define DxMODE_VBLANK_ACK (1 << 4)
665 # define DxMODE_VBLANK_STAT (1 << 12)
666 # define DxMODE_VBLANK_INTERRUPT (1 << 16)
667 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
668 #define D1MODE_VLINE_STATUS 0x653c
669 #define D2MODE_VLINE_STATUS 0x6d3c
670 # define DxMODE_VLINE_OCCURRED (1 << 0)
671 # define DxMODE_VLINE_ACK (1 << 4)
672 # define DxMODE_VLINE_STAT (1 << 12)
673 # define DxMODE_VLINE_INTERRUPT (1 << 16)
674 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
675 #define DxMODE_INT_MASK 0x6540
676 # define D1MODE_VBLANK_INT_MASK (1 << 0)
677 # define D1MODE_VLINE_INT_MASK (1 << 4)
678 # define D2MODE_VBLANK_INT_MASK (1 << 8)
679 # define D2MODE_VLINE_INT_MASK (1 << 12)
680 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
681 # define DC_HPD1_INTERRUPT (1 << 18)
682 # define DC_HPD2_INTERRUPT (1 << 19)
683 #define DISP_INTERRUPT_STATUS 0x7edc
684 # define LB_D1_VLINE_INTERRUPT (1 << 2)
685 # define LB_D2_VLINE_INTERRUPT (1 << 3)
686 # define LB_D1_VBLANK_INTERRUPT (1 << 4)
687 # define LB_D2_VBLANK_INTERRUPT (1 << 5)
688 # define DACA_AUTODETECT_INTERRUPT (1 << 16)
689 # define DACB_AUTODETECT_INTERRUPT (1 << 17)
690 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
691 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
692 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
693 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
694 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
695 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
696 # define DC_HPD4_INTERRUPT (1 << 14)
697 # define DC_HPD4_RX_INTERRUPT (1 << 15)
698 # define DC_HPD3_INTERRUPT (1 << 28)
699 # define DC_HPD1_RX_INTERRUPT (1 << 29)
700 # define DC_HPD2_RX_INTERRUPT (1 << 30)
701 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
702 # define DC_HPD3_RX_INTERRUPT (1 << 0)
703 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
704 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
705 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
706 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
707 # define AUX1_SW_DONE_INTERRUPT (1 << 5)
708 # define AUX1_LS_DONE_INTERRUPT (1 << 6)
709 # define AUX2_SW_DONE_INTERRUPT (1 << 7)
710 # define AUX2_LS_DONE_INTERRUPT (1 << 8)
711 # define AUX3_SW_DONE_INTERRUPT (1 << 9)
712 # define AUX3_LS_DONE_INTERRUPT (1 << 10)
713 # define AUX4_SW_DONE_INTERRUPT (1 << 11)
714 # define AUX4_LS_DONE_INTERRUPT (1 << 12)
715 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
716 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
718 # define AUX5_SW_DONE_INTERRUPT (1 << 15)
719 # define AUX5_LS_DONE_INTERRUPT (1 << 16)
720 # define AUX6_SW_DONE_INTERRUPT (1 << 17)
721 # define AUX6_LS_DONE_INTERRUPT (1 << 18)
722 # define DC_HPD5_INTERRUPT (1 << 19)
723 # define DC_HPD5_RX_INTERRUPT (1 << 20)
724 # define DC_HPD6_INTERRUPT (1 << 21)
725 # define DC_HPD6_RX_INTERRUPT (1 << 22)
727 #define DACA_AUTO_DETECT_CONTROL 0x7828
728 #define DACB_AUTO_DETECT_CONTROL 0x7a28
729 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
730 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
731 # define DACx_AUTODETECT_MODE(x) ((x) << 0)
732 # define DACx_AUTODETECT_MODE_NONE 0
733 # define DACx_AUTODETECT_MODE_CONNECT 1
734 # define DACx_AUTODETECT_MODE_DISCONNECT 2
735 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
736 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
737 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
739 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
740 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
741 #define DACA_AUTODETECT_INT_CONTROL 0x7838
742 #define DACB_AUTODETECT_INT_CONTROL 0x7a38
743 # define DACx_AUTODETECT_ACK (1 << 0)
744 # define DACx_AUTODETECT_INT_ENABLE (1 << 16)
746 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
747 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
748 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
749 # define DC_HOT_PLUG_DETECTx_EN (1 << 0)
751 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
752 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
753 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
754 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
755 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
758 #define DC_HPD1_INT_STATUS 0x7d00
759 #define DC_HPD2_INT_STATUS 0x7d0c
760 #define DC_HPD3_INT_STATUS 0x7d18
761 #define DC_HPD4_INT_STATUS 0x7d24
763 #define DC_HPD5_INT_STATUS 0x7dc0
764 #define DC_HPD6_INT_STATUS 0x7df4
765 # define DC_HPDx_INT_STATUS (1 << 0)
766 # define DC_HPDx_SENSE (1 << 1)
767 # define DC_HPDx_RX_INT_STATUS (1 << 8)
769 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
770 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
771 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
772 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
773 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
774 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
776 #define DC_HPD1_INT_CONTROL 0x7d04
777 #define DC_HPD2_INT_CONTROL 0x7d10
778 #define DC_HPD3_INT_CONTROL 0x7d1c
779 #define DC_HPD4_INT_CONTROL 0x7d28
781 #define DC_HPD5_INT_CONTROL 0x7dc4
782 #define DC_HPD6_INT_CONTROL 0x7df8
783 # define DC_HPDx_INT_ACK (1 << 0)
784 # define DC_HPDx_INT_POLARITY (1 << 8)
785 # define DC_HPDx_INT_EN (1 << 16)
786 # define DC_HPDx_RX_INT_ACK (1 << 20)
787 # define DC_HPDx_RX_INT_EN (1 << 24)
790 #define DC_HPD1_CONTROL 0x7d08
791 #define DC_HPD2_CONTROL 0x7d14
792 #define DC_HPD3_CONTROL 0x7d20
793 #define DC_HPD4_CONTROL 0x7d2c
795 #define DC_HPD5_CONTROL 0x7dc8
796 #define DC_HPD6_CONTROL 0x7dfc
797 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
798 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
800 # define DC_HPDx_EN (1 << 28)
802 #define D1GRPH_INTERRUPT_STATUS 0x6158
803 #define D2GRPH_INTERRUPT_STATUS 0x6958
804 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
805 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
806 #define D1GRPH_INTERRUPT_CONTROL 0x615c
807 #define D2GRPH_INTERRUPT_CONTROL 0x695c
808 # define DxGRPH_PFLIP_INT_MASK (1 << 0)
809 # define DxGRPH_PFLIP_INT_TYPE (1 << 8)
811 /* PCIE link stuff */
812 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
813 # define LC_POINT_7_PLUS_EN (1 << 6)
814 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
815 # define LC_LINK_WIDTH_SHIFT 0
816 # define LC_LINK_WIDTH_MASK 0x7
817 # define LC_LINK_WIDTH_X0 0
818 # define LC_LINK_WIDTH_X1 1
819 # define LC_LINK_WIDTH_X2 2
820 # define LC_LINK_WIDTH_X4 3
821 # define LC_LINK_WIDTH_X8 4
822 # define LC_LINK_WIDTH_X16 6
823 # define LC_LINK_WIDTH_RD_SHIFT 4
824 # define LC_LINK_WIDTH_RD_MASK 0x70
825 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
826 # define LC_RECONFIG_NOW (1 << 8)
827 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
828 # define LC_RENEGOTIATE_EN (1 << 10)
829 # define LC_SHORT_RECONFIG_EN (1 << 11)
830 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
831 # define LC_UPCONFIGURE_DIS (1 << 13)
832 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
833 # define LC_GEN2_EN_STRAP (1 << 0)
834 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
835 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
836 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
837 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
838 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
839 # define LC_CURRENT_DATA_RATE (1 << 11)
840 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
841 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
842 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
843 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
844 #define MM_CFGREGS_CNTL 0x544c
845 # define MM_WR_TO_CFG_EN (1 << 3)
846 #define LINK_CNTL2 0x88 /* F0 */
847 # define TARGET_LINK_SPEED_MASK (0xf << 0)
848 # define SELECTABLE_DEEMPHASIS (1 << 6)
851 #define DCCG_AUDIO_DTO0_PHASE 0x0514
852 #define DCCG_AUDIO_DTO0_MODULE 0x0518
853 #define DCCG_AUDIO_DTO0_LOAD 0x051c
854 # define DTO_LOAD (1 << 31)
855 #define DCCG_AUDIO_DTO0_CNTL 0x0520
857 #define DCCG_AUDIO_DTO1_PHASE 0x0524
858 #define DCCG_AUDIO_DTO1_MODULE 0x0528
859 #define DCCG_AUDIO_DTO1_LOAD 0x052c
860 #define DCCG_AUDIO_DTO1_CNTL 0x0530
862 #define DCCG_AUDIO_DTO_SELECT 0x0534
865 #define TMDSA_CNTL 0x7880
866 # define TMDSA_HDMI_EN (1 << 2)
867 #define LVTMA_CNTL 0x7a80
868 # define LVTMA_HDMI_EN (1 << 2)
869 #define DDIA_CNTL 0x7200
870 # define DDIA_HDMI_EN (1 << 2)
871 #define DIG0_CNTL 0x75a0
872 # define DIG_MODE(x) (((x) & 7) << 8)
873 # define DIG_MODE_DP 0
874 # define DIG_MODE_LVDS 1
875 # define DIG_MODE_TMDS_DVI 2
876 # define DIG_MODE_TMDS_HDMI 3
877 # define DIG_MODE_SDVO 4
878 #define DIG1_CNTL 0x79a0
880 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
881 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly
882 * different due to the new DIG blocks, but also have 2 instances.
883 * DCE 3.0 HDMI blocks are part of each DIG encoder.
886 /* rs6xx/rs740/r6xx/dce3 */
887 #define HDMI0_CONTROL 0x7400
888 /* rs6xx/rs740/r6xx */
889 # define HDMI0_ENABLE (1 << 0)
890 # define HDMI0_STREAM(x) (((x) & 3) << 2)
891 # define HDMI0_STREAM_TMDSA 0
892 # define HDMI0_STREAM_LVTMA 1
893 # define HDMI0_STREAM_DVOA 2
894 # define HDMI0_STREAM_DDIA 3
895 /* rs6xx/r6xx/dce3 */
896 # define HDMI0_ERROR_ACK (1 << 8)
897 # define HDMI0_ERROR_MASK (1 << 9)
898 #define HDMI0_STATUS 0x7404
899 # define HDMI0_ACTIVE_AVMUTE (1 << 0)
900 # define HDMI0_AUDIO_ENABLE (1 << 4)
901 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28)
902 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
903 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408
904 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
905 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
906 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
907 # define HDMI0_AUDIO_TEST_EN (1 << 12)
908 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
909 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
910 # define HDMI0_60958_CS_UPDATE (1 << 26)
911 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
912 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)
913 #define HDMI0_AUDIO_CRC_CONTROL 0x740c
914 # define HDMI0_AUDIO_CRC_EN (1 << 0)
915 #define HDMI0_VBI_PACKET_CONTROL 0x7410
916 # define HDMI0_NULL_SEND (1 << 0)
917 # define HDMI0_GC_SEND (1 << 4)
918 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
919 #define HDMI0_INFOFRAME_CONTROL0 0x7414
920 # define HDMI0_AVI_INFO_SEND (1 << 0)
921 # define HDMI0_AVI_INFO_CONT (1 << 1)
922 # define HDMI0_AUDIO_INFO_SEND (1 << 4)
923 # define HDMI0_AUDIO_INFO_CONT (1 << 5)
924 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
925 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
926 # define HDMI0_MPEG_INFO_SEND (1 << 8)
927 # define HDMI0_MPEG_INFO_CONT (1 << 9)
928 # define HDMI0_MPEG_INFO_UPDATE (1 << 10)
929 #define HDMI0_INFOFRAME_CONTROL1 0x7418
930 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
931 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
932 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
933 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c
934 # define HDMI0_GENERIC0_SEND (1 << 0)
935 # define HDMI0_GENERIC0_CONT (1 << 1)
936 # define HDMI0_GENERIC0_UPDATE (1 << 2)
937 # define HDMI0_GENERIC1_SEND (1 << 4)
938 # define HDMI0_GENERIC1_CONT (1 << 5)
939 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
940 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
941 #define HDMI0_GC 0x7428
942 # define HDMI0_GC_AVMUTE (1 << 0)
943 #define HDMI0_AVI_INFO0 0x7454
944 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
945 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)
946 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)
947 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)
948 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)
949 # define HDMI0_AVI_INFO_Y_RGB 0
950 # define HDMI0_AVI_INFO_Y_YCBCR422 1
951 # define HDMI0_AVI_INFO_Y_YCBCR444 2
952 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
953 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)
954 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)
955 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)
956 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
957 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)
958 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
959 #define HDMI0_AVI_INFO1 0x7458
960 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
961 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
962 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
963 #define HDMI0_AVI_INFO2 0x745c
964 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
965 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
966 #define HDMI0_AVI_INFO3 0x7460
967 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
968 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)
969 #define HDMI0_MPEG_INFO0 0x7464
970 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
971 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
972 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
973 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
974 #define HDMI0_MPEG_INFO1 0x7468
975 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
976 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)
977 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)
978 #define HDMI0_GENERIC0_HDR 0x746c
979 #define HDMI0_GENERIC0_0 0x7470
980 #define HDMI0_GENERIC0_1 0x7474
981 #define HDMI0_GENERIC0_2 0x7478
982 #define HDMI0_GENERIC0_3 0x747c
983 #define HDMI0_GENERIC0_4 0x7480
984 #define HDMI0_GENERIC0_5 0x7484
985 #define HDMI0_GENERIC0_6 0x7488
986 #define HDMI0_GENERIC1_HDR 0x748c
987 #define HDMI0_GENERIC1_0 0x7490
988 #define HDMI0_GENERIC1_1 0x7494
989 #define HDMI0_GENERIC1_2 0x7498
990 #define HDMI0_GENERIC1_3 0x749c
991 #define HDMI0_GENERIC1_4 0x74a0
992 #define HDMI0_GENERIC1_5 0x74a4
993 #define HDMI0_GENERIC1_6 0x74a8
994 #define HDMI0_ACR_32_0 0x74ac
995 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
996 #define HDMI0_ACR_32_1 0x74b0
997 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
998 #define HDMI0_ACR_44_0 0x74b4
999 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
1000 #define HDMI0_ACR_44_1 0x74b8
1001 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
1002 #define HDMI0_ACR_48_0 0x74bc
1003 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
1004 #define HDMI0_ACR_48_1 0x74c0
1005 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
1006 #define HDMI0_ACR_STATUS_0 0x74c4
1007 #define HDMI0_ACR_STATUS_1 0x74c8
1008 #define HDMI0_AUDIO_INFO0 0x74cc
1009 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
1010 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)
1011 #define HDMI0_AUDIO_INFO1 0x74d0
1012 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
1013 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
1014 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
1015 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
1016 #define HDMI0_60958_0 0x74d4
1017 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0)
1018 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1)
1019 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2)
1020 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3)
1021 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)
1022 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
1023 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
1024 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
1025 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
1026 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
1027 #define HDMI0_60958_1 0x74d8
1028 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
1029 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
1030 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
1031 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
1032 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
1033 #define HDMI0_ACR_PACKET_CONTROL 0x74dc
1034 # define HDMI0_ACR_SEND (1 << 0)
1035 # define HDMI0_ACR_CONT (1 << 1)
1036 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)
1037 # define HDMI0_ACR_HW 0
1038 # define HDMI0_ACR_32 1
1039 # define HDMI0_ACR_44 2
1040 # define HDMI0_ACR_48 3
1041 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
1042 # define HDMI0_ACR_AUTO_SEND (1 << 12)
1043 #define HDMI0_RAMP_CONTROL0 0x74e0
1044 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
1045 #define HDMI0_RAMP_CONTROL1 0x74e4
1046 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
1047 #define HDMI0_RAMP_CONTROL2 0x74e8
1048 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
1049 #define HDMI0_RAMP_CONTROL3 0x74ec
1050 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
1051 /* HDMI0_60958_2 is r7xx only */
1052 #define HDMI0_60958_2 0x74f0
1053 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
1054 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
1055 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
1056 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
1057 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
1058 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
1059 /* r6xx only; second instance starts at 0x7700 */
1060 #define HDMI1_CONTROL 0x7700
1061 #define HDMI1_STATUS 0x7704
1062 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708
1063 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */
1064 #define DCE3_HDMI1_CONTROL 0x7800
1065 #define DCE3_HDMI1_STATUS 0x7804
1066 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808
1067 /* DCE3.2 (for interrupts) */
1068 #define AFMT_STATUS 0x7600
1069 # define AFMT_AUDIO_ENABLE (1 << 4)
1070 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
1071 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
1072 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
1073 #define AFMT_AUDIO_PACKET_CONTROL 0x7604
1074 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
1075 # define AFMT_AUDIO_TEST_EN (1 << 12)
1076 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
1077 # define AFMT_60958_CS_UPDATE (1 << 26)
1078 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
1079 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
1080 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
1081 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1086 #define PACKET_TYPE0 0
1087 #define PACKET_TYPE1 1
1088 #define PACKET_TYPE2 2
1089 #define PACKET_TYPE3 3
1091 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1092 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1093 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1094 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1095 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1096 (((reg) >> 2) & 0xFFFF) | \
1097 ((n) & 0x3FFF) << 16)
1098 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1099 (((op) & 0xFF) << 8) | \
1100 ((n) & 0x3FFF) << 16)
1102 /* Packet 3 types */
1103 #define PACKET3_NOP 0x10
1104 #define PACKET3_INDIRECT_BUFFER_END 0x17
1105 #define PACKET3_SET_PREDICATION 0x20
1106 #define PACKET3_REG_RMW 0x21
1107 #define PACKET3_COND_EXEC 0x22
1108 #define PACKET3_PRED_EXEC 0x23
1109 #define PACKET3_START_3D_CMDBUF 0x24
1110 #define PACKET3_DRAW_INDEX_2 0x27
1111 #define PACKET3_CONTEXT_CONTROL 0x28
1112 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29
1113 #define PACKET3_INDEX_TYPE 0x2A
1114 #define PACKET3_DRAW_INDEX 0x2B
1115 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1116 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1117 #define PACKET3_NUM_INSTANCES 0x2F
1118 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1119 #define PACKET3_INDIRECT_BUFFER_MP 0x38
1120 #define PACKET3_MEM_SEMAPHORE 0x39
1121 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
1122 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1123 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1124 #define PACKET3_MPEG_INDEX 0x3A
1125 #define PACKET3_COPY_DW 0x3B
1126 #define PACKET3_WAIT_REG_MEM 0x3C
1127 #define PACKET3_MEM_WRITE 0x3D
1128 #define PACKET3_INDIRECT_BUFFER 0x32
1129 #define PACKET3_SURFACE_SYNC 0x43
1130 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1131 # define PACKET3_TC_ACTION_ENA (1 << 23)
1132 # define PACKET3_VC_ACTION_ENA (1 << 24)
1133 # define PACKET3_CB_ACTION_ENA (1 << 25)
1134 # define PACKET3_DB_ACTION_ENA (1 << 26)
1135 # define PACKET3_SH_ACTION_ENA (1 << 27)
1136 # define PACKET3_SMX_ACTION_ENA (1 << 28)
1137 #define PACKET3_ME_INITIALIZE 0x44
1138 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1139 #define PACKET3_COND_WRITE 0x45
1140 #define PACKET3_EVENT_WRITE 0x46
1141 #define EVENT_TYPE(x) ((x) << 0)
1142 #define EVENT_INDEX(x) ((x) << 8)
1143 /* 0 - any non-TS event
1145 * 2 - SAMPLE_PIPELINESTAT
1146 * 3 - SAMPLE_STREAMOUTSTAT*
1147 * 4 - *S_PARTIAL_FLUSH
1150 #define PACKET3_EVENT_WRITE_EOP 0x47
1151 #define DATA_SEL(x) ((x) << 29)
1153 * 1 - send low 32bit data
1154 * 2 - send 64bit data
1155 * 3 - send 64bit counter value
1157 #define INT_SEL(x) ((x) << 24)
1159 * 1 - interrupt only (DATA_SEL = 0)
1160 * 2 - interrupt when data write is confirmed
1162 #define PACKET3_ONE_REG_WRITE 0x57
1163 #define PACKET3_SET_CONFIG_REG 0x68
1164 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
1165 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1166 #define PACKET3_SET_CONTEXT_REG 0x69
1167 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
1168 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1169 #define PACKET3_SET_ALU_CONST 0x6A
1170 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
1171 #define PACKET3_SET_ALU_CONST_END 0x00032000
1172 #define PACKET3_SET_BOOL_CONST 0x6B
1173 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
1174 #define PACKET3_SET_BOOL_CONST_END 0x00040000
1175 #define PACKET3_SET_LOOP_CONST 0x6C
1176 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
1177 #define PACKET3_SET_LOOP_CONST_END 0x0003e380
1178 #define PACKET3_SET_RESOURCE 0x6D
1179 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000
1180 #define PACKET3_SET_RESOURCE_END 0x0003c000
1181 #define PACKET3_SET_SAMPLER 0x6E
1182 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
1183 #define PACKET3_SET_SAMPLER_END 0x0003cff0
1184 #define PACKET3_SET_CTL_CONST 0x6F
1185 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
1186 #define PACKET3_SET_CTL_CONST_END 0x0003e200
1187 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1188 #define PACKET3_SURFACE_BASE_UPDATE 0x73
1191 #define R_008020_GRBM_SOFT_RESET 0x8020
1192 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
1193 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
1194 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
1195 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
1196 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
1197 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
1198 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
1199 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
1200 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
1201 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
1202 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
1203 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
1204 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
1205 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
1206 #define R_008010_GRBM_STATUS 0x8010
1207 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
1208 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
1209 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
1210 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
1211 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
1212 #define S_008010_VC_BUSY(x) (((x) & 1) << 11)
1213 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
1214 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
1215 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
1216 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
1217 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
1218 #define S_008010_TC_BUSY(x) (((x) & 1) << 19)
1219 #define S_008010_SX_BUSY(x) (((x) & 1) << 20)
1220 #define S_008010_SH_BUSY(x) (((x) & 1) << 21)
1221 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
1222 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
1223 #define S_008010_SC_BUSY(x) (((x) & 1) << 24)
1224 #define S_008010_PA_BUSY(x) (((x) & 1) << 25)
1225 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
1226 #define S_008010_CR_BUSY(x) (((x) & 1) << 27)
1227 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
1228 #define S_008010_CP_BUSY(x) (((x) & 1) << 29)
1229 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
1230 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
1231 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
1232 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
1233 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
1234 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
1235 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
1236 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
1237 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
1238 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
1239 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
1240 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
1241 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
1242 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
1243 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
1244 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
1245 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
1246 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
1247 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
1248 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
1249 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
1250 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
1251 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
1252 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
1253 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
1254 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
1255 #define R_008014_GRBM_STATUS2 0x8014
1256 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
1257 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
1258 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
1259 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
1260 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
1261 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
1262 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
1263 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
1264 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
1265 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
1266 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
1267 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
1268 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
1269 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
1270 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
1271 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
1272 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
1273 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
1274 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
1275 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
1276 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
1277 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
1278 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
1279 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
1280 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
1281 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
1282 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
1283 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
1284 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
1285 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
1286 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
1287 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
1288 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
1289 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
1290 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
1291 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
1292 #define R_000E50_SRBM_STATUS 0x0E50
1293 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
1294 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
1295 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
1296 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
1297 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
1298 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
1299 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
1300 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
1301 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
1302 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
1303 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
1304 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
1305 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
1306 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
1307 #define R_000E60_SRBM_SOFT_RESET 0x0E60
1308 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
1309 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
1310 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
1311 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
1312 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
1313 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
1314 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
1315 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
1316 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
1317 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
1318 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
1319 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
1320 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
1321 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
1323 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
1325 #define R_028C04_PA_SC_AA_CONFIG 0x028C04
1326 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
1327 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
1328 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
1329 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
1330 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
1331 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
1332 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
1333 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
1334 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
1335 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0
1336 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1337 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1338 #define C_0280E0_BASE_256B 0x00000000
1339 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4
1340 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8
1341 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC
1342 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0
1343 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4
1344 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8
1345 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC
1346 #define R_0280C0_CB_COLOR0_TILE 0x0280C0
1347 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1348 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1349 #define C_0280C0_BASE_256B 0x00000000
1350 #define R_0280C4_CB_COLOR1_TILE 0x0280C4
1351 #define R_0280C8_CB_COLOR2_TILE 0x0280C8
1352 #define R_0280CC_CB_COLOR3_TILE 0x0280CC
1353 #define R_0280D0_CB_COLOR4_TILE 0x0280D0
1354 #define R_0280D4_CB_COLOR5_TILE 0x0280D4
1355 #define R_0280D8_CB_COLOR6_TILE 0x0280D8
1356 #define R_0280DC_CB_COLOR7_TILE 0x0280DC
1357 #define R_0280A0_CB_COLOR0_INFO 0x0280A0
1358 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
1359 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
1360 #define C_0280A0_ENDIAN 0xFFFFFFFC
1361 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
1362 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
1363 #define C_0280A0_FORMAT 0xFFFFFF03
1364 #define V_0280A0_COLOR_INVALID 0x00000000
1365 #define V_0280A0_COLOR_8 0x00000001
1366 #define V_0280A0_COLOR_4_4 0x00000002
1367 #define V_0280A0_COLOR_3_3_2 0x00000003
1368 #define V_0280A0_COLOR_16 0x00000005
1369 #define V_0280A0_COLOR_16_FLOAT 0x00000006
1370 #define V_0280A0_COLOR_8_8 0x00000007
1371 #define V_0280A0_COLOR_5_6_5 0x00000008
1372 #define V_0280A0_COLOR_6_5_5 0x00000009
1373 #define V_0280A0_COLOR_1_5_5_5 0x0000000A
1374 #define V_0280A0_COLOR_4_4_4_4 0x0000000B
1375 #define V_0280A0_COLOR_5_5_5_1 0x0000000C
1376 #define V_0280A0_COLOR_32 0x0000000D
1377 #define V_0280A0_COLOR_32_FLOAT 0x0000000E
1378 #define V_0280A0_COLOR_16_16 0x0000000F
1379 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010
1380 #define V_0280A0_COLOR_8_24 0x00000011
1381 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012
1382 #define V_0280A0_COLOR_24_8 0x00000013
1383 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014
1384 #define V_0280A0_COLOR_10_11_11 0x00000015
1385 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
1386 #define V_0280A0_COLOR_11_11_10 0x00000017
1387 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
1388 #define V_0280A0_COLOR_2_10_10_10 0x00000019
1389 #define V_0280A0_COLOR_8_8_8_8 0x0000001A
1390 #define V_0280A0_COLOR_10_10_10_2 0x0000001B
1391 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
1392 #define V_0280A0_COLOR_32_32 0x0000001D
1393 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
1394 #define V_0280A0_COLOR_16_16_16_16 0x0000001F
1395 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
1396 #define V_0280A0_COLOR_32_32_32_32 0x00000022
1397 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
1398 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
1399 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1400 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF
1401 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
1402 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
1403 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
1404 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
1405 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1406 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1407 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
1408 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
1409 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
1410 #define C_0280A0_READ_SIZE 0xFFFF7FFF
1411 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
1412 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
1413 #define C_0280A0_COMP_SWAP 0xFFFCFFFF
1414 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1415 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1416 #define C_0280A0_TILE_MODE 0xFFF3FFFF
1417 #define V_0280A0_TILE_DISABLE 0
1418 #define V_0280A0_CLEAR_ENABLE 1
1419 #define V_0280A0_FRAG_ENABLE 2
1420 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1421 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1422 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
1423 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
1424 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
1425 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
1426 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
1427 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
1428 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
1429 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
1430 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
1431 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
1432 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
1433 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
1434 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
1435 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
1436 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
1437 #define C_0280A0_ROUND_MODE 0xFDFFFFFF
1438 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
1439 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1440 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF
1441 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1442 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1443 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1444 #define R_0280A4_CB_COLOR1_INFO 0x0280A4
1445 #define R_0280A8_CB_COLOR2_INFO 0x0280A8
1446 #define R_0280AC_CB_COLOR3_INFO 0x0280AC
1447 #define R_0280B0_CB_COLOR4_INFO 0x0280B0
1448 #define R_0280B4_CB_COLOR5_INFO 0x0280B4
1449 #define R_0280B8_CB_COLOR6_INFO 0x0280B8
1450 #define R_0280BC_CB_COLOR7_INFO 0x0280BC
1451 #define R_028060_CB_COLOR0_SIZE 0x028060
1452 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1453 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1454 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1455 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1456 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1457 #define C_028060_SLICE_TILE_MAX 0xC00003FF
1458 #define R_028064_CB_COLOR1_SIZE 0x028064
1459 #define R_028068_CB_COLOR2_SIZE 0x028068
1460 #define R_02806C_CB_COLOR3_SIZE 0x02806C
1461 #define R_028070_CB_COLOR4_SIZE 0x028070
1462 #define R_028074_CB_COLOR5_SIZE 0x028074
1463 #define R_028078_CB_COLOR6_SIZE 0x028078
1464 #define R_02807C_CB_COLOR7_SIZE 0x02807C
1465 #define R_028238_CB_TARGET_MASK 0x028238
1466 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
1467 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
1468 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
1469 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
1470 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
1471 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
1472 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
1473 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
1474 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
1475 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
1476 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
1477 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
1478 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
1479 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
1480 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
1481 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
1482 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
1483 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
1484 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
1485 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
1486 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
1487 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
1488 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
1489 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
1490 #define R_02823C_CB_SHADER_MASK 0x02823C
1491 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
1492 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
1493 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
1494 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
1495 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
1496 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
1497 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
1498 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
1499 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
1500 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
1501 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
1502 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
1503 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
1504 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
1505 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
1506 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
1507 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
1508 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
1509 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
1510 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
1511 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
1512 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
1513 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
1514 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
1515 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0
1516 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
1517 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
1518 #define C_028AB0_STREAMOUT 0xFFFFFFFE
1519 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
1520 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
1521 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
1522 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE
1523 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
1524 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
1525 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD
1526 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
1527 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
1528 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB
1529 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
1530 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
1531 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7
1532 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1533 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1534 #define C_028B20_SIZE 0x00000000
1535 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
1536 #define S_038000_DIM(x) (((x) & 0x7) << 0)
1537 #define G_038000_DIM(x) (((x) >> 0) & 0x7)
1538 #define C_038000_DIM 0xFFFFFFF8
1539 #define V_038000_SQ_TEX_DIM_1D 0x00000000
1540 #define V_038000_SQ_TEX_DIM_2D 0x00000001
1541 #define V_038000_SQ_TEX_DIM_3D 0x00000002
1542 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
1543 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1544 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1545 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
1546 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1547 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1548 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1549 #define C_038000_TILE_MODE 0xFFFFFF87
1550 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
1551 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
1552 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
1553 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
1554 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1555 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1556 #define C_038000_TILE_TYPE 0xFFFFFF7F
1557 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
1558 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
1559 #define C_038000_PITCH 0xFFF800FF
1560 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
1561 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
1562 #define C_038000_TEX_WIDTH 0x0007FFFF
1563 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
1564 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
1565 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
1566 #define C_038004_TEX_HEIGHT 0xFFFFE000
1567 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
1568 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
1569 #define C_038004_TEX_DEPTH 0xFC001FFF
1570 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
1571 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
1572 #define C_038004_DATA_FORMAT 0x03FFFFFF
1573 #define V_038004_COLOR_INVALID 0x00000000
1574 #define V_038004_COLOR_8 0x00000001
1575 #define V_038004_COLOR_4_4 0x00000002
1576 #define V_038004_COLOR_3_3_2 0x00000003
1577 #define V_038004_COLOR_16 0x00000005
1578 #define V_038004_COLOR_16_FLOAT 0x00000006
1579 #define V_038004_COLOR_8_8 0x00000007
1580 #define V_038004_COLOR_5_6_5 0x00000008
1581 #define V_038004_COLOR_6_5_5 0x00000009
1582 #define V_038004_COLOR_1_5_5_5 0x0000000A
1583 #define V_038004_COLOR_4_4_4_4 0x0000000B
1584 #define V_038004_COLOR_5_5_5_1 0x0000000C
1585 #define V_038004_COLOR_32 0x0000000D
1586 #define V_038004_COLOR_32_FLOAT 0x0000000E
1587 #define V_038004_COLOR_16_16 0x0000000F
1588 #define V_038004_COLOR_16_16_FLOAT 0x00000010
1589 #define V_038004_COLOR_8_24 0x00000011
1590 #define V_038004_COLOR_8_24_FLOAT 0x00000012
1591 #define V_038004_COLOR_24_8 0x00000013
1592 #define V_038004_COLOR_24_8_FLOAT 0x00000014
1593 #define V_038004_COLOR_10_11_11 0x00000015
1594 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016
1595 #define V_038004_COLOR_11_11_10 0x00000017
1596 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018
1597 #define V_038004_COLOR_2_10_10_10 0x00000019
1598 #define V_038004_COLOR_8_8_8_8 0x0000001A
1599 #define V_038004_COLOR_10_10_10_2 0x0000001B
1600 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
1601 #define V_038004_COLOR_32_32 0x0000001D
1602 #define V_038004_COLOR_32_32_FLOAT 0x0000001E
1603 #define V_038004_COLOR_16_16_16_16 0x0000001F
1604 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
1605 #define V_038004_COLOR_32_32_32_32 0x00000022
1606 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
1607 #define V_038004_FMT_1 0x00000025
1608 #define V_038004_FMT_GB_GR 0x00000027
1609 #define V_038004_FMT_BG_RG 0x00000028
1610 #define V_038004_FMT_32_AS_8 0x00000029
1611 #define V_038004_FMT_32_AS_8_8 0x0000002A
1612 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
1613 #define V_038004_FMT_8_8_8 0x0000002C
1614 #define V_038004_FMT_16_16_16 0x0000002D
1615 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E
1616 #define V_038004_FMT_32_32_32 0x0000002F
1617 #define V_038004_FMT_32_32_32_FLOAT 0x00000030
1618 #define V_038004_FMT_BC1 0x00000031
1619 #define V_038004_FMT_BC2 0x00000032
1620 #define V_038004_FMT_BC3 0x00000033
1621 #define V_038004_FMT_BC4 0x00000034
1622 #define V_038004_FMT_BC5 0x00000035
1623 #define V_038004_FMT_BC6 0x00000036
1624 #define V_038004_FMT_BC7 0x00000037
1625 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038
1626 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1627 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1628 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1629 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC
1630 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1631 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1632 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
1633 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1634 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1635 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
1636 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1637 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1638 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F
1639 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1640 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1641 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
1642 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1643 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1644 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF
1645 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1646 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1647 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
1648 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1649 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1650 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF
1651 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
1652 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
1653 #define C_038010_REQUEST_SIZE 0xFFFF3FFF
1654 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
1655 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1656 #define C_038010_DST_SEL_X 0xFFF8FFFF
1657 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1658 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1659 #define C_038010_DST_SEL_Y 0xFFC7FFFF
1660 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1661 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1662 #define C_038010_DST_SEL_Z 0xFE3FFFFF
1663 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
1664 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1665 #define C_038010_DST_SEL_W 0xF1FFFFFF
1672 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1673 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1674 #define C_038010_BASE_LEVEL 0x0FFFFFFF
1675 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
1676 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1677 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1678 #define C_038014_LAST_LEVEL 0xFFFFFFF0
1679 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1680 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1681 #define C_038014_BASE_ARRAY 0xFFFE000F
1682 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1683 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1684 #define C_038014_LAST_ARRAY 0xC001FFFF
1685 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
1686 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1687 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1688 #define C_0288A8_ITEMSIZE 0xFFFF8000
1689 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
1690 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1691 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1692 #define C_008C44_MEM_SIZE 0x00000000
1693 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
1694 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1695 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1696 #define C_0288B0_ITEMSIZE 0xFFFF8000
1697 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
1698 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1699 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1700 #define C_008C54_MEM_SIZE 0x00000000
1701 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
1702 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1703 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1704 #define C_0288C0_ITEMSIZE 0xFFFF8000
1705 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
1706 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1707 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1708 #define C_008C74_MEM_SIZE 0x00000000
1709 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
1710 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1711 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1712 #define C_0288B4_ITEMSIZE 0xFFFF8000
1713 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
1714 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1715 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1716 #define C_008C5C_MEM_SIZE 0x00000000
1717 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
1718 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1719 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1720 #define C_0288AC_ITEMSIZE 0xFFFF8000
1721 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
1722 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1723 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1724 #define C_008C4C_MEM_SIZE 0x00000000
1725 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
1726 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1727 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1728 #define C_0288BC_ITEMSIZE 0xFFFF8000
1729 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
1730 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1731 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1732 #define C_008C6C_MEM_SIZE 0x00000000
1733 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
1734 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1735 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1736 #define C_0288C4_ITEMSIZE 0xFFFF8000
1737 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
1738 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1739 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1740 #define C_008C7C_MEM_SIZE 0x00000000
1741 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
1742 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1743 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1744 #define C_0288B8_ITEMSIZE 0xFFFF8000
1745 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
1746 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1747 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1748 #define C_008C64_MEM_SIZE 0x00000000
1749 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
1750 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1751 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1752 #define C_0288C8_ITEMSIZE 0xFFFF8000
1753 #define R_028010_DB_DEPTH_INFO 0x028010
1754 #define S_028010_FORMAT(x) (((x) & 0x7) << 0)
1755 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
1756 #define C_028010_FORMAT 0xFFFFFFF8
1757 #define V_028010_DEPTH_INVALID 0x00000000
1758 #define V_028010_DEPTH_16 0x00000001
1759 #define V_028010_DEPTH_X8_24 0x00000002
1760 #define V_028010_DEPTH_8_24 0x00000003
1761 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004
1762 #define V_028010_DEPTH_8_24_FLOAT 0x00000005
1763 #define V_028010_DEPTH_32_FLOAT 0x00000006
1764 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
1765 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
1766 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
1767 #define C_028010_READ_SIZE 0xFFFFFFF7
1768 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1769 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1770 #define C_028010_ARRAY_MODE 0xFFF87FFF
1771 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
1772 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
1773 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1774 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1775 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
1776 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
1777 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1778 #define C_028010_TILE_COMPACT 0xFBFFFFFF
1779 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1780 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1781 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
1782 #define R_028000_DB_DEPTH_SIZE 0x028000
1783 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1784 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1785 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00
1786 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1787 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1788 #define C_028000_SLICE_TILE_MAX 0xC00003FF
1789 #define R_028004_DB_DEPTH_VIEW 0x028004
1790 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
1791 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
1792 #define C_028004_SLICE_START 0xFFFFF800
1793 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1794 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1795 #define C_028004_SLICE_MAX 0xFF001FFF
1796 #define R_028800_DB_DEPTH_CONTROL 0x028800
1797 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1798 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1799 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1800 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1801 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1802 #define C_028800_Z_ENABLE 0xFFFFFFFD
1803 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1804 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1805 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1806 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1807 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1808 #define C_028800_ZFUNC 0xFFFFFF8F
1809 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1810 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1811 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1812 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1813 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1814 #define C_028800_STENCILFUNC 0xFFFFF8FF
1815 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1816 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1817 #define C_028800_STENCILFAIL 0xFFFFC7FF
1818 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1819 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1820 #define C_028800_STENCILZPASS 0xFFFE3FFF
1821 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1822 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1823 #define C_028800_STENCILZFAIL 0xFFF1FFFF
1824 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1825 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1826 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1827 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1828 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1829 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1830 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1831 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1832 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1833 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1834 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1835 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF