2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
77 #include <drm/drm_gem.h>
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121 /* RADEON_IB_POOL_SIZE must be a power of 2 */
122 #define RADEON_IB_POOL_SIZE 16
123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
124 #define RADEONFB_CONN_LIMIT 4
125 #define RADEON_BIOS_NUM_SCRATCH 8
127 /* internal ring indices */
128 /* r1xx+ has gfx CP ring */
129 #define RADEON_RING_TYPE_GFX_INDEX 0
131 /* cayman has 2 compute CP rings */
132 #define CAYMAN_RING_TYPE_CP1_INDEX 1
133 #define CAYMAN_RING_TYPE_CP2_INDEX 2
135 /* R600+ has an async dma ring */
136 #define R600_RING_TYPE_DMA_INDEX 3
137 /* cayman add a second async dma ring */
138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
141 #define R600_RING_TYPE_UVD_INDEX 5
144 #define TN_RING_TYPE_VCE1_INDEX 6
145 #define TN_RING_TYPE_VCE2_INDEX 7
147 /* max number of rings */
148 #define RADEON_NUM_RINGS 8
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
153 /* number of hw syncs before falling back on blocking */
154 #define RADEON_NUM_SYNCS 4
156 /* hardcode those limit for now */
157 #define RADEON_VA_IB_OFFSET (1 << 20)
158 #define RADEON_VA_RESERVED_SIZE (8 << 20)
159 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
161 /* hard reset data */
162 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
165 #define RADEON_RESET_GFX (1 << 0)
166 #define RADEON_RESET_COMPUTE (1 << 1)
167 #define RADEON_RESET_DMA (1 << 2)
168 #define RADEON_RESET_CP (1 << 3)
169 #define RADEON_RESET_GRBM (1 << 4)
170 #define RADEON_RESET_DMA1 (1 << 5)
171 #define RADEON_RESET_RLC (1 << 6)
172 #define RADEON_RESET_SEM (1 << 7)
173 #define RADEON_RESET_IH (1 << 8)
174 #define RADEON_RESET_VMC (1 << 9)
175 #define RADEON_RESET_MC (1 << 10)
176 #define RADEON_RESET_DISPLAY (1 << 11)
179 #define RADEON_CG_BLOCK_GFX (1 << 0)
180 #define RADEON_CG_BLOCK_MC (1 << 1)
181 #define RADEON_CG_BLOCK_SDMA (1 << 2)
182 #define RADEON_CG_BLOCK_UVD (1 << 3)
183 #define RADEON_CG_BLOCK_VCE (1 << 4)
184 #define RADEON_CG_BLOCK_HDP (1 << 5)
185 #define RADEON_CG_BLOCK_BIF (1 << 6)
188 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
207 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
208 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210 #define RADEON_PG_SUPPORT_UVD (1 << 3)
211 #define RADEON_PG_SUPPORT_VCE (1 << 4)
212 #define RADEON_PG_SUPPORT_CP (1 << 5)
213 #define RADEON_PG_SUPPORT_GDS (1 << 6)
214 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
216 #define RADEON_PG_SUPPORT_ACP (1 << 9)
217 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
219 /* max cursor sizes (in pixels) */
220 #define CURSOR_WIDTH 64
221 #define CURSOR_HEIGHT 64
223 #define CIK_CURSOR_WIDTH 128
224 #define CIK_CURSOR_HEIGHT 128
227 * Errata workarounds.
229 enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
236 struct radeon_device;
242 bool radeon_get_bios(struct radeon_device *rdev);
247 struct radeon_dummy_page {
251 int radeon_dummy_page_init(struct radeon_device *rdev);
252 void radeon_dummy_page_fini(struct radeon_device *rdev);
258 struct radeon_clock {
259 struct radeon_pll p1pll;
260 struct radeon_pll p2pll;
261 struct radeon_pll dcpll;
262 struct radeon_pll spll;
263 struct radeon_pll mpll;
265 uint32_t default_mclk;
266 uint32_t default_sclk;
267 uint32_t default_dispclk;
268 uint32_t current_dispclk;
270 uint32_t max_pixel_clock;
276 int radeon_pm_init(struct radeon_device *rdev);
277 int radeon_pm_late_init(struct radeon_device *rdev);
278 void radeon_pm_fini(struct radeon_device *rdev);
279 void radeon_pm_compute_clocks(struct radeon_device *rdev);
280 void radeon_pm_suspend(struct radeon_device *rdev);
281 void radeon_pm_resume(struct radeon_device *rdev);
282 void radeon_combios_get_power_modes(struct radeon_device *rdev);
283 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
284 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
288 struct atom_clock_dividers *dividers);
289 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
292 struct atom_mpll_param *mpll_param);
293 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
294 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
295 u16 voltage_level, u8 voltage_type,
296 u32 *gpio_value, u32 *gpio_mask);
297 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
298 u32 eng_clock, u32 mem_clock);
299 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
300 u8 voltage_type, u16 *voltage_step);
301 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
302 u16 voltage_id, u16 *voltage);
303 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
306 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
308 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
319 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode,
325 struct atom_voltage_table *voltage_table);
326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
328 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
337 struct atom_mc_reg_table *reg_table);
338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
339 u8 module_index, struct atom_memory_info *mem_info);
340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
341 bool gddr5, u8 module_index,
342 struct atom_memory_clock_range_table *mclk_range_table);
343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
344 u16 voltage_id, u16 *voltage);
345 void rs690_pm_info(struct radeon_device *rdev);
346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
353 struct radeon_fence_driver {
354 struct radeon_device *rdev;
355 uint32_t scratch_reg;
357 volatile uint32_t *cpu_addr;
358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
361 bool initialized, delayed_irq;
362 struct delayed_work lockup_work;
365 struct radeon_fence {
368 struct radeon_device *rdev;
373 wait_queue_t fence_wake;
376 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
377 int radeon_fence_driver_init(struct radeon_device *rdev);
378 void radeon_fence_driver_fini(struct radeon_device *rdev);
379 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
380 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
381 void radeon_fence_process(struct radeon_device *rdev, int ring);
382 bool radeon_fence_signaled(struct radeon_fence *fence);
383 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
384 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
385 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
386 int radeon_fence_wait_any(struct radeon_device *rdev,
387 struct radeon_fence **fences,
389 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
390 void radeon_fence_unref(struct radeon_fence **fence);
391 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
392 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
393 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
394 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
395 struct radeon_fence *b)
405 BUG_ON(a->ring != b->ring);
407 if (a->seq > b->seq) {
414 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
415 struct radeon_fence *b)
425 BUG_ON(a->ring != b->ring);
427 return a->seq < b->seq;
433 struct radeon_surface_reg {
434 struct radeon_bo *bo;
437 #define RADEON_GEM_MAX_SURFACES 8
443 struct ttm_bo_global_ref bo_global_ref;
444 struct drm_global_reference mem_global_ref;
445 struct ttm_bo_device bdev;
446 bool mem_global_referenced;
449 #if defined(CONFIG_DEBUG_FS)
455 /* bo virtual address in a specific vm */
456 struct radeon_bo_va {
457 /* protected by bo being reserved */
458 struct list_head bo_list;
463 /* protected by vm mutex */
464 struct interval_tree_node it;
465 struct list_head vm_status;
467 /* constant after initialization */
468 struct radeon_vm *vm;
469 struct radeon_bo *bo;
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
477 struct ttm_place placements[4];
478 struct ttm_placement placement;
479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
487 /* list of all virtual address to which this bo
491 /* Constant after initialization */
492 struct radeon_device *rdev;
493 struct drm_gem_object gem_base;
495 struct ttm_bo_kmap_obj dma_buf_vmap;
498 struct radeon_mn *mn;
499 struct interval_tree_node mn_it;
501 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
503 int radeon_gem_debugfs_init(struct radeon_device *rdev);
505 /* sub-allocation manager, it has to be protected by another lock.
506 * By conception this is an helper for other part of the driver
507 * like the indirect buffer or semaphore, which both have their
510 * Principe is simple, we keep a list of sub allocation in offset
511 * order (first entry has offset == 0, last entry has the highest
514 * When allocating new object we first check if there is room at
515 * the end total_size - (last_object_offset + last_object_size) >=
516 * alloc_size. If so we allocate new object there.
518 * When there is not enough room at the end, we start waiting for
519 * each sub object until we reach object_offset+object_size >=
520 * alloc_size, this object then become the sub object we return.
522 * Alignment can't be bigger than page size.
524 * Hole are not considered for allocation to keep things simple.
525 * Assumption is that there won't be hole (all object on same
528 struct radeon_sa_manager {
529 wait_queue_head_t wq;
530 struct radeon_bo *bo;
531 struct list_head *hole;
532 struct list_head flist[RADEON_NUM_RINGS];
533 struct list_head olist;
543 /* sub-allocation buffer */
544 struct radeon_sa_bo {
545 struct list_head olist;
546 struct list_head flist;
547 struct radeon_sa_manager *manager;
550 struct radeon_fence *fence;
558 struct list_head objects;
561 int radeon_gem_init(struct radeon_device *rdev);
562 void radeon_gem_fini(struct radeon_device *rdev);
563 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
564 int alignment, int initial_domain,
565 u32 flags, bool kernel,
566 struct drm_gem_object **obj);
568 int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571 int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);
578 struct radeon_semaphore {
579 struct radeon_sa_bo *sa_bo;
582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
585 int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
587 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore);
589 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore);
591 void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593 int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
597 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
600 void radeon_semaphore_free(struct radeon_device *rdev,
601 struct radeon_semaphore **semaphore,
602 struct radeon_fence *fence);
605 * GART structures, functions & helpers
609 #define RADEON_GPU_PAGE_SIZE 4096
610 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
611 #define RADEON_GPU_PAGE_SHIFT 12
612 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
614 #define RADEON_GART_PAGE_DUMMY 0
615 #define RADEON_GART_PAGE_VALID (1 << 0)
616 #define RADEON_GART_PAGE_READ (1 << 1)
617 #define RADEON_GART_PAGE_WRITE (1 << 2)
618 #define RADEON_GART_PAGE_SNOOP (1 << 3)
621 dma_addr_t table_addr;
622 struct radeon_bo *robj;
624 unsigned num_gpu_pages;
625 unsigned num_cpu_pages;
628 dma_addr_t *pages_addr;
632 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
633 void radeon_gart_table_ram_free(struct radeon_device *rdev);
634 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
635 void radeon_gart_table_vram_free(struct radeon_device *rdev);
636 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
637 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
638 int radeon_gart_init(struct radeon_device *rdev);
639 void radeon_gart_fini(struct radeon_device *rdev);
640 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
642 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
643 int pages, struct page **pagelist,
644 dma_addr_t *dma_addr, uint32_t flags);
648 * GPU MC structures, functions & helpers
651 resource_size_t aper_size;
652 resource_size_t aper_base;
653 resource_size_t agp_base;
654 /* for some chips with <= 32MB we need to lie
655 * about vram size near mc fb location */
657 u64 visible_vram_size;
667 bool igp_sideport_enabled;
672 bool radeon_combios_sideport_present(struct radeon_device *rdev);
673 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
676 * GPU scratch registers structures, functions & helpers
678 struct radeon_scratch {
685 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
686 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
689 * GPU doorbell structures, functions & helpers
691 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
693 struct radeon_doorbell {
695 resource_size_t base;
696 resource_size_t size;
698 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
699 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
702 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
704 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
705 phys_addr_t *aperture_base,
706 size_t *aperture_size,
707 size_t *start_offset);
713 struct radeon_flip_work {
714 struct work_struct flip_work;
715 struct work_struct unpin_work;
716 struct radeon_device *rdev;
719 struct drm_pending_vblank_event *event;
720 struct radeon_bo *old_rbo;
724 struct r500_irq_stat_regs {
729 struct r600_irq_stat_regs {
739 struct evergreen_irq_stat_regs {
760 struct cik_irq_stat_regs {
776 union radeon_irq_stat_regs {
777 struct r500_irq_stat_regs r500;
778 struct r600_irq_stat_regs r600;
779 struct evergreen_irq_stat_regs evergreen;
780 struct cik_irq_stat_regs cik;
786 atomic_t ring_int[RADEON_NUM_RINGS];
787 bool crtc_vblank_int[RADEON_MAX_CRTCS];
788 atomic_t pflip[RADEON_MAX_CRTCS];
789 wait_queue_head_t vblank_queue;
790 bool hpd[RADEON_MAX_HPD_PINS];
791 bool afmt[RADEON_MAX_AFMT_BLOCKS];
792 union radeon_irq_stat_regs stat_regs;
796 int radeon_irq_kms_init(struct radeon_device *rdev);
797 void radeon_irq_kms_fini(struct radeon_device *rdev);
798 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
799 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
800 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
801 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
802 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
803 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
804 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
805 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
806 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
813 struct radeon_sa_bo *sa_bo;
818 struct radeon_fence *fence;
819 struct radeon_vm *vm;
821 struct radeon_semaphore *semaphore;
825 struct radeon_bo *ring_obj;
826 volatile uint32_t *ring;
828 unsigned rptr_save_reg;
829 u64 next_rptr_gpu_addr;
830 volatile u32 *next_rptr_cpu_addr;
834 unsigned ring_free_dw;
837 atomic64_t last_activity;
844 u64 last_semaphore_signal_addr;
845 u64 last_semaphore_wait_addr;
850 struct radeon_bo *mqd_obj;
856 struct radeon_bo *hpd_eop_obj;
857 u64 hpd_eop_gpu_addr;
867 /* maximum number of VMIDs */
868 #define RADEON_NUM_VM 16
870 /* number of entries in page table */
871 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
873 /* PTBs (Page Table Blocks) need to be aligned to 32K */
874 #define RADEON_VM_PTB_ALIGN_SIZE 32768
875 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
876 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
878 #define R600_PTE_VALID (1 << 0)
879 #define R600_PTE_SYSTEM (1 << 1)
880 #define R600_PTE_SNOOPED (1 << 2)
881 #define R600_PTE_READABLE (1 << 5)
882 #define R600_PTE_WRITEABLE (1 << 6)
884 /* PTE (Page Table Entry) fragment field for different page sizes */
885 #define R600_PTE_FRAG_4KB (0 << 7)
886 #define R600_PTE_FRAG_64KB (4 << 7)
887 #define R600_PTE_FRAG_256KB (6 << 7)
889 /* flags needed to be set so we can copy directly from the GART table */
890 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
891 R600_PTE_SYSTEM | R600_PTE_VALID )
893 struct radeon_vm_pt {
894 struct radeon_bo *bo;
902 /* BOs moved, but not yet updated in the PT */
903 struct list_head invalidated;
905 /* BOs freed, but not yet updated in the PT */
906 struct list_head freed;
908 /* contains the page directory */
909 struct radeon_bo *page_directory;
910 uint64_t pd_gpu_addr;
911 unsigned max_pde_used;
913 /* array of page tables, one for each page directory entry */
914 struct radeon_vm_pt *page_tables;
916 struct radeon_bo_va *ib_bo_va;
919 /* last fence for cs using this vm */
920 struct radeon_fence *fence;
921 /* last flush or NULL if we still need to flush */
922 struct radeon_fence *last_flush;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
927 struct radeon_vm_manager {
928 struct radeon_fence *active[RADEON_NUM_VM];
930 /* number of VMIDs */
932 /* vram base address for page table entry */
933 u64 vram_base_offset;
936 /* for hw to save the PD addr on suspend/resume */
937 uint32_t saved_table_addr[RADEON_NUM_VM];
941 * file private structure
943 struct radeon_fpriv {
951 struct radeon_bo *ring_obj;
952 volatile uint32_t *ring;
964 #include "clearstate_defs.h"
967 /* for power gating */
968 struct radeon_bo *save_restore_obj;
969 uint64_t save_restore_gpu_addr;
970 volatile uint32_t *sr_ptr;
973 /* for clear state */
974 struct radeon_bo *clear_state_obj;
975 uint64_t clear_state_gpu_addr;
976 volatile uint32_t *cs_ptr;
977 const struct cs_section_def *cs_data;
978 u32 clear_state_size;
980 struct radeon_bo *cp_table_obj;
981 uint64_t cp_table_gpu_addr;
982 volatile uint32_t *cp_table_ptr;
986 int radeon_ib_get(struct radeon_device *rdev, int ring,
987 struct radeon_ib *ib, struct radeon_vm *vm,
989 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
990 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
991 struct radeon_ib *const_ib, bool hdp_flush);
992 int radeon_ib_pool_init(struct radeon_device *rdev);
993 void radeon_ib_pool_fini(struct radeon_device *rdev);
994 int radeon_ib_ring_tests(struct radeon_device *rdev);
995 /* Ring access between begin & end cannot sleep */
996 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
997 struct radeon_ring *ring);
998 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
999 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1000 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1001 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1003 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1005 void radeon_ring_undo(struct radeon_ring *ring);
1006 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1007 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1008 void radeon_ring_lockup_update(struct radeon_device *rdev,
1009 struct radeon_ring *ring);
1010 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1011 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1013 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1014 unsigned size, uint32_t *data);
1015 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1016 unsigned rptr_offs, u32 nop);
1017 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1020 /* r600 async dma */
1021 void r600_dma_stop(struct radeon_device *rdev);
1022 int r600_dma_resume(struct radeon_device *rdev);
1023 void r600_dma_fini(struct radeon_device *rdev);
1025 void cayman_dma_stop(struct radeon_device *rdev);
1026 int cayman_dma_resume(struct radeon_device *rdev);
1027 void cayman_dma_fini(struct radeon_device *rdev);
1032 struct radeon_cs_reloc {
1033 struct drm_gem_object *gobj;
1034 struct radeon_bo *robj;
1035 struct ttm_validate_buffer tv;
1036 uint64_t gpu_offset;
1037 unsigned prefered_domains;
1038 unsigned allowed_domains;
1039 uint32_t tiling_flags;
1043 struct radeon_cs_chunk {
1047 void __user *user_ptr;
1050 struct radeon_cs_parser {
1052 struct radeon_device *rdev;
1053 struct drm_file *filp;
1056 struct radeon_cs_chunk *chunks;
1057 uint64_t *chunks_array;
1062 struct radeon_cs_reloc *relocs;
1063 struct radeon_cs_reloc **relocs_ptr;
1064 struct radeon_cs_reloc *vm_bos;
1065 struct list_head validated;
1066 unsigned dma_reloc_idx;
1067 /* indices of various chunks */
1069 int chunk_relocs_idx;
1070 int chunk_flags_idx;
1071 int chunk_const_ib_idx;
1072 struct radeon_ib ib;
1073 struct radeon_ib const_ib;
1080 struct ww_acquire_ctx ticket;
1083 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1085 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1088 return ibc->kdata[idx];
1089 return p->ib.ptr[idx];
1093 struct radeon_cs_packet {
1099 unsigned one_reg_wr;
1102 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1103 struct radeon_cs_packet *pkt,
1104 unsigned idx, unsigned reg);
1105 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1106 struct radeon_cs_packet *pkt);
1112 int radeon_agp_init(struct radeon_device *rdev);
1113 void radeon_agp_resume(struct radeon_device *rdev);
1114 void radeon_agp_suspend(struct radeon_device *rdev);
1115 void radeon_agp_fini(struct radeon_device *rdev);
1122 struct radeon_bo *wb_obj;
1123 volatile uint32_t *wb;
1129 #define RADEON_WB_SCRATCH_OFFSET 0
1130 #define RADEON_WB_RING0_NEXT_RPTR 256
1131 #define RADEON_WB_CP_RPTR_OFFSET 1024
1132 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1133 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1134 #define R600_WB_DMA_RPTR_OFFSET 1792
1135 #define R600_WB_IH_WPTR_OFFSET 2048
1136 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1137 #define R600_WB_EVENT_OFFSET 3072
1138 #define CIK_WB_CP1_WPTR_OFFSET 3328
1139 #define CIK_WB_CP2_WPTR_OFFSET 3584
1140 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1141 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1144 * struct radeon_pm - power management datas
1145 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1146 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1147 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1148 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1149 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1150 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1151 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1152 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1153 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1154 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1155 * @needed_bandwidth: current bandwidth needs
1157 * It keeps track of various data needed to take powermanagement decision.
1158 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1159 * Equation between gpu/memory clock and available bandwidth is hw dependent
1160 * (type of memory, bus size, efficiency, ...)
1163 enum radeon_pm_method {
1169 enum radeon_dynpm_state {
1170 DYNPM_STATE_DISABLED,
1171 DYNPM_STATE_MINIMUM,
1174 DYNPM_STATE_SUSPENDED,
1176 enum radeon_dynpm_action {
1178 DYNPM_ACTION_MINIMUM,
1179 DYNPM_ACTION_DOWNCLOCK,
1180 DYNPM_ACTION_UPCLOCK,
1181 DYNPM_ACTION_DEFAULT
1184 enum radeon_voltage_type {
1191 enum radeon_pm_state_type {
1192 /* not used for dpm */
1193 POWER_STATE_TYPE_DEFAULT,
1194 POWER_STATE_TYPE_POWERSAVE,
1195 /* user selectable states */
1196 POWER_STATE_TYPE_BATTERY,
1197 POWER_STATE_TYPE_BALANCED,
1198 POWER_STATE_TYPE_PERFORMANCE,
1199 /* internal states */
1200 POWER_STATE_TYPE_INTERNAL_UVD,
1201 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1202 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1203 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1204 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1205 POWER_STATE_TYPE_INTERNAL_BOOT,
1206 POWER_STATE_TYPE_INTERNAL_THERMAL,
1207 POWER_STATE_TYPE_INTERNAL_ACPI,
1208 POWER_STATE_TYPE_INTERNAL_ULV,
1209 POWER_STATE_TYPE_INTERNAL_3DPERF,
1212 enum radeon_pm_profile_type {
1220 #define PM_PROFILE_DEFAULT_IDX 0
1221 #define PM_PROFILE_LOW_SH_IDX 1
1222 #define PM_PROFILE_MID_SH_IDX 2
1223 #define PM_PROFILE_HIGH_SH_IDX 3
1224 #define PM_PROFILE_LOW_MH_IDX 4
1225 #define PM_PROFILE_MID_MH_IDX 5
1226 #define PM_PROFILE_HIGH_MH_IDX 6
1227 #define PM_PROFILE_MAX 7
1229 struct radeon_pm_profile {
1230 int dpms_off_ps_idx;
1232 int dpms_off_cm_idx;
1236 enum radeon_int_thermal_type {
1238 THERMAL_TYPE_EXTERNAL,
1239 THERMAL_TYPE_EXTERNAL_GPIO,
1242 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1243 THERMAL_TYPE_EVERGREEN,
1247 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1252 struct radeon_voltage {
1253 enum radeon_voltage_type type;
1255 struct radeon_gpio_rec gpio;
1256 u32 delay; /* delay in usec from voltage drop to sclk change */
1257 bool active_high; /* voltage drop is active when bit is high */
1259 u8 vddc_id; /* index into vddc voltage table */
1260 u8 vddci_id; /* index into vddci voltage table */
1264 /* evergreen+ vddci */
1268 /* clock mode flags */
1269 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1271 struct radeon_pm_clock_info {
1277 struct radeon_voltage voltage;
1278 /* standardized clock flags */
1283 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1285 struct radeon_power_state {
1286 enum radeon_pm_state_type type;
1287 struct radeon_pm_clock_info *clock_info;
1288 /* number of valid clock modes in this power state */
1289 int num_clock_modes;
1290 struct radeon_pm_clock_info *default_clock_mode;
1291 /* standardized state flags */
1293 u32 misc; /* vbios specific flags */
1294 u32 misc2; /* vbios specific flags */
1295 int pcie_lanes; /* pcie lanes */
1299 * Some modes are overclocked by very low value, accept them
1301 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1303 enum radeon_dpm_auto_throttle_src {
1304 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1305 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1308 enum radeon_dpm_event_src {
1309 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1310 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1311 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1312 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1313 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1316 #define RADEON_MAX_VCE_LEVELS 6
1318 enum radeon_vce_level {
1319 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1320 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1321 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1322 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1323 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1324 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1328 u32 caps; /* vbios flags */
1329 u32 class; /* vbios flags */
1330 u32 class2; /* vbios flags */
1338 enum radeon_vce_level vce_level;
1343 struct radeon_dpm_thermal {
1344 /* thermal interrupt work */
1345 struct work_struct work;
1346 /* low temperature threshold */
1348 /* high temperature threshold */
1350 /* was interrupt low to high or high to low */
1354 enum radeon_clk_action
1360 struct radeon_blacklist_clocks
1364 enum radeon_clk_action action;
1367 struct radeon_clock_and_voltage_limits {
1374 struct radeon_clock_array {
1379 struct radeon_clock_voltage_dependency_entry {
1384 struct radeon_clock_voltage_dependency_table {
1386 struct radeon_clock_voltage_dependency_entry *entries;
1389 union radeon_cac_leakage_entry {
1401 struct radeon_cac_leakage_table {
1403 union radeon_cac_leakage_entry *entries;
1406 struct radeon_phase_shedding_limits_entry {
1412 struct radeon_phase_shedding_limits_table {
1414 struct radeon_phase_shedding_limits_entry *entries;
1417 struct radeon_uvd_clock_voltage_dependency_entry {
1423 struct radeon_uvd_clock_voltage_dependency_table {
1425 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1428 struct radeon_vce_clock_voltage_dependency_entry {
1434 struct radeon_vce_clock_voltage_dependency_table {
1436 struct radeon_vce_clock_voltage_dependency_entry *entries;
1439 struct radeon_ppm_table {
1441 u16 cpu_core_number;
1443 u32 small_ac_platform_tdp;
1445 u32 small_ac_platform_tdc;
1452 struct radeon_cac_tdp_table {
1454 u16 configurable_tdp;
1456 u16 battery_power_limit;
1457 u16 small_power_limit;
1458 u16 low_cac_leakage;
1459 u16 high_cac_leakage;
1460 u16 maximum_power_delivery_limit;
1463 struct radeon_dpm_dynamic_state {
1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1465 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1466 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1467 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1469 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1470 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1471 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1472 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1473 struct radeon_clock_array valid_sclk_values;
1474 struct radeon_clock_array valid_mclk_values;
1475 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1476 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1477 u32 mclk_sclk_ratio;
1478 u32 sclk_mclk_delta;
1479 u16 vddc_vddci_delta;
1480 u16 min_vddc_for_pcie_gen2;
1481 struct radeon_cac_leakage_table cac_leakage_table;
1482 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1483 struct radeon_ppm_table *ppm_table;
1484 struct radeon_cac_tdp_table *cac_tdp_table;
1487 struct radeon_dpm_fan {
1498 u16 default_max_fan_pwm;
1499 u16 default_fan_output_sensitivity;
1500 u16 fan_output_sensitivity;
1501 bool ucode_fan_control;
1504 enum radeon_pcie_gen {
1505 RADEON_PCIE_GEN1 = 0,
1506 RADEON_PCIE_GEN2 = 1,
1507 RADEON_PCIE_GEN3 = 2,
1508 RADEON_PCIE_GEN_INVALID = 0xffff
1511 enum radeon_dpm_forced_level {
1512 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1513 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1514 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1517 struct radeon_vce_state {
1529 struct radeon_ps *ps;
1530 /* number of valid power states */
1532 /* current power state that is active */
1533 struct radeon_ps *current_ps;
1534 /* requested power state */
1535 struct radeon_ps *requested_ps;
1536 /* boot up power state */
1537 struct radeon_ps *boot_ps;
1538 /* default uvd power state */
1539 struct radeon_ps *uvd_ps;
1540 /* vce requirements */
1541 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1542 enum radeon_vce_level vce_level;
1543 enum radeon_pm_state_type state;
1544 enum radeon_pm_state_type user_state;
1546 u32 voltage_response_time;
1547 u32 backbias_response_time;
1549 u32 new_active_crtcs;
1550 int new_active_crtc_count;
1551 u32 current_active_crtcs;
1552 int current_active_crtc_count;
1553 struct radeon_dpm_dynamic_state dyn_state;
1554 struct radeon_dpm_fan fan;
1557 u32 near_tdp_limit_adjusted;
1558 u32 sq_ramping_threshold;
1562 u16 load_line_slope;
1565 /* special states active */
1566 bool thermal_active;
1569 /* thermal handling */
1570 struct radeon_dpm_thermal thermal;
1572 enum radeon_dpm_forced_level forced_level;
1573 /* track UVD streams */
1578 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1579 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1583 /* write locked while reprogramming mclk */
1584 struct rw_semaphore mclk_lock;
1586 int active_crtc_count;
1589 fixed20_12 max_bandwidth;
1590 fixed20_12 igp_sideport_mclk;
1591 fixed20_12 igp_system_mclk;
1592 fixed20_12 igp_ht_link_clk;
1593 fixed20_12 igp_ht_link_width;
1594 fixed20_12 k8_bandwidth;
1595 fixed20_12 sideport_bandwidth;
1596 fixed20_12 ht_bandwidth;
1597 fixed20_12 core_bandwidth;
1600 fixed20_12 needed_bandwidth;
1601 struct radeon_power_state *power_state;
1602 /* number of valid power states */
1603 int num_power_states;
1604 int current_power_state_index;
1605 int current_clock_mode_index;
1606 int requested_power_state_index;
1607 int requested_clock_mode_index;
1608 int default_power_state_index;
1617 struct radeon_i2c_chan *i2c_bus;
1618 /* selected pm method */
1619 enum radeon_pm_method pm_method;
1620 /* dynpm power management */
1621 struct delayed_work dynpm_idle_work;
1622 enum radeon_dynpm_state dynpm_state;
1623 enum radeon_dynpm_action dynpm_planned_action;
1624 unsigned long dynpm_action_timeout;
1625 bool dynpm_can_upclock;
1626 bool dynpm_can_downclock;
1627 /* profile-based power management */
1628 enum radeon_pm_profile_type profile;
1630 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1631 /* internal thermal controller on rv6xx+ */
1632 enum radeon_int_thermal_type int_thermal_type;
1633 struct device *int_hwmon_dev;
1634 /* fan control parameters */
1636 u8 fan_pulses_per_revolution;
1641 struct radeon_dpm dpm;
1644 int radeon_pm_get_type_index(struct radeon_device *rdev,
1645 enum radeon_pm_state_type ps_type,
1650 #define RADEON_MAX_UVD_HANDLES 10
1651 #define RADEON_UVD_STACK_SIZE (1024*1024)
1652 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1655 struct radeon_bo *vcpu_bo;
1659 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1660 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1661 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1662 struct delayed_work idle_work;
1665 int radeon_uvd_init(struct radeon_device *rdev);
1666 void radeon_uvd_fini(struct radeon_device *rdev);
1667 int radeon_uvd_suspend(struct radeon_device *rdev);
1668 int radeon_uvd_resume(struct radeon_device *rdev);
1669 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1670 uint32_t handle, struct radeon_fence **fence);
1671 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1672 uint32_t handle, struct radeon_fence **fence);
1673 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1674 uint32_t allowed_domains);
1675 void radeon_uvd_free_handles(struct radeon_device *rdev,
1676 struct drm_file *filp);
1677 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1678 void radeon_uvd_note_usage(struct radeon_device *rdev);
1679 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1680 unsigned vclk, unsigned dclk,
1681 unsigned vco_min, unsigned vco_max,
1682 unsigned fb_factor, unsigned fb_mask,
1683 unsigned pd_min, unsigned pd_max,
1685 unsigned *optimal_fb_div,
1686 unsigned *optimal_vclk_div,
1687 unsigned *optimal_dclk_div);
1688 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1689 unsigned cg_upll_func_cntl);
1694 #define RADEON_MAX_VCE_HANDLES 16
1695 #define RADEON_VCE_STACK_SIZE (1024*1024)
1696 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1699 struct radeon_bo *vcpu_bo;
1701 unsigned fw_version;
1702 unsigned fb_version;
1703 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1704 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1705 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1706 struct delayed_work idle_work;
1709 int radeon_vce_init(struct radeon_device *rdev);
1710 void radeon_vce_fini(struct radeon_device *rdev);
1711 int radeon_vce_suspend(struct radeon_device *rdev);
1712 int radeon_vce_resume(struct radeon_device *rdev);
1713 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1714 uint32_t handle, struct radeon_fence **fence);
1715 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1716 uint32_t handle, struct radeon_fence **fence);
1717 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1718 void radeon_vce_note_usage(struct radeon_device *rdev);
1719 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1720 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1721 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1722 struct radeon_ring *ring,
1723 struct radeon_semaphore *semaphore,
1725 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1726 void radeon_vce_fence_emit(struct radeon_device *rdev,
1727 struct radeon_fence *fence);
1728 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1729 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1731 struct r600_audio_pin {
1734 int bits_per_sample;
1744 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1751 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1757 void radeon_test_moves(struct radeon_device *rdev);
1758 void radeon_test_ring_sync(struct radeon_device *rdev,
1759 struct radeon_ring *cpA,
1760 struct radeon_ring *cpB);
1761 void radeon_test_syncing(struct radeon_device *rdev);
1766 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1767 void radeon_mn_unregister(struct radeon_bo *bo);
1772 struct radeon_debugfs {
1773 struct drm_info_list *files;
1777 int radeon_debugfs_add_files(struct radeon_device *rdev,
1778 struct drm_info_list *files,
1780 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1783 * ASIC ring specific functions.
1785 struct radeon_asic_ring {
1786 /* ring read/write ptr handling */
1787 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1788 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1789 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1791 /* validating and patching of IBs */
1792 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1793 int (*cs_parse)(struct radeon_cs_parser *p);
1795 /* command emmit functions */
1796 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1797 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1798 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1799 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1800 struct radeon_semaphore *semaphore, bool emit_wait);
1801 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1802 unsigned vm_id, uint64_t pd_addr);
1804 /* testing functions */
1805 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1806 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1807 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1810 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1814 * ASIC specific functions.
1816 struct radeon_asic {
1817 int (*init)(struct radeon_device *rdev);
1818 void (*fini)(struct radeon_device *rdev);
1819 int (*resume)(struct radeon_device *rdev);
1820 int (*suspend)(struct radeon_device *rdev);
1821 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1822 int (*asic_reset)(struct radeon_device *rdev);
1823 /* Flush the HDP cache via MMIO */
1824 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1825 /* check if 3D engine is idle */
1826 bool (*gui_idle)(struct radeon_device *rdev);
1827 /* wait for mc_idle */
1828 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1829 /* get the reference clock */
1830 u32 (*get_xclk)(struct radeon_device *rdev);
1831 /* get the gpu clock counter */
1832 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1835 void (*tlb_flush)(struct radeon_device *rdev);
1836 void (*set_page)(struct radeon_device *rdev, unsigned i,
1837 uint64_t addr, uint32_t flags);
1840 int (*init)(struct radeon_device *rdev);
1841 void (*fini)(struct radeon_device *rdev);
1842 void (*copy_pages)(struct radeon_device *rdev,
1843 struct radeon_ib *ib,
1844 uint64_t pe, uint64_t src,
1846 void (*write_pages)(struct radeon_device *rdev,
1847 struct radeon_ib *ib,
1849 uint64_t addr, unsigned count,
1850 uint32_t incr, uint32_t flags);
1851 void (*set_pages)(struct radeon_device *rdev,
1852 struct radeon_ib *ib,
1854 uint64_t addr, unsigned count,
1855 uint32_t incr, uint32_t flags);
1856 void (*pad_ib)(struct radeon_ib *ib);
1858 /* ring specific callbacks */
1859 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1862 int (*set)(struct radeon_device *rdev);
1863 int (*process)(struct radeon_device *rdev);
1867 /* display watermarks */
1868 void (*bandwidth_update)(struct radeon_device *rdev);
1869 /* get frame count */
1870 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1871 /* wait for vblank */
1872 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1873 /* set backlight level */
1874 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1875 /* get backlight level */
1876 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1877 /* audio callbacks */
1878 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1879 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1881 /* copy functions for bo handling */
1883 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1884 uint64_t src_offset,
1885 uint64_t dst_offset,
1886 unsigned num_gpu_pages,
1887 struct reservation_object *resv);
1888 u32 blit_ring_index;
1889 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1890 uint64_t src_offset,
1891 uint64_t dst_offset,
1892 unsigned num_gpu_pages,
1893 struct reservation_object *resv);
1895 /* method used for bo copy */
1896 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1897 uint64_t src_offset,
1898 uint64_t dst_offset,
1899 unsigned num_gpu_pages,
1900 struct reservation_object *resv);
1901 /* ring used for bo copies */
1902 u32 copy_ring_index;
1906 int (*set_reg)(struct radeon_device *rdev, int reg,
1907 uint32_t tiling_flags, uint32_t pitch,
1908 uint32_t offset, uint32_t obj_size);
1909 void (*clear_reg)(struct radeon_device *rdev, int reg);
1911 /* hotplug detect */
1913 void (*init)(struct radeon_device *rdev);
1914 void (*fini)(struct radeon_device *rdev);
1915 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1916 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1918 /* static power management */
1920 void (*misc)(struct radeon_device *rdev);
1921 void (*prepare)(struct radeon_device *rdev);
1922 void (*finish)(struct radeon_device *rdev);
1923 void (*init_profile)(struct radeon_device *rdev);
1924 void (*get_dynpm_state)(struct radeon_device *rdev);
1925 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1926 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1927 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1928 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1929 int (*get_pcie_lanes)(struct radeon_device *rdev);
1930 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1931 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1932 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1933 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1934 int (*get_temperature)(struct radeon_device *rdev);
1936 /* dynamic power management */
1938 int (*init)(struct radeon_device *rdev);
1939 void (*setup_asic)(struct radeon_device *rdev);
1940 int (*enable)(struct radeon_device *rdev);
1941 int (*late_enable)(struct radeon_device *rdev);
1942 void (*disable)(struct radeon_device *rdev);
1943 int (*pre_set_power_state)(struct radeon_device *rdev);
1944 int (*set_power_state)(struct radeon_device *rdev);
1945 void (*post_set_power_state)(struct radeon_device *rdev);
1946 void (*display_configuration_changed)(struct radeon_device *rdev);
1947 void (*fini)(struct radeon_device *rdev);
1948 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1949 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1950 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1951 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1952 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1953 bool (*vblank_too_short)(struct radeon_device *rdev);
1954 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1955 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1959 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1960 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1968 const unsigned *reg_safe_bm;
1969 unsigned reg_safe_bm_size;
1974 const unsigned *reg_safe_bm;
1975 unsigned reg_safe_bm_size;
1982 unsigned max_tile_pipes;
1984 unsigned max_backends;
1986 unsigned max_threads;
1987 unsigned max_stack_entries;
1988 unsigned max_hw_contexts;
1989 unsigned max_gs_threads;
1990 unsigned sx_max_export_size;
1991 unsigned sx_max_export_pos_size;
1992 unsigned sx_max_export_smx_size;
1993 unsigned sq_num_cf_insts;
1994 unsigned tiling_nbanks;
1995 unsigned tiling_npipes;
1996 unsigned tiling_group_size;
1997 unsigned tile_config;
1998 unsigned backend_map;
1999 unsigned active_simds;
2004 unsigned max_tile_pipes;
2006 unsigned max_backends;
2008 unsigned max_threads;
2009 unsigned max_stack_entries;
2010 unsigned max_hw_contexts;
2011 unsigned max_gs_threads;
2012 unsigned sx_max_export_size;
2013 unsigned sx_max_export_pos_size;
2014 unsigned sx_max_export_smx_size;
2015 unsigned sq_num_cf_insts;
2016 unsigned sx_num_of_sets;
2017 unsigned sc_prim_fifo_size;
2018 unsigned sc_hiz_tile_fifo_size;
2019 unsigned sc_earlyz_tile_fifo_fize;
2020 unsigned tiling_nbanks;
2021 unsigned tiling_npipes;
2022 unsigned tiling_group_size;
2023 unsigned tile_config;
2024 unsigned backend_map;
2025 unsigned active_simds;
2028 struct evergreen_asic {
2031 unsigned max_tile_pipes;
2033 unsigned max_backends;
2035 unsigned max_threads;
2036 unsigned max_stack_entries;
2037 unsigned max_hw_contexts;
2038 unsigned max_gs_threads;
2039 unsigned sx_max_export_size;
2040 unsigned sx_max_export_pos_size;
2041 unsigned sx_max_export_smx_size;
2042 unsigned sq_num_cf_insts;
2043 unsigned sx_num_of_sets;
2044 unsigned sc_prim_fifo_size;
2045 unsigned sc_hiz_tile_fifo_size;
2046 unsigned sc_earlyz_tile_fifo_size;
2047 unsigned tiling_nbanks;
2048 unsigned tiling_npipes;
2049 unsigned tiling_group_size;
2050 unsigned tile_config;
2051 unsigned backend_map;
2052 unsigned active_simds;
2055 struct cayman_asic {
2056 unsigned max_shader_engines;
2057 unsigned max_pipes_per_simd;
2058 unsigned max_tile_pipes;
2059 unsigned max_simds_per_se;
2060 unsigned max_backends_per_se;
2061 unsigned max_texture_channel_caches;
2063 unsigned max_threads;
2064 unsigned max_gs_threads;
2065 unsigned max_stack_entries;
2066 unsigned sx_num_of_sets;
2067 unsigned sx_max_export_size;
2068 unsigned sx_max_export_pos_size;
2069 unsigned sx_max_export_smx_size;
2070 unsigned max_hw_contexts;
2071 unsigned sq_num_cf_insts;
2072 unsigned sc_prim_fifo_size;
2073 unsigned sc_hiz_tile_fifo_size;
2074 unsigned sc_earlyz_tile_fifo_size;
2076 unsigned num_shader_engines;
2077 unsigned num_shader_pipes_per_simd;
2078 unsigned num_tile_pipes;
2079 unsigned num_simds_per_se;
2080 unsigned num_backends_per_se;
2081 unsigned backend_disable_mask_per_asic;
2082 unsigned backend_map;
2083 unsigned num_texture_channel_caches;
2084 unsigned mem_max_burst_length_bytes;
2085 unsigned mem_row_size_in_kb;
2086 unsigned shader_engine_tile_size;
2088 unsigned multi_gpu_tile_size;
2090 unsigned tile_config;
2091 unsigned active_simds;
2095 unsigned max_shader_engines;
2096 unsigned max_tile_pipes;
2097 unsigned max_cu_per_sh;
2098 unsigned max_sh_per_se;
2099 unsigned max_backends_per_se;
2100 unsigned max_texture_channel_caches;
2102 unsigned max_gs_threads;
2103 unsigned max_hw_contexts;
2104 unsigned sc_prim_fifo_size_frontend;
2105 unsigned sc_prim_fifo_size_backend;
2106 unsigned sc_hiz_tile_fifo_size;
2107 unsigned sc_earlyz_tile_fifo_size;
2109 unsigned num_tile_pipes;
2110 unsigned backend_enable_mask;
2111 unsigned backend_disable_mask_per_asic;
2112 unsigned backend_map;
2113 unsigned num_texture_channel_caches;
2114 unsigned mem_max_burst_length_bytes;
2115 unsigned mem_row_size_in_kb;
2116 unsigned shader_engine_tile_size;
2118 unsigned multi_gpu_tile_size;
2120 unsigned tile_config;
2121 uint32_t tile_mode_array[32];
2122 uint32_t active_cus;
2126 unsigned max_shader_engines;
2127 unsigned max_tile_pipes;
2128 unsigned max_cu_per_sh;
2129 unsigned max_sh_per_se;
2130 unsigned max_backends_per_se;
2131 unsigned max_texture_channel_caches;
2133 unsigned max_gs_threads;
2134 unsigned max_hw_contexts;
2135 unsigned sc_prim_fifo_size_frontend;
2136 unsigned sc_prim_fifo_size_backend;
2137 unsigned sc_hiz_tile_fifo_size;
2138 unsigned sc_earlyz_tile_fifo_size;
2140 unsigned num_tile_pipes;
2141 unsigned backend_enable_mask;
2142 unsigned backend_disable_mask_per_asic;
2143 unsigned backend_map;
2144 unsigned num_texture_channel_caches;
2145 unsigned mem_max_burst_length_bytes;
2146 unsigned mem_row_size_in_kb;
2147 unsigned shader_engine_tile_size;
2149 unsigned multi_gpu_tile_size;
2151 unsigned tile_config;
2152 uint32_t tile_mode_array[32];
2153 uint32_t macrotile_mode_array[16];
2154 uint32_t active_cus;
2157 union radeon_asic_config {
2158 struct r300_asic r300;
2159 struct r100_asic r100;
2160 struct r600_asic r600;
2161 struct rv770_asic rv770;
2162 struct evergreen_asic evergreen;
2163 struct cayman_asic cayman;
2165 struct cik_asic cik;
2169 * asic initizalization from radeon_asic.c
2171 void radeon_agp_disable(struct radeon_device *rdev);
2172 int radeon_asic_init(struct radeon_device *rdev);
2178 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2179 struct drm_file *filp);
2180 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *filp);
2182 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2183 struct drm_file *filp);
2184 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2185 struct drm_file *file_priv);
2186 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2187 struct drm_file *file_priv);
2188 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2189 struct drm_file *file_priv);
2190 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2191 struct drm_file *file_priv);
2192 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2193 struct drm_file *filp);
2194 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2195 struct drm_file *filp);
2196 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2197 struct drm_file *filp);
2198 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2199 struct drm_file *filp);
2200 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2201 struct drm_file *filp);
2202 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2203 struct drm_file *filp);
2204 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2205 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2206 struct drm_file *filp);
2207 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2208 struct drm_file *filp);
2210 /* VRAM scratch page for HDP bug, default vram page */
2211 struct r600_vram_scratch {
2212 struct radeon_bo *robj;
2213 volatile uint32_t *ptr;
2220 struct radeon_atif_notification_cfg {
2225 struct radeon_atif_notifications {
2226 bool display_switch;
2227 bool expansion_mode_change;
2229 bool forced_power_state;
2230 bool system_power_state;
2231 bool display_conf_change;
2233 bool brightness_change;
2234 bool dgpu_display_event;
2237 struct radeon_atif_functions {
2239 bool sbios_requests;
2240 bool select_active_disp;
2242 bool get_tv_standard;
2243 bool set_tv_standard;
2244 bool get_panel_expansion_mode;
2245 bool set_panel_expansion_mode;
2246 bool temperature_change;
2247 bool graphics_device_types;
2250 struct radeon_atif {
2251 struct radeon_atif_notifications notifications;
2252 struct radeon_atif_functions functions;
2253 struct radeon_atif_notification_cfg notification_cfg;
2254 struct radeon_encoder *encoder_for_bl;
2257 struct radeon_atcs_functions {
2261 bool pcie_bus_width;
2264 struct radeon_atcs {
2265 struct radeon_atcs_functions functions;
2269 * Core structure, functions and helpers.
2271 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2272 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2274 struct radeon_device {
2276 struct drm_device *ddev;
2277 struct pci_dev *pdev;
2278 struct rw_semaphore exclusive_lock;
2280 union radeon_asic_config config;
2281 enum radeon_family family;
2282 unsigned long flags;
2284 enum radeon_pll_errata pll_errata;
2291 uint16_t bios_header_start;
2292 struct radeon_bo *stollen_vga_memory;
2294 resource_size_t rmmio_base;
2295 resource_size_t rmmio_size;
2296 /* protects concurrent MM_INDEX/DATA based register access */
2297 spinlock_t mmio_idx_lock;
2298 /* protects concurrent SMC based register access */
2299 spinlock_t smc_idx_lock;
2300 /* protects concurrent PLL register access */
2301 spinlock_t pll_idx_lock;
2302 /* protects concurrent MC register access */
2303 spinlock_t mc_idx_lock;
2304 /* protects concurrent PCIE register access */
2305 spinlock_t pcie_idx_lock;
2306 /* protects concurrent PCIE_PORT register access */
2307 spinlock_t pciep_idx_lock;
2308 /* protects concurrent PIF register access */
2309 spinlock_t pif_idx_lock;
2310 /* protects concurrent CG register access */
2311 spinlock_t cg_idx_lock;
2312 /* protects concurrent UVD register access */
2313 spinlock_t uvd_idx_lock;
2314 /* protects concurrent RCU register access */
2315 spinlock_t rcu_idx_lock;
2316 /* protects concurrent DIDT register access */
2317 spinlock_t didt_idx_lock;
2318 /* protects concurrent ENDPOINT (audio) register access */
2319 spinlock_t end_idx_lock;
2320 void __iomem *rmmio;
2321 radeon_rreg_t mc_rreg;
2322 radeon_wreg_t mc_wreg;
2323 radeon_rreg_t pll_rreg;
2324 radeon_wreg_t pll_wreg;
2325 uint32_t pcie_reg_mask;
2326 radeon_rreg_t pciep_rreg;
2327 radeon_wreg_t pciep_wreg;
2329 void __iomem *rio_mem;
2330 resource_size_t rio_mem_size;
2331 struct radeon_clock clock;
2332 struct radeon_mc mc;
2333 struct radeon_gart gart;
2334 struct radeon_mode_info mode_info;
2335 struct radeon_scratch scratch;
2336 struct radeon_doorbell doorbell;
2337 struct radeon_mman mman;
2338 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2339 wait_queue_head_t fence_queue;
2340 unsigned fence_context;
2341 struct mutex ring_lock;
2342 struct radeon_ring ring[RADEON_NUM_RINGS];
2344 struct radeon_sa_manager ring_tmp_bo;
2345 struct radeon_irq irq;
2346 struct radeon_asic *asic;
2347 struct radeon_gem gem;
2348 struct radeon_pm pm;
2349 struct radeon_uvd uvd;
2350 struct radeon_vce vce;
2351 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2352 struct radeon_wb wb;
2353 struct radeon_dummy_page dummy_page;
2358 bool fastfb_working; /* IGP feature*/
2359 bool needs_reset, in_reset;
2360 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2361 const struct firmware *me_fw; /* all family ME firmware */
2362 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2363 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2364 const struct firmware *mc_fw; /* NI MC firmware */
2365 const struct firmware *ce_fw; /* SI CE firmware */
2366 const struct firmware *mec_fw; /* CIK MEC firmware */
2367 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2368 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2369 const struct firmware *smc_fw; /* SMC firmware */
2370 const struct firmware *uvd_fw; /* UVD firmware */
2371 const struct firmware *vce_fw; /* VCE firmware */
2373 struct r600_vram_scratch vram_scratch;
2374 int msi_enabled; /* msi enabled */
2375 struct r600_ih ih; /* r6/700 interrupt ring */
2376 struct radeon_rlc rlc;
2377 struct radeon_mec mec;
2378 struct work_struct hotplug_work;
2379 struct work_struct audio_work;
2380 int num_crtc; /* number of crtcs */
2381 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2383 struct r600_audio audio; /* audio stuff */
2384 struct notifier_block acpi_nb;
2385 /* only one userspace can use Hyperz features or CMASK at a time */
2386 struct drm_file *hyperz_filp;
2387 struct drm_file *cmask_filp;
2389 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2391 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2392 unsigned debugfs_count;
2393 /* virtual memory */
2394 struct radeon_vm_manager vm_manager;
2395 struct mutex gpu_clock_mutex;
2397 atomic64_t vram_usage;
2398 atomic64_t gtt_usage;
2399 atomic64_t num_bytes_moved;
2400 /* ACPI interface */
2401 struct radeon_atif atif;
2402 struct radeon_atcs atcs;
2403 /* srbm instance registers */
2404 struct mutex srbm_mutex;
2405 /* GRBM index mutex. Protects concurrents access to GRBM index */
2406 struct mutex grbm_idx_mutex;
2407 /* clock, powergating flags */
2411 struct dev_pm_domain vga_pm_domain;
2412 bool have_disp_power_ref;
2415 /* tracking pinned memory */
2419 /* amdkfd interface */
2420 struct kfd_dev *kfd;
2421 struct radeon_sa_manager kfd_bo;
2423 struct mutex mn_lock;
2424 DECLARE_HASHTABLE(mn_hash, 7);
2427 bool radeon_is_px(struct drm_device *dev);
2428 int radeon_device_init(struct radeon_device *rdev,
2429 struct drm_device *ddev,
2430 struct pci_dev *pdev,
2432 void radeon_device_fini(struct radeon_device *rdev);
2433 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2435 #define RADEON_MIN_MMIO_SIZE 0x10000
2437 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2438 bool always_indirect)
2440 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2441 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2442 return readl(((void __iomem *)rdev->rmmio) + reg);
2444 unsigned long flags;
2447 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2448 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2449 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2450 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2456 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2457 bool always_indirect)
2459 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2460 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2462 unsigned long flags;
2464 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2465 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2466 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2467 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2471 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2472 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2474 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2475 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2480 extern const struct fence_ops radeon_fence_ops;
2482 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2484 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2486 if (__f->base.ops == &radeon_fence_ops)
2493 * Registers read & write functions.
2495 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2496 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2497 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2498 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2499 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2500 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2501 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2502 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2503 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2504 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2505 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2506 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2507 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2508 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2509 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2510 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2511 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2512 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2513 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2514 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2515 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2516 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2517 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2518 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2519 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2520 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2521 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2522 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2523 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2524 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2525 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2526 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2527 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2528 #define WREG32_P(reg, val, mask) \
2530 uint32_t tmp_ = RREG32(reg); \
2532 tmp_ |= ((val) & ~(mask)); \
2533 WREG32(reg, tmp_); \
2535 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2536 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2537 #define WREG32_PLL_P(reg, val, mask) \
2539 uint32_t tmp_ = RREG32_PLL(reg); \
2541 tmp_ |= ((val) & ~(mask)); \
2542 WREG32_PLL(reg, tmp_); \
2544 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2545 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2546 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2548 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2549 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2552 * Indirect registers accessor
2554 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2556 unsigned long flags;
2559 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2560 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2561 r = RREG32(RADEON_PCIE_DATA);
2562 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2566 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2568 unsigned long flags;
2570 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2571 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2572 WREG32(RADEON_PCIE_DATA, (v));
2573 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2576 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2578 unsigned long flags;
2581 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2582 WREG32(TN_SMC_IND_INDEX_0, (reg));
2583 r = RREG32(TN_SMC_IND_DATA_0);
2584 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2588 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2590 unsigned long flags;
2592 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2593 WREG32(TN_SMC_IND_INDEX_0, (reg));
2594 WREG32(TN_SMC_IND_DATA_0, (v));
2595 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2598 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2600 unsigned long flags;
2603 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2604 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2605 r = RREG32(R600_RCU_DATA);
2606 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2610 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2612 unsigned long flags;
2614 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2615 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2616 WREG32(R600_RCU_DATA, (v));
2617 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2620 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2622 unsigned long flags;
2625 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2626 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2627 r = RREG32(EVERGREEN_CG_IND_DATA);
2628 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2632 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2634 unsigned long flags;
2636 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2637 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2638 WREG32(EVERGREEN_CG_IND_DATA, (v));
2639 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2642 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2644 unsigned long flags;
2647 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2648 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2649 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2650 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2654 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2656 unsigned long flags;
2658 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2659 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2660 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2661 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2664 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2666 unsigned long flags;
2669 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2670 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2671 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2672 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2676 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2678 unsigned long flags;
2680 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2681 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2682 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2683 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2686 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2688 unsigned long flags;
2691 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2692 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2693 r = RREG32(R600_UVD_CTX_DATA);
2694 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2698 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2700 unsigned long flags;
2702 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2703 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2704 WREG32(R600_UVD_CTX_DATA, (v));
2705 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2709 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2711 unsigned long flags;
2714 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2715 WREG32(CIK_DIDT_IND_INDEX, (reg));
2716 r = RREG32(CIK_DIDT_IND_DATA);
2717 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2721 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2723 unsigned long flags;
2725 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2726 WREG32(CIK_DIDT_IND_INDEX, (reg));
2727 WREG32(CIK_DIDT_IND_DATA, (v));
2728 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2731 void r100_pll_errata_after_index(struct radeon_device *rdev);
2737 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2738 (rdev->pdev->device == 0x5969))
2739 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2740 (rdev->family == CHIP_RV200) || \
2741 (rdev->family == CHIP_RS100) || \
2742 (rdev->family == CHIP_RS200) || \
2743 (rdev->family == CHIP_RV250) || \
2744 (rdev->family == CHIP_RV280) || \
2745 (rdev->family == CHIP_RS300))
2746 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2747 (rdev->family == CHIP_RV350) || \
2748 (rdev->family == CHIP_R350) || \
2749 (rdev->family == CHIP_RV380) || \
2750 (rdev->family == CHIP_R420) || \
2751 (rdev->family == CHIP_R423) || \
2752 (rdev->family == CHIP_RV410) || \
2753 (rdev->family == CHIP_RS400) || \
2754 (rdev->family == CHIP_RS480))
2755 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2756 (rdev->ddev->pdev->device == 0x9443) || \
2757 (rdev->ddev->pdev->device == 0x944B) || \
2758 (rdev->ddev->pdev->device == 0x9506) || \
2759 (rdev->ddev->pdev->device == 0x9509) || \
2760 (rdev->ddev->pdev->device == 0x950F) || \
2761 (rdev->ddev->pdev->device == 0x689C) || \
2762 (rdev->ddev->pdev->device == 0x689D))
2763 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2764 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2765 (rdev->family == CHIP_RS690) || \
2766 (rdev->family == CHIP_RS740) || \
2767 (rdev->family >= CHIP_R600))
2768 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2769 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2770 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2771 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2772 (rdev->flags & RADEON_IS_IGP))
2773 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2774 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2775 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2776 (rdev->flags & RADEON_IS_IGP))
2777 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2778 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2779 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2780 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2781 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2782 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2783 (rdev->family == CHIP_MULLINS))
2785 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2786 (rdev->ddev->pdev->device == 0x6850) || \
2787 (rdev->ddev->pdev->device == 0x6858) || \
2788 (rdev->ddev->pdev->device == 0x6859) || \
2789 (rdev->ddev->pdev->device == 0x6840) || \
2790 (rdev->ddev->pdev->device == 0x6841) || \
2791 (rdev->ddev->pdev->device == 0x6842) || \
2792 (rdev->ddev->pdev->device == 0x6843))
2797 #define RBIOS8(i) (rdev->bios[i])
2798 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2799 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2801 int radeon_combios_init(struct radeon_device *rdev);
2802 void radeon_combios_fini(struct radeon_device *rdev);
2803 int radeon_atombios_init(struct radeon_device *rdev);
2804 void radeon_atombios_fini(struct radeon_device *rdev);
2812 * radeon_ring_write - write a value to the ring
2814 * @ring: radeon_ring structure holding ring information
2815 * @v: dword (dw) value to write
2817 * Write a value to the requested ring buffer (all asics).
2819 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2821 if (ring->count_dw <= 0)
2822 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2824 ring->ring[ring->wptr++] = v;
2825 ring->wptr &= ring->ptr_mask;
2827 ring->ring_free_dw--;
2833 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2834 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2835 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2836 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2837 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2838 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2839 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2840 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2841 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2842 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2843 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2844 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2845 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2846 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2847 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2848 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2849 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2850 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2851 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2852 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2853 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2854 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2855 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2856 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2857 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2858 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2859 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2860 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2861 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2862 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2863 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2864 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2865 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2866 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2867 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2868 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2869 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2870 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2871 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2872 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2873 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2874 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2875 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2876 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2877 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2878 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2879 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2880 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2881 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2882 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2883 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2884 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2885 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2886 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2887 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2888 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2889 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2890 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2891 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2892 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2893 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2894 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2895 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2896 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2897 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2898 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2899 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2900 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2901 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2902 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2903 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2904 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2905 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2906 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2907 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2908 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2909 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2910 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2911 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2912 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2913 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2914 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2915 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2916 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2917 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2918 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2919 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2921 /* Common functions */
2923 extern int radeon_gpu_reset(struct radeon_device *rdev);
2924 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2925 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2926 extern void radeon_agp_disable(struct radeon_device *rdev);
2927 extern int radeon_modeset_init(struct radeon_device *rdev);
2928 extern void radeon_modeset_fini(struct radeon_device *rdev);
2929 extern bool radeon_card_posted(struct radeon_device *rdev);
2930 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2931 extern void radeon_update_display_priority(struct radeon_device *rdev);
2932 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2933 extern void radeon_scratch_init(struct radeon_device *rdev);
2934 extern void radeon_wb_fini(struct radeon_device *rdev);
2935 extern int radeon_wb_init(struct radeon_device *rdev);
2936 extern void radeon_wb_disable(struct radeon_device *rdev);
2937 extern void radeon_surface_init(struct radeon_device *rdev);
2938 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2939 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2940 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2941 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2942 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2943 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2945 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2946 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2947 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2948 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2949 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2950 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2951 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2952 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2953 const u32 *registers,
2954 const u32 array_size);
2959 int radeon_vm_manager_init(struct radeon_device *rdev);
2960 void radeon_vm_manager_fini(struct radeon_device *rdev);
2961 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2962 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2963 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2964 struct radeon_vm *vm,
2965 struct list_head *head);
2966 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2967 struct radeon_vm *vm, int ring);
2968 void radeon_vm_flush(struct radeon_device *rdev,
2969 struct radeon_vm *vm,
2971 void radeon_vm_fence(struct radeon_device *rdev,
2972 struct radeon_vm *vm,
2973 struct radeon_fence *fence);
2974 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2975 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2976 struct radeon_vm *vm);
2977 int radeon_vm_clear_freed(struct radeon_device *rdev,
2978 struct radeon_vm *vm);
2979 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2980 struct radeon_vm *vm);
2981 int radeon_vm_bo_update(struct radeon_device *rdev,
2982 struct radeon_bo_va *bo_va,
2983 struct ttm_mem_reg *mem);
2984 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2985 struct radeon_bo *bo);
2986 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2987 struct radeon_bo *bo);
2988 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2989 struct radeon_vm *vm,
2990 struct radeon_bo *bo);
2991 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2992 struct radeon_bo_va *bo_va,
2995 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2996 struct radeon_bo_va *bo_va);
2999 void r600_audio_update_hdmi(struct work_struct *work);
3000 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3001 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
3002 void r600_audio_enable(struct radeon_device *rdev,
3003 struct r600_audio_pin *pin,
3005 void dce6_audio_enable(struct radeon_device *rdev,
3006 struct r600_audio_pin *pin,
3010 * R600 vram scratch functions
3012 int r600_vram_scratch_init(struct radeon_device *rdev);
3013 void r600_vram_scratch_fini(struct radeon_device *rdev);
3016 * r600 cs checking helper
3018 unsigned r600_mip_minify(unsigned size, unsigned level);
3019 bool r600_fmt_is_valid_color(u32 format);
3020 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3021 int r600_fmt_get_blocksize(u32 format);
3022 int r600_fmt_get_nblocksx(u32 format, u32 w);
3023 int r600_fmt_get_nblocksy(u32 format, u32 h);
3026 * r600 functions used by radeon_encoder.c
3028 struct radeon_hdmi_acr {
3042 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3044 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3045 u32 tiling_pipe_num,
3047 u32 total_max_rb_num,
3048 u32 enabled_rb_mask);
3051 * evergreen functions used by radeon_encoder.c
3054 extern int ni_init_microcode(struct radeon_device *rdev);
3055 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3058 #if defined(CONFIG_ACPI)
3059 extern int radeon_acpi_init(struct radeon_device *rdev);
3060 extern void radeon_acpi_fini(struct radeon_device *rdev);
3061 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3062 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3063 u8 perf_req, bool advertise);
3064 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3066 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3067 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3070 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3071 struct radeon_cs_packet *pkt,
3073 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3074 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3075 struct radeon_cs_packet *pkt);
3076 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3077 struct radeon_cs_reloc **cs_reloc,
3079 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3080 uint32_t *vline_start_end,
3081 uint32_t *vline_status);
3083 #include "radeon_object.h"