2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 /* RADEON_IB_POOL_SIZE must be a power of 2 */
101 #define RADEON_IB_POOL_SIZE 16
102 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
103 #define RADEONFB_CONN_LIMIT 4
104 #define RADEON_BIOS_NUM_SCRATCH 8
107 * Errata workarounds.
109 enum radeon_pll_errata {
110 CHIP_ERRATA_R300_CG = 0x00000001,
111 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
112 CHIP_ERRATA_PLL_DELAY = 0x00000004
116 struct radeon_device;
122 #define ATRM_BIOS_PAGE 4096
124 #if defined(CONFIG_VGA_SWITCHEROO)
125 bool radeon_atrm_supported(struct pci_dev *pdev);
126 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
128 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 bool radeon_get_bios(struct radeon_device *rdev);
143 struct radeon_dummy_page {
147 int radeon_dummy_page_init(struct radeon_device *rdev);
148 void radeon_dummy_page_fini(struct radeon_device *rdev);
154 struct radeon_clock {
155 struct radeon_pll p1pll;
156 struct radeon_pll p2pll;
157 struct radeon_pll dcpll;
158 struct radeon_pll spll;
159 struct radeon_pll mpll;
161 uint32_t default_mclk;
162 uint32_t default_sclk;
163 uint32_t default_dispclk;
170 int radeon_pm_init(struct radeon_device *rdev);
171 void radeon_pm_fini(struct radeon_device *rdev);
172 void radeon_pm_compute_clocks(struct radeon_device *rdev);
173 void radeon_combios_get_power_modes(struct radeon_device *rdev);
174 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 struct radeon_fence_driver {
180 uint32_t scratch_reg;
183 unsigned long count_timeout;
184 wait_queue_head_t queue;
186 struct list_head created;
187 struct list_head emited;
188 struct list_head signaled;
192 struct radeon_fence {
193 struct radeon_device *rdev;
195 struct list_head list;
196 /* protected by radeon_fence.lock */
198 unsigned long timeout;
203 int radeon_fence_driver_init(struct radeon_device *rdev);
204 void radeon_fence_driver_fini(struct radeon_device *rdev);
205 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
206 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
207 void radeon_fence_process(struct radeon_device *rdev);
208 bool radeon_fence_signaled(struct radeon_fence *fence);
209 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
210 int radeon_fence_wait_next(struct radeon_device *rdev);
211 int radeon_fence_wait_last(struct radeon_device *rdev);
212 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
213 void radeon_fence_unref(struct radeon_fence **fence);
218 struct radeon_surface_reg {
219 struct radeon_bo *bo;
222 #define RADEON_GEM_MAX_SURFACES 8
228 struct ttm_bo_global_ref bo_global_ref;
229 struct ttm_global_reference mem_global_ref;
230 struct ttm_bo_device bdev;
231 bool mem_global_referenced;
236 /* Protected by gem.mutex */
237 struct list_head list;
238 /* Protected by tbo.reserved */
240 struct ttm_placement placement;
241 struct ttm_buffer_object tbo;
242 struct ttm_bo_kmap_obj kmap;
248 /* Constant after initialization */
249 struct radeon_device *rdev;
250 struct drm_gem_object *gobj;
253 struct radeon_bo_list {
254 struct list_head list;
255 struct radeon_bo *bo;
267 struct list_head objects;
270 int radeon_gem_init(struct radeon_device *rdev);
271 void radeon_gem_fini(struct radeon_device *rdev);
272 int radeon_gem_object_create(struct radeon_device *rdev, int size,
273 int alignment, int initial_domain,
274 bool discardable, bool kernel,
275 struct drm_gem_object **obj);
276 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
278 void radeon_gem_object_unpin(struct drm_gem_object *obj);
282 * GART structures, functions & helpers
286 struct radeon_gart_table_ram {
287 volatile uint32_t *ptr;
290 struct radeon_gart_table_vram {
291 struct radeon_bo *robj;
292 volatile uint32_t *ptr;
295 union radeon_gart_table {
296 struct radeon_gart_table_ram ram;
297 struct radeon_gart_table_vram vram;
300 #define RADEON_GPU_PAGE_SIZE 4096
301 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
304 dma_addr_t table_addr;
305 unsigned num_gpu_pages;
306 unsigned num_cpu_pages;
308 union radeon_gart_table table;
310 dma_addr_t *pages_addr;
314 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
315 void radeon_gart_table_ram_free(struct radeon_device *rdev);
316 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
317 void radeon_gart_table_vram_free(struct radeon_device *rdev);
318 int radeon_gart_init(struct radeon_device *rdev);
319 void radeon_gart_fini(struct radeon_device *rdev);
320 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
322 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
323 int pages, struct page **pagelist);
327 * GPU MC structures, functions & helpers
330 resource_size_t aper_size;
331 resource_size_t aper_base;
332 resource_size_t agp_base;
333 /* for some chips with <= 32MB we need to lie
334 * about vram size near mc fb location */
336 u64 visible_vram_size;
346 bool igp_sideport_enabled;
349 bool radeon_combios_sideport_present(struct radeon_device *rdev);
350 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
353 * GPU scratch registers structures, functions & helpers
355 struct radeon_scratch {
361 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
362 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
371 /* FIXME: use a define max crtc rather than hardcode it */
372 bool crtc_vblank_int[2];
373 wait_queue_head_t vblank_queue;
374 /* FIXME: use defines for max hpd/dacs */
380 int radeon_irq_kms_init(struct radeon_device *rdev);
381 void radeon_irq_kms_fini(struct radeon_device *rdev);
382 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
383 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
389 struct list_head list;
392 struct radeon_fence *fence;
400 * mutex protects scheduled_ibs, ready, alloc_bm
402 struct radeon_ib_pool {
404 struct radeon_bo *robj;
405 struct list_head bogus_ib;
406 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
412 struct radeon_bo *ring_obj;
413 volatile uint32_t *ring;
418 unsigned ring_free_dw;
431 struct radeon_bo *ring_obj;
432 volatile uint32_t *ring;
445 struct radeon_bo *shader_obj;
447 u32 vs_offset, ps_offset;
450 u32 vb_used, vb_total;
451 struct radeon_ib *vb_ib;
454 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
455 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
456 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
457 int radeon_ib_pool_init(struct radeon_device *rdev);
458 void radeon_ib_pool_fini(struct radeon_device *rdev);
459 int radeon_ib_test(struct radeon_device *rdev);
460 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
461 /* Ring access between begin & end cannot sleep */
462 void radeon_ring_free_size(struct radeon_device *rdev);
463 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
464 void radeon_ring_unlock_commit(struct radeon_device *rdev);
465 void radeon_ring_unlock_undo(struct radeon_device *rdev);
466 int radeon_ring_test(struct radeon_device *rdev);
467 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
468 void radeon_ring_fini(struct radeon_device *rdev);
474 struct radeon_cs_reloc {
475 struct drm_gem_object *gobj;
476 struct radeon_bo *robj;
477 struct radeon_bo_list lobj;
482 struct radeon_cs_chunk {
488 void __user *user_ptr;
489 int last_copied_page;
493 struct radeon_cs_parser {
495 struct radeon_device *rdev;
496 struct drm_file *filp;
499 struct radeon_cs_chunk *chunks;
500 uint64_t *chunks_array;
505 struct radeon_cs_reloc *relocs;
506 struct radeon_cs_reloc **relocs_ptr;
507 struct list_head validated;
508 /* indices of various chunks */
510 int chunk_relocs_idx;
511 struct radeon_ib *ib;
517 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
518 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
521 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
523 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
524 u32 pg_idx, pg_offset;
528 pg_idx = (idx * 4) / PAGE_SIZE;
529 pg_offset = (idx * 4) % PAGE_SIZE;
531 if (ibc->kpage_idx[0] == pg_idx)
532 return ibc->kpage[0][pg_offset/4];
533 if (ibc->kpage_idx[1] == pg_idx)
534 return ibc->kpage[1][pg_offset/4];
536 new_page = radeon_cs_update_pages(p, pg_idx);
538 p->parser_error = new_page;
542 idx_value = ibc->kpage[new_page][pg_offset/4];
546 struct radeon_cs_packet {
555 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
556 struct radeon_cs_packet *pkt,
557 unsigned idx, unsigned reg);
558 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
559 struct radeon_cs_packet *pkt);
565 int radeon_agp_init(struct radeon_device *rdev);
566 void radeon_agp_resume(struct radeon_device *rdev);
567 void radeon_agp_fini(struct radeon_device *rdev);
574 struct radeon_bo *wb_obj;
575 volatile uint32_t *wb;
580 * struct radeon_pm - power management datas
581 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
582 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
583 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
584 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
585 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
586 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
587 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
588 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
589 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
590 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
591 * @needed_bandwidth: current bandwidth needs
593 * It keeps track of various data needed to take powermanagement decision.
594 * Bandwith need is used to determine minimun clock of the GPU and memory.
595 * Equation between gpu/memory clock and available bandwidth is hw dependent
596 * (type of memory, bus size, efficiency, ...)
598 enum radeon_pm_state {
604 enum radeon_pm_action {
611 enum radeon_voltage_type {
618 enum radeon_pm_state_type {
619 POWER_STATE_TYPE_DEFAULT,
620 POWER_STATE_TYPE_POWERSAVE,
621 POWER_STATE_TYPE_BATTERY,
622 POWER_STATE_TYPE_BALANCED,
623 POWER_STATE_TYPE_PERFORMANCE,
626 enum radeon_pm_clock_mode_type {
627 POWER_MODE_TYPE_DEFAULT,
630 POWER_MODE_TYPE_HIGH,
633 struct radeon_voltage {
634 enum radeon_voltage_type type;
636 struct radeon_gpio_rec gpio;
637 u32 delay; /* delay in usec from voltage drop to sclk change */
638 bool active_high; /* voltage drop is active when bit is high */
640 u8 vddc_id; /* index into vddc voltage table */
641 u8 vddci_id; /* index into vddci voltage table */
647 struct radeon_pm_non_clock_info {
650 /* standardized non-clock flags */
654 struct radeon_pm_clock_info {
660 struct radeon_voltage voltage;
661 /* standardized clock flags - not sure we'll need these */
665 struct radeon_power_state {
666 enum radeon_pm_state_type type;
667 /* XXX: use a define for num clock modes */
668 struct radeon_pm_clock_info clock_info[8];
669 /* number of valid clock modes in this power state */
671 struct radeon_pm_clock_info *default_clock_mode;
672 /* non clock info about this state */
673 struct radeon_pm_non_clock_info non_clock_info;
674 bool voltage_drop_active;
678 * Some modes are overclocked by very low value, accept them
680 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
684 struct delayed_work idle_work;
685 enum radeon_pm_state state;
686 enum radeon_pm_action planned_action;
687 unsigned long action_timeout;
692 fixed20_12 max_bandwidth;
693 fixed20_12 igp_sideport_mclk;
694 fixed20_12 igp_system_mclk;
695 fixed20_12 igp_ht_link_clk;
696 fixed20_12 igp_ht_link_width;
697 fixed20_12 k8_bandwidth;
698 fixed20_12 sideport_bandwidth;
699 fixed20_12 ht_bandwidth;
700 fixed20_12 core_bandwidth;
703 fixed20_12 needed_bandwidth;
704 /* XXX: use a define for num power modes */
705 struct radeon_power_state power_state[8];
706 /* number of valid power states */
707 int num_power_states;
708 struct radeon_power_state *current_power_state;
709 struct radeon_pm_clock_info *current_clock_mode;
710 struct radeon_power_state *requested_power_state;
711 struct radeon_pm_clock_info *requested_clock_mode;
712 struct radeon_power_state *default_power_state;
713 struct radeon_i2c_chan *i2c_bus;
720 void radeon_benchmark(struct radeon_device *rdev);
726 void radeon_test_moves(struct radeon_device *rdev);
732 int radeon_debugfs_add_files(struct radeon_device *rdev,
733 struct drm_info_list *files,
735 int radeon_debugfs_fence_init(struct radeon_device *rdev);
739 * ASIC specific functions.
742 int (*init)(struct radeon_device *rdev);
743 void (*fini)(struct radeon_device *rdev);
744 int (*resume)(struct radeon_device *rdev);
745 int (*suspend)(struct radeon_device *rdev);
746 void (*vga_set_state)(struct radeon_device *rdev, bool state);
747 int (*gpu_reset)(struct radeon_device *rdev);
748 void (*gart_tlb_flush)(struct radeon_device *rdev);
749 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
750 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
751 void (*cp_fini)(struct radeon_device *rdev);
752 void (*cp_disable)(struct radeon_device *rdev);
753 void (*cp_commit)(struct radeon_device *rdev);
754 void (*ring_start)(struct radeon_device *rdev);
755 int (*ring_test)(struct radeon_device *rdev);
756 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
757 int (*irq_set)(struct radeon_device *rdev);
758 int (*irq_process)(struct radeon_device *rdev);
759 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
760 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
761 int (*cs_parse)(struct radeon_cs_parser *p);
762 int (*copy_blit)(struct radeon_device *rdev,
766 struct radeon_fence *fence);
767 int (*copy_dma)(struct radeon_device *rdev,
771 struct radeon_fence *fence);
772 int (*copy)(struct radeon_device *rdev,
776 struct radeon_fence *fence);
777 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
778 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
779 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
780 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
781 int (*get_pcie_lanes)(struct radeon_device *rdev);
782 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
783 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
784 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
785 uint32_t tiling_flags, uint32_t pitch,
786 uint32_t offset, uint32_t obj_size);
787 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
788 void (*bandwidth_update)(struct radeon_device *rdev);
789 void (*hpd_init)(struct radeon_device *rdev);
790 void (*hpd_fini)(struct radeon_device *rdev);
791 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
792 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
793 /* ioctl hw specific callback. Some hw might want to perform special
794 * operation on specific ioctl. For instance on wait idle some hw
795 * might want to perform and HDP flush through MMIO as it seems that
796 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
799 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
806 const unsigned *reg_safe_bm;
807 unsigned reg_safe_bm_size;
812 const unsigned *reg_safe_bm;
813 unsigned reg_safe_bm_size;
820 unsigned max_tile_pipes;
822 unsigned max_backends;
824 unsigned max_threads;
825 unsigned max_stack_entries;
826 unsigned max_hw_contexts;
827 unsigned max_gs_threads;
828 unsigned sx_max_export_size;
829 unsigned sx_max_export_pos_size;
830 unsigned sx_max_export_smx_size;
831 unsigned sq_num_cf_insts;
832 unsigned tiling_nbanks;
833 unsigned tiling_npipes;
834 unsigned tiling_group_size;
839 unsigned max_tile_pipes;
841 unsigned max_backends;
843 unsigned max_threads;
844 unsigned max_stack_entries;
845 unsigned max_hw_contexts;
846 unsigned max_gs_threads;
847 unsigned sx_max_export_size;
848 unsigned sx_max_export_pos_size;
849 unsigned sx_max_export_smx_size;
850 unsigned sq_num_cf_insts;
851 unsigned sx_num_of_sets;
852 unsigned sc_prim_fifo_size;
853 unsigned sc_hiz_tile_fifo_size;
854 unsigned sc_earlyz_tile_fifo_fize;
855 unsigned tiling_nbanks;
856 unsigned tiling_npipes;
857 unsigned tiling_group_size;
860 union radeon_asic_config {
861 struct r300_asic r300;
862 struct r100_asic r100;
863 struct r600_asic r600;
864 struct rv770_asic rv770;
868 * asic initizalization from radeon_asic.c
870 void radeon_agp_disable(struct radeon_device *rdev);
871 int radeon_asic_init(struct radeon_device *rdev);
877 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *filp);
879 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
880 struct drm_file *filp);
881 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
890 struct drm_file *filp);
891 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *filp);
893 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
894 struct drm_file *filp);
895 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
896 struct drm_file *filp);
897 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
898 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
899 struct drm_file *filp);
900 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *filp);
905 * Core structure, functions and helpers.
907 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
908 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
910 struct radeon_device {
912 struct drm_device *ddev;
913 struct pci_dev *pdev;
915 union radeon_asic_config config;
916 enum radeon_family family;
919 enum radeon_pll_errata pll_errata;
926 uint16_t bios_header_start;
927 struct radeon_bo *stollen_vga_memory;
928 struct fb_info *fbdev_info;
929 struct radeon_bo *fbdev_rbo;
930 struct radeon_framebuffer *fbdev_rfb;
932 resource_size_t rmmio_base;
933 resource_size_t rmmio_size;
935 radeon_rreg_t mc_rreg;
936 radeon_wreg_t mc_wreg;
937 radeon_rreg_t pll_rreg;
938 radeon_wreg_t pll_wreg;
939 uint32_t pcie_reg_mask;
940 radeon_rreg_t pciep_rreg;
941 radeon_wreg_t pciep_wreg;
942 struct radeon_clock clock;
944 struct radeon_gart gart;
945 struct radeon_mode_info mode_info;
946 struct radeon_scratch scratch;
947 struct radeon_mman mman;
948 struct radeon_fence_driver fence_drv;
950 struct radeon_ib_pool ib_pool;
951 struct radeon_irq irq;
952 struct radeon_asic *asic;
953 struct radeon_gem gem;
955 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
956 struct mutex cs_mutex;
958 struct radeon_dummy_page dummy_page;
964 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
965 const struct firmware *me_fw; /* all family ME firmware */
966 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
967 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
968 struct r600_blit r600_blit;
969 int msi_enabled; /* msi enabled */
970 struct r600_ih ih; /* r6/700 interrupt ring */
971 struct workqueue_struct *wq;
972 struct work_struct hotplug_work;
973 int num_crtc; /* number of crtcs */
974 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
977 struct timer_list audio_timer;
980 int audio_bits_per_sample;
981 uint8_t audio_status_bits;
982 uint8_t audio_category_code;
987 int radeon_device_init(struct radeon_device *rdev,
988 struct drm_device *ddev,
989 struct pci_dev *pdev,
991 void radeon_device_fini(struct radeon_device *rdev);
992 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
995 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
996 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
997 void r600_kms_blit_copy(struct radeon_device *rdev,
998 u64 src_gpu_addr, u64 dst_gpu_addr,
1001 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1003 if (reg < rdev->rmmio_size)
1004 return readl(((void __iomem *)rdev->rmmio) + reg);
1006 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1007 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1011 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1013 if (reg < rdev->rmmio_size)
1014 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1016 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1017 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1024 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1027 * Registers read & write functions.
1029 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1030 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1031 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1032 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1033 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1034 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1035 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1036 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1037 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1038 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1039 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1040 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1041 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1042 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1043 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1044 #define WREG32_P(reg, val, mask) \
1046 uint32_t tmp_ = RREG32(reg); \
1048 tmp_ |= ((val) & ~(mask)); \
1049 WREG32(reg, tmp_); \
1051 #define WREG32_PLL_P(reg, val, mask) \
1053 uint32_t tmp_ = RREG32_PLL(reg); \
1055 tmp_ |= ((val) & ~(mask)); \
1056 WREG32_PLL(reg, tmp_); \
1058 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1061 * Indirect registers accessor
1063 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1067 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1068 r = RREG32(RADEON_PCIE_DATA);
1072 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1074 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1075 WREG32(RADEON_PCIE_DATA, (v));
1078 void r100_pll_errata_after_index(struct radeon_device *rdev);
1084 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1085 (rdev->pdev->device == 0x5969))
1086 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1087 (rdev->family == CHIP_RV200) || \
1088 (rdev->family == CHIP_RS100) || \
1089 (rdev->family == CHIP_RS200) || \
1090 (rdev->family == CHIP_RV250) || \
1091 (rdev->family == CHIP_RV280) || \
1092 (rdev->family == CHIP_RS300))
1093 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1094 (rdev->family == CHIP_RV350) || \
1095 (rdev->family == CHIP_R350) || \
1096 (rdev->family == CHIP_RV380) || \
1097 (rdev->family == CHIP_R420) || \
1098 (rdev->family == CHIP_R423) || \
1099 (rdev->family == CHIP_RV410) || \
1100 (rdev->family == CHIP_RS400) || \
1101 (rdev->family == CHIP_RS480))
1102 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1103 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1104 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1105 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1110 #define RBIOS8(i) (rdev->bios[i])
1111 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1112 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1114 int radeon_combios_init(struct radeon_device *rdev);
1115 void radeon_combios_fini(struct radeon_device *rdev);
1116 int radeon_atombios_init(struct radeon_device *rdev);
1117 void radeon_atombios_fini(struct radeon_device *rdev);
1123 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1126 if (rdev->cp.count_dw <= 0) {
1127 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1130 rdev->cp.ring[rdev->cp.wptr++] = v;
1131 rdev->cp.wptr &= rdev->cp.ptr_mask;
1132 rdev->cp.count_dw--;
1133 rdev->cp.ring_free_dw--;
1140 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1141 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1142 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1143 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1144 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1145 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1146 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1147 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1148 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1149 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1150 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1151 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1152 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1153 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1154 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1155 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1156 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1157 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1158 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1159 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1160 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1161 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1162 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1163 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1164 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1165 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1166 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1167 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1168 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1169 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1170 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1171 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1172 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1173 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1175 /* Common functions */
1177 extern void radeon_agp_disable(struct radeon_device *rdev);
1178 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1179 extern void radeon_gart_restore(struct radeon_device *rdev);
1180 extern int radeon_modeset_init(struct radeon_device *rdev);
1181 extern void radeon_modeset_fini(struct radeon_device *rdev);
1182 extern bool radeon_card_posted(struct radeon_device *rdev);
1183 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1184 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1185 extern int radeon_clocks_init(struct radeon_device *rdev);
1186 extern void radeon_clocks_fini(struct radeon_device *rdev);
1187 extern void radeon_scratch_init(struct radeon_device *rdev);
1188 extern void radeon_surface_init(struct radeon_device *rdev);
1189 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1190 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1191 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1192 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1193 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1194 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1195 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1196 extern int radeon_resume_kms(struct drm_device *dev);
1197 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1199 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1201 /* rv200,rv250,rv280 */
1202 extern void r200_set_safe_registers(struct radeon_device *rdev);
1204 /* r300,r350,rv350,rv370,rv380 */
1205 extern void r300_set_reg_safe(struct radeon_device *rdev);
1206 extern void r300_mc_program(struct radeon_device *rdev);
1207 extern void r300_mc_init(struct radeon_device *rdev);
1208 extern void r300_clock_startup(struct radeon_device *rdev);
1209 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1210 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1211 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1212 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1213 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1215 /* r420,r423,rv410 */
1216 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1217 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1218 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1219 extern void r420_pipes_init(struct radeon_device *rdev);
1222 struct rv515_mc_save {
1225 u32 vga_render_control;
1226 u32 vga_hdp_control;
1230 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1231 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1232 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1233 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1234 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1235 extern void rv515_clock_startup(struct radeon_device *rdev);
1236 extern void rv515_debugfs(struct radeon_device *rdev);
1237 extern int rv515_suspend(struct radeon_device *rdev);
1240 extern int rs400_gart_init(struct radeon_device *rdev);
1241 extern int rs400_gart_enable(struct radeon_device *rdev);
1242 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1243 extern void rs400_gart_disable(struct radeon_device *rdev);
1244 extern void rs400_gart_fini(struct radeon_device *rdev);
1247 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1248 extern int rs600_irq_set(struct radeon_device *rdev);
1249 extern void rs600_irq_disable(struct radeon_device *rdev);
1252 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1253 struct drm_display_mode *mode1,
1254 struct drm_display_mode *mode2);
1256 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1257 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1258 extern bool r600_card_posted(struct radeon_device *rdev);
1259 extern void r600_cp_stop(struct radeon_device *rdev);
1260 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1261 extern int r600_cp_resume(struct radeon_device *rdev);
1262 extern void r600_cp_fini(struct radeon_device *rdev);
1263 extern int r600_count_pipe_bits(uint32_t val);
1264 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1265 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1266 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1267 extern int r600_ib_test(struct radeon_device *rdev);
1268 extern int r600_ring_test(struct radeon_device *rdev);
1269 extern void r600_wb_fini(struct radeon_device *rdev);
1270 extern int r600_wb_enable(struct radeon_device *rdev);
1271 extern void r600_wb_disable(struct radeon_device *rdev);
1272 extern void r600_scratch_init(struct radeon_device *rdev);
1273 extern int r600_blit_init(struct radeon_device *rdev);
1274 extern void r600_blit_fini(struct radeon_device *rdev);
1275 extern int r600_init_microcode(struct radeon_device *rdev);
1276 extern int r600_gpu_reset(struct radeon_device *rdev);
1278 extern int r600_irq_init(struct radeon_device *rdev);
1279 extern void r600_irq_fini(struct radeon_device *rdev);
1280 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1281 extern int r600_irq_set(struct radeon_device *rdev);
1282 extern void r600_irq_suspend(struct radeon_device *rdev);
1284 extern int r600_audio_init(struct radeon_device *rdev);
1285 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1286 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1287 extern void r600_audio_fini(struct radeon_device *rdev);
1288 extern void r600_hdmi_init(struct drm_encoder *encoder);
1289 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1290 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1291 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1292 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1293 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1297 uint8_t status_bits,
1298 uint8_t category_code);
1301 struct evergreen_mc_save {
1303 u32 vga_render_control;
1304 u32 vga_hdp_control;
1305 u32 crtc_control[6];
1308 #include "radeon_object.h"