2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
77 #include <drm/drm_gem.h>
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121 /* RADEON_IB_POOL_SIZE must be a power of 2 */
122 #define RADEON_IB_POOL_SIZE 16
123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
124 #define RADEONFB_CONN_LIMIT 4
125 #define RADEON_BIOS_NUM_SCRATCH 8
127 /* internal ring indices */
128 /* r1xx+ has gfx CP ring */
129 #define RADEON_RING_TYPE_GFX_INDEX 0
131 /* cayman has 2 compute CP rings */
132 #define CAYMAN_RING_TYPE_CP1_INDEX 1
133 #define CAYMAN_RING_TYPE_CP2_INDEX 2
135 /* R600+ has an async dma ring */
136 #define R600_RING_TYPE_DMA_INDEX 3
137 /* cayman add a second async dma ring */
138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
141 #define R600_RING_TYPE_UVD_INDEX 5
144 #define TN_RING_TYPE_VCE1_INDEX 6
145 #define TN_RING_TYPE_VCE2_INDEX 7
147 /* max number of rings */
148 #define RADEON_NUM_RINGS 8
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
153 /* hardcode those limit for now */
154 #define RADEON_VA_IB_OFFSET (1 << 20)
155 #define RADEON_VA_RESERVED_SIZE (8 << 20)
156 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
158 /* hard reset data */
159 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
162 #define RADEON_RESET_GFX (1 << 0)
163 #define RADEON_RESET_COMPUTE (1 << 1)
164 #define RADEON_RESET_DMA (1 << 2)
165 #define RADEON_RESET_CP (1 << 3)
166 #define RADEON_RESET_GRBM (1 << 4)
167 #define RADEON_RESET_DMA1 (1 << 5)
168 #define RADEON_RESET_RLC (1 << 6)
169 #define RADEON_RESET_SEM (1 << 7)
170 #define RADEON_RESET_IH (1 << 8)
171 #define RADEON_RESET_VMC (1 << 9)
172 #define RADEON_RESET_MC (1 << 10)
173 #define RADEON_RESET_DISPLAY (1 << 11)
176 #define RADEON_CG_BLOCK_GFX (1 << 0)
177 #define RADEON_CG_BLOCK_MC (1 << 1)
178 #define RADEON_CG_BLOCK_SDMA (1 << 2)
179 #define RADEON_CG_BLOCK_UVD (1 << 3)
180 #define RADEON_CG_BLOCK_VCE (1 << 4)
181 #define RADEON_CG_BLOCK_HDP (1 << 5)
182 #define RADEON_CG_BLOCK_BIF (1 << 6)
185 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
186 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
187 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
188 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
189 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
190 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
191 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
192 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
193 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
194 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
195 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
196 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
197 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
198 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
199 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
200 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
201 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
204 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
205 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
206 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
207 #define RADEON_PG_SUPPORT_UVD (1 << 3)
208 #define RADEON_PG_SUPPORT_VCE (1 << 4)
209 #define RADEON_PG_SUPPORT_CP (1 << 5)
210 #define RADEON_PG_SUPPORT_GDS (1 << 6)
211 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
212 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
213 #define RADEON_PG_SUPPORT_ACP (1 << 9)
214 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
216 /* max cursor sizes (in pixels) */
217 #define CURSOR_WIDTH 64
218 #define CURSOR_HEIGHT 64
220 #define CIK_CURSOR_WIDTH 128
221 #define CIK_CURSOR_HEIGHT 128
224 * Errata workarounds.
226 enum radeon_pll_errata {
227 CHIP_ERRATA_R300_CG = 0x00000001,
228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
229 CHIP_ERRATA_PLL_DELAY = 0x00000004
233 struct radeon_device;
239 bool radeon_get_bios(struct radeon_device *rdev);
244 struct radeon_dummy_page {
248 int radeon_dummy_page_init(struct radeon_device *rdev);
249 void radeon_dummy_page_fini(struct radeon_device *rdev);
255 struct radeon_clock {
256 struct radeon_pll p1pll;
257 struct radeon_pll p2pll;
258 struct radeon_pll dcpll;
259 struct radeon_pll spll;
260 struct radeon_pll mpll;
262 uint32_t default_mclk;
263 uint32_t default_sclk;
264 uint32_t default_dispclk;
265 uint32_t current_dispclk;
267 uint32_t max_pixel_clock;
273 int radeon_pm_init(struct radeon_device *rdev);
274 int radeon_pm_late_init(struct radeon_device *rdev);
275 void radeon_pm_fini(struct radeon_device *rdev);
276 void radeon_pm_compute_clocks(struct radeon_device *rdev);
277 void radeon_pm_suspend(struct radeon_device *rdev);
278 void radeon_pm_resume(struct radeon_device *rdev);
279 void radeon_combios_get_power_modes(struct radeon_device *rdev);
280 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
281 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
285 struct atom_clock_dividers *dividers);
286 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
289 struct atom_mpll_param *mpll_param);
290 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
291 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
292 u16 voltage_level, u8 voltage_type,
293 u32 *gpio_value, u32 *gpio_mask);
294 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
295 u32 eng_clock, u32 mem_clock);
296 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
297 u8 voltage_type, u16 *voltage_step);
298 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
299 u16 voltage_id, u16 *voltage);
300 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
303 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
305 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
306 u16 *vddc, u16 *vddci,
307 u16 virtual_voltage_id,
308 u16 vbios_voltage_id);
309 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
310 u16 virtual_voltage_id,
312 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
317 u8 voltage_type, u16 *min_voltage);
318 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *max_voltage);
320 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
321 u8 voltage_type, u8 voltage_mode,
322 struct atom_voltage_table *voltage_table);
323 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode);
325 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
327 u8 *svd_gpio_id, u8 *svc_gpio_id);
328 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
330 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
332 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
334 struct atom_mc_reg_table *reg_table);
335 int radeon_atom_get_memory_info(struct radeon_device *rdev,
336 u8 module_index, struct atom_memory_info *mem_info);
337 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
338 bool gddr5, u8 module_index,
339 struct atom_memory_clock_range_table *mclk_range_table);
340 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
341 u16 voltage_id, u16 *voltage);
342 void rs690_pm_info(struct radeon_device *rdev);
343 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 unsigned *bankh, unsigned *mtaspect,
345 unsigned *tile_split);
350 struct radeon_fence_driver {
351 struct radeon_device *rdev;
352 uint32_t scratch_reg;
354 volatile uint32_t *cpu_addr;
355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
358 bool initialized, delayed_irq;
359 struct delayed_work lockup_work;
362 struct radeon_fence {
365 struct radeon_device *rdev;
371 wait_queue_t fence_wake;
374 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
375 int radeon_fence_driver_init(struct radeon_device *rdev);
376 void radeon_fence_driver_fini(struct radeon_device *rdev);
377 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
378 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
379 void radeon_fence_process(struct radeon_device *rdev, int ring);
380 bool radeon_fence_signaled(struct radeon_fence *fence);
381 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
382 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
383 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
384 int radeon_fence_wait_any(struct radeon_device *rdev,
385 struct radeon_fence **fences,
387 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
388 void radeon_fence_unref(struct radeon_fence **fence);
389 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
390 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
391 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
392 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
393 struct radeon_fence *b)
403 BUG_ON(a->ring != b->ring);
405 if (a->seq > b->seq) {
412 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
413 struct radeon_fence *b)
423 BUG_ON(a->ring != b->ring);
425 return a->seq < b->seq;
431 struct radeon_surface_reg {
432 struct radeon_bo *bo;
435 #define RADEON_GEM_MAX_SURFACES 8
441 struct ttm_bo_global_ref bo_global_ref;
442 struct drm_global_reference mem_global_ref;
443 struct ttm_bo_device bdev;
444 bool mem_global_referenced;
447 #if defined(CONFIG_DEBUG_FS)
453 /* bo virtual address in a specific vm */
454 struct radeon_bo_va {
455 /* protected by bo being reserved */
456 struct list_head bo_list;
461 /* protected by vm mutex */
462 struct interval_tree_node it;
463 struct list_head vm_status;
465 /* constant after initialization */
466 struct radeon_vm *vm;
467 struct radeon_bo *bo;
471 /* Protected by gem.mutex */
472 struct list_head list;
473 /* Protected by tbo.reserved */
475 struct ttm_place placements[4];
476 struct ttm_placement placement;
477 struct ttm_buffer_object tbo;
478 struct ttm_bo_kmap_obj kmap;
485 /* list of all virtual address to which this bo
489 /* Constant after initialization */
490 struct radeon_device *rdev;
491 struct drm_gem_object gem_base;
493 struct ttm_bo_kmap_obj dma_buf_vmap;
496 struct radeon_mn *mn;
497 struct interval_tree_node mn_it;
499 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
501 int radeon_gem_debugfs_init(struct radeon_device *rdev);
503 /* sub-allocation manager, it has to be protected by another lock.
504 * By conception this is an helper for other part of the driver
505 * like the indirect buffer or semaphore, which both have their
508 * Principe is simple, we keep a list of sub allocation in offset
509 * order (first entry has offset == 0, last entry has the highest
512 * When allocating new object we first check if there is room at
513 * the end total_size - (last_object_offset + last_object_size) >=
514 * alloc_size. If so we allocate new object there.
516 * When there is not enough room at the end, we start waiting for
517 * each sub object until we reach object_offset+object_size >=
518 * alloc_size, this object then become the sub object we return.
520 * Alignment can't be bigger than page size.
522 * Hole are not considered for allocation to keep things simple.
523 * Assumption is that there won't be hole (all object on same
526 struct radeon_sa_manager {
527 wait_queue_head_t wq;
528 struct radeon_bo *bo;
529 struct list_head *hole;
530 struct list_head flist[RADEON_NUM_RINGS];
531 struct list_head olist;
541 /* sub-allocation buffer */
542 struct radeon_sa_bo {
543 struct list_head olist;
544 struct list_head flist;
545 struct radeon_sa_manager *manager;
548 struct radeon_fence *fence;
556 struct list_head objects;
559 int radeon_gem_init(struct radeon_device *rdev);
560 void radeon_gem_fini(struct radeon_device *rdev);
561 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
562 int alignment, int initial_domain,
563 u32 flags, bool kernel,
564 struct drm_gem_object **obj);
566 int radeon_mode_dumb_create(struct drm_file *file_priv,
567 struct drm_device *dev,
568 struct drm_mode_create_dumb *args);
569 int radeon_mode_dumb_mmap(struct drm_file *filp,
570 struct drm_device *dev,
571 uint32_t handle, uint64_t *offset_p);
576 struct radeon_semaphore {
577 struct radeon_sa_bo *sa_bo;
582 int radeon_semaphore_create(struct radeon_device *rdev,
583 struct radeon_semaphore **semaphore);
584 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
585 struct radeon_semaphore *semaphore);
586 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
587 struct radeon_semaphore *semaphore);
588 void radeon_semaphore_free(struct radeon_device *rdev,
589 struct radeon_semaphore **semaphore,
590 struct radeon_fence *fence);
596 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
597 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
598 struct radeon_fence *last_vm_update;
601 void radeon_sync_create(struct radeon_sync *sync);
602 void radeon_sync_fence(struct radeon_sync *sync,
603 struct radeon_fence *fence);
604 int radeon_sync_resv(struct radeon_device *rdev,
605 struct radeon_sync *sync,
606 struct reservation_object *resv,
608 int radeon_sync_rings(struct radeon_device *rdev,
609 struct radeon_sync *sync,
611 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
612 struct radeon_fence *fence);
615 * GART structures, functions & helpers
619 #define RADEON_GPU_PAGE_SIZE 4096
620 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
621 #define RADEON_GPU_PAGE_SHIFT 12
622 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
624 #define RADEON_GART_PAGE_DUMMY 0
625 #define RADEON_GART_PAGE_VALID (1 << 0)
626 #define RADEON_GART_PAGE_READ (1 << 1)
627 #define RADEON_GART_PAGE_WRITE (1 << 2)
628 #define RADEON_GART_PAGE_SNOOP (1 << 3)
631 dma_addr_t table_addr;
632 struct radeon_bo *robj;
634 unsigned num_gpu_pages;
635 unsigned num_cpu_pages;
638 dma_addr_t *pages_addr;
642 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
643 void radeon_gart_table_ram_free(struct radeon_device *rdev);
644 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
645 void radeon_gart_table_vram_free(struct radeon_device *rdev);
646 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
647 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
648 int radeon_gart_init(struct radeon_device *rdev);
649 void radeon_gart_fini(struct radeon_device *rdev);
650 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
652 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
653 int pages, struct page **pagelist,
654 dma_addr_t *dma_addr, uint32_t flags);
658 * GPU MC structures, functions & helpers
661 resource_size_t aper_size;
662 resource_size_t aper_base;
663 resource_size_t agp_base;
664 /* for some chips with <= 32MB we need to lie
665 * about vram size near mc fb location */
667 u64 visible_vram_size;
677 bool igp_sideport_enabled;
682 bool radeon_combios_sideport_present(struct radeon_device *rdev);
683 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
686 * GPU scratch registers structures, functions & helpers
688 struct radeon_scratch {
695 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
696 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
699 * GPU doorbell structures, functions & helpers
701 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
703 struct radeon_doorbell {
705 resource_size_t base;
706 resource_size_t size;
708 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
709 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
712 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
713 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
714 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
715 phys_addr_t *aperture_base,
716 size_t *aperture_size,
717 size_t *start_offset);
723 struct radeon_flip_work {
724 struct work_struct flip_work;
725 struct work_struct unpin_work;
726 struct radeon_device *rdev;
729 struct drm_pending_vblank_event *event;
730 struct radeon_bo *old_rbo;
734 struct r500_irq_stat_regs {
739 struct r600_irq_stat_regs {
749 struct evergreen_irq_stat_regs {
770 struct cik_irq_stat_regs {
786 union radeon_irq_stat_regs {
787 struct r500_irq_stat_regs r500;
788 struct r600_irq_stat_regs r600;
789 struct evergreen_irq_stat_regs evergreen;
790 struct cik_irq_stat_regs cik;
796 atomic_t ring_int[RADEON_NUM_RINGS];
797 bool crtc_vblank_int[RADEON_MAX_CRTCS];
798 atomic_t pflip[RADEON_MAX_CRTCS];
799 wait_queue_head_t vblank_queue;
800 bool hpd[RADEON_MAX_HPD_PINS];
801 bool afmt[RADEON_MAX_AFMT_BLOCKS];
802 union radeon_irq_stat_regs stat_regs;
806 int radeon_irq_kms_init(struct radeon_device *rdev);
807 void radeon_irq_kms_fini(struct radeon_device *rdev);
808 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
809 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
810 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
811 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
812 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
813 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
814 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
815 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
816 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
823 struct radeon_sa_bo *sa_bo;
828 struct radeon_fence *fence;
829 struct radeon_vm *vm;
831 struct radeon_sync sync;
835 struct radeon_bo *ring_obj;
836 volatile uint32_t *ring;
838 unsigned rptr_save_reg;
839 u64 next_rptr_gpu_addr;
840 volatile u32 *next_rptr_cpu_addr;
844 unsigned ring_free_dw;
847 atomic64_t last_activity;
854 u64 last_semaphore_signal_addr;
855 u64 last_semaphore_wait_addr;
860 struct radeon_bo *mqd_obj;
866 struct radeon_bo *hpd_eop_obj;
867 u64 hpd_eop_gpu_addr;
877 /* maximum number of VMIDs */
878 #define RADEON_NUM_VM 16
880 /* number of entries in page table */
881 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
883 /* PTBs (Page Table Blocks) need to be aligned to 32K */
884 #define RADEON_VM_PTB_ALIGN_SIZE 32768
885 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
886 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
888 #define R600_PTE_VALID (1 << 0)
889 #define R600_PTE_SYSTEM (1 << 1)
890 #define R600_PTE_SNOOPED (1 << 2)
891 #define R600_PTE_READABLE (1 << 5)
892 #define R600_PTE_WRITEABLE (1 << 6)
894 /* PTE (Page Table Entry) fragment field for different page sizes */
895 #define R600_PTE_FRAG_4KB (0 << 7)
896 #define R600_PTE_FRAG_64KB (4 << 7)
897 #define R600_PTE_FRAG_256KB (6 << 7)
899 /* flags needed to be set so we can copy directly from the GART table */
900 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
901 R600_PTE_SYSTEM | R600_PTE_VALID )
903 struct radeon_vm_pt {
904 struct radeon_bo *bo;
912 /* BOs moved, but not yet updated in the PT */
913 struct list_head invalidated;
915 /* BOs freed, but not yet updated in the PT */
916 struct list_head freed;
918 /* contains the page directory */
919 struct radeon_bo *page_directory;
920 uint64_t pd_gpu_addr;
921 unsigned max_pde_used;
923 /* array of page tables, one for each page directory entry */
924 struct radeon_vm_pt *page_tables;
926 struct radeon_bo_va *ib_bo_va;
929 /* last fence for cs using this vm */
930 struct radeon_fence *fence;
931 /* last flushed PD/PT update */
932 struct radeon_fence *flushed_updates;
933 /* last use of vmid */
934 struct radeon_fence *last_id_use;
937 struct radeon_vm_manager {
938 struct radeon_fence *active[RADEON_NUM_VM];
940 /* number of VMIDs */
942 /* vram base address for page table entry */
943 u64 vram_base_offset;
946 /* for hw to save the PD addr on suspend/resume */
947 uint32_t saved_table_addr[RADEON_NUM_VM];
951 * file private structure
953 struct radeon_fpriv {
961 struct radeon_bo *ring_obj;
962 volatile uint32_t *ring;
974 #include "clearstate_defs.h"
977 /* for power gating */
978 struct radeon_bo *save_restore_obj;
979 uint64_t save_restore_gpu_addr;
980 volatile uint32_t *sr_ptr;
983 /* for clear state */
984 struct radeon_bo *clear_state_obj;
985 uint64_t clear_state_gpu_addr;
986 volatile uint32_t *cs_ptr;
987 const struct cs_section_def *cs_data;
988 u32 clear_state_size;
990 struct radeon_bo *cp_table_obj;
991 uint64_t cp_table_gpu_addr;
992 volatile uint32_t *cp_table_ptr;
996 int radeon_ib_get(struct radeon_device *rdev, int ring,
997 struct radeon_ib *ib, struct radeon_vm *vm,
999 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1000 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1001 struct radeon_ib *const_ib, bool hdp_flush);
1002 int radeon_ib_pool_init(struct radeon_device *rdev);
1003 void radeon_ib_pool_fini(struct radeon_device *rdev);
1004 int radeon_ib_ring_tests(struct radeon_device *rdev);
1005 /* Ring access between begin & end cannot sleep */
1006 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1007 struct radeon_ring *ring);
1008 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1009 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1010 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1011 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1013 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1015 void radeon_ring_undo(struct radeon_ring *ring);
1016 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1017 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1018 void radeon_ring_lockup_update(struct radeon_device *rdev,
1019 struct radeon_ring *ring);
1020 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1021 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1023 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1024 unsigned size, uint32_t *data);
1025 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1026 unsigned rptr_offs, u32 nop);
1027 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1030 /* r600 async dma */
1031 void r600_dma_stop(struct radeon_device *rdev);
1032 int r600_dma_resume(struct radeon_device *rdev);
1033 void r600_dma_fini(struct radeon_device *rdev);
1035 void cayman_dma_stop(struct radeon_device *rdev);
1036 int cayman_dma_resume(struct radeon_device *rdev);
1037 void cayman_dma_fini(struct radeon_device *rdev);
1042 struct radeon_cs_reloc {
1043 struct drm_gem_object *gobj;
1044 struct radeon_bo *robj;
1045 struct ttm_validate_buffer tv;
1046 uint64_t gpu_offset;
1047 unsigned prefered_domains;
1048 unsigned allowed_domains;
1049 uint32_t tiling_flags;
1053 struct radeon_cs_chunk {
1057 void __user *user_ptr;
1060 struct radeon_cs_parser {
1062 struct radeon_device *rdev;
1063 struct drm_file *filp;
1066 struct radeon_cs_chunk *chunks;
1067 uint64_t *chunks_array;
1072 struct radeon_cs_reloc *relocs;
1073 struct radeon_cs_reloc **relocs_ptr;
1074 struct radeon_cs_reloc *vm_bos;
1075 struct list_head validated;
1076 unsigned dma_reloc_idx;
1077 /* indices of various chunks */
1079 int chunk_relocs_idx;
1080 int chunk_flags_idx;
1081 int chunk_const_ib_idx;
1082 struct radeon_ib ib;
1083 struct radeon_ib const_ib;
1090 struct ww_acquire_ctx ticket;
1093 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1095 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1098 return ibc->kdata[idx];
1099 return p->ib.ptr[idx];
1103 struct radeon_cs_packet {
1109 unsigned one_reg_wr;
1112 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt,
1114 unsigned idx, unsigned reg);
1115 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1116 struct radeon_cs_packet *pkt);
1122 int radeon_agp_init(struct radeon_device *rdev);
1123 void radeon_agp_resume(struct radeon_device *rdev);
1124 void radeon_agp_suspend(struct radeon_device *rdev);
1125 void radeon_agp_fini(struct radeon_device *rdev);
1132 struct radeon_bo *wb_obj;
1133 volatile uint32_t *wb;
1139 #define RADEON_WB_SCRATCH_OFFSET 0
1140 #define RADEON_WB_RING0_NEXT_RPTR 256
1141 #define RADEON_WB_CP_RPTR_OFFSET 1024
1142 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1143 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1144 #define R600_WB_DMA_RPTR_OFFSET 1792
1145 #define R600_WB_IH_WPTR_OFFSET 2048
1146 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1147 #define R600_WB_EVENT_OFFSET 3072
1148 #define CIK_WB_CP1_WPTR_OFFSET 3328
1149 #define CIK_WB_CP2_WPTR_OFFSET 3584
1150 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1151 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1154 * struct radeon_pm - power management datas
1155 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1156 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1157 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1158 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1159 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1160 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1161 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1162 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1163 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1164 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1165 * @needed_bandwidth: current bandwidth needs
1167 * It keeps track of various data needed to take powermanagement decision.
1168 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1169 * Equation between gpu/memory clock and available bandwidth is hw dependent
1170 * (type of memory, bus size, efficiency, ...)
1173 enum radeon_pm_method {
1179 enum radeon_dynpm_state {
1180 DYNPM_STATE_DISABLED,
1181 DYNPM_STATE_MINIMUM,
1184 DYNPM_STATE_SUSPENDED,
1186 enum radeon_dynpm_action {
1188 DYNPM_ACTION_MINIMUM,
1189 DYNPM_ACTION_DOWNCLOCK,
1190 DYNPM_ACTION_UPCLOCK,
1191 DYNPM_ACTION_DEFAULT
1194 enum radeon_voltage_type {
1201 enum radeon_pm_state_type {
1202 /* not used for dpm */
1203 POWER_STATE_TYPE_DEFAULT,
1204 POWER_STATE_TYPE_POWERSAVE,
1205 /* user selectable states */
1206 POWER_STATE_TYPE_BATTERY,
1207 POWER_STATE_TYPE_BALANCED,
1208 POWER_STATE_TYPE_PERFORMANCE,
1209 /* internal states */
1210 POWER_STATE_TYPE_INTERNAL_UVD,
1211 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1212 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1213 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1214 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1215 POWER_STATE_TYPE_INTERNAL_BOOT,
1216 POWER_STATE_TYPE_INTERNAL_THERMAL,
1217 POWER_STATE_TYPE_INTERNAL_ACPI,
1218 POWER_STATE_TYPE_INTERNAL_ULV,
1219 POWER_STATE_TYPE_INTERNAL_3DPERF,
1222 enum radeon_pm_profile_type {
1230 #define PM_PROFILE_DEFAULT_IDX 0
1231 #define PM_PROFILE_LOW_SH_IDX 1
1232 #define PM_PROFILE_MID_SH_IDX 2
1233 #define PM_PROFILE_HIGH_SH_IDX 3
1234 #define PM_PROFILE_LOW_MH_IDX 4
1235 #define PM_PROFILE_MID_MH_IDX 5
1236 #define PM_PROFILE_HIGH_MH_IDX 6
1237 #define PM_PROFILE_MAX 7
1239 struct radeon_pm_profile {
1240 int dpms_off_ps_idx;
1242 int dpms_off_cm_idx;
1246 enum radeon_int_thermal_type {
1248 THERMAL_TYPE_EXTERNAL,
1249 THERMAL_TYPE_EXTERNAL_GPIO,
1252 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1253 THERMAL_TYPE_EVERGREEN,
1257 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1262 struct radeon_voltage {
1263 enum radeon_voltage_type type;
1265 struct radeon_gpio_rec gpio;
1266 u32 delay; /* delay in usec from voltage drop to sclk change */
1267 bool active_high; /* voltage drop is active when bit is high */
1269 u8 vddc_id; /* index into vddc voltage table */
1270 u8 vddci_id; /* index into vddci voltage table */
1274 /* evergreen+ vddci */
1278 /* clock mode flags */
1279 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1281 struct radeon_pm_clock_info {
1287 struct radeon_voltage voltage;
1288 /* standardized clock flags */
1293 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1295 struct radeon_power_state {
1296 enum radeon_pm_state_type type;
1297 struct radeon_pm_clock_info *clock_info;
1298 /* number of valid clock modes in this power state */
1299 int num_clock_modes;
1300 struct radeon_pm_clock_info *default_clock_mode;
1301 /* standardized state flags */
1303 u32 misc; /* vbios specific flags */
1304 u32 misc2; /* vbios specific flags */
1305 int pcie_lanes; /* pcie lanes */
1309 * Some modes are overclocked by very low value, accept them
1311 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1313 enum radeon_dpm_auto_throttle_src {
1314 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1315 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1318 enum radeon_dpm_event_src {
1319 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1320 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1321 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1322 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1323 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1326 #define RADEON_MAX_VCE_LEVELS 6
1328 enum radeon_vce_level {
1329 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1330 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1331 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1332 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1333 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1334 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1338 u32 caps; /* vbios flags */
1339 u32 class; /* vbios flags */
1340 u32 class2; /* vbios flags */
1348 enum radeon_vce_level vce_level;
1353 struct radeon_dpm_thermal {
1354 /* thermal interrupt work */
1355 struct work_struct work;
1356 /* low temperature threshold */
1358 /* high temperature threshold */
1360 /* was interrupt low to high or high to low */
1364 enum radeon_clk_action
1370 struct radeon_blacklist_clocks
1374 enum radeon_clk_action action;
1377 struct radeon_clock_and_voltage_limits {
1384 struct radeon_clock_array {
1389 struct radeon_clock_voltage_dependency_entry {
1394 struct radeon_clock_voltage_dependency_table {
1396 struct radeon_clock_voltage_dependency_entry *entries;
1399 union radeon_cac_leakage_entry {
1411 struct radeon_cac_leakage_table {
1413 union radeon_cac_leakage_entry *entries;
1416 struct radeon_phase_shedding_limits_entry {
1422 struct radeon_phase_shedding_limits_table {
1424 struct radeon_phase_shedding_limits_entry *entries;
1427 struct radeon_uvd_clock_voltage_dependency_entry {
1433 struct radeon_uvd_clock_voltage_dependency_table {
1435 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1438 struct radeon_vce_clock_voltage_dependency_entry {
1444 struct radeon_vce_clock_voltage_dependency_table {
1446 struct radeon_vce_clock_voltage_dependency_entry *entries;
1449 struct radeon_ppm_table {
1451 u16 cpu_core_number;
1453 u32 small_ac_platform_tdp;
1455 u32 small_ac_platform_tdc;
1462 struct radeon_cac_tdp_table {
1464 u16 configurable_tdp;
1466 u16 battery_power_limit;
1467 u16 small_power_limit;
1468 u16 low_cac_leakage;
1469 u16 high_cac_leakage;
1470 u16 maximum_power_delivery_limit;
1473 struct radeon_dpm_dynamic_state {
1474 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1475 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1476 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1477 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1478 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1479 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1480 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1481 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1482 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1483 struct radeon_clock_array valid_sclk_values;
1484 struct radeon_clock_array valid_mclk_values;
1485 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1486 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1487 u32 mclk_sclk_ratio;
1488 u32 sclk_mclk_delta;
1489 u16 vddc_vddci_delta;
1490 u16 min_vddc_for_pcie_gen2;
1491 struct radeon_cac_leakage_table cac_leakage_table;
1492 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1493 struct radeon_ppm_table *ppm_table;
1494 struct radeon_cac_tdp_table *cac_tdp_table;
1497 struct radeon_dpm_fan {
1508 u16 default_max_fan_pwm;
1509 u16 default_fan_output_sensitivity;
1510 u16 fan_output_sensitivity;
1511 bool ucode_fan_control;
1514 enum radeon_pcie_gen {
1515 RADEON_PCIE_GEN1 = 0,
1516 RADEON_PCIE_GEN2 = 1,
1517 RADEON_PCIE_GEN3 = 2,
1518 RADEON_PCIE_GEN_INVALID = 0xffff
1521 enum radeon_dpm_forced_level {
1522 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1523 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1524 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1527 struct radeon_vce_state {
1539 struct radeon_ps *ps;
1540 /* number of valid power states */
1542 /* current power state that is active */
1543 struct radeon_ps *current_ps;
1544 /* requested power state */
1545 struct radeon_ps *requested_ps;
1546 /* boot up power state */
1547 struct radeon_ps *boot_ps;
1548 /* default uvd power state */
1549 struct radeon_ps *uvd_ps;
1550 /* vce requirements */
1551 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1552 enum radeon_vce_level vce_level;
1553 enum radeon_pm_state_type state;
1554 enum radeon_pm_state_type user_state;
1556 u32 voltage_response_time;
1557 u32 backbias_response_time;
1559 u32 new_active_crtcs;
1560 int new_active_crtc_count;
1561 u32 current_active_crtcs;
1562 int current_active_crtc_count;
1563 struct radeon_dpm_dynamic_state dyn_state;
1564 struct radeon_dpm_fan fan;
1567 u32 near_tdp_limit_adjusted;
1568 u32 sq_ramping_threshold;
1572 u16 load_line_slope;
1575 /* special states active */
1576 bool thermal_active;
1579 /* thermal handling */
1580 struct radeon_dpm_thermal thermal;
1582 enum radeon_dpm_forced_level forced_level;
1583 /* track UVD streams */
1588 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1589 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1593 /* write locked while reprogramming mclk */
1594 struct rw_semaphore mclk_lock;
1596 int active_crtc_count;
1599 fixed20_12 max_bandwidth;
1600 fixed20_12 igp_sideport_mclk;
1601 fixed20_12 igp_system_mclk;
1602 fixed20_12 igp_ht_link_clk;
1603 fixed20_12 igp_ht_link_width;
1604 fixed20_12 k8_bandwidth;
1605 fixed20_12 sideport_bandwidth;
1606 fixed20_12 ht_bandwidth;
1607 fixed20_12 core_bandwidth;
1610 fixed20_12 needed_bandwidth;
1611 struct radeon_power_state *power_state;
1612 /* number of valid power states */
1613 int num_power_states;
1614 int current_power_state_index;
1615 int current_clock_mode_index;
1616 int requested_power_state_index;
1617 int requested_clock_mode_index;
1618 int default_power_state_index;
1627 struct radeon_i2c_chan *i2c_bus;
1628 /* selected pm method */
1629 enum radeon_pm_method pm_method;
1630 /* dynpm power management */
1631 struct delayed_work dynpm_idle_work;
1632 enum radeon_dynpm_state dynpm_state;
1633 enum radeon_dynpm_action dynpm_planned_action;
1634 unsigned long dynpm_action_timeout;
1635 bool dynpm_can_upclock;
1636 bool dynpm_can_downclock;
1637 /* profile-based power management */
1638 enum radeon_pm_profile_type profile;
1640 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1641 /* internal thermal controller on rv6xx+ */
1642 enum radeon_int_thermal_type int_thermal_type;
1643 struct device *int_hwmon_dev;
1644 /* fan control parameters */
1646 u8 fan_pulses_per_revolution;
1651 struct radeon_dpm dpm;
1654 int radeon_pm_get_type_index(struct radeon_device *rdev,
1655 enum radeon_pm_state_type ps_type,
1660 #define RADEON_MAX_UVD_HANDLES 10
1661 #define RADEON_UVD_STACK_SIZE (1024*1024)
1662 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1665 struct radeon_bo *vcpu_bo;
1669 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1670 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1671 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1672 struct delayed_work idle_work;
1675 int radeon_uvd_init(struct radeon_device *rdev);
1676 void radeon_uvd_fini(struct radeon_device *rdev);
1677 int radeon_uvd_suspend(struct radeon_device *rdev);
1678 int radeon_uvd_resume(struct radeon_device *rdev);
1679 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1680 uint32_t handle, struct radeon_fence **fence);
1681 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1682 uint32_t handle, struct radeon_fence **fence);
1683 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1684 uint32_t allowed_domains);
1685 void radeon_uvd_free_handles(struct radeon_device *rdev,
1686 struct drm_file *filp);
1687 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1688 void radeon_uvd_note_usage(struct radeon_device *rdev);
1689 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1690 unsigned vclk, unsigned dclk,
1691 unsigned vco_min, unsigned vco_max,
1692 unsigned fb_factor, unsigned fb_mask,
1693 unsigned pd_min, unsigned pd_max,
1695 unsigned *optimal_fb_div,
1696 unsigned *optimal_vclk_div,
1697 unsigned *optimal_dclk_div);
1698 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1699 unsigned cg_upll_func_cntl);
1704 #define RADEON_MAX_VCE_HANDLES 16
1705 #define RADEON_VCE_STACK_SIZE (1024*1024)
1706 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1709 struct radeon_bo *vcpu_bo;
1711 unsigned fw_version;
1712 unsigned fb_version;
1713 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1714 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1715 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1716 struct delayed_work idle_work;
1719 int radeon_vce_init(struct radeon_device *rdev);
1720 void radeon_vce_fini(struct radeon_device *rdev);
1721 int radeon_vce_suspend(struct radeon_device *rdev);
1722 int radeon_vce_resume(struct radeon_device *rdev);
1723 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1724 uint32_t handle, struct radeon_fence **fence);
1725 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1726 uint32_t handle, struct radeon_fence **fence);
1727 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1728 void radeon_vce_note_usage(struct radeon_device *rdev);
1729 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1730 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1731 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1732 struct radeon_ring *ring,
1733 struct radeon_semaphore *semaphore,
1735 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1736 void radeon_vce_fence_emit(struct radeon_device *rdev,
1737 struct radeon_fence *fence);
1738 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1739 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1741 struct r600_audio_pin {
1744 int bits_per_sample;
1754 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1761 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1767 void radeon_test_moves(struct radeon_device *rdev);
1768 void radeon_test_ring_sync(struct radeon_device *rdev,
1769 struct radeon_ring *cpA,
1770 struct radeon_ring *cpB);
1771 void radeon_test_syncing(struct radeon_device *rdev);
1776 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1777 void radeon_mn_unregister(struct radeon_bo *bo);
1782 struct radeon_debugfs {
1783 struct drm_info_list *files;
1787 int radeon_debugfs_add_files(struct radeon_device *rdev,
1788 struct drm_info_list *files,
1790 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1793 * ASIC ring specific functions.
1795 struct radeon_asic_ring {
1796 /* ring read/write ptr handling */
1797 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1798 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1799 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1801 /* validating and patching of IBs */
1802 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1803 int (*cs_parse)(struct radeon_cs_parser *p);
1805 /* command emmit functions */
1806 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1807 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1808 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1809 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1810 struct radeon_semaphore *semaphore, bool emit_wait);
1811 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1812 unsigned vm_id, uint64_t pd_addr);
1814 /* testing functions */
1815 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1816 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1817 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1820 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1824 * ASIC specific functions.
1826 struct radeon_asic {
1827 int (*init)(struct radeon_device *rdev);
1828 void (*fini)(struct radeon_device *rdev);
1829 int (*resume)(struct radeon_device *rdev);
1830 int (*suspend)(struct radeon_device *rdev);
1831 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1832 int (*asic_reset)(struct radeon_device *rdev);
1833 /* Flush the HDP cache via MMIO */
1834 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1835 /* check if 3D engine is idle */
1836 bool (*gui_idle)(struct radeon_device *rdev);
1837 /* wait for mc_idle */
1838 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1839 /* get the reference clock */
1840 u32 (*get_xclk)(struct radeon_device *rdev);
1841 /* get the gpu clock counter */
1842 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1845 void (*tlb_flush)(struct radeon_device *rdev);
1846 void (*set_page)(struct radeon_device *rdev, unsigned i,
1847 uint64_t addr, uint32_t flags);
1850 int (*init)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 void (*copy_pages)(struct radeon_device *rdev,
1853 struct radeon_ib *ib,
1854 uint64_t pe, uint64_t src,
1856 void (*write_pages)(struct radeon_device *rdev,
1857 struct radeon_ib *ib,
1859 uint64_t addr, unsigned count,
1860 uint32_t incr, uint32_t flags);
1861 void (*set_pages)(struct radeon_device *rdev,
1862 struct radeon_ib *ib,
1864 uint64_t addr, unsigned count,
1865 uint32_t incr, uint32_t flags);
1866 void (*pad_ib)(struct radeon_ib *ib);
1868 /* ring specific callbacks */
1869 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1872 int (*set)(struct radeon_device *rdev);
1873 int (*process)(struct radeon_device *rdev);
1877 /* display watermarks */
1878 void (*bandwidth_update)(struct radeon_device *rdev);
1879 /* get frame count */
1880 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1881 /* wait for vblank */
1882 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1883 /* set backlight level */
1884 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1885 /* get backlight level */
1886 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1887 /* audio callbacks */
1888 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1889 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1891 /* copy functions for bo handling */
1893 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1894 uint64_t src_offset,
1895 uint64_t dst_offset,
1896 unsigned num_gpu_pages,
1897 struct reservation_object *resv);
1898 u32 blit_ring_index;
1899 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1900 uint64_t src_offset,
1901 uint64_t dst_offset,
1902 unsigned num_gpu_pages,
1903 struct reservation_object *resv);
1905 /* method used for bo copy */
1906 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1907 uint64_t src_offset,
1908 uint64_t dst_offset,
1909 unsigned num_gpu_pages,
1910 struct reservation_object *resv);
1911 /* ring used for bo copies */
1912 u32 copy_ring_index;
1916 int (*set_reg)(struct radeon_device *rdev, int reg,
1917 uint32_t tiling_flags, uint32_t pitch,
1918 uint32_t offset, uint32_t obj_size);
1919 void (*clear_reg)(struct radeon_device *rdev, int reg);
1921 /* hotplug detect */
1923 void (*init)(struct radeon_device *rdev);
1924 void (*fini)(struct radeon_device *rdev);
1925 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1926 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1928 /* static power management */
1930 void (*misc)(struct radeon_device *rdev);
1931 void (*prepare)(struct radeon_device *rdev);
1932 void (*finish)(struct radeon_device *rdev);
1933 void (*init_profile)(struct radeon_device *rdev);
1934 void (*get_dynpm_state)(struct radeon_device *rdev);
1935 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1936 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1937 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1938 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1939 int (*get_pcie_lanes)(struct radeon_device *rdev);
1940 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1941 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1942 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1943 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1944 int (*get_temperature)(struct radeon_device *rdev);
1946 /* dynamic power management */
1948 int (*init)(struct radeon_device *rdev);
1949 void (*setup_asic)(struct radeon_device *rdev);
1950 int (*enable)(struct radeon_device *rdev);
1951 int (*late_enable)(struct radeon_device *rdev);
1952 void (*disable)(struct radeon_device *rdev);
1953 int (*pre_set_power_state)(struct radeon_device *rdev);
1954 int (*set_power_state)(struct radeon_device *rdev);
1955 void (*post_set_power_state)(struct radeon_device *rdev);
1956 void (*display_configuration_changed)(struct radeon_device *rdev);
1957 void (*fini)(struct radeon_device *rdev);
1958 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1959 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1960 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1961 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1962 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1963 bool (*vblank_too_short)(struct radeon_device *rdev);
1964 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1965 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1969 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1970 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1978 const unsigned *reg_safe_bm;
1979 unsigned reg_safe_bm_size;
1984 const unsigned *reg_safe_bm;
1985 unsigned reg_safe_bm_size;
1992 unsigned max_tile_pipes;
1994 unsigned max_backends;
1996 unsigned max_threads;
1997 unsigned max_stack_entries;
1998 unsigned max_hw_contexts;
1999 unsigned max_gs_threads;
2000 unsigned sx_max_export_size;
2001 unsigned sx_max_export_pos_size;
2002 unsigned sx_max_export_smx_size;
2003 unsigned sq_num_cf_insts;
2004 unsigned tiling_nbanks;
2005 unsigned tiling_npipes;
2006 unsigned tiling_group_size;
2007 unsigned tile_config;
2008 unsigned backend_map;
2009 unsigned active_simds;
2014 unsigned max_tile_pipes;
2016 unsigned max_backends;
2018 unsigned max_threads;
2019 unsigned max_stack_entries;
2020 unsigned max_hw_contexts;
2021 unsigned max_gs_threads;
2022 unsigned sx_max_export_size;
2023 unsigned sx_max_export_pos_size;
2024 unsigned sx_max_export_smx_size;
2025 unsigned sq_num_cf_insts;
2026 unsigned sx_num_of_sets;
2027 unsigned sc_prim_fifo_size;
2028 unsigned sc_hiz_tile_fifo_size;
2029 unsigned sc_earlyz_tile_fifo_fize;
2030 unsigned tiling_nbanks;
2031 unsigned tiling_npipes;
2032 unsigned tiling_group_size;
2033 unsigned tile_config;
2034 unsigned backend_map;
2035 unsigned active_simds;
2038 struct evergreen_asic {
2041 unsigned max_tile_pipes;
2043 unsigned max_backends;
2045 unsigned max_threads;
2046 unsigned max_stack_entries;
2047 unsigned max_hw_contexts;
2048 unsigned max_gs_threads;
2049 unsigned sx_max_export_size;
2050 unsigned sx_max_export_pos_size;
2051 unsigned sx_max_export_smx_size;
2052 unsigned sq_num_cf_insts;
2053 unsigned sx_num_of_sets;
2054 unsigned sc_prim_fifo_size;
2055 unsigned sc_hiz_tile_fifo_size;
2056 unsigned sc_earlyz_tile_fifo_size;
2057 unsigned tiling_nbanks;
2058 unsigned tiling_npipes;
2059 unsigned tiling_group_size;
2060 unsigned tile_config;
2061 unsigned backend_map;
2062 unsigned active_simds;
2065 struct cayman_asic {
2066 unsigned max_shader_engines;
2067 unsigned max_pipes_per_simd;
2068 unsigned max_tile_pipes;
2069 unsigned max_simds_per_se;
2070 unsigned max_backends_per_se;
2071 unsigned max_texture_channel_caches;
2073 unsigned max_threads;
2074 unsigned max_gs_threads;
2075 unsigned max_stack_entries;
2076 unsigned sx_num_of_sets;
2077 unsigned sx_max_export_size;
2078 unsigned sx_max_export_pos_size;
2079 unsigned sx_max_export_smx_size;
2080 unsigned max_hw_contexts;
2081 unsigned sq_num_cf_insts;
2082 unsigned sc_prim_fifo_size;
2083 unsigned sc_hiz_tile_fifo_size;
2084 unsigned sc_earlyz_tile_fifo_size;
2086 unsigned num_shader_engines;
2087 unsigned num_shader_pipes_per_simd;
2088 unsigned num_tile_pipes;
2089 unsigned num_simds_per_se;
2090 unsigned num_backends_per_se;
2091 unsigned backend_disable_mask_per_asic;
2092 unsigned backend_map;
2093 unsigned num_texture_channel_caches;
2094 unsigned mem_max_burst_length_bytes;
2095 unsigned mem_row_size_in_kb;
2096 unsigned shader_engine_tile_size;
2098 unsigned multi_gpu_tile_size;
2100 unsigned tile_config;
2101 unsigned active_simds;
2105 unsigned max_shader_engines;
2106 unsigned max_tile_pipes;
2107 unsigned max_cu_per_sh;
2108 unsigned max_sh_per_se;
2109 unsigned max_backends_per_se;
2110 unsigned max_texture_channel_caches;
2112 unsigned max_gs_threads;
2113 unsigned max_hw_contexts;
2114 unsigned sc_prim_fifo_size_frontend;
2115 unsigned sc_prim_fifo_size_backend;
2116 unsigned sc_hiz_tile_fifo_size;
2117 unsigned sc_earlyz_tile_fifo_size;
2119 unsigned num_tile_pipes;
2120 unsigned backend_enable_mask;
2121 unsigned backend_disable_mask_per_asic;
2122 unsigned backend_map;
2123 unsigned num_texture_channel_caches;
2124 unsigned mem_max_burst_length_bytes;
2125 unsigned mem_row_size_in_kb;
2126 unsigned shader_engine_tile_size;
2128 unsigned multi_gpu_tile_size;
2130 unsigned tile_config;
2131 uint32_t tile_mode_array[32];
2132 uint32_t active_cus;
2136 unsigned max_shader_engines;
2137 unsigned max_tile_pipes;
2138 unsigned max_cu_per_sh;
2139 unsigned max_sh_per_se;
2140 unsigned max_backends_per_se;
2141 unsigned max_texture_channel_caches;
2143 unsigned max_gs_threads;
2144 unsigned max_hw_contexts;
2145 unsigned sc_prim_fifo_size_frontend;
2146 unsigned sc_prim_fifo_size_backend;
2147 unsigned sc_hiz_tile_fifo_size;
2148 unsigned sc_earlyz_tile_fifo_size;
2150 unsigned num_tile_pipes;
2151 unsigned backend_enable_mask;
2152 unsigned backend_disable_mask_per_asic;
2153 unsigned backend_map;
2154 unsigned num_texture_channel_caches;
2155 unsigned mem_max_burst_length_bytes;
2156 unsigned mem_row_size_in_kb;
2157 unsigned shader_engine_tile_size;
2159 unsigned multi_gpu_tile_size;
2161 unsigned tile_config;
2162 uint32_t tile_mode_array[32];
2163 uint32_t macrotile_mode_array[16];
2164 uint32_t active_cus;
2167 union radeon_asic_config {
2168 struct r300_asic r300;
2169 struct r100_asic r100;
2170 struct r600_asic r600;
2171 struct rv770_asic rv770;
2172 struct evergreen_asic evergreen;
2173 struct cayman_asic cayman;
2175 struct cik_asic cik;
2179 * asic initizalization from radeon_asic.c
2181 void radeon_agp_disable(struct radeon_device *rdev);
2182 int radeon_asic_init(struct radeon_device *rdev);
2188 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2189 struct drm_file *filp);
2190 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2191 struct drm_file *filp);
2192 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2193 struct drm_file *filp);
2194 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2195 struct drm_file *file_priv);
2196 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2197 struct drm_file *file_priv);
2198 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2199 struct drm_file *file_priv);
2200 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2201 struct drm_file *file_priv);
2202 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2203 struct drm_file *filp);
2204 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2205 struct drm_file *filp);
2206 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2207 struct drm_file *filp);
2208 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2209 struct drm_file *filp);
2210 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2211 struct drm_file *filp);
2212 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2213 struct drm_file *filp);
2214 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2215 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2216 struct drm_file *filp);
2217 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *filp);
2220 /* VRAM scratch page for HDP bug, default vram page */
2221 struct r600_vram_scratch {
2222 struct radeon_bo *robj;
2223 volatile uint32_t *ptr;
2230 struct radeon_atif_notification_cfg {
2235 struct radeon_atif_notifications {
2236 bool display_switch;
2237 bool expansion_mode_change;
2239 bool forced_power_state;
2240 bool system_power_state;
2241 bool display_conf_change;
2243 bool brightness_change;
2244 bool dgpu_display_event;
2247 struct radeon_atif_functions {
2249 bool sbios_requests;
2250 bool select_active_disp;
2252 bool get_tv_standard;
2253 bool set_tv_standard;
2254 bool get_panel_expansion_mode;
2255 bool set_panel_expansion_mode;
2256 bool temperature_change;
2257 bool graphics_device_types;
2260 struct radeon_atif {
2261 struct radeon_atif_notifications notifications;
2262 struct radeon_atif_functions functions;
2263 struct radeon_atif_notification_cfg notification_cfg;
2264 struct radeon_encoder *encoder_for_bl;
2267 struct radeon_atcs_functions {
2271 bool pcie_bus_width;
2274 struct radeon_atcs {
2275 struct radeon_atcs_functions functions;
2279 * Core structure, functions and helpers.
2281 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2282 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2284 struct radeon_device {
2286 struct drm_device *ddev;
2287 struct pci_dev *pdev;
2288 struct rw_semaphore exclusive_lock;
2290 union radeon_asic_config config;
2291 enum radeon_family family;
2292 unsigned long flags;
2294 enum radeon_pll_errata pll_errata;
2301 uint16_t bios_header_start;
2302 struct radeon_bo *stollen_vga_memory;
2304 resource_size_t rmmio_base;
2305 resource_size_t rmmio_size;
2306 /* protects concurrent MM_INDEX/DATA based register access */
2307 spinlock_t mmio_idx_lock;
2308 /* protects concurrent SMC based register access */
2309 spinlock_t smc_idx_lock;
2310 /* protects concurrent PLL register access */
2311 spinlock_t pll_idx_lock;
2312 /* protects concurrent MC register access */
2313 spinlock_t mc_idx_lock;
2314 /* protects concurrent PCIE register access */
2315 spinlock_t pcie_idx_lock;
2316 /* protects concurrent PCIE_PORT register access */
2317 spinlock_t pciep_idx_lock;
2318 /* protects concurrent PIF register access */
2319 spinlock_t pif_idx_lock;
2320 /* protects concurrent CG register access */
2321 spinlock_t cg_idx_lock;
2322 /* protects concurrent UVD register access */
2323 spinlock_t uvd_idx_lock;
2324 /* protects concurrent RCU register access */
2325 spinlock_t rcu_idx_lock;
2326 /* protects concurrent DIDT register access */
2327 spinlock_t didt_idx_lock;
2328 /* protects concurrent ENDPOINT (audio) register access */
2329 spinlock_t end_idx_lock;
2330 void __iomem *rmmio;
2331 radeon_rreg_t mc_rreg;
2332 radeon_wreg_t mc_wreg;
2333 radeon_rreg_t pll_rreg;
2334 radeon_wreg_t pll_wreg;
2335 uint32_t pcie_reg_mask;
2336 radeon_rreg_t pciep_rreg;
2337 radeon_wreg_t pciep_wreg;
2339 void __iomem *rio_mem;
2340 resource_size_t rio_mem_size;
2341 struct radeon_clock clock;
2342 struct radeon_mc mc;
2343 struct radeon_gart gart;
2344 struct radeon_mode_info mode_info;
2345 struct radeon_scratch scratch;
2346 struct radeon_doorbell doorbell;
2347 struct radeon_mman mman;
2348 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2349 wait_queue_head_t fence_queue;
2350 unsigned fence_context;
2351 struct mutex ring_lock;
2352 struct radeon_ring ring[RADEON_NUM_RINGS];
2354 struct radeon_sa_manager ring_tmp_bo;
2355 struct radeon_irq irq;
2356 struct radeon_asic *asic;
2357 struct radeon_gem gem;
2358 struct radeon_pm pm;
2359 struct radeon_uvd uvd;
2360 struct radeon_vce vce;
2361 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2362 struct radeon_wb wb;
2363 struct radeon_dummy_page dummy_page;
2368 bool fastfb_working; /* IGP feature*/
2369 bool needs_reset, in_reset;
2370 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2371 const struct firmware *me_fw; /* all family ME firmware */
2372 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2373 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2374 const struct firmware *mc_fw; /* NI MC firmware */
2375 const struct firmware *ce_fw; /* SI CE firmware */
2376 const struct firmware *mec_fw; /* CIK MEC firmware */
2377 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2378 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2379 const struct firmware *smc_fw; /* SMC firmware */
2380 const struct firmware *uvd_fw; /* UVD firmware */
2381 const struct firmware *vce_fw; /* VCE firmware */
2383 struct r600_vram_scratch vram_scratch;
2384 int msi_enabled; /* msi enabled */
2385 struct r600_ih ih; /* r6/700 interrupt ring */
2386 struct radeon_rlc rlc;
2387 struct radeon_mec mec;
2388 struct work_struct hotplug_work;
2389 struct work_struct audio_work;
2390 int num_crtc; /* number of crtcs */
2391 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2393 struct r600_audio audio; /* audio stuff */
2394 struct notifier_block acpi_nb;
2395 /* only one userspace can use Hyperz features or CMASK at a time */
2396 struct drm_file *hyperz_filp;
2397 struct drm_file *cmask_filp;
2399 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2401 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2402 unsigned debugfs_count;
2403 /* virtual memory */
2404 struct radeon_vm_manager vm_manager;
2405 struct mutex gpu_clock_mutex;
2407 atomic64_t vram_usage;
2408 atomic64_t gtt_usage;
2409 atomic64_t num_bytes_moved;
2410 /* ACPI interface */
2411 struct radeon_atif atif;
2412 struct radeon_atcs atcs;
2413 /* srbm instance registers */
2414 struct mutex srbm_mutex;
2415 /* GRBM index mutex. Protects concurrents access to GRBM index */
2416 struct mutex grbm_idx_mutex;
2417 /* clock, powergating flags */
2421 struct dev_pm_domain vga_pm_domain;
2422 bool have_disp_power_ref;
2425 /* tracking pinned memory */
2429 /* amdkfd interface */
2430 struct kfd_dev *kfd;
2431 struct radeon_sa_manager kfd_bo;
2433 struct mutex mn_lock;
2434 DECLARE_HASHTABLE(mn_hash, 7);
2437 bool radeon_is_px(struct drm_device *dev);
2438 int radeon_device_init(struct radeon_device *rdev,
2439 struct drm_device *ddev,
2440 struct pci_dev *pdev,
2442 void radeon_device_fini(struct radeon_device *rdev);
2443 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2445 #define RADEON_MIN_MMIO_SIZE 0x10000
2447 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2448 bool always_indirect)
2450 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2451 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2452 return readl(((void __iomem *)rdev->rmmio) + reg);
2454 unsigned long flags;
2457 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2458 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2459 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2460 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2466 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2467 bool always_indirect)
2469 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2470 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2472 unsigned long flags;
2474 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2475 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2476 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2477 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2481 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2482 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2484 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2485 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2490 extern const struct fence_ops radeon_fence_ops;
2492 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2494 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2496 if (__f->base.ops == &radeon_fence_ops)
2503 * Registers read & write functions.
2505 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2506 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2507 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2508 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2509 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2510 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2511 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2512 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2513 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2514 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2515 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2516 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2517 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2518 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2519 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2520 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2521 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2522 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2523 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2524 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2525 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2526 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2527 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2528 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2529 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2530 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2531 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2532 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2533 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2534 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2535 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2536 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2537 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2538 #define WREG32_P(reg, val, mask) \
2540 uint32_t tmp_ = RREG32(reg); \
2542 tmp_ |= ((val) & ~(mask)); \
2543 WREG32(reg, tmp_); \
2545 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2546 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2547 #define WREG32_PLL_P(reg, val, mask) \
2549 uint32_t tmp_ = RREG32_PLL(reg); \
2551 tmp_ |= ((val) & ~(mask)); \
2552 WREG32_PLL(reg, tmp_); \
2554 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2555 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2556 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2558 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2559 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2562 * Indirect registers accessor
2564 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2566 unsigned long flags;
2569 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2570 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2571 r = RREG32(RADEON_PCIE_DATA);
2572 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2576 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2578 unsigned long flags;
2580 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2581 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2582 WREG32(RADEON_PCIE_DATA, (v));
2583 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2586 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2588 unsigned long flags;
2591 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2592 WREG32(TN_SMC_IND_INDEX_0, (reg));
2593 r = RREG32(TN_SMC_IND_DATA_0);
2594 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2598 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2600 unsigned long flags;
2602 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2603 WREG32(TN_SMC_IND_INDEX_0, (reg));
2604 WREG32(TN_SMC_IND_DATA_0, (v));
2605 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2608 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2610 unsigned long flags;
2613 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2614 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2615 r = RREG32(R600_RCU_DATA);
2616 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2620 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2622 unsigned long flags;
2624 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2625 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2626 WREG32(R600_RCU_DATA, (v));
2627 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2630 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2632 unsigned long flags;
2635 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2636 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2637 r = RREG32(EVERGREEN_CG_IND_DATA);
2638 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2642 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2644 unsigned long flags;
2646 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2647 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2648 WREG32(EVERGREEN_CG_IND_DATA, (v));
2649 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2652 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2654 unsigned long flags;
2657 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2658 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2659 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2660 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2664 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2666 unsigned long flags;
2668 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2669 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2670 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2671 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2674 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2676 unsigned long flags;
2679 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2680 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2681 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2682 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2686 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2688 unsigned long flags;
2690 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2691 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2692 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2693 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2696 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2698 unsigned long flags;
2701 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2702 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2703 r = RREG32(R600_UVD_CTX_DATA);
2704 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2708 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2710 unsigned long flags;
2712 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2713 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2714 WREG32(R600_UVD_CTX_DATA, (v));
2715 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2719 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2721 unsigned long flags;
2724 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2725 WREG32(CIK_DIDT_IND_INDEX, (reg));
2726 r = RREG32(CIK_DIDT_IND_DATA);
2727 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2731 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2733 unsigned long flags;
2735 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2736 WREG32(CIK_DIDT_IND_INDEX, (reg));
2737 WREG32(CIK_DIDT_IND_DATA, (v));
2738 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2741 void r100_pll_errata_after_index(struct radeon_device *rdev);
2747 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2748 (rdev->pdev->device == 0x5969))
2749 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2750 (rdev->family == CHIP_RV200) || \
2751 (rdev->family == CHIP_RS100) || \
2752 (rdev->family == CHIP_RS200) || \
2753 (rdev->family == CHIP_RV250) || \
2754 (rdev->family == CHIP_RV280) || \
2755 (rdev->family == CHIP_RS300))
2756 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2757 (rdev->family == CHIP_RV350) || \
2758 (rdev->family == CHIP_R350) || \
2759 (rdev->family == CHIP_RV380) || \
2760 (rdev->family == CHIP_R420) || \
2761 (rdev->family == CHIP_R423) || \
2762 (rdev->family == CHIP_RV410) || \
2763 (rdev->family == CHIP_RS400) || \
2764 (rdev->family == CHIP_RS480))
2765 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2766 (rdev->ddev->pdev->device == 0x9443) || \
2767 (rdev->ddev->pdev->device == 0x944B) || \
2768 (rdev->ddev->pdev->device == 0x9506) || \
2769 (rdev->ddev->pdev->device == 0x9509) || \
2770 (rdev->ddev->pdev->device == 0x950F) || \
2771 (rdev->ddev->pdev->device == 0x689C) || \
2772 (rdev->ddev->pdev->device == 0x689D))
2773 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2774 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2775 (rdev->family == CHIP_RS690) || \
2776 (rdev->family == CHIP_RS740) || \
2777 (rdev->family >= CHIP_R600))
2778 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2779 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2780 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2781 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2782 (rdev->flags & RADEON_IS_IGP))
2783 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2784 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2785 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2786 (rdev->flags & RADEON_IS_IGP))
2787 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2788 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2789 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2790 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2791 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2792 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2793 (rdev->family == CHIP_MULLINS))
2795 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2796 (rdev->ddev->pdev->device == 0x6850) || \
2797 (rdev->ddev->pdev->device == 0x6858) || \
2798 (rdev->ddev->pdev->device == 0x6859) || \
2799 (rdev->ddev->pdev->device == 0x6840) || \
2800 (rdev->ddev->pdev->device == 0x6841) || \
2801 (rdev->ddev->pdev->device == 0x6842) || \
2802 (rdev->ddev->pdev->device == 0x6843))
2807 #define RBIOS8(i) (rdev->bios[i])
2808 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2809 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2811 int radeon_combios_init(struct radeon_device *rdev);
2812 void radeon_combios_fini(struct radeon_device *rdev);
2813 int radeon_atombios_init(struct radeon_device *rdev);
2814 void radeon_atombios_fini(struct radeon_device *rdev);
2822 * radeon_ring_write - write a value to the ring
2824 * @ring: radeon_ring structure holding ring information
2825 * @v: dword (dw) value to write
2827 * Write a value to the requested ring buffer (all asics).
2829 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2831 if (ring->count_dw <= 0)
2832 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2834 ring->ring[ring->wptr++] = v;
2835 ring->wptr &= ring->ptr_mask;
2837 ring->ring_free_dw--;
2843 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2844 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2845 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2846 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2847 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2848 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2849 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2850 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2851 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2852 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2853 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2854 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2855 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2856 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2857 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2858 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2859 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2860 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2861 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2862 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2863 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2864 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2865 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2866 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2867 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2868 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2869 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2870 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2871 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2872 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2873 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2874 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2875 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2876 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2877 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2878 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2879 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2880 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2881 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2882 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2883 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2884 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2885 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2886 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2887 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2888 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2889 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2890 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2891 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2892 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2893 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2894 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2895 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2896 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2897 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2898 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2899 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2900 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2901 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2902 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2903 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2904 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2905 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2906 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2907 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2908 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2909 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2910 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2911 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2912 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2913 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2914 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2915 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2916 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2917 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2918 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2919 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2920 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2921 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2922 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2923 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2924 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2925 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2926 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2927 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2928 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2929 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2931 /* Common functions */
2933 extern int radeon_gpu_reset(struct radeon_device *rdev);
2934 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2935 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2936 extern void radeon_agp_disable(struct radeon_device *rdev);
2937 extern int radeon_modeset_init(struct radeon_device *rdev);
2938 extern void radeon_modeset_fini(struct radeon_device *rdev);
2939 extern bool radeon_card_posted(struct radeon_device *rdev);
2940 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2941 extern void radeon_update_display_priority(struct radeon_device *rdev);
2942 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2943 extern void radeon_scratch_init(struct radeon_device *rdev);
2944 extern void radeon_wb_fini(struct radeon_device *rdev);
2945 extern int radeon_wb_init(struct radeon_device *rdev);
2946 extern void radeon_wb_disable(struct radeon_device *rdev);
2947 extern void radeon_surface_init(struct radeon_device *rdev);
2948 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2949 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2950 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2951 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2952 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2953 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2955 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2956 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2957 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2958 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2959 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2960 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2961 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2962 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2963 const u32 *registers,
2964 const u32 array_size);
2969 int radeon_vm_manager_init(struct radeon_device *rdev);
2970 void radeon_vm_manager_fini(struct radeon_device *rdev);
2971 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2972 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2973 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2974 struct radeon_vm *vm,
2975 struct list_head *head);
2976 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2977 struct radeon_vm *vm, int ring);
2978 void radeon_vm_flush(struct radeon_device *rdev,
2979 struct radeon_vm *vm,
2980 int ring, struct radeon_fence *fence);
2981 void radeon_vm_fence(struct radeon_device *rdev,
2982 struct radeon_vm *vm,
2983 struct radeon_fence *fence);
2984 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2985 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2986 struct radeon_vm *vm);
2987 int radeon_vm_clear_freed(struct radeon_device *rdev,
2988 struct radeon_vm *vm);
2989 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2990 struct radeon_vm *vm);
2991 int radeon_vm_bo_update(struct radeon_device *rdev,
2992 struct radeon_bo_va *bo_va,
2993 struct ttm_mem_reg *mem);
2994 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2995 struct radeon_bo *bo);
2996 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2997 struct radeon_bo *bo);
2998 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2999 struct radeon_vm *vm,
3000 struct radeon_bo *bo);
3001 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3002 struct radeon_bo_va *bo_va,
3005 void radeon_vm_bo_rmv(struct radeon_device *rdev,
3006 struct radeon_bo_va *bo_va);
3009 void r600_audio_update_hdmi(struct work_struct *work);
3010 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3011 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
3012 void r600_audio_enable(struct radeon_device *rdev,
3013 struct r600_audio_pin *pin,
3015 void dce6_audio_enable(struct radeon_device *rdev,
3016 struct r600_audio_pin *pin,
3020 * R600 vram scratch functions
3022 int r600_vram_scratch_init(struct radeon_device *rdev);
3023 void r600_vram_scratch_fini(struct radeon_device *rdev);
3026 * r600 cs checking helper
3028 unsigned r600_mip_minify(unsigned size, unsigned level);
3029 bool r600_fmt_is_valid_color(u32 format);
3030 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3031 int r600_fmt_get_blocksize(u32 format);
3032 int r600_fmt_get_nblocksx(u32 format, u32 w);
3033 int r600_fmt_get_nblocksy(u32 format, u32 h);
3036 * r600 functions used by radeon_encoder.c
3038 struct radeon_hdmi_acr {
3052 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3054 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3055 u32 tiling_pipe_num,
3057 u32 total_max_rb_num,
3058 u32 enabled_rb_mask);
3061 * evergreen functions used by radeon_encoder.c
3064 extern int ni_init_microcode(struct radeon_device *rdev);
3065 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3068 #if defined(CONFIG_ACPI)
3069 extern int radeon_acpi_init(struct radeon_device *rdev);
3070 extern void radeon_acpi_fini(struct radeon_device *rdev);
3071 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3072 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3073 u8 perf_req, bool advertise);
3074 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3076 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3077 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3080 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3081 struct radeon_cs_packet *pkt,
3083 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3084 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3085 struct radeon_cs_packet *pkt);
3086 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3087 struct radeon_cs_reloc **cs_reloc,
3089 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3090 uint32_t *vline_start_end,
3091 uint32_t *vline_status);
3093 #include "radeon_object.h"