2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_dynpm;
93 extern int radeon_audio;
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 #define RADEON_IB_POOL_SIZE 16
101 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
102 #define RADEONFB_CONN_LIMIT 4
103 #define RADEON_BIOS_NUM_SCRATCH 8
106 * Errata workarounds.
108 enum radeon_pll_errata {
109 CHIP_ERRATA_R300_CG = 0x00000001,
110 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
111 CHIP_ERRATA_PLL_DELAY = 0x00000004
115 struct radeon_device;
121 bool radeon_get_bios(struct radeon_device *rdev);
127 struct radeon_dummy_page {
131 int radeon_dummy_page_init(struct radeon_device *rdev);
132 void radeon_dummy_page_fini(struct radeon_device *rdev);
138 struct radeon_clock {
139 struct radeon_pll p1pll;
140 struct radeon_pll p2pll;
141 struct radeon_pll spll;
142 struct radeon_pll mpll;
144 uint32_t default_mclk;
145 uint32_t default_sclk;
151 int radeon_pm_init(struct radeon_device *rdev);
152 void radeon_pm_compute_clocks(struct radeon_device *rdev);
157 struct radeon_fence_driver {
158 uint32_t scratch_reg;
161 unsigned long count_timeout;
162 wait_queue_head_t queue;
164 struct list_head created;
165 struct list_head emited;
166 struct list_head signaled;
170 struct radeon_fence {
171 struct radeon_device *rdev;
173 struct list_head list;
174 /* protected by radeon_fence.lock */
176 unsigned long timeout;
181 int radeon_fence_driver_init(struct radeon_device *rdev);
182 void radeon_fence_driver_fini(struct radeon_device *rdev);
183 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
184 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
185 void radeon_fence_process(struct radeon_device *rdev);
186 bool radeon_fence_signaled(struct radeon_fence *fence);
187 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
188 int radeon_fence_wait_next(struct radeon_device *rdev);
189 int radeon_fence_wait_last(struct radeon_device *rdev);
190 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
191 void radeon_fence_unref(struct radeon_fence **fence);
196 struct radeon_surface_reg {
197 struct radeon_bo *bo;
200 #define RADEON_GEM_MAX_SURFACES 8
206 struct ttm_bo_global_ref bo_global_ref;
207 struct ttm_global_reference mem_global_ref;
208 struct ttm_bo_device bdev;
209 bool mem_global_referenced;
214 /* Protected by gem.mutex */
215 struct list_head list;
216 /* Protected by tbo.reserved */
218 struct ttm_placement placement;
219 struct ttm_buffer_object tbo;
220 struct ttm_bo_kmap_obj kmap;
226 /* Constant after initialization */
227 struct radeon_device *rdev;
228 struct drm_gem_object *gobj;
231 struct radeon_bo_list {
232 struct list_head list;
233 struct radeon_bo *bo;
245 struct list_head objects;
248 int radeon_gem_init(struct radeon_device *rdev);
249 void radeon_gem_fini(struct radeon_device *rdev);
250 int radeon_gem_object_create(struct radeon_device *rdev, int size,
251 int alignment, int initial_domain,
252 bool discardable, bool kernel,
253 struct drm_gem_object **obj);
254 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
256 void radeon_gem_object_unpin(struct drm_gem_object *obj);
260 * GART structures, functions & helpers
264 struct radeon_gart_table_ram {
265 volatile uint32_t *ptr;
268 struct radeon_gart_table_vram {
269 struct radeon_bo *robj;
270 volatile uint32_t *ptr;
273 union radeon_gart_table {
274 struct radeon_gart_table_ram ram;
275 struct radeon_gart_table_vram vram;
278 #define RADEON_GPU_PAGE_SIZE 4096
281 dma_addr_t table_addr;
282 unsigned num_gpu_pages;
283 unsigned num_cpu_pages;
285 union radeon_gart_table table;
287 dma_addr_t *pages_addr;
291 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
292 void radeon_gart_table_ram_free(struct radeon_device *rdev);
293 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
294 void radeon_gart_table_vram_free(struct radeon_device *rdev);
295 int radeon_gart_init(struct radeon_device *rdev);
296 void radeon_gart_fini(struct radeon_device *rdev);
297 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
299 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
300 int pages, struct page **pagelist);
304 * GPU MC structures, functions & helpers
307 resource_size_t aper_size;
308 resource_size_t aper_base;
309 resource_size_t agp_base;
310 /* for some chips with <= 32MB we need to lie
311 * about vram size near mc fb location */
324 bool igp_sideport_enabled;
327 int radeon_mc_setup(struct radeon_device *rdev);
328 bool radeon_combios_sideport_present(struct radeon_device *rdev);
329 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
332 * GPU scratch registers structures, functions & helpers
334 struct radeon_scratch {
340 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
341 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
350 /* FIXME: use a define max crtc rather than hardcode it */
351 bool crtc_vblank_int[2];
352 /* FIXME: use defines for max hpd/dacs */
358 int radeon_irq_kms_init(struct radeon_device *rdev);
359 void radeon_irq_kms_fini(struct radeon_device *rdev);
360 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
361 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
367 struct list_head list;
370 struct radeon_fence *fence;
377 * mutex protects scheduled_ibs, ready, alloc_bm
379 struct radeon_ib_pool {
381 struct radeon_bo *robj;
382 struct list_head scheduled_ibs;
383 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
385 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
389 struct radeon_bo *ring_obj;
390 volatile uint32_t *ring;
395 unsigned ring_free_dw;
408 struct radeon_bo *ring_obj;
409 volatile uint32_t *ring;
422 struct radeon_bo *shader_obj;
424 u32 vs_offset, ps_offset;
427 u32 vb_used, vb_total;
428 struct radeon_ib *vb_ib;
431 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
432 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
433 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
434 int radeon_ib_pool_init(struct radeon_device *rdev);
435 void radeon_ib_pool_fini(struct radeon_device *rdev);
436 int radeon_ib_test(struct radeon_device *rdev);
437 /* Ring access between begin & end cannot sleep */
438 void radeon_ring_free_size(struct radeon_device *rdev);
439 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
440 void radeon_ring_unlock_commit(struct radeon_device *rdev);
441 void radeon_ring_unlock_undo(struct radeon_device *rdev);
442 int radeon_ring_test(struct radeon_device *rdev);
443 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
444 void radeon_ring_fini(struct radeon_device *rdev);
450 struct radeon_cs_reloc {
451 struct drm_gem_object *gobj;
452 struct radeon_bo *robj;
453 struct radeon_bo_list lobj;
458 struct radeon_cs_chunk {
464 void __user *user_ptr;
465 int last_copied_page;
469 struct radeon_cs_parser {
471 struct radeon_device *rdev;
472 struct drm_file *filp;
475 struct radeon_cs_chunk *chunks;
476 uint64_t *chunks_array;
481 struct radeon_cs_reloc *relocs;
482 struct radeon_cs_reloc **relocs_ptr;
483 struct list_head validated;
484 /* indices of various chunks */
486 int chunk_relocs_idx;
487 struct radeon_ib *ib;
493 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
494 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
497 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
499 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
500 u32 pg_idx, pg_offset;
504 pg_idx = (idx * 4) / PAGE_SIZE;
505 pg_offset = (idx * 4) % PAGE_SIZE;
507 if (ibc->kpage_idx[0] == pg_idx)
508 return ibc->kpage[0][pg_offset/4];
509 if (ibc->kpage_idx[1] == pg_idx)
510 return ibc->kpage[1][pg_offset/4];
512 new_page = radeon_cs_update_pages(p, pg_idx);
514 p->parser_error = new_page;
518 idx_value = ibc->kpage[new_page][pg_offset/4];
522 struct radeon_cs_packet {
531 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
532 struct radeon_cs_packet *pkt,
533 unsigned idx, unsigned reg);
534 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
535 struct radeon_cs_packet *pkt);
541 int radeon_agp_init(struct radeon_device *rdev);
542 void radeon_agp_resume(struct radeon_device *rdev);
543 void radeon_agp_fini(struct radeon_device *rdev);
550 struct radeon_bo *wb_obj;
551 volatile uint32_t *wb;
556 * struct radeon_pm - power management datas
557 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
558 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
560 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
562 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
563 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
564 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
565 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
566 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
567 * @needed_bandwidth: current bandwidth needs
569 * It keeps track of various data needed to take powermanagement decision.
570 * Bandwith need is used to determine minimun clock of the GPU and memory.
571 * Equation between gpu/memory clock and available bandwidth is hw dependent
572 * (type of memory, bus size, efficiency, ...)
574 enum radeon_pm_state {
580 enum radeon_pm_action {
588 struct work_struct reclock_work;
589 struct delayed_work idle_work;
590 enum radeon_pm_state state;
591 enum radeon_pm_action planned_action;
592 unsigned long action_timeout;
594 bool vblank_callback;
597 uint32_t min_gpu_engine_clock;
598 uint32_t min_gpu_memory_clock;
599 uint32_t min_mode_engine_clock;
600 uint32_t min_mode_memory_clock;
601 fixed20_12 max_bandwidth;
602 fixed20_12 igp_sideport_mclk;
603 fixed20_12 igp_system_mclk;
604 fixed20_12 igp_ht_link_clk;
605 fixed20_12 igp_ht_link_width;
606 fixed20_12 k8_bandwidth;
607 fixed20_12 sideport_bandwidth;
608 fixed20_12 ht_bandwidth;
609 fixed20_12 core_bandwidth;
611 fixed20_12 needed_bandwidth;
618 void radeon_benchmark(struct radeon_device *rdev);
624 void radeon_test_moves(struct radeon_device *rdev);
630 int radeon_debugfs_add_files(struct radeon_device *rdev,
631 struct drm_info_list *files,
633 int radeon_debugfs_fence_init(struct radeon_device *rdev);
634 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
635 int r100_debugfs_cp_init(struct radeon_device *rdev);
639 * ASIC specific functions.
642 int (*init)(struct radeon_device *rdev);
643 void (*fini)(struct radeon_device *rdev);
644 int (*resume)(struct radeon_device *rdev);
645 int (*suspend)(struct radeon_device *rdev);
646 void (*vga_set_state)(struct radeon_device *rdev, bool state);
647 int (*gpu_reset)(struct radeon_device *rdev);
648 void (*gart_tlb_flush)(struct radeon_device *rdev);
649 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
650 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
651 void (*cp_fini)(struct radeon_device *rdev);
652 void (*cp_disable)(struct radeon_device *rdev);
653 void (*cp_commit)(struct radeon_device *rdev);
654 void (*ring_start)(struct radeon_device *rdev);
655 int (*ring_test)(struct radeon_device *rdev);
656 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
657 int (*irq_set)(struct radeon_device *rdev);
658 int (*irq_process)(struct radeon_device *rdev);
659 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
660 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
661 int (*cs_parse)(struct radeon_cs_parser *p);
662 int (*copy_blit)(struct radeon_device *rdev,
666 struct radeon_fence *fence);
667 int (*copy_dma)(struct radeon_device *rdev,
671 struct radeon_fence *fence);
672 int (*copy)(struct radeon_device *rdev,
676 struct radeon_fence *fence);
677 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
678 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
679 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
680 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
681 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
682 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
683 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
684 uint32_t tiling_flags, uint32_t pitch,
685 uint32_t offset, uint32_t obj_size);
686 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
687 void (*bandwidth_update)(struct radeon_device *rdev);
688 void (*hpd_init)(struct radeon_device *rdev);
689 void (*hpd_fini)(struct radeon_device *rdev);
690 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
691 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
692 /* ioctl hw specific callback. Some hw might want to perform special
693 * operation on specific ioctl. For instance on wait idle some hw
694 * might want to perform and HDP flush through MMIO as it seems that
695 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
698 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
705 const unsigned *reg_safe_bm;
706 unsigned reg_safe_bm_size;
711 const unsigned *reg_safe_bm;
712 unsigned reg_safe_bm_size;
719 unsigned max_tile_pipes;
721 unsigned max_backends;
723 unsigned max_threads;
724 unsigned max_stack_entries;
725 unsigned max_hw_contexts;
726 unsigned max_gs_threads;
727 unsigned sx_max_export_size;
728 unsigned sx_max_export_pos_size;
729 unsigned sx_max_export_smx_size;
730 unsigned sq_num_cf_insts;
735 unsigned max_tile_pipes;
737 unsigned max_backends;
739 unsigned max_threads;
740 unsigned max_stack_entries;
741 unsigned max_hw_contexts;
742 unsigned max_gs_threads;
743 unsigned sx_max_export_size;
744 unsigned sx_max_export_pos_size;
745 unsigned sx_max_export_smx_size;
746 unsigned sq_num_cf_insts;
747 unsigned sx_num_of_sets;
748 unsigned sc_prim_fifo_size;
749 unsigned sc_hiz_tile_fifo_size;
750 unsigned sc_earlyz_tile_fifo_fize;
753 union radeon_asic_config {
754 struct r300_asic r300;
755 struct r100_asic r100;
756 struct r600_asic r600;
757 struct rv770_asic rv770;
764 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
765 struct drm_file *filp);
766 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
767 struct drm_file *filp);
768 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
769 struct drm_file *file_priv);
770 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
771 struct drm_file *file_priv);
772 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
773 struct drm_file *file_priv);
774 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
775 struct drm_file *file_priv);
776 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
777 struct drm_file *filp);
778 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
779 struct drm_file *filp);
780 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
781 struct drm_file *filp);
782 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
783 struct drm_file *filp);
784 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
785 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
786 struct drm_file *filp);
787 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
788 struct drm_file *filp);
792 * Core structure, functions and helpers.
794 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
795 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
797 struct radeon_device {
799 struct drm_device *ddev;
800 struct pci_dev *pdev;
802 union radeon_asic_config config;
803 enum radeon_family family;
806 enum radeon_pll_errata pll_errata;
813 uint16_t bios_header_start;
814 struct radeon_bo *stollen_vga_memory;
815 struct fb_info *fbdev_info;
816 struct radeon_bo *fbdev_rbo;
817 struct radeon_framebuffer *fbdev_rfb;
819 resource_size_t rmmio_base;
820 resource_size_t rmmio_size;
822 radeon_rreg_t mc_rreg;
823 radeon_wreg_t mc_wreg;
824 radeon_rreg_t pll_rreg;
825 radeon_wreg_t pll_wreg;
826 uint32_t pcie_reg_mask;
827 radeon_rreg_t pciep_rreg;
828 radeon_wreg_t pciep_wreg;
829 struct radeon_clock clock;
831 struct radeon_gart gart;
832 struct radeon_mode_info mode_info;
833 struct radeon_scratch scratch;
834 struct radeon_mman mman;
835 struct radeon_fence_driver fence_drv;
837 struct radeon_ib_pool ib_pool;
838 struct radeon_irq irq;
839 struct radeon_asic *asic;
840 struct radeon_gem gem;
842 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
843 struct mutex cs_mutex;
845 struct radeon_dummy_page dummy_page;
851 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
852 const struct firmware *me_fw; /* all family ME firmware */
853 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
854 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
855 struct r600_blit r600_blit;
856 int msi_enabled; /* msi enabled */
857 struct r600_ih ih; /* r6/700 interrupt ring */
858 struct workqueue_struct *wq;
859 struct work_struct hotplug_work;
860 int num_crtc; /* number of crtcs */
861 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
864 struct timer_list audio_timer;
867 int audio_bits_per_sample;
868 uint8_t audio_status_bits;
869 uint8_t audio_category_code;
872 int radeon_device_init(struct radeon_device *rdev,
873 struct drm_device *ddev,
874 struct pci_dev *pdev,
876 void radeon_device_fini(struct radeon_device *rdev);
877 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
880 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
881 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
882 void r600_kms_blit_copy(struct radeon_device *rdev,
883 u64 src_gpu_addr, u64 dst_gpu_addr,
886 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
888 if (reg < rdev->rmmio_size)
889 return readl(((void __iomem *)rdev->rmmio) + reg);
891 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
892 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
896 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
898 if (reg < rdev->rmmio_size)
899 writel(v, ((void __iomem *)rdev->rmmio) + reg);
901 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
902 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
909 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
912 * Registers read & write functions.
914 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
915 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
916 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
917 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
918 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
919 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
920 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
921 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
922 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
923 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
924 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
925 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
926 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
927 #define WREG32_P(reg, val, mask) \
929 uint32_t tmp_ = RREG32(reg); \
931 tmp_ |= ((val) & ~(mask)); \
934 #define WREG32_PLL_P(reg, val, mask) \
936 uint32_t tmp_ = RREG32_PLL(reg); \
938 tmp_ |= ((val) & ~(mask)); \
939 WREG32_PLL(reg, tmp_); \
941 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
944 * Indirect registers accessor
946 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
950 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
951 r = RREG32(RADEON_PCIE_DATA);
955 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
957 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
958 WREG32(RADEON_PCIE_DATA, (v));
961 void r100_pll_errata_after_index(struct radeon_device *rdev);
967 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
968 (rdev->pdev->device == 0x5969))
969 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
970 (rdev->family == CHIP_RV200) || \
971 (rdev->family == CHIP_RS100) || \
972 (rdev->family == CHIP_RS200) || \
973 (rdev->family == CHIP_RV250) || \
974 (rdev->family == CHIP_RV280) || \
975 (rdev->family == CHIP_RS300))
976 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
977 (rdev->family == CHIP_RV350) || \
978 (rdev->family == CHIP_R350) || \
979 (rdev->family == CHIP_RV380) || \
980 (rdev->family == CHIP_R420) || \
981 (rdev->family == CHIP_R423) || \
982 (rdev->family == CHIP_RV410) || \
983 (rdev->family == CHIP_RS400) || \
984 (rdev->family == CHIP_RS480))
985 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
986 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
987 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
993 #define RBIOS8(i) (rdev->bios[i])
994 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
995 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
997 int radeon_combios_init(struct radeon_device *rdev);
998 void radeon_combios_fini(struct radeon_device *rdev);
999 int radeon_atombios_init(struct radeon_device *rdev);
1000 void radeon_atombios_fini(struct radeon_device *rdev);
1006 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1009 if (rdev->cp.count_dw <= 0) {
1010 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1013 rdev->cp.ring[rdev->cp.wptr++] = v;
1014 rdev->cp.wptr &= rdev->cp.ptr_mask;
1015 rdev->cp.count_dw--;
1016 rdev->cp.ring_free_dw--;
1023 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1024 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1025 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1026 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1027 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1028 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1029 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
1030 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1031 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1032 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1033 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1034 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1035 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1036 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1037 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1038 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1039 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1040 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1041 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1042 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1043 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1044 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1045 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1046 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1047 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1048 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1049 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1050 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1051 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1052 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1053 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1054 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1055 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1057 /* Common functions */
1059 extern void radeon_agp_disable(struct radeon_device *rdev);
1060 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1061 extern int radeon_modeset_init(struct radeon_device *rdev);
1062 extern void radeon_modeset_fini(struct radeon_device *rdev);
1063 extern bool radeon_card_posted(struct radeon_device *rdev);
1064 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1065 extern int radeon_clocks_init(struct radeon_device *rdev);
1066 extern void radeon_clocks_fini(struct radeon_device *rdev);
1067 extern void radeon_scratch_init(struct radeon_device *rdev);
1068 extern void radeon_surface_init(struct radeon_device *rdev);
1069 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1070 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1071 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1072 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1073 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1075 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1076 struct r100_mc_save {
1084 extern void r100_cp_disable(struct radeon_device *rdev);
1085 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1086 extern void r100_cp_fini(struct radeon_device *rdev);
1087 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1088 extern int r100_pci_gart_init(struct radeon_device *rdev);
1089 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1090 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1091 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1092 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1093 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1094 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1095 extern void r100_ib_fini(struct radeon_device *rdev);
1096 extern int r100_ib_init(struct radeon_device *rdev);
1097 extern void r100_irq_disable(struct radeon_device *rdev);
1098 extern int r100_irq_set(struct radeon_device *rdev);
1099 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1100 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1101 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1102 extern void r100_wb_disable(struct radeon_device *rdev);
1103 extern void r100_wb_fini(struct radeon_device *rdev);
1104 extern int r100_wb_init(struct radeon_device *rdev);
1105 extern void r100_hdp_reset(struct radeon_device *rdev);
1106 extern int r100_rb2d_reset(struct radeon_device *rdev);
1107 extern int r100_cp_reset(struct radeon_device *rdev);
1108 extern void r100_vga_render_disable(struct radeon_device *rdev);
1109 extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1110 struct radeon_cs_packet *pkt,
1111 struct radeon_bo *robj);
1112 extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt,
1114 const unsigned *auth, unsigned n,
1115 radeon_packet0_check_t check);
1116 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt,
1119 extern void r100_enable_bm(struct radeon_device *rdev);
1120 extern void r100_set_common_regs(struct radeon_device *rdev);
1122 /* rv200,rv250,rv280 */
1123 extern void r200_set_safe_registers(struct radeon_device *rdev);
1125 /* r300,r350,rv350,rv370,rv380 */
1126 extern void r300_set_reg_safe(struct radeon_device *rdev);
1127 extern void r300_mc_program(struct radeon_device *rdev);
1128 extern void r300_vram_info(struct radeon_device *rdev);
1129 extern void r300_clock_startup(struct radeon_device *rdev);
1130 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1131 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1132 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1133 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1134 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1136 /* r420,r423,rv410 */
1137 extern int r420_mc_init(struct radeon_device *rdev);
1138 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1139 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1140 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1141 extern void r420_pipes_init(struct radeon_device *rdev);
1144 struct rv515_mc_save {
1147 u32 vga_render_control;
1148 u32 vga_hdp_control;
1152 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1153 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1154 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1155 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1156 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1157 extern void rv515_clock_startup(struct radeon_device *rdev);
1158 extern void rv515_debugfs(struct radeon_device *rdev);
1159 extern int rv515_suspend(struct radeon_device *rdev);
1162 extern int rs400_gart_init(struct radeon_device *rdev);
1163 extern int rs400_gart_enable(struct radeon_device *rdev);
1164 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1165 extern void rs400_gart_disable(struct radeon_device *rdev);
1166 extern void rs400_gart_fini(struct radeon_device *rdev);
1169 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1170 extern int rs600_irq_set(struct radeon_device *rdev);
1171 extern void rs600_irq_disable(struct radeon_device *rdev);
1174 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1175 struct drm_display_mode *mode1,
1176 struct drm_display_mode *mode2);
1178 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1179 extern bool r600_card_posted(struct radeon_device *rdev);
1180 extern void r600_cp_stop(struct radeon_device *rdev);
1181 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1182 extern int r600_cp_resume(struct radeon_device *rdev);
1183 extern void r600_cp_fini(struct radeon_device *rdev);
1184 extern int r600_count_pipe_bits(uint32_t val);
1185 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1186 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1187 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1188 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1189 extern int r600_ib_test(struct radeon_device *rdev);
1190 extern int r600_ring_test(struct radeon_device *rdev);
1191 extern void r600_wb_fini(struct radeon_device *rdev);
1192 extern int r600_wb_enable(struct radeon_device *rdev);
1193 extern void r600_wb_disable(struct radeon_device *rdev);
1194 extern void r600_scratch_init(struct radeon_device *rdev);
1195 extern int r600_blit_init(struct radeon_device *rdev);
1196 extern void r600_blit_fini(struct radeon_device *rdev);
1197 extern int r600_init_microcode(struct radeon_device *rdev);
1198 extern int r600_gpu_reset(struct radeon_device *rdev);
1200 extern int r600_irq_init(struct radeon_device *rdev);
1201 extern void r600_irq_fini(struct radeon_device *rdev);
1202 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1203 extern int r600_irq_set(struct radeon_device *rdev);
1204 extern void r600_irq_suspend(struct radeon_device *rdev);
1206 extern int r600_audio_init(struct radeon_device *rdev);
1207 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1208 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1209 extern void r600_audio_fini(struct radeon_device *rdev);
1210 extern void r600_hdmi_init(struct drm_encoder *encoder);
1211 extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1212 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1213 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1214 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1218 uint8_t status_bits,
1219 uint8_t category_code);
1221 #include "radeon_object.h"