2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_object.h"
33 /* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
47 #include <asm/atomic.h>
48 #include <linux/wait.h>
49 #include <linux/list.h>
50 #include <linux/kref.h>
52 #include "radeon_mode.h"
53 #include "radeon_reg.h"
58 extern int radeon_no_wb;
59 extern int radeon_modeset;
60 extern int radeon_dynclks;
61 extern int radeon_r4xx_atom;
62 extern int radeon_agpmode;
63 extern int radeon_vram_limit;
64 extern int radeon_gart_size;
65 extern int radeon_benchmarking;
66 extern int radeon_testing;
67 extern int radeon_connector_table;
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
74 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75 #define RADEON_IB_POOL_SIZE 16
76 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
77 #define RADEONFB_CONN_LIMIT 4
78 #define RADEON_BIOS_NUM_SCRATCH 8
123 enum radeon_chip_flags {
124 RADEON_FAMILY_MASK = 0x0000ffffUL,
125 RADEON_FLAGS_MASK = 0xffff0000UL,
126 RADEON_IS_MOBILITY = 0x00010000UL,
127 RADEON_IS_IGP = 0x00020000UL,
128 RADEON_SINGLE_CRTC = 0x00040000UL,
129 RADEON_IS_AGP = 0x00080000UL,
130 RADEON_HAS_HIERZ = 0x00100000UL,
131 RADEON_IS_PCIE = 0x00200000UL,
132 RADEON_NEW_MEMMAP = 0x00400000UL,
133 RADEON_IS_PCI = 0x00800000UL,
134 RADEON_IS_IGPGART = 0x01000000UL,
139 * Errata workarounds.
141 enum radeon_pll_errata {
142 CHIP_ERRATA_R300_CG = 0x00000001,
143 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
144 CHIP_ERRATA_PLL_DELAY = 0x00000004
148 struct radeon_device;
154 bool radeon_get_bios(struct radeon_device *rdev);
160 struct radeon_dummy_page {
164 int radeon_dummy_page_init(struct radeon_device *rdev);
165 void radeon_dummy_page_fini(struct radeon_device *rdev);
171 struct radeon_clock {
172 struct radeon_pll p1pll;
173 struct radeon_pll p2pll;
174 struct radeon_pll spll;
175 struct radeon_pll mpll;
177 uint32_t default_mclk;
178 uint32_t default_sclk;
185 struct radeon_fence_driver {
186 uint32_t scratch_reg;
189 unsigned long count_timeout;
190 wait_queue_head_t queue;
192 struct list_head created;
193 struct list_head emited;
194 struct list_head signaled;
197 struct radeon_fence {
198 struct radeon_device *rdev;
200 struct list_head list;
201 /* protected by radeon_fence.lock */
203 unsigned long timeout;
208 int radeon_fence_driver_init(struct radeon_device *rdev);
209 void radeon_fence_driver_fini(struct radeon_device *rdev);
210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
212 void radeon_fence_process(struct radeon_device *rdev);
213 bool radeon_fence_signaled(struct radeon_fence *fence);
214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
215 int radeon_fence_wait_next(struct radeon_device *rdev);
216 int radeon_fence_wait_last(struct radeon_device *rdev);
217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
218 void radeon_fence_unref(struct radeon_fence **fence);
223 struct radeon_surface_reg {
224 struct radeon_object *robj;
227 #define RADEON_GEM_MAX_SURFACES 8
232 struct radeon_object;
234 struct radeon_object_list {
235 struct list_head list;
236 struct radeon_object *robj;
240 uint32_t tiling_flags;
243 int radeon_object_init(struct radeon_device *rdev);
244 void radeon_object_fini(struct radeon_device *rdev);
245 int radeon_object_create(struct radeon_device *rdev,
246 struct drm_gem_object *gobj,
251 struct radeon_object **robj_ptr);
252 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
253 void radeon_object_kunmap(struct radeon_object *robj);
254 void radeon_object_unref(struct radeon_object **robj);
255 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
257 void radeon_object_unpin(struct radeon_object *robj);
258 int radeon_object_wait(struct radeon_object *robj);
259 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
260 int radeon_object_evict_vram(struct radeon_device *rdev);
261 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
262 void radeon_object_force_delete(struct radeon_device *rdev);
263 void radeon_object_list_add_object(struct radeon_object_list *lobj,
264 struct list_head *head);
265 int radeon_object_list_validate(struct list_head *head, void *fence);
266 void radeon_object_list_unvalidate(struct list_head *head);
267 void radeon_object_list_clean(struct list_head *head);
268 int radeon_object_fbdev_mmap(struct radeon_object *robj,
269 struct vm_area_struct *vma);
270 unsigned long radeon_object_size(struct radeon_object *robj);
271 void radeon_object_clear_surface_reg(struct radeon_object *robj);
272 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
274 void radeon_object_set_tiling_flags(struct radeon_object *robj,
275 uint32_t tiling_flags, uint32_t pitch);
276 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
277 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
278 struct ttm_mem_reg *mem);
279 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
284 struct list_head objects;
287 int radeon_gem_init(struct radeon_device *rdev);
288 void radeon_gem_fini(struct radeon_device *rdev);
289 int radeon_gem_object_create(struct radeon_device *rdev, int size,
290 int alignment, int initial_domain,
291 bool discardable, bool kernel,
293 struct drm_gem_object **obj);
294 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
296 void radeon_gem_object_unpin(struct drm_gem_object *obj);
300 * GART structures, functions & helpers
304 struct radeon_gart_table_ram {
305 volatile uint32_t *ptr;
308 struct radeon_gart_table_vram {
309 struct radeon_object *robj;
310 volatile uint32_t *ptr;
313 union radeon_gart_table {
314 struct radeon_gart_table_ram ram;
315 struct radeon_gart_table_vram vram;
319 dma_addr_t table_addr;
320 unsigned num_gpu_pages;
321 unsigned num_cpu_pages;
323 union radeon_gart_table table;
325 dma_addr_t *pages_addr;
329 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
330 void radeon_gart_table_ram_free(struct radeon_device *rdev);
331 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
332 void radeon_gart_table_vram_free(struct radeon_device *rdev);
333 int radeon_gart_init(struct radeon_device *rdev);
334 void radeon_gart_fini(struct radeon_device *rdev);
335 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
337 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
338 int pages, struct page **pagelist);
342 * GPU MC structures, functions & helpers
345 resource_size_t aper_size;
346 resource_size_t aper_base;
347 resource_size_t agp_base;
348 /* for some chips with <= 32MB we need to lie
349 * about vram size near mc fb location */
364 int radeon_mc_setup(struct radeon_device *rdev);
368 * GPU scratch registers structures, functions & helpers
370 struct radeon_scratch {
376 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
377 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
386 /* FIXME: use a define max crtc rather than hardcode it */
387 bool crtc_vblank_int[2];
390 int radeon_irq_kms_init(struct radeon_device *rdev);
391 void radeon_irq_kms_fini(struct radeon_device *rdev);
398 struct list_head list;
401 struct radeon_fence *fence;
402 volatile uint32_t *ptr;
408 * mutex protects scheduled_ibs, ready, alloc_bm
410 struct radeon_ib_pool {
412 struct radeon_object *robj;
413 struct list_head scheduled_ibs;
414 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
416 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
420 struct radeon_object *ring_obj;
421 volatile uint32_t *ring;
426 unsigned ring_free_dw;
436 struct radeon_object *shader_obj;
438 u32 vs_offset, ps_offset;
441 u32 vb_used, vb_total;
442 struct radeon_ib *vb_ib;
445 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
446 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
447 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
448 int radeon_ib_pool_init(struct radeon_device *rdev);
449 void radeon_ib_pool_fini(struct radeon_device *rdev);
450 int radeon_ib_test(struct radeon_device *rdev);
451 /* Ring access between begin & end cannot sleep */
452 void radeon_ring_free_size(struct radeon_device *rdev);
453 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
454 void radeon_ring_unlock_commit(struct radeon_device *rdev);
455 void radeon_ring_unlock_undo(struct radeon_device *rdev);
456 int radeon_ring_test(struct radeon_device *rdev);
457 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
458 void radeon_ring_fini(struct radeon_device *rdev);
464 struct radeon_cs_reloc {
465 struct drm_gem_object *gobj;
466 struct radeon_object *robj;
467 struct radeon_object_list lobj;
472 struct radeon_cs_chunk {
478 struct radeon_cs_parser {
479 struct radeon_device *rdev;
480 struct drm_file *filp;
483 struct radeon_cs_chunk *chunks;
484 uint64_t *chunks_array;
489 struct radeon_cs_reloc *relocs;
490 struct radeon_cs_reloc **relocs_ptr;
491 struct list_head validated;
492 /* indices of various chunks */
494 int chunk_relocs_idx;
495 struct radeon_ib *ib;
500 struct radeon_cs_packet {
509 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
510 struct radeon_cs_packet *pkt,
511 unsigned idx, unsigned reg);
512 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
513 struct radeon_cs_packet *pkt);
519 int radeon_agp_init(struct radeon_device *rdev);
520 void radeon_agp_fini(struct radeon_device *rdev);
527 struct radeon_object *wb_obj;
528 volatile uint32_t *wb;
533 * struct radeon_pm - power management datas
534 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
535 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
536 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
537 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
538 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
539 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
540 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
541 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
542 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
543 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
544 * @needed_bandwidth: current bandwidth needs
546 * It keeps track of various data needed to take powermanagement decision.
547 * Bandwith need is used to determine minimun clock of the GPU and memory.
548 * Equation between gpu/memory clock and available bandwidth is hw dependent
549 * (type of memory, bus size, efficiency, ...)
552 fixed20_12 max_bandwidth;
553 fixed20_12 igp_sideport_mclk;
554 fixed20_12 igp_system_mclk;
555 fixed20_12 igp_ht_link_clk;
556 fixed20_12 igp_ht_link_width;
557 fixed20_12 k8_bandwidth;
558 fixed20_12 sideport_bandwidth;
559 fixed20_12 ht_bandwidth;
560 fixed20_12 core_bandwidth;
562 fixed20_12 needed_bandwidth;
569 void radeon_benchmark(struct radeon_device *rdev);
575 void radeon_test_moves(struct radeon_device *rdev);
581 int radeon_debugfs_add_files(struct radeon_device *rdev,
582 struct drm_info_list *files,
584 int radeon_debugfs_fence_init(struct radeon_device *rdev);
585 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
586 int r100_debugfs_cp_init(struct radeon_device *rdev);
590 * ASIC specific functions.
593 int (*init)(struct radeon_device *rdev);
594 void (*fini)(struct radeon_device *rdev);
595 int (*resume)(struct radeon_device *rdev);
596 int (*suspend)(struct radeon_device *rdev);
597 void (*errata)(struct radeon_device *rdev);
598 void (*vram_info)(struct radeon_device *rdev);
599 int (*gpu_reset)(struct radeon_device *rdev);
600 int (*mc_init)(struct radeon_device *rdev);
601 void (*mc_fini)(struct radeon_device *rdev);
602 int (*wb_init)(struct radeon_device *rdev);
603 void (*wb_fini)(struct radeon_device *rdev);
604 int (*gart_init)(struct radeon_device *rdev);
605 void (*gart_fini)(struct radeon_device *rdev);
606 int (*gart_enable)(struct radeon_device *rdev);
607 void (*gart_disable)(struct radeon_device *rdev);
608 void (*gart_tlb_flush)(struct radeon_device *rdev);
609 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
610 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
611 void (*cp_fini)(struct radeon_device *rdev);
612 void (*cp_disable)(struct radeon_device *rdev);
613 void (*cp_commit)(struct radeon_device *rdev);
614 void (*ring_start)(struct radeon_device *rdev);
615 int (*ring_test)(struct radeon_device *rdev);
616 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
617 int (*ib_test)(struct radeon_device *rdev);
618 int (*irq_set)(struct radeon_device *rdev);
619 int (*irq_process)(struct radeon_device *rdev);
620 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
621 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
622 int (*cs_parse)(struct radeon_cs_parser *p);
623 int (*copy_blit)(struct radeon_device *rdev,
627 struct radeon_fence *fence);
628 int (*copy_dma)(struct radeon_device *rdev,
632 struct radeon_fence *fence);
633 int (*copy)(struct radeon_device *rdev,
637 struct radeon_fence *fence);
638 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
639 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
640 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
641 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
642 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
643 uint32_t tiling_flags, uint32_t pitch,
644 uint32_t offset, uint32_t obj_size);
645 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
646 void (*bandwidth_update)(struct radeon_device *rdev);
653 const unsigned *reg_safe_bm;
654 unsigned reg_safe_bm_size;
658 const unsigned *reg_safe_bm;
659 unsigned reg_safe_bm_size;
664 unsigned max_tile_pipes;
666 unsigned max_backends;
668 unsigned max_threads;
669 unsigned max_stack_entries;
670 unsigned max_hw_contexts;
671 unsigned max_gs_threads;
672 unsigned sx_max_export_size;
673 unsigned sx_max_export_pos_size;
674 unsigned sx_max_export_smx_size;
675 unsigned sq_num_cf_insts;
680 unsigned max_tile_pipes;
682 unsigned max_backends;
684 unsigned max_threads;
685 unsigned max_stack_entries;
686 unsigned max_hw_contexts;
687 unsigned max_gs_threads;
688 unsigned sx_max_export_size;
689 unsigned sx_max_export_pos_size;
690 unsigned sx_max_export_smx_size;
691 unsigned sq_num_cf_insts;
692 unsigned sx_num_of_sets;
693 unsigned sc_prim_fifo_size;
694 unsigned sc_hiz_tile_fifo_size;
695 unsigned sc_earlyz_tile_fifo_fize;
698 union radeon_asic_config {
699 struct r300_asic r300;
700 struct r100_asic r100;
701 struct r600_asic r600;
702 struct rv770_asic rv770;
709 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
710 struct drm_file *filp);
711 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
712 struct drm_file *filp);
713 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
714 struct drm_file *file_priv);
715 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
716 struct drm_file *file_priv);
717 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
718 struct drm_file *file_priv);
719 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *file_priv);
721 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *filp);
723 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *filp);
725 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *filp);
727 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *filp);
729 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
730 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
731 struct drm_file *filp);
732 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
733 struct drm_file *filp);
737 * Core structure, functions and helpers.
739 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
740 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
742 struct radeon_device {
744 struct drm_device *ddev;
745 struct pci_dev *pdev;
747 union radeon_asic_config config;
748 enum radeon_family family;
751 enum radeon_pll_errata pll_errata;
758 uint16_t bios_header_start;
759 struct radeon_object *stollen_vga_memory;
760 struct fb_info *fbdev_info;
761 struct radeon_object *fbdev_robj;
762 struct radeon_framebuffer *fbdev_rfb;
764 resource_size_t rmmio_base;
765 resource_size_t rmmio_size;
767 radeon_rreg_t mc_rreg;
768 radeon_wreg_t mc_wreg;
769 radeon_rreg_t pll_rreg;
770 radeon_wreg_t pll_wreg;
771 uint32_t pcie_reg_mask;
772 radeon_rreg_t pciep_rreg;
773 radeon_wreg_t pciep_wreg;
774 struct radeon_clock clock;
776 struct radeon_gart gart;
777 struct radeon_mode_info mode_info;
778 struct radeon_scratch scratch;
779 struct radeon_mman mman;
780 struct radeon_fence_driver fence_drv;
782 struct radeon_ib_pool ib_pool;
783 struct radeon_irq irq;
784 struct radeon_asic *asic;
785 struct radeon_gem gem;
787 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
788 struct mutex cs_mutex;
790 struct radeon_dummy_page dummy_page;
797 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
798 const struct firmware *me_fw; /* all family ME firmware */
799 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
800 struct r600_blit r600_blit;
803 int radeon_device_init(struct radeon_device *rdev,
804 struct drm_device *ddev,
805 struct pci_dev *pdev,
807 void radeon_device_fini(struct radeon_device *rdev);
808 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
811 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
812 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
813 void r600_kms_blit_copy(struct radeon_device *rdev,
814 u64 src_gpu_addr, u64 dst_gpu_addr,
817 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
820 return readl(((void __iomem *)rdev->rmmio) + reg);
822 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
823 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
827 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
830 writel(v, ((void __iomem *)rdev->rmmio) + reg);
832 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
833 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
839 * Registers read & write functions.
841 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
842 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
843 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
844 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
845 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
846 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
847 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
848 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
849 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
850 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
851 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
852 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
853 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
854 #define WREG32_P(reg, val, mask) \
856 uint32_t tmp_ = RREG32(reg); \
858 tmp_ |= ((val) & ~(mask)); \
861 #define WREG32_PLL_P(reg, val, mask) \
863 uint32_t tmp_ = RREG32_PLL(reg); \
865 tmp_ |= ((val) & ~(mask)); \
866 WREG32_PLL(reg, tmp_); \
868 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
871 * Indirect registers accessor
873 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
877 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
878 r = RREG32(RADEON_PCIE_DATA);
882 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
884 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
885 WREG32(RADEON_PCIE_DATA, (v));
888 void r100_pll_errata_after_index(struct radeon_device *rdev);
894 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
895 (rdev->pdev->device == 0x5969))
896 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
897 (rdev->family == CHIP_RV200) || \
898 (rdev->family == CHIP_RS100) || \
899 (rdev->family == CHIP_RS200) || \
900 (rdev->family == CHIP_RV250) || \
901 (rdev->family == CHIP_RV280) || \
902 (rdev->family == CHIP_RS300))
903 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
904 (rdev->family == CHIP_RV350) || \
905 (rdev->family == CHIP_R350) || \
906 (rdev->family == CHIP_RV380) || \
907 (rdev->family == CHIP_R420) || \
908 (rdev->family == CHIP_R423) || \
909 (rdev->family == CHIP_RV410) || \
910 (rdev->family == CHIP_RS400) || \
911 (rdev->family == CHIP_RS480))
912 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
913 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
914 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
920 #define RBIOS8(i) (rdev->bios[i])
921 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
922 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
924 int radeon_combios_init(struct radeon_device *rdev);
925 void radeon_combios_fini(struct radeon_device *rdev);
926 int radeon_atombios_init(struct radeon_device *rdev);
927 void radeon_atombios_fini(struct radeon_device *rdev);
933 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
936 if (rdev->cp.count_dw <= 0) {
937 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
940 rdev->cp.ring[rdev->cp.wptr++] = v;
941 rdev->cp.wptr &= rdev->cp.ptr_mask;
943 rdev->cp.ring_free_dw--;
950 #define radeon_init(rdev) (rdev)->asic->init((rdev))
951 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
952 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
953 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
954 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
955 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
956 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
957 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
958 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
959 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
960 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
961 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
962 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
963 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
964 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
965 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
966 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
967 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
968 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
969 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
970 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
971 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
972 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
973 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
974 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
975 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
976 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
977 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
978 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
979 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
980 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
981 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
982 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
983 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
984 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
985 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
986 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
987 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
988 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
989 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
991 /* Common functions */
992 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
993 extern int radeon_modeset_init(struct radeon_device *rdev);
994 extern void radeon_modeset_fini(struct radeon_device *rdev);
995 extern bool radeon_card_posted(struct radeon_device *rdev);
996 extern int radeon_clocks_init(struct radeon_device *rdev);
997 extern void radeon_clocks_fini(struct radeon_device *rdev);
998 extern void radeon_scratch_init(struct radeon_device *rdev);
999 extern void radeon_surface_init(struct radeon_device *rdev);
1000 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1002 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1003 struct r100_mc_save {
1011 extern void r100_cp_disable(struct radeon_device *rdev);
1012 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1013 extern void r100_cp_fini(struct radeon_device *rdev);
1014 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1015 extern int r100_pci_gart_init(struct radeon_device *rdev);
1016 extern void r100_pci_gart_fini(struct radeon_device *rdev);
1017 extern int r100_pci_gart_enable(struct radeon_device *rdev);
1018 extern void r100_pci_gart_disable(struct radeon_device *rdev);
1019 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1020 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1021 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1022 extern void r100_ib_fini(struct radeon_device *rdev);
1023 extern int r100_ib_init(struct radeon_device *rdev);
1024 extern void r100_irq_disable(struct radeon_device *rdev);
1025 extern int r100_irq_set(struct radeon_device *rdev);
1026 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1027 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1028 extern void r100_vram_init_sizes(struct radeon_device *rdev);
1029 extern void r100_wb_disable(struct radeon_device *rdev);
1030 extern void r100_wb_fini(struct radeon_device *rdev);
1031 extern int r100_wb_init(struct radeon_device *rdev);
1033 /* r300,r350,rv350,rv370,rv380 */
1034 extern void r300_set_reg_safe(struct radeon_device *rdev);
1035 extern void r300_mc_program(struct radeon_device *rdev);
1036 extern void r300_vram_info(struct radeon_device *rdev);
1037 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1038 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1039 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1040 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1042 /* r420,r423,rv410 */
1043 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1044 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1045 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1048 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1051 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1052 struct drm_display_mode *mode1,
1053 struct drm_display_mode *mode2);
1055 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1056 extern bool r600_card_posted(struct radeon_device *rdev);
1057 extern void r600_cp_stop(struct radeon_device *rdev);
1058 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1059 extern int r600_cp_resume(struct radeon_device *rdev);
1060 extern int r600_count_pipe_bits(uint32_t val);
1061 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1062 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1063 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1064 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1065 extern int r600_ib_test(struct radeon_device *rdev);
1066 extern int r600_ring_test(struct radeon_device *rdev);
1067 extern int r600_wb_init(struct radeon_device *rdev);
1068 extern void r600_wb_fini(struct radeon_device *rdev);
1069 extern void r600_scratch_init(struct radeon_device *rdev);
1070 extern int r600_blit_init(struct radeon_device *rdev);
1071 extern void r600_blit_fini(struct radeon_device *rdev);
1072 extern int r600_cp_init_microcode(struct radeon_device *rdev);
1073 extern int r600_gpu_reset(struct radeon_device *rdev);