2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
109 * Errata workarounds.
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
118 struct radeon_device;
124 #define ATRM_BIOS_PAGE 4096
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
139 bool radeon_get_bios(struct radeon_device *rdev);
145 struct radeon_dummy_page {
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
180 void rs690_pm_info(struct radeon_device *rdev);
181 extern u32 rv6xx_get_temp(struct radeon_device *rdev);
182 extern u32 rv770_get_temp(struct radeon_device *rdev);
183 extern u32 evergreen_get_temp(struct radeon_device *rdev);
188 struct radeon_fence_driver {
189 uint32_t scratch_reg;
192 unsigned long last_jiffies;
193 unsigned long last_timeout;
194 wait_queue_head_t queue;
196 struct list_head created;
197 struct list_head emited;
198 struct list_head signaled;
202 struct radeon_fence {
203 struct radeon_device *rdev;
205 struct list_head list;
206 /* protected by radeon_fence.lock */
212 int radeon_fence_driver_init(struct radeon_device *rdev);
213 void radeon_fence_driver_fini(struct radeon_device *rdev);
214 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
215 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
216 void radeon_fence_process(struct radeon_device *rdev);
217 bool radeon_fence_signaled(struct radeon_fence *fence);
218 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
219 int radeon_fence_wait_next(struct radeon_device *rdev);
220 int radeon_fence_wait_last(struct radeon_device *rdev);
221 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
222 void radeon_fence_unref(struct radeon_fence **fence);
227 struct radeon_surface_reg {
228 struct radeon_bo *bo;
231 #define RADEON_GEM_MAX_SURFACES 8
237 struct ttm_bo_global_ref bo_global_ref;
238 struct drm_global_reference mem_global_ref;
239 struct ttm_bo_device bdev;
240 bool mem_global_referenced;
245 /* Protected by gem.mutex */
246 struct list_head list;
247 /* Protected by tbo.reserved */
249 struct ttm_placement placement;
250 struct ttm_buffer_object tbo;
251 struct ttm_bo_kmap_obj kmap;
257 /* Constant after initialization */
258 struct radeon_device *rdev;
259 struct drm_gem_object *gobj;
262 struct radeon_bo_list {
263 struct list_head list;
264 struct radeon_bo *bo;
277 struct list_head objects;
280 int radeon_gem_init(struct radeon_device *rdev);
281 void radeon_gem_fini(struct radeon_device *rdev);
282 int radeon_gem_object_create(struct radeon_device *rdev, int size,
283 int alignment, int initial_domain,
284 bool discardable, bool kernel,
285 struct drm_gem_object **obj);
286 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
288 void radeon_gem_object_unpin(struct drm_gem_object *obj);
292 * GART structures, functions & helpers
296 struct radeon_gart_table_ram {
297 volatile uint32_t *ptr;
300 struct radeon_gart_table_vram {
301 struct radeon_bo *robj;
302 volatile uint32_t *ptr;
305 union radeon_gart_table {
306 struct radeon_gart_table_ram ram;
307 struct radeon_gart_table_vram vram;
310 #define RADEON_GPU_PAGE_SIZE 4096
311 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
314 dma_addr_t table_addr;
315 unsigned num_gpu_pages;
316 unsigned num_cpu_pages;
318 union radeon_gart_table table;
320 dma_addr_t *pages_addr;
324 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
325 void radeon_gart_table_ram_free(struct radeon_device *rdev);
326 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
327 void radeon_gart_table_vram_free(struct radeon_device *rdev);
328 int radeon_gart_init(struct radeon_device *rdev);
329 void radeon_gart_fini(struct radeon_device *rdev);
330 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
332 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
333 int pages, struct page **pagelist);
337 * GPU MC structures, functions & helpers
340 resource_size_t aper_size;
341 resource_size_t aper_base;
342 resource_size_t agp_base;
343 /* for some chips with <= 32MB we need to lie
344 * about vram size near mc fb location */
346 u64 visible_vram_size;
347 u64 active_vram_size;
357 bool igp_sideport_enabled;
361 bool radeon_combios_sideport_present(struct radeon_device *rdev);
362 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
365 * GPU scratch registers structures, functions & helpers
367 struct radeon_scratch {
373 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
374 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
383 /* FIXME: use a define max crtc rather than hardcode it */
384 bool crtc_vblank_int[6];
385 wait_queue_head_t vblank_queue;
386 /* FIXME: use defines for max hpd/dacs */
390 wait_queue_head_t idle_queue;
391 /* FIXME: use defines for max HDMI blocks */
397 int radeon_irq_kms_init(struct radeon_device *rdev);
398 void radeon_irq_kms_fini(struct radeon_device *rdev);
399 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
400 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
406 struct list_head list;
409 struct radeon_fence *fence;
417 * mutex protects scheduled_ibs, ready, alloc_bm
419 struct radeon_ib_pool {
421 struct radeon_bo *robj;
422 struct list_head bogus_ib;
423 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
429 struct radeon_bo *ring_obj;
430 volatile uint32_t *ring;
435 unsigned ring_free_dw;
448 struct radeon_bo *ring_obj;
449 volatile uint32_t *ring;
462 struct radeon_bo *shader_obj;
464 u32 vs_offset, ps_offset;
467 u32 vb_used, vb_total;
468 struct radeon_ib *vb_ib;
471 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
472 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
473 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
474 int radeon_ib_pool_init(struct radeon_device *rdev);
475 void radeon_ib_pool_fini(struct radeon_device *rdev);
476 int radeon_ib_test(struct radeon_device *rdev);
477 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
478 /* Ring access between begin & end cannot sleep */
479 void radeon_ring_free_size(struct radeon_device *rdev);
480 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
481 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
482 void radeon_ring_commit(struct radeon_device *rdev);
483 void radeon_ring_unlock_commit(struct radeon_device *rdev);
484 void radeon_ring_unlock_undo(struct radeon_device *rdev);
485 int radeon_ring_test(struct radeon_device *rdev);
486 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
487 void radeon_ring_fini(struct radeon_device *rdev);
493 struct radeon_cs_reloc {
494 struct drm_gem_object *gobj;
495 struct radeon_bo *robj;
496 struct radeon_bo_list lobj;
501 struct radeon_cs_chunk {
507 void __user *user_ptr;
508 int last_copied_page;
512 struct radeon_cs_parser {
514 struct radeon_device *rdev;
515 struct drm_file *filp;
518 struct radeon_cs_chunk *chunks;
519 uint64_t *chunks_array;
524 struct radeon_cs_reloc *relocs;
525 struct radeon_cs_reloc **relocs_ptr;
526 struct list_head validated;
527 /* indices of various chunks */
529 int chunk_relocs_idx;
530 struct radeon_ib *ib;
536 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
537 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
540 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
542 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
543 u32 pg_idx, pg_offset;
547 pg_idx = (idx * 4) / PAGE_SIZE;
548 pg_offset = (idx * 4) % PAGE_SIZE;
550 if (ibc->kpage_idx[0] == pg_idx)
551 return ibc->kpage[0][pg_offset/4];
552 if (ibc->kpage_idx[1] == pg_idx)
553 return ibc->kpage[1][pg_offset/4];
555 new_page = radeon_cs_update_pages(p, pg_idx);
557 p->parser_error = new_page;
561 idx_value = ibc->kpage[new_page][pg_offset/4];
565 struct radeon_cs_packet {
574 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
575 struct radeon_cs_packet *pkt,
576 unsigned idx, unsigned reg);
577 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
578 struct radeon_cs_packet *pkt);
584 int radeon_agp_init(struct radeon_device *rdev);
585 void radeon_agp_resume(struct radeon_device *rdev);
586 void radeon_agp_suspend(struct radeon_device *rdev);
587 void radeon_agp_fini(struct radeon_device *rdev);
594 struct radeon_bo *wb_obj;
595 volatile uint32_t *wb;
600 * struct radeon_pm - power management datas
601 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
602 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
603 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
604 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
605 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
606 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
607 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
608 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
609 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
610 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
611 * @needed_bandwidth: current bandwidth needs
613 * It keeps track of various data needed to take powermanagement decision.
614 * Bandwith need is used to determine minimun clock of the GPU and memory.
615 * Equation between gpu/memory clock and available bandwidth is hw dependent
616 * (type of memory, bus size, efficiency, ...)
619 enum radeon_pm_method {
624 enum radeon_dynpm_state {
625 DYNPM_STATE_DISABLED,
629 DYNPM_STATE_SUSPENDED,
631 enum radeon_dynpm_action {
633 DYNPM_ACTION_MINIMUM,
634 DYNPM_ACTION_DOWNCLOCK,
635 DYNPM_ACTION_UPCLOCK,
639 enum radeon_voltage_type {
646 enum radeon_pm_state_type {
647 POWER_STATE_TYPE_DEFAULT,
648 POWER_STATE_TYPE_POWERSAVE,
649 POWER_STATE_TYPE_BATTERY,
650 POWER_STATE_TYPE_BALANCED,
651 POWER_STATE_TYPE_PERFORMANCE,
654 enum radeon_pm_profile_type {
662 #define PM_PROFILE_DEFAULT_IDX 0
663 #define PM_PROFILE_LOW_SH_IDX 1
664 #define PM_PROFILE_MID_SH_IDX 2
665 #define PM_PROFILE_HIGH_SH_IDX 3
666 #define PM_PROFILE_LOW_MH_IDX 4
667 #define PM_PROFILE_MID_MH_IDX 5
668 #define PM_PROFILE_HIGH_MH_IDX 6
669 #define PM_PROFILE_MAX 7
671 struct radeon_pm_profile {
678 enum radeon_int_thermal_type {
682 THERMAL_TYPE_EVERGREEN,
685 struct radeon_voltage {
686 enum radeon_voltage_type type;
688 struct radeon_gpio_rec gpio;
689 u32 delay; /* delay in usec from voltage drop to sclk change */
690 bool active_high; /* voltage drop is active when bit is high */
692 u8 vddc_id; /* index into vddc voltage table */
693 u8 vddci_id; /* index into vddci voltage table */
699 /* clock mode flags */
700 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
702 struct radeon_pm_clock_info {
708 struct radeon_voltage voltage;
709 /* standardized clock flags */
714 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
716 struct radeon_power_state {
717 enum radeon_pm_state_type type;
718 /* XXX: use a define for num clock modes */
719 struct radeon_pm_clock_info clock_info[8];
720 /* number of valid clock modes in this power state */
722 struct radeon_pm_clock_info *default_clock_mode;
723 /* standardized state flags */
725 u32 misc; /* vbios specific flags */
726 u32 misc2; /* vbios specific flags */
727 int pcie_lanes; /* pcie lanes */
731 * Some modes are overclocked by very low value, accept them
733 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
738 int active_crtc_count;
742 fixed20_12 max_bandwidth;
743 fixed20_12 igp_sideport_mclk;
744 fixed20_12 igp_system_mclk;
745 fixed20_12 igp_ht_link_clk;
746 fixed20_12 igp_ht_link_width;
747 fixed20_12 k8_bandwidth;
748 fixed20_12 sideport_bandwidth;
749 fixed20_12 ht_bandwidth;
750 fixed20_12 core_bandwidth;
753 fixed20_12 needed_bandwidth;
754 /* XXX: use a define for num power modes */
755 struct radeon_power_state power_state[8];
756 /* number of valid power states */
757 int num_power_states;
758 int current_power_state_index;
759 int current_clock_mode_index;
760 int requested_power_state_index;
761 int requested_clock_mode_index;
762 int default_power_state_index;
766 struct radeon_i2c_chan *i2c_bus;
767 /* selected pm method */
768 enum radeon_pm_method pm_method;
769 /* dynpm power management */
770 struct delayed_work dynpm_idle_work;
771 enum radeon_dynpm_state dynpm_state;
772 enum radeon_dynpm_action dynpm_planned_action;
773 unsigned long dynpm_action_timeout;
774 bool dynpm_can_upclock;
775 bool dynpm_can_downclock;
776 /* profile-based power management */
777 enum radeon_pm_profile_type profile;
779 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
780 /* internal thermal controller on rv6xx+ */
781 enum radeon_int_thermal_type int_thermal_type;
782 struct device *int_hwmon_dev;
789 void radeon_benchmark(struct radeon_device *rdev);
795 void radeon_test_moves(struct radeon_device *rdev);
801 int radeon_debugfs_add_files(struct radeon_device *rdev,
802 struct drm_info_list *files,
804 int radeon_debugfs_fence_init(struct radeon_device *rdev);
808 * ASIC specific functions.
811 int (*init)(struct radeon_device *rdev);
812 void (*fini)(struct radeon_device *rdev);
813 int (*resume)(struct radeon_device *rdev);
814 int (*suspend)(struct radeon_device *rdev);
815 void (*vga_set_state)(struct radeon_device *rdev, bool state);
816 bool (*gpu_is_lockup)(struct radeon_device *rdev);
817 int (*asic_reset)(struct radeon_device *rdev);
818 void (*gart_tlb_flush)(struct radeon_device *rdev);
819 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
820 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
821 void (*cp_fini)(struct radeon_device *rdev);
822 void (*cp_disable)(struct radeon_device *rdev);
823 void (*cp_commit)(struct radeon_device *rdev);
824 void (*ring_start)(struct radeon_device *rdev);
825 int (*ring_test)(struct radeon_device *rdev);
826 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
827 int (*irq_set)(struct radeon_device *rdev);
828 int (*irq_process)(struct radeon_device *rdev);
829 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
830 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
831 int (*cs_parse)(struct radeon_cs_parser *p);
832 int (*copy_blit)(struct radeon_device *rdev,
836 struct radeon_fence *fence);
837 int (*copy_dma)(struct radeon_device *rdev,
841 struct radeon_fence *fence);
842 int (*copy)(struct radeon_device *rdev,
846 struct radeon_fence *fence);
847 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
848 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
849 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
850 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
851 int (*get_pcie_lanes)(struct radeon_device *rdev);
852 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
853 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
854 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
855 uint32_t tiling_flags, uint32_t pitch,
856 uint32_t offset, uint32_t obj_size);
857 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
858 void (*bandwidth_update)(struct radeon_device *rdev);
859 void (*hpd_init)(struct radeon_device *rdev);
860 void (*hpd_fini)(struct radeon_device *rdev);
861 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
862 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
863 /* ioctl hw specific callback. Some hw might want to perform special
864 * operation on specific ioctl. For instance on wait idle some hw
865 * might want to perform and HDP flush through MMIO as it seems that
866 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
869 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
870 bool (*gui_idle)(struct radeon_device *rdev);
871 /* power management */
872 void (*pm_misc)(struct radeon_device *rdev);
873 void (*pm_prepare)(struct radeon_device *rdev);
874 void (*pm_finish)(struct radeon_device *rdev);
875 void (*pm_init_profile)(struct radeon_device *rdev);
876 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
882 struct r100_gpu_lockup {
883 unsigned long last_jiffies;
888 const unsigned *reg_safe_bm;
889 unsigned reg_safe_bm_size;
891 struct r100_gpu_lockup lockup;
895 const unsigned *reg_safe_bm;
896 unsigned reg_safe_bm_size;
899 struct r100_gpu_lockup lockup;
904 unsigned max_tile_pipes;
906 unsigned max_backends;
908 unsigned max_threads;
909 unsigned max_stack_entries;
910 unsigned max_hw_contexts;
911 unsigned max_gs_threads;
912 unsigned sx_max_export_size;
913 unsigned sx_max_export_pos_size;
914 unsigned sx_max_export_smx_size;
915 unsigned sq_num_cf_insts;
916 unsigned tiling_nbanks;
917 unsigned tiling_npipes;
918 unsigned tiling_group_size;
919 unsigned tile_config;
920 struct r100_gpu_lockup lockup;
925 unsigned max_tile_pipes;
927 unsigned max_backends;
929 unsigned max_threads;
930 unsigned max_stack_entries;
931 unsigned max_hw_contexts;
932 unsigned max_gs_threads;
933 unsigned sx_max_export_size;
934 unsigned sx_max_export_pos_size;
935 unsigned sx_max_export_smx_size;
936 unsigned sq_num_cf_insts;
937 unsigned sx_num_of_sets;
938 unsigned sc_prim_fifo_size;
939 unsigned sc_hiz_tile_fifo_size;
940 unsigned sc_earlyz_tile_fifo_fize;
941 unsigned tiling_nbanks;
942 unsigned tiling_npipes;
943 unsigned tiling_group_size;
944 unsigned tile_config;
945 struct r100_gpu_lockup lockup;
948 struct evergreen_asic {
951 unsigned max_tile_pipes;
953 unsigned max_backends;
955 unsigned max_threads;
956 unsigned max_stack_entries;
957 unsigned max_hw_contexts;
958 unsigned max_gs_threads;
959 unsigned sx_max_export_size;
960 unsigned sx_max_export_pos_size;
961 unsigned sx_max_export_smx_size;
962 unsigned sq_num_cf_insts;
963 unsigned sx_num_of_sets;
964 unsigned sc_prim_fifo_size;
965 unsigned sc_hiz_tile_fifo_size;
966 unsigned sc_earlyz_tile_fifo_size;
967 unsigned tiling_nbanks;
968 unsigned tiling_npipes;
969 unsigned tiling_group_size;
970 unsigned tile_config;
973 union radeon_asic_config {
974 struct r300_asic r300;
975 struct r100_asic r100;
976 struct r600_asic r600;
977 struct rv770_asic rv770;
978 struct evergreen_asic evergreen;
982 * asic initizalization from radeon_asic.c
984 void radeon_agp_disable(struct radeon_device *rdev);
985 int radeon_asic_init(struct radeon_device *rdev);
991 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *filp);
993 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *filp);
995 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file_priv);
997 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *file_priv);
999 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv);
1003 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1004 struct drm_file *filp);
1005 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *filp);
1007 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *filp);
1009 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1010 struct drm_file *filp);
1011 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1012 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1013 struct drm_file *filp);
1014 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *filp);
1017 /* VRAM scratch page for HDP bug */
1018 struct r700_vram_scratch {
1019 struct radeon_bo *robj;
1020 volatile uint32_t *ptr;
1024 * Core structure, functions and helpers.
1026 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1027 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1029 struct radeon_device {
1031 struct drm_device *ddev;
1032 struct pci_dev *pdev;
1034 union radeon_asic_config config;
1035 enum radeon_family family;
1036 unsigned long flags;
1038 enum radeon_pll_errata pll_errata;
1045 uint16_t bios_header_start;
1046 struct radeon_bo *stollen_vga_memory;
1048 resource_size_t rmmio_base;
1049 resource_size_t rmmio_size;
1051 radeon_rreg_t mc_rreg;
1052 radeon_wreg_t mc_wreg;
1053 radeon_rreg_t pll_rreg;
1054 radeon_wreg_t pll_wreg;
1055 uint32_t pcie_reg_mask;
1056 radeon_rreg_t pciep_rreg;
1057 radeon_wreg_t pciep_wreg;
1059 void __iomem *rio_mem;
1060 resource_size_t rio_mem_size;
1061 struct radeon_clock clock;
1062 struct radeon_mc mc;
1063 struct radeon_gart gart;
1064 struct radeon_mode_info mode_info;
1065 struct radeon_scratch scratch;
1066 struct radeon_mman mman;
1067 struct radeon_fence_driver fence_drv;
1068 struct radeon_cp cp;
1069 struct radeon_ib_pool ib_pool;
1070 struct radeon_irq irq;
1071 struct radeon_asic *asic;
1072 struct radeon_gem gem;
1073 struct radeon_pm pm;
1074 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1075 struct mutex cs_mutex;
1076 struct radeon_wb wb;
1077 struct radeon_dummy_page dummy_page;
1083 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1084 const struct firmware *me_fw; /* all family ME firmware */
1085 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1086 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1087 struct r600_blit r600_blit;
1088 struct r700_vram_scratch vram_scratch;
1089 int msi_enabled; /* msi enabled */
1090 struct r600_ih ih; /* r6/700 interrupt ring */
1091 struct workqueue_struct *wq;
1092 struct work_struct hotplug_work;
1093 int num_crtc; /* number of crtcs */
1094 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1095 struct mutex vram_mutex;
1099 struct timer_list audio_timer;
1102 int audio_bits_per_sample;
1103 uint8_t audio_status_bits;
1104 uint8_t audio_category_code;
1107 struct notifier_block acpi_nb;
1108 /* only one userspace can use Hyperz features at a time */
1109 struct drm_file *hyperz_filp;
1111 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1114 int radeon_device_init(struct radeon_device *rdev,
1115 struct drm_device *ddev,
1116 struct pci_dev *pdev,
1118 void radeon_device_fini(struct radeon_device *rdev);
1119 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1122 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1123 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1124 void r600_kms_blit_copy(struct radeon_device *rdev,
1125 u64 src_gpu_addr, u64 dst_gpu_addr,
1128 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1130 if (reg < rdev->rmmio_size)
1131 return readl(((void __iomem *)rdev->rmmio) + reg);
1133 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1134 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1138 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1140 if (reg < rdev->rmmio_size)
1141 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1143 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1144 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1148 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1150 if (reg < rdev->rio_mem_size)
1151 return ioread32(rdev->rio_mem + reg);
1153 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1154 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1158 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1160 if (reg < rdev->rio_mem_size)
1161 iowrite32(v, rdev->rio_mem + reg);
1163 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1164 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1171 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1174 * Registers read & write functions.
1176 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1177 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1178 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1179 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1180 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1181 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1182 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1183 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1184 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1185 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1186 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1187 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1188 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1189 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1190 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1191 #define WREG32_P(reg, val, mask) \
1193 uint32_t tmp_ = RREG32(reg); \
1195 tmp_ |= ((val) & ~(mask)); \
1196 WREG32(reg, tmp_); \
1198 #define WREG32_PLL_P(reg, val, mask) \
1200 uint32_t tmp_ = RREG32_PLL(reg); \
1202 tmp_ |= ((val) & ~(mask)); \
1203 WREG32_PLL(reg, tmp_); \
1205 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1206 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1207 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1210 * Indirect registers accessor
1212 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1216 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1217 r = RREG32(RADEON_PCIE_DATA);
1221 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1223 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1224 WREG32(RADEON_PCIE_DATA, (v));
1227 void r100_pll_errata_after_index(struct radeon_device *rdev);
1233 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1234 (rdev->pdev->device == 0x5969))
1235 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1236 (rdev->family == CHIP_RV200) || \
1237 (rdev->family == CHIP_RS100) || \
1238 (rdev->family == CHIP_RS200) || \
1239 (rdev->family == CHIP_RV250) || \
1240 (rdev->family == CHIP_RV280) || \
1241 (rdev->family == CHIP_RS300))
1242 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1243 (rdev->family == CHIP_RV350) || \
1244 (rdev->family == CHIP_R350) || \
1245 (rdev->family == CHIP_RV380) || \
1246 (rdev->family == CHIP_R420) || \
1247 (rdev->family == CHIP_R423) || \
1248 (rdev->family == CHIP_RV410) || \
1249 (rdev->family == CHIP_RS400) || \
1250 (rdev->family == CHIP_RS480))
1251 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1252 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1253 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1254 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1259 #define RBIOS8(i) (rdev->bios[i])
1260 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1261 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1263 int radeon_combios_init(struct radeon_device *rdev);
1264 void radeon_combios_fini(struct radeon_device *rdev);
1265 int radeon_atombios_init(struct radeon_device *rdev);
1266 void radeon_atombios_fini(struct radeon_device *rdev);
1272 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1275 if (rdev->cp.count_dw <= 0) {
1276 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1279 rdev->cp.ring[rdev->cp.wptr++] = v;
1280 rdev->cp.wptr &= rdev->cp.ptr_mask;
1281 rdev->cp.count_dw--;
1282 rdev->cp.ring_free_dw--;
1289 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1290 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1291 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1292 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1293 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1294 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1295 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1296 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1297 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1298 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1299 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1300 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1301 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1302 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1303 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1304 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1305 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1306 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1307 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1308 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1309 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1310 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1311 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1312 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1313 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1314 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1315 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1316 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1317 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1318 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1319 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1320 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1321 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1322 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1323 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1324 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1325 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1326 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1327 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1328 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1329 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1331 /* Common functions */
1333 extern int radeon_gpu_reset(struct radeon_device *rdev);
1334 extern void radeon_agp_disable(struct radeon_device *rdev);
1335 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1336 extern void radeon_gart_restore(struct radeon_device *rdev);
1337 extern int radeon_modeset_init(struct radeon_device *rdev);
1338 extern void radeon_modeset_fini(struct radeon_device *rdev);
1339 extern bool radeon_card_posted(struct radeon_device *rdev);
1340 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1341 extern void radeon_update_display_priority(struct radeon_device *rdev);
1342 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1343 extern void radeon_scratch_init(struct radeon_device *rdev);
1344 extern void radeon_surface_init(struct radeon_device *rdev);
1345 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1346 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1347 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1348 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1349 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1350 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1351 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1352 extern int radeon_resume_kms(struct drm_device *dev);
1353 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1355 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1356 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1357 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1359 /* rv200,rv250,rv280 */
1360 extern void r200_set_safe_registers(struct radeon_device *rdev);
1362 /* r300,r350,rv350,rv370,rv380 */
1363 extern void r300_set_reg_safe(struct radeon_device *rdev);
1364 extern void r300_mc_program(struct radeon_device *rdev);
1365 extern void r300_mc_init(struct radeon_device *rdev);
1366 extern void r300_clock_startup(struct radeon_device *rdev);
1367 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1368 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1369 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1370 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1371 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1373 /* r420,r423,rv410 */
1374 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1375 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1376 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1377 extern void r420_pipes_init(struct radeon_device *rdev);
1380 struct rv515_mc_save {
1383 u32 vga_render_control;
1384 u32 vga_hdp_control;
1388 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1389 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1390 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1391 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1392 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1393 extern void rv515_clock_startup(struct radeon_device *rdev);
1394 extern void rv515_debugfs(struct radeon_device *rdev);
1395 extern int rv515_suspend(struct radeon_device *rdev);
1398 extern int rs400_gart_init(struct radeon_device *rdev);
1399 extern int rs400_gart_enable(struct radeon_device *rdev);
1400 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1401 extern void rs400_gart_disable(struct radeon_device *rdev);
1402 extern void rs400_gart_fini(struct radeon_device *rdev);
1405 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1406 extern int rs600_irq_set(struct radeon_device *rdev);
1407 extern void rs600_irq_disable(struct radeon_device *rdev);
1410 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1411 struct drm_display_mode *mode1,
1412 struct drm_display_mode *mode2);
1414 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1415 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1416 extern bool r600_card_posted(struct radeon_device *rdev);
1417 extern void r600_cp_stop(struct radeon_device *rdev);
1418 extern int r600_cp_start(struct radeon_device *rdev);
1419 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1420 extern int r600_cp_resume(struct radeon_device *rdev);
1421 extern void r600_cp_fini(struct radeon_device *rdev);
1422 extern int r600_count_pipe_bits(uint32_t val);
1423 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1424 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1425 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1426 extern int r600_ib_test(struct radeon_device *rdev);
1427 extern int r600_ring_test(struct radeon_device *rdev);
1428 extern void r600_wb_fini(struct radeon_device *rdev);
1429 extern int r600_wb_enable(struct radeon_device *rdev);
1430 extern void r600_wb_disable(struct radeon_device *rdev);
1431 extern void r600_scratch_init(struct radeon_device *rdev);
1432 extern int r600_blit_init(struct radeon_device *rdev);
1433 extern void r600_blit_fini(struct radeon_device *rdev);
1434 extern int r600_init_microcode(struct radeon_device *rdev);
1435 extern int r600_asic_reset(struct radeon_device *rdev);
1437 extern int r600_irq_init(struct radeon_device *rdev);
1438 extern void r600_irq_fini(struct radeon_device *rdev);
1439 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1440 extern int r600_irq_set(struct radeon_device *rdev);
1441 extern void r600_irq_suspend(struct radeon_device *rdev);
1442 extern void r600_disable_interrupts(struct radeon_device *rdev);
1443 extern void r600_rlc_stop(struct radeon_device *rdev);
1445 extern int r600_audio_init(struct radeon_device *rdev);
1446 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1447 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1448 extern int r600_audio_channels(struct radeon_device *rdev);
1449 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1450 extern int r600_audio_rate(struct radeon_device *rdev);
1451 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1452 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1453 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1454 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1455 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1456 extern void r600_audio_fini(struct radeon_device *rdev);
1457 extern void r600_hdmi_init(struct drm_encoder *encoder);
1458 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1459 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1460 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1461 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1462 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1464 extern void r700_cp_stop(struct radeon_device *rdev);
1465 extern void r700_cp_fini(struct radeon_device *rdev);
1466 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1467 extern int evergreen_irq_set(struct radeon_device *rdev);
1470 #if defined(CONFIG_ACPI)
1471 extern int radeon_acpi_init(struct radeon_device *rdev);
1473 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1477 struct evergreen_mc_save {
1479 u32 vga_render_control;
1480 u32 vga_hdp_control;
1481 u32 crtc_control[6];
1484 #include "radeon_object.h"