drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175
 176 static struct radeon_asic_ring r100_gfx_ring = {
 177         .ib_execute = &r100_ring_ib_execute,
 178         .emit_fence = &r100_fence_ring_emit,
 179         .emit_semaphore = &r100_semaphore_ring_emit,
 180         .cs_parse = &r100_cs_parse,
 181         .ring_start = &r100_ring_start,
 182         .ring_test = &r100_ring_test,
 183         .ib_test = &r100_ib_test,
 184         .is_lockup = &r100_gpu_is_lockup,
 185         .get_rptr = &radeon_ring_generic_get_rptr,
 186         .get_wptr = &radeon_ring_generic_get_wptr,
 187         .set_wptr = &radeon_ring_generic_set_wptr,
 188 };
 189
 190 static struct radeon_asic r100_asic = {
 191         .init = &r100_init,
 192         .fini = &r100_fini,
 193         .suspend = &r100_suspend,
 194         .resume = &r100_resume,
 195         .vga_set_state = &r100_vga_set_state,
 196         .asic_reset = &r100_asic_reset,
 197         .ioctl_wait_idle = NULL,
 198         .gui_idle = &r100_gui_idle,
 199         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 200         .gart = {
 201                 .tlb_flush = &r100_pci_gart_tlb_flush,
 202                 .set_page = &r100_pci_gart_set_page,
 203         },
 204         .ring = {
 205                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 206         },
 207         .irq = {
 208                 .set = &r100_irq_set,
 209                 .process = &r100_irq_process,
 210         },
 211         .display = {
 212                 .bandwidth_update = &r100_bandwidth_update,
 213                 .get_vblank_counter = &r100_get_vblank_counter,
 214                 .wait_for_vblank = &r100_wait_for_vblank,
 215                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 216                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 217         },
 218         .copy = {
 219                 .blit = &r100_copy_blit,
 220                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 221                 .dma = NULL,
 222                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 223                 .copy = &r100_copy_blit,
 224                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 225         },
 226         .surface = {
 227                 .set_reg = r100_set_surface_reg,
 228                 .clear_reg = r100_clear_surface_reg,
 229         },
 230         .hpd = {
 231                 .init = &r100_hpd_init,
 232                 .fini = &r100_hpd_fini,
 233                 .sense = &r100_hpd_sense,
 234                 .set_polarity = &r100_hpd_set_polarity,
 235         },
 236         .pm = {
 237                 .misc = &r100_pm_misc,
 238                 .prepare = &r100_pm_prepare,
 239                 .finish = &r100_pm_finish,
 240                 .init_profile = &r100_pm_init_profile,
 241                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 242                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 243                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 244                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 245                 .set_memory_clock = NULL,
 246                 .get_pcie_lanes = NULL,
 247                 .set_pcie_lanes = NULL,
 248                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 249         },
 250         .pflip = {
 251                 .pre_page_flip = &r100_pre_page_flip,
 252                 .page_flip = &r100_page_flip,
 253                 .post_page_flip = &r100_post_page_flip,
 254         },
 255 };
 256
 257 static struct radeon_asic r200_asic = {
 258         .init = &r100_init,
 259         .fini = &r100_fini,
 260         .suspend = &r100_suspend,
 261         .resume = &r100_resume,
 262         .vga_set_state = &r100_vga_set_state,
 263         .asic_reset = &r100_asic_reset,
 264         .ioctl_wait_idle = NULL,
 265         .gui_idle = &r100_gui_idle,
 266         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 267         .gart = {
 268                 .tlb_flush = &r100_pci_gart_tlb_flush,
 269                 .set_page = &r100_pci_gart_set_page,
 270         },
 271         .ring = {
 272                 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
 273         },
 274         .irq = {
 275                 .set = &r100_irq_set,
 276                 .process = &r100_irq_process,
 277         },
 278         .display = {
 279                 .bandwidth_update = &r100_bandwidth_update,
 280                 .get_vblank_counter = &r100_get_vblank_counter,
 281                 .wait_for_vblank = &r100_wait_for_vblank,
 282                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 283                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 284         },
 285         .copy = {
 286                 .blit = &r100_copy_blit,
 287                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 288                 .dma = &r200_copy_dma,
 289                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 290                 .copy = &r100_copy_blit,
 291                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 292         },
 293         .surface = {
 294                 .set_reg = r100_set_surface_reg,
 295                 .clear_reg = r100_clear_surface_reg,
 296         },
 297         .hpd = {
 298                 .init = &r100_hpd_init,
 299                 .fini = &r100_hpd_fini,
 300                 .sense = &r100_hpd_sense,
 301                 .set_polarity = &r100_hpd_set_polarity,
 302         },
 303         .pm = {
 304                 .misc = &r100_pm_misc,
 305                 .prepare = &r100_pm_prepare,
 306                 .finish = &r100_pm_finish,
 307                 .init_profile = &r100_pm_init_profile,
 308                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 309                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 310                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 311                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 312                 .set_memory_clock = NULL,
 313                 .get_pcie_lanes = NULL,
 314                 .set_pcie_lanes = NULL,
 315                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 316         },
 317         .pflip = {
 318                 .pre_page_flip = &r100_pre_page_flip,
 319                 .page_flip = &r100_page_flip,
 320                 .post_page_flip = &r100_post_page_flip,
 321         },
 322 };
 323
 324 static struct radeon_asic_ring r300_gfx_ring = {
 325         .ib_execute = &r100_ring_ib_execute,
 326         .emit_fence = &r300_fence_ring_emit,
 327         .emit_semaphore = &r100_semaphore_ring_emit,
 328         .cs_parse = &r300_cs_parse,
 329         .ring_start = &r300_ring_start,
 330         .ring_test = &r100_ring_test,
 331         .ib_test = &r100_ib_test,
 332         .is_lockup = &r100_gpu_is_lockup,
 333         .get_rptr = &radeon_ring_generic_get_rptr,
 334         .get_wptr = &radeon_ring_generic_get_wptr,
 335         .set_wptr = &radeon_ring_generic_set_wptr,
 336 };
 337
 338 static struct radeon_asic r300_asic = {
 339         .init = &r300_init,
 340         .fini = &r300_fini,
 341         .suspend = &r300_suspend,
 342         .resume = &r300_resume,
 343         .vga_set_state = &r100_vga_set_state,
 344         .asic_reset = &r300_asic_reset,
 345         .ioctl_wait_idle = NULL,
 346         .gui_idle = &r100_gui_idle,
 347         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 348         .gart = {
 349                 .tlb_flush = &r100_pci_gart_tlb_flush,
 350                 .set_page = &r100_pci_gart_set_page,
 351         },
 352         .ring = {
 353                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 354         },
 355         .irq = {
 356                 .set = &r100_irq_set,
 357                 .process = &r100_irq_process,
 358         },
 359         .display = {
 360                 .bandwidth_update = &r100_bandwidth_update,
 361                 .get_vblank_counter = &r100_get_vblank_counter,
 362                 .wait_for_vblank = &r100_wait_for_vblank,
 363                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 364                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 365         },
 366         .copy = {
 367                 .blit = &r100_copy_blit,
 368                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 369                 .dma = &r200_copy_dma,
 370                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 371                 .copy = &r100_copy_blit,
 372                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 373         },
 374         .surface = {
 375                 .set_reg = r100_set_surface_reg,
 376                 .clear_reg = r100_clear_surface_reg,
 377         },
 378         .hpd = {
 379                 .init = &r100_hpd_init,
 380                 .fini = &r100_hpd_fini,
 381                 .sense = &r100_hpd_sense,
 382                 .set_polarity = &r100_hpd_set_polarity,
 383         },
 384         .pm = {
 385                 .misc = &r100_pm_misc,
 386                 .prepare = &r100_pm_prepare,
 387                 .finish = &r100_pm_finish,
 388                 .init_profile = &r100_pm_init_profile,
 389                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 390                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 391                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 392                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 393                 .set_memory_clock = NULL,
 394                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 395                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 396                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 397         },
 398         .pflip = {
 399                 .pre_page_flip = &r100_pre_page_flip,
 400                 .page_flip = &r100_page_flip,
 401                 .post_page_flip = &r100_post_page_flip,
 402         },
 403 };
 404
 405 static struct radeon_asic r300_asic_pcie = {
 406         .init = &r300_init,
 407         .fini = &r300_fini,
 408         .suspend = &r300_suspend,
 409         .resume = &r300_resume,
 410         .vga_set_state = &r100_vga_set_state,
 411         .asic_reset = &r300_asic_reset,
 412         .ioctl_wait_idle = NULL,
 413         .gui_idle = &r100_gui_idle,
 414         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 415         .gart = {
 416                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 417                 .set_page = &rv370_pcie_gart_set_page,
 418         },
 419         .ring = {
 420                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 421         },
 422         .irq = {
 423                 .set = &r100_irq_set,
 424                 .process = &r100_irq_process,
 425         },
 426         .display = {
 427                 .bandwidth_update = &r100_bandwidth_update,
 428                 .get_vblank_counter = &r100_get_vblank_counter,
 429                 .wait_for_vblank = &r100_wait_for_vblank,
 430                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 431                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 432         },
 433         .copy = {
 434                 .blit = &r100_copy_blit,
 435                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 436                 .dma = &r200_copy_dma,
 437                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 438                 .copy = &r100_copy_blit,
 439                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 440         },
 441         .surface = {
 442                 .set_reg = r100_set_surface_reg,
 443                 .clear_reg = r100_clear_surface_reg,
 444         },
 445         .hpd = {
 446                 .init = &r100_hpd_init,
 447                 .fini = &r100_hpd_fini,
 448                 .sense = &r100_hpd_sense,
 449                 .set_polarity = &r100_hpd_set_polarity,
 450         },
 451         .pm = {
 452                 .misc = &r100_pm_misc,
 453                 .prepare = &r100_pm_prepare,
 454                 .finish = &r100_pm_finish,
 455                 .init_profile = &r100_pm_init_profile,
 456                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 457                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 458                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 459                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 460                 .set_memory_clock = NULL,
 461                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 462                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 463                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 464         },
 465         .pflip = {
 466                 .pre_page_flip = &r100_pre_page_flip,
 467                 .page_flip = &r100_page_flip,
 468                 .post_page_flip = &r100_post_page_flip,
 469         },
 470 };
 471
 472 static struct radeon_asic r420_asic = {
 473         .init = &r420_init,
 474         .fini = &r420_fini,
 475         .suspend = &r420_suspend,
 476         .resume = &r420_resume,
 477         .vga_set_state = &r100_vga_set_state,
 478         .asic_reset = &r300_asic_reset,
 479         .ioctl_wait_idle = NULL,
 480         .gui_idle = &r100_gui_idle,
 481         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 482         .gart = {
 483                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 484                 .set_page = &rv370_pcie_gart_set_page,
 485         },
 486         .ring = {
 487                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 488         },
 489         .irq = {
 490                 .set = &r100_irq_set,
 491                 .process = &r100_irq_process,
 492         },
 493         .display = {
 494                 .bandwidth_update = &r100_bandwidth_update,
 495                 .get_vblank_counter = &r100_get_vblank_counter,
 496                 .wait_for_vblank = &r100_wait_for_vblank,
 497                 .set_backlight_level = &atombios_set_backlight_level,
 498                 .get_backlight_level = &atombios_get_backlight_level,
 499         },
 500         .copy = {
 501                 .blit = &r100_copy_blit,
 502                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 503                 .dma = &r200_copy_dma,
 504                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 505                 .copy = &r100_copy_blit,
 506                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 507         },
 508         .surface = {
 509                 .set_reg = r100_set_surface_reg,
 510                 .clear_reg = r100_clear_surface_reg,
 511         },
 512         .hpd = {
 513                 .init = &r100_hpd_init,
 514                 .fini = &r100_hpd_fini,
 515                 .sense = &r100_hpd_sense,
 516                 .set_polarity = &r100_hpd_set_polarity,
 517         },
 518         .pm = {
 519                 .misc = &r100_pm_misc,
 520                 .prepare = &r100_pm_prepare,
 521                 .finish = &r100_pm_finish,
 522                 .init_profile = &r420_pm_init_profile,
 523                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 524                 .get_engine_clock = &radeon_atom_get_engine_clock,
 525                 .set_engine_clock = &radeon_atom_set_engine_clock,
 526                 .get_memory_clock = &radeon_atom_get_memory_clock,
 527                 .set_memory_clock = &radeon_atom_set_memory_clock,
 528                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 529                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 530                 .set_clock_gating = &radeon_atom_set_clock_gating,
 531         },
 532         .pflip = {
 533                 .pre_page_flip = &r100_pre_page_flip,
 534                 .page_flip = &r100_page_flip,
 535                 .post_page_flip = &r100_post_page_flip,
 536         },
 537 };
 538
 539 static struct radeon_asic rs400_asic = {
 540         .init = &rs400_init,
 541         .fini = &rs400_fini,
 542         .suspend = &rs400_suspend,
 543         .resume = &rs400_resume,
 544         .vga_set_state = &r100_vga_set_state,
 545         .asic_reset = &r300_asic_reset,
 546         .ioctl_wait_idle = NULL,
 547         .gui_idle = &r100_gui_idle,
 548         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 549         .gart = {
 550                 .tlb_flush = &rs400_gart_tlb_flush,
 551                 .set_page = &rs400_gart_set_page,
 552         },
 553         .ring = {
 554                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 555         },
 556         .irq = {
 557                 .set = &r100_irq_set,
 558                 .process = &r100_irq_process,
 559         },
 560         .display = {
 561                 .bandwidth_update = &r100_bandwidth_update,
 562                 .get_vblank_counter = &r100_get_vblank_counter,
 563                 .wait_for_vblank = &r100_wait_for_vblank,
 564                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 565                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 566         },
 567         .copy = {
 568                 .blit = &r100_copy_blit,
 569                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 570                 .dma = &r200_copy_dma,
 571                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 572                 .copy = &r100_copy_blit,
 573                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 574         },
 575         .surface = {
 576                 .set_reg = r100_set_surface_reg,
 577                 .clear_reg = r100_clear_surface_reg,
 578         },
 579         .hpd = {
 580                 .init = &r100_hpd_init,
 581                 .fini = &r100_hpd_fini,
 582                 .sense = &r100_hpd_sense,
 583                 .set_polarity = &r100_hpd_set_polarity,
 584         },
 585         .pm = {
 586                 .misc = &r100_pm_misc,
 587                 .prepare = &r100_pm_prepare,
 588                 .finish = &r100_pm_finish,
 589                 .init_profile = &r100_pm_init_profile,
 590                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 591                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 592                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 593                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 594                 .set_memory_clock = NULL,
 595                 .get_pcie_lanes = NULL,
 596                 .set_pcie_lanes = NULL,
 597                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 598         },
 599         .pflip = {
 600                 .pre_page_flip = &r100_pre_page_flip,
 601                 .page_flip = &r100_page_flip,
 602                 .post_page_flip = &r100_post_page_flip,
 603         },
 604 };
 605
 606 static struct radeon_asic rs600_asic = {
 607         .init = &rs600_init,
 608         .fini = &rs600_fini,
 609         .suspend = &rs600_suspend,
 610         .resume = &rs600_resume,
 611         .vga_set_state = &r100_vga_set_state,
 612         .asic_reset = &rs600_asic_reset,
 613         .ioctl_wait_idle = NULL,
 614         .gui_idle = &r100_gui_idle,
 615         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 616         .gart = {
 617                 .tlb_flush = &rs600_gart_tlb_flush,
 618                 .set_page = &rs600_gart_set_page,
 619         },
 620         .ring = {
 621                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 622         },
 623         .irq = {
 624                 .set = &rs600_irq_set,
 625                 .process = &rs600_irq_process,
 626         },
 627         .display = {
 628                 .bandwidth_update = &rs600_bandwidth_update,
 629                 .get_vblank_counter = &rs600_get_vblank_counter,
 630                 .wait_for_vblank = &avivo_wait_for_vblank,
 631                 .set_backlight_level = &atombios_set_backlight_level,
 632                 .get_backlight_level = &atombios_get_backlight_level,
 633                 .hdmi_enable = &r600_hdmi_enable,
 634                 .hdmi_setmode = &r600_hdmi_setmode,
 635         },
 636         .copy = {
 637                 .blit = &r100_copy_blit,
 638                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 639                 .dma = &r200_copy_dma,
 640                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 641                 .copy = &r100_copy_blit,
 642                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 643         },
 644         .surface = {
 645                 .set_reg = r100_set_surface_reg,
 646                 .clear_reg = r100_clear_surface_reg,
 647         },
 648         .hpd = {
 649                 .init = &rs600_hpd_init,
 650                 .fini = &rs600_hpd_fini,
 651                 .sense = &rs600_hpd_sense,
 652                 .set_polarity = &rs600_hpd_set_polarity,
 653         },
 654         .pm = {
 655                 .misc = &rs600_pm_misc,
 656                 .prepare = &rs600_pm_prepare,
 657                 .finish = &rs600_pm_finish,
 658                 .init_profile = &r420_pm_init_profile,
 659                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 660                 .get_engine_clock = &radeon_atom_get_engine_clock,
 661                 .set_engine_clock = &radeon_atom_set_engine_clock,
 662                 .get_memory_clock = &radeon_atom_get_memory_clock,
 663                 .set_memory_clock = &radeon_atom_set_memory_clock,
 664                 .get_pcie_lanes = NULL,
 665                 .set_pcie_lanes = NULL,
 666                 .set_clock_gating = &radeon_atom_set_clock_gating,
 667         },
 668         .pflip = {
 669                 .pre_page_flip = &rs600_pre_page_flip,
 670                 .page_flip = &rs600_page_flip,
 671                 .post_page_flip = &rs600_post_page_flip,
 672         },
 673 };
 674
 675 static struct radeon_asic rs690_asic = {
 676         .init = &rs690_init,
 677         .fini = &rs690_fini,
 678         .suspend = &rs690_suspend,
 679         .resume = &rs690_resume,
 680         .vga_set_state = &r100_vga_set_state,
 681         .asic_reset = &rs600_asic_reset,
 682         .ioctl_wait_idle = NULL,
 683         .gui_idle = &r100_gui_idle,
 684         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 685         .gart = {
 686                 .tlb_flush = &rs400_gart_tlb_flush,
 687                 .set_page = &rs400_gart_set_page,
 688         },
 689         .ring = {
 690                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 691         },
 692         .irq = {
 693                 .set = &rs600_irq_set,
 694                 .process = &rs600_irq_process,
 695         },
 696         .display = {
 697                 .get_vblank_counter = &rs600_get_vblank_counter,
 698                 .bandwidth_update = &rs690_bandwidth_update,
 699                 .wait_for_vblank = &avivo_wait_for_vblank,
 700                 .set_backlight_level = &atombios_set_backlight_level,
 701                 .get_backlight_level = &atombios_get_backlight_level,
 702                 .hdmi_enable = &r600_hdmi_enable,
 703                 .hdmi_setmode = &r600_hdmi_setmode,
 704         },
 705         .copy = {
 706                 .blit = &r100_copy_blit,
 707                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 708                 .dma = &r200_copy_dma,
 709                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 710                 .copy = &r200_copy_dma,
 711                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 712         },
 713         .surface = {
 714                 .set_reg = r100_set_surface_reg,
 715                 .clear_reg = r100_clear_surface_reg,
 716         },
 717         .hpd = {
 718                 .init = &rs600_hpd_init,
 719                 .fini = &rs600_hpd_fini,
 720                 .sense = &rs600_hpd_sense,
 721                 .set_polarity = &rs600_hpd_set_polarity,
 722         },
 723         .pm = {
 724                 .misc = &rs600_pm_misc,
 725                 .prepare = &rs600_pm_prepare,
 726                 .finish = &rs600_pm_finish,
 727                 .init_profile = &r420_pm_init_profile,
 728                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 729                 .get_engine_clock = &radeon_atom_get_engine_clock,
 730                 .set_engine_clock = &radeon_atom_set_engine_clock,
 731                 .get_memory_clock = &radeon_atom_get_memory_clock,
 732                 .set_memory_clock = &radeon_atom_set_memory_clock,
 733                 .get_pcie_lanes = NULL,
 734                 .set_pcie_lanes = NULL,
 735                 .set_clock_gating = &radeon_atom_set_clock_gating,
 736         },
 737         .pflip = {
 738                 .pre_page_flip = &rs600_pre_page_flip,
 739                 .page_flip = &rs600_page_flip,
 740                 .post_page_flip = &rs600_post_page_flip,
 741         },
 742 };
 743
 744 static struct radeon_asic rv515_asic = {
 745         .init = &rv515_init,
 746         .fini = &rv515_fini,
 747         .suspend = &rv515_suspend,
 748         .resume = &rv515_resume,
 749         .vga_set_state = &r100_vga_set_state,
 750         .asic_reset = &rs600_asic_reset,
 751         .ioctl_wait_idle = NULL,
 752         .gui_idle = &r100_gui_idle,
 753         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 754         .gart = {
 755                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 756                 .set_page = &rv370_pcie_gart_set_page,
 757         },
 758         .ring = {
 759                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 760         },
 761         .irq = {
 762                 .set = &rs600_irq_set,
 763                 .process = &rs600_irq_process,
 764         },
 765         .display = {
 766                 .get_vblank_counter = &rs600_get_vblank_counter,
 767                 .bandwidth_update = &rv515_bandwidth_update,
 768                 .wait_for_vblank = &avivo_wait_for_vblank,
 769                 .set_backlight_level = &atombios_set_backlight_level,
 770                 .get_backlight_level = &atombios_get_backlight_level,
 771         },
 772         .copy = {
 773                 .blit = &r100_copy_blit,
 774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 775                 .dma = &r200_copy_dma,
 776                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 777                 .copy = &r100_copy_blit,
 778                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 779         },
 780         .surface = {
 781                 .set_reg = r100_set_surface_reg,
 782                 .clear_reg = r100_clear_surface_reg,
 783         },
 784         .hpd = {
 785                 .init = &rs600_hpd_init,
 786                 .fini = &rs600_hpd_fini,
 787                 .sense = &rs600_hpd_sense,
 788                 .set_polarity = &rs600_hpd_set_polarity,
 789         },
 790         .pm = {
 791                 .misc = &rs600_pm_misc,
 792                 .prepare = &rs600_pm_prepare,
 793                 .finish = &rs600_pm_finish,
 794                 .init_profile = &r420_pm_init_profile,
 795                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 796                 .get_engine_clock = &radeon_atom_get_engine_clock,
 797                 .set_engine_clock = &radeon_atom_set_engine_clock,
 798                 .get_memory_clock = &radeon_atom_get_memory_clock,
 799                 .set_memory_clock = &radeon_atom_set_memory_clock,
 800                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 801                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 802                 .set_clock_gating = &radeon_atom_set_clock_gating,
 803         },
 804         .pflip = {
 805                 .pre_page_flip = &rs600_pre_page_flip,
 806                 .page_flip = &rs600_page_flip,
 807                 .post_page_flip = &rs600_post_page_flip,
 808         },
 809 };
 810
 811 static struct radeon_asic r520_asic = {
 812         .init = &r520_init,
 813         .fini = &rv515_fini,
 814         .suspend = &rv515_suspend,
 815         .resume = &r520_resume,
 816         .vga_set_state = &r100_vga_set_state,
 817         .asic_reset = &rs600_asic_reset,
 818         .ioctl_wait_idle = NULL,
 819         .gui_idle = &r100_gui_idle,
 820         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 821         .gart = {
 822                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 823                 .set_page = &rv370_pcie_gart_set_page,
 824         },
 825         .ring = {
 826                 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
 827         },
 828         .irq = {
 829                 .set = &rs600_irq_set,
 830                 .process = &rs600_irq_process,
 831         },
 832         .display = {
 833                 .bandwidth_update = &rv515_bandwidth_update,
 834                 .get_vblank_counter = &rs600_get_vblank_counter,
 835                 .wait_for_vblank = &avivo_wait_for_vblank,
 836                 .set_backlight_level = &atombios_set_backlight_level,
 837                 .get_backlight_level = &atombios_get_backlight_level,
 838         },
 839         .copy = {
 840                 .blit = &r100_copy_blit,
 841                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 842                 .dma = &r200_copy_dma,
 843                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 844                 .copy = &r100_copy_blit,
 845                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 846         },
 847         .surface = {
 848                 .set_reg = r100_set_surface_reg,
 849                 .clear_reg = r100_clear_surface_reg,
 850         },
 851         .hpd = {
 852                 .init = &rs600_hpd_init,
 853                 .fini = &rs600_hpd_fini,
 854                 .sense = &rs600_hpd_sense,
 855                 .set_polarity = &rs600_hpd_set_polarity,
 856         },
 857         .pm = {
 858                 .misc = &rs600_pm_misc,
 859                 .prepare = &rs600_pm_prepare,
 860                 .finish = &rs600_pm_finish,
 861                 .init_profile = &r420_pm_init_profile,
 862                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 863                 .get_engine_clock = &radeon_atom_get_engine_clock,
 864                 .set_engine_clock = &radeon_atom_set_engine_clock,
 865                 .get_memory_clock = &radeon_atom_get_memory_clock,
 866                 .set_memory_clock = &radeon_atom_set_memory_clock,
 867                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 868                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 869                 .set_clock_gating = &radeon_atom_set_clock_gating,
 870         },
 871         .pflip = {
 872                 .pre_page_flip = &rs600_pre_page_flip,
 873                 .page_flip = &rs600_page_flip,
 874                 .post_page_flip = &rs600_post_page_flip,
 875         },
 876 };
 877
 878 static struct radeon_asic_ring r600_gfx_ring = {
 879         .ib_execute = &r600_ring_ib_execute,
 880         .emit_fence = &r600_fence_ring_emit,
 881         .emit_semaphore = &r600_semaphore_ring_emit,
 882         .cs_parse = &r600_cs_parse,
 883         .ring_test = &r600_ring_test,
 884         .ib_test = &r600_ib_test,
 885         .is_lockup = &r600_gfx_is_lockup,
 886         .get_rptr = &radeon_ring_generic_get_rptr,
 887         .get_wptr = &radeon_ring_generic_get_wptr,
 888         .set_wptr = &radeon_ring_generic_set_wptr,
 889 };
 890
 891 static struct radeon_asic_ring r600_dma_ring = {
 892         .ib_execute = &r600_dma_ring_ib_execute,
 893         .emit_fence = &r600_dma_fence_ring_emit,
 894         .emit_semaphore = &r600_dma_semaphore_ring_emit,
 895         .cs_parse = &r600_dma_cs_parse,
 896         .ring_test = &r600_dma_ring_test,
 897         .ib_test = &r600_dma_ib_test,
 898         .is_lockup = &r600_dma_is_lockup,
 899         .get_rptr = &r600_dma_get_rptr,
 900         .get_wptr = &r600_dma_get_wptr,
 901         .set_wptr = &r600_dma_set_wptr,
 902 };
 903
 904 static struct radeon_asic r600_asic = {
 905         .init = &r600_init,
 906         .fini = &r600_fini,
 907         .suspend = &r600_suspend,
 908         .resume = &r600_resume,
 909         .vga_set_state = &r600_vga_set_state,
 910         .asic_reset = &r600_asic_reset,
 911         .ioctl_wait_idle = r600_ioctl_wait_idle,
 912         .gui_idle = &r600_gui_idle,
 913         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 914         .get_xclk = &r600_get_xclk,
 915         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 916         .gart = {
 917                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 918                 .set_page = &rs600_gart_set_page,
 919         },
 920         .ring = {
 921                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 922                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 923         },
 924         .irq = {
 925                 .set = &r600_irq_set,
 926                 .process = &r600_irq_process,
 927         },
 928         .display = {
 929                 .bandwidth_update = &rv515_bandwidth_update,
 930                 .get_vblank_counter = &rs600_get_vblank_counter,
 931                 .wait_for_vblank = &avivo_wait_for_vblank,
 932                 .set_backlight_level = &atombios_set_backlight_level,
 933                 .get_backlight_level = &atombios_get_backlight_level,
 934                 .hdmi_enable = &r600_hdmi_enable,
 935                 .hdmi_setmode = &r600_hdmi_setmode,
 936         },
 937         .copy = {
 938                 .blit = &r600_copy_cpdma,
 939                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 940                 .dma = &r600_copy_dma,
 941                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
 942                 .copy = &r600_copy_cpdma,
 943                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 944         },
 945         .surface = {
 946                 .set_reg = r600_set_surface_reg,
 947                 .clear_reg = r600_clear_surface_reg,
 948         },
 949         .hpd = {
 950                 .init = &r600_hpd_init,
 951                 .fini = &r600_hpd_fini,
 952                 .sense = &r600_hpd_sense,
 953                 .set_polarity = &r600_hpd_set_polarity,
 954         },
 955         .pm = {
 956                 .misc = &r600_pm_misc,
 957                 .prepare = &rs600_pm_prepare,
 958                 .finish = &rs600_pm_finish,
 959                 .init_profile = &r600_pm_init_profile,
 960                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 961                 .get_engine_clock = &radeon_atom_get_engine_clock,
 962                 .set_engine_clock = &radeon_atom_set_engine_clock,
 963                 .get_memory_clock = &radeon_atom_get_memory_clock,
 964                 .set_memory_clock = &radeon_atom_set_memory_clock,
 965                 .get_pcie_lanes = &r600_get_pcie_lanes,
 966                 .set_pcie_lanes = &r600_set_pcie_lanes,
 967                 .set_clock_gating = NULL,
 968                 .get_temperature = &rv6xx_get_temp,
 969         },
 970         .pflip = {
 971                 .pre_page_flip = &rs600_pre_page_flip,
 972                 .page_flip = &rs600_page_flip,
 973                 .post_page_flip = &rs600_post_page_flip,
 974         },
 975 };
 976
 977 static struct radeon_asic rv6xx_asic = {
 978         .init = &r600_init,
 979         .fini = &r600_fini,
 980         .suspend = &r600_suspend,
 981         .resume = &r600_resume,
 982         .vga_set_state = &r600_vga_set_state,
 983         .asic_reset = &r600_asic_reset,
 984         .ioctl_wait_idle = r600_ioctl_wait_idle,
 985         .gui_idle = &r600_gui_idle,
 986         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 987         .get_xclk = &r600_get_xclk,
 988         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 989         .gart = {
 990                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 991                 .set_page = &rs600_gart_set_page,
 992         },
 993         .ring = {
 994                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
 995                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
 996         },
 997         .irq = {
 998                 .set = &r600_irq_set,
 999                 .process = &r600_irq_process,
1000         },
1001         .display = {
1002                 .bandwidth_update = &rv515_bandwidth_update,
1003                 .get_vblank_counter = &rs600_get_vblank_counter,
1004                 .wait_for_vblank = &avivo_wait_for_vblank,
1005                 .set_backlight_level = &atombios_set_backlight_level,
1006                 .get_backlight_level = &atombios_get_backlight_level,
1007         },
1008         .copy = {
1009                 .blit = &r600_copy_cpdma,
1010                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1011                 .dma = &r600_copy_dma,
1012                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1013                 .copy = &r600_copy_cpdma,
1014                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1015         },
1016         .surface = {
1017                 .set_reg = r600_set_surface_reg,
1018                 .clear_reg = r600_clear_surface_reg,
1019         },
1020         .hpd = {
1021                 .init = &r600_hpd_init,
1022                 .fini = &r600_hpd_fini,
1023                 .sense = &r600_hpd_sense,
1024                 .set_polarity = &r600_hpd_set_polarity,
1025         },
1026         .pm = {
1027                 .misc = &r600_pm_misc,
1028                 .prepare = &rs600_pm_prepare,
1029                 .finish = &rs600_pm_finish,
1030                 .init_profile = &r600_pm_init_profile,
1031                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1032                 .get_engine_clock = &radeon_atom_get_engine_clock,
1033                 .set_engine_clock = &radeon_atom_set_engine_clock,
1034                 .get_memory_clock = &radeon_atom_get_memory_clock,
1035                 .set_memory_clock = &radeon_atom_set_memory_clock,
1036                 .get_pcie_lanes = &r600_get_pcie_lanes,
1037                 .set_pcie_lanes = &r600_set_pcie_lanes,
1038                 .set_clock_gating = NULL,
1039                 .get_temperature = &rv6xx_get_temp,
1040                 .set_uvd_clocks = &r600_set_uvd_clocks,
1041         },
1042         .dpm = {
1043                 .init = &rv6xx_dpm_init,
1044                 .setup_asic = &rv6xx_setup_asic,
1045                 .enable = &rv6xx_dpm_enable,
1046                 .disable = &rv6xx_dpm_disable,
1047                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1048                 .set_power_state = &rv6xx_dpm_set_power_state,
1049                 .post_set_power_state = &r600_dpm_post_set_power_state,
1050                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1051                 .fini = &rv6xx_dpm_fini,
1052                 .get_sclk = &rv6xx_dpm_get_sclk,
1053                 .get_mclk = &rv6xx_dpm_get_mclk,
1054                 .print_power_state = &rv6xx_dpm_print_power_state,
1055                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1056                 .force_performance_level = &rv6xx_dpm_force_performance_level,
1057         },
1058         .pflip = {
1059                 .pre_page_flip = &rs600_pre_page_flip,
1060                 .page_flip = &rs600_page_flip,
1061                 .post_page_flip = &rs600_post_page_flip,
1062         },
1063 };
1064
1065 static struct radeon_asic rs780_asic = {
1066         .init = &r600_init,
1067         .fini = &r600_fini,
1068         .suspend = &r600_suspend,
1069         .resume = &r600_resume,
1070         .vga_set_state = &r600_vga_set_state,
1071         .asic_reset = &r600_asic_reset,
1072         .ioctl_wait_idle = r600_ioctl_wait_idle,
1073         .gui_idle = &r600_gui_idle,
1074         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1075         .get_xclk = &r600_get_xclk,
1076         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1077         .gart = {
1078                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1079                 .set_page = &rs600_gart_set_page,
1080         },
1081         .ring = {
1082                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1083                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1084         },
1085         .irq = {
1086                 .set = &r600_irq_set,
1087                 .process = &r600_irq_process,
1088         },
1089         .display = {
1090                 .bandwidth_update = &rs690_bandwidth_update,
1091                 .get_vblank_counter = &rs600_get_vblank_counter,
1092                 .wait_for_vblank = &avivo_wait_for_vblank,
1093                 .set_backlight_level = &atombios_set_backlight_level,
1094                 .get_backlight_level = &atombios_get_backlight_level,
1095                 .hdmi_enable = &r600_hdmi_enable,
1096                 .hdmi_setmode = &r600_hdmi_setmode,
1097         },
1098         .copy = {
1099                 .blit = &r600_copy_cpdma,
1100                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1101                 .dma = &r600_copy_dma,
1102                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1103                 .copy = &r600_copy_cpdma,
1104                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1105         },
1106         .surface = {
1107                 .set_reg = r600_set_surface_reg,
1108                 .clear_reg = r600_clear_surface_reg,
1109         },
1110         .hpd = {
1111                 .init = &r600_hpd_init,
1112                 .fini = &r600_hpd_fini,
1113                 .sense = &r600_hpd_sense,
1114                 .set_polarity = &r600_hpd_set_polarity,
1115         },
1116         .pm = {
1117                 .misc = &r600_pm_misc,
1118                 .prepare = &rs600_pm_prepare,
1119                 .finish = &rs600_pm_finish,
1120                 .init_profile = &rs780_pm_init_profile,
1121                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1122                 .get_engine_clock = &radeon_atom_get_engine_clock,
1123                 .set_engine_clock = &radeon_atom_set_engine_clock,
1124                 .get_memory_clock = NULL,
1125                 .set_memory_clock = NULL,
1126                 .get_pcie_lanes = NULL,
1127                 .set_pcie_lanes = NULL,
1128                 .set_clock_gating = NULL,
1129                 .get_temperature = &rv6xx_get_temp,
1130                 .set_uvd_clocks = &r600_set_uvd_clocks,
1131         },
1132         .dpm = {
1133                 .init = &rs780_dpm_init,
1134                 .setup_asic = &rs780_dpm_setup_asic,
1135                 .enable = &rs780_dpm_enable,
1136                 .disable = &rs780_dpm_disable,
1137                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1138                 .set_power_state = &rs780_dpm_set_power_state,
1139                 .post_set_power_state = &r600_dpm_post_set_power_state,
1140                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1141                 .fini = &rs780_dpm_fini,
1142                 .get_sclk = &rs780_dpm_get_sclk,
1143                 .get_mclk = &rs780_dpm_get_mclk,
1144                 .print_power_state = &rs780_dpm_print_power_state,
1145                 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1146                 .force_performance_level = &rs780_dpm_force_performance_level,
1147         },
1148         .pflip = {
1149                 .pre_page_flip = &rs600_pre_page_flip,
1150                 .page_flip = &rs600_page_flip,
1151                 .post_page_flip = &rs600_post_page_flip,
1152         },
1153 };
1154
1155 static struct radeon_asic_ring rv770_uvd_ring = {
1156         .ib_execute = &uvd_v1_0_ib_execute,
1157         .emit_fence = &uvd_v2_2_fence_emit,
1158         .emit_semaphore = &uvd_v1_0_semaphore_emit,
1159         .cs_parse = &radeon_uvd_cs_parse,
1160         .ring_test = &uvd_v1_0_ring_test,
1161         .ib_test = &uvd_v1_0_ib_test,
1162         .is_lockup = &radeon_ring_test_lockup,
1163         .get_rptr = &uvd_v1_0_get_rptr,
1164         .get_wptr = &uvd_v1_0_get_wptr,
1165         .set_wptr = &uvd_v1_0_set_wptr,
1166 };
1167
1168 static struct radeon_asic rv770_asic = {
1169         .init = &rv770_init,
1170         .fini = &rv770_fini,
1171         .suspend = &rv770_suspend,
1172         .resume = &rv770_resume,
1173         .asic_reset = &r600_asic_reset,
1174         .vga_set_state = &r600_vga_set_state,
1175         .ioctl_wait_idle = r600_ioctl_wait_idle,
1176         .gui_idle = &r600_gui_idle,
1177         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1178         .get_xclk = &rv770_get_xclk,
1179         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1180         .gart = {
1181                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1182                 .set_page = &rs600_gart_set_page,
1183         },
1184         .ring = {
1185                 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1186                 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1187                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1188         },
1189         .irq = {
1190                 .set = &r600_irq_set,
1191                 .process = &r600_irq_process,
1192         },
1193         .display = {
1194                 .bandwidth_update = &rv515_bandwidth_update,
1195                 .get_vblank_counter = &rs600_get_vblank_counter,
1196                 .wait_for_vblank = &avivo_wait_for_vblank,
1197                 .set_backlight_level = &atombios_set_backlight_level,
1198                 .get_backlight_level = &atombios_get_backlight_level,
1199                 .hdmi_enable = &r600_hdmi_enable,
1200                 .hdmi_setmode = &r600_hdmi_setmode,
1201         },
1202         .copy = {
1203                 .blit = &r600_copy_cpdma,
1204                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1205                 .dma = &rv770_copy_dma,
1206                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1207                 .copy = &rv770_copy_dma,
1208                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1209         },
1210         .surface = {
1211                 .set_reg = r600_set_surface_reg,
1212                 .clear_reg = r600_clear_surface_reg,
1213         },
1214         .hpd = {
1215                 .init = &r600_hpd_init,
1216                 .fini = &r600_hpd_fini,
1217                 .sense = &r600_hpd_sense,
1218                 .set_polarity = &r600_hpd_set_polarity,
1219         },
1220         .pm = {
1221                 .misc = &rv770_pm_misc,
1222                 .prepare = &rs600_pm_prepare,
1223                 .finish = &rs600_pm_finish,
1224                 .init_profile = &r600_pm_init_profile,
1225                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1226                 .get_engine_clock = &radeon_atom_get_engine_clock,
1227                 .set_engine_clock = &radeon_atom_set_engine_clock,
1228                 .get_memory_clock = &radeon_atom_get_memory_clock,
1229                 .set_memory_clock = &radeon_atom_set_memory_clock,
1230                 .get_pcie_lanes = &r600_get_pcie_lanes,
1231                 .set_pcie_lanes = &r600_set_pcie_lanes,
1232                 .set_clock_gating = &radeon_atom_set_clock_gating,
1233                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1234                 .get_temperature = &rv770_get_temp,
1235         },
1236         .dpm = {
1237                 .init = &rv770_dpm_init,
1238                 .setup_asic = &rv770_dpm_setup_asic,
1239                 .enable = &rv770_dpm_enable,
1240                 .disable = &rv770_dpm_disable,
1241                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1242                 .set_power_state = &rv770_dpm_set_power_state,
1243                 .post_set_power_state = &r600_dpm_post_set_power_state,
1244                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1245                 .fini = &rv770_dpm_fini,
1246                 .get_sclk = &rv770_dpm_get_sclk,
1247                 .get_mclk = &rv770_dpm_get_mclk,
1248                 .print_power_state = &rv770_dpm_print_power_state,
1249                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1250                 .force_performance_level = &rv770_dpm_force_performance_level,
1251                 .vblank_too_short = &rv770_dpm_vblank_too_short,
1252         },
1253         .pflip = {
1254                 .pre_page_flip = &rs600_pre_page_flip,
1255                 .page_flip = &rv770_page_flip,
1256                 .post_page_flip = &rs600_post_page_flip,
1257         },
1258 };
1259
1260 static struct radeon_asic_ring evergreen_gfx_ring = {
1261         .ib_execute = &evergreen_ring_ib_execute,
1262         .emit_fence = &r600_fence_ring_emit,
1263         .emit_semaphore = &r600_semaphore_ring_emit,
1264         .cs_parse = &evergreen_cs_parse,
1265         .ring_test = &r600_ring_test,
1266         .ib_test = &r600_ib_test,
1267         .is_lockup = &evergreen_gfx_is_lockup,
1268         .get_rptr = &radeon_ring_generic_get_rptr,
1269         .get_wptr = &radeon_ring_generic_get_wptr,
1270         .set_wptr = &radeon_ring_generic_set_wptr,
1271 };
1272
1273 static struct radeon_asic_ring evergreen_dma_ring = {
1274         .ib_execute = &evergreen_dma_ring_ib_execute,
1275         .emit_fence = &evergreen_dma_fence_ring_emit,
1276         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1277         .cs_parse = &evergreen_dma_cs_parse,
1278         .ring_test = &r600_dma_ring_test,
1279         .ib_test = &r600_dma_ib_test,
1280         .is_lockup = &evergreen_dma_is_lockup,
1281         .get_rptr = &r600_dma_get_rptr,
1282         .get_wptr = &r600_dma_get_wptr,
1283         .set_wptr = &r600_dma_set_wptr,
1284 };
1285
1286 static struct radeon_asic evergreen_asic = {
1287         .init = &evergreen_init,
1288         .fini = &evergreen_fini,
1289         .suspend = &evergreen_suspend,
1290         .resume = &evergreen_resume,
1291         .asic_reset = &evergreen_asic_reset,
1292         .vga_set_state = &r600_vga_set_state,
1293         .ioctl_wait_idle = r600_ioctl_wait_idle,
1294         .gui_idle = &r600_gui_idle,
1295         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1296         .get_xclk = &rv770_get_xclk,
1297         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1298         .gart = {
1299                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1300                 .set_page = &rs600_gart_set_page,
1301         },
1302         .ring = {
1303                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1304                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1305                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1306         },
1307         .irq = {
1308                 .set = &evergreen_irq_set,
1309                 .process = &evergreen_irq_process,
1310         },
1311         .display = {
1312                 .bandwidth_update = &evergreen_bandwidth_update,
1313                 .get_vblank_counter = &evergreen_get_vblank_counter,
1314                 .wait_for_vblank = &dce4_wait_for_vblank,
1315                 .set_backlight_level = &atombios_set_backlight_level,
1316                 .get_backlight_level = &atombios_get_backlight_level,
1317                 .hdmi_enable = &evergreen_hdmi_enable,
1318                 .hdmi_setmode = &evergreen_hdmi_setmode,
1319         },
1320         .copy = {
1321                 .blit = &r600_copy_cpdma,
1322                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1323                 .dma = &evergreen_copy_dma,
1324                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1325                 .copy = &evergreen_copy_dma,
1326                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1327         },
1328         .surface = {
1329                 .set_reg = r600_set_surface_reg,
1330                 .clear_reg = r600_clear_surface_reg,
1331         },
1332         .hpd = {
1333                 .init = &evergreen_hpd_init,
1334                 .fini = &evergreen_hpd_fini,
1335                 .sense = &evergreen_hpd_sense,
1336                 .set_polarity = &evergreen_hpd_set_polarity,
1337         },
1338         .pm = {
1339                 .misc = &evergreen_pm_misc,
1340                 .prepare = &evergreen_pm_prepare,
1341                 .finish = &evergreen_pm_finish,
1342                 .init_profile = &r600_pm_init_profile,
1343                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1344                 .get_engine_clock = &radeon_atom_get_engine_clock,
1345                 .set_engine_clock = &radeon_atom_set_engine_clock,
1346                 .get_memory_clock = &radeon_atom_get_memory_clock,
1347                 .set_memory_clock = &radeon_atom_set_memory_clock,
1348                 .get_pcie_lanes = &r600_get_pcie_lanes,
1349                 .set_pcie_lanes = &r600_set_pcie_lanes,
1350                 .set_clock_gating = NULL,
1351                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1352                 .get_temperature = &evergreen_get_temp,
1353         },
1354         .dpm = {
1355                 .init = &cypress_dpm_init,
1356                 .setup_asic = &cypress_dpm_setup_asic,
1357                 .enable = &cypress_dpm_enable,
1358                 .disable = &cypress_dpm_disable,
1359                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1360                 .set_power_state = &cypress_dpm_set_power_state,
1361                 .post_set_power_state = &r600_dpm_post_set_power_state,
1362                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1363                 .fini = &cypress_dpm_fini,
1364                 .get_sclk = &rv770_dpm_get_sclk,
1365                 .get_mclk = &rv770_dpm_get_mclk,
1366                 .print_power_state = &rv770_dpm_print_power_state,
1367                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1368                 .force_performance_level = &rv770_dpm_force_performance_level,
1369                 .vblank_too_short = &cypress_dpm_vblank_too_short,
1370         },
1371         .pflip = {
1372                 .pre_page_flip = &evergreen_pre_page_flip,
1373                 .page_flip = &evergreen_page_flip,
1374                 .post_page_flip = &evergreen_post_page_flip,
1375         },
1376 };
1377
1378 static struct radeon_asic sumo_asic = {
1379         .init = &evergreen_init,
1380         .fini = &evergreen_fini,
1381         .suspend = &evergreen_suspend,
1382         .resume = &evergreen_resume,
1383         .asic_reset = &evergreen_asic_reset,
1384         .vga_set_state = &r600_vga_set_state,
1385         .ioctl_wait_idle = r600_ioctl_wait_idle,
1386         .gui_idle = &r600_gui_idle,
1387         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1388         .get_xclk = &r600_get_xclk,
1389         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1390         .gart = {
1391                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1392                 .set_page = &rs600_gart_set_page,
1393         },
1394         .ring = {
1395                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1396                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1397                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1398         },
1399         .irq = {
1400                 .set = &evergreen_irq_set,
1401                 .process = &evergreen_irq_process,
1402         },
1403         .display = {
1404                 .bandwidth_update = &evergreen_bandwidth_update,
1405                 .get_vblank_counter = &evergreen_get_vblank_counter,
1406                 .wait_for_vblank = &dce4_wait_for_vblank,
1407                 .set_backlight_level = &atombios_set_backlight_level,
1408                 .get_backlight_level = &atombios_get_backlight_level,
1409                 .hdmi_enable = &evergreen_hdmi_enable,
1410                 .hdmi_setmode = &evergreen_hdmi_setmode,
1411         },
1412         .copy = {
1413                 .blit = &r600_copy_cpdma,
1414                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1415                 .dma = &evergreen_copy_dma,
1416                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1417                 .copy = &evergreen_copy_dma,
1418                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1419         },
1420         .surface = {
1421                 .set_reg = r600_set_surface_reg,
1422                 .clear_reg = r600_clear_surface_reg,
1423         },
1424         .hpd = {
1425                 .init = &evergreen_hpd_init,
1426                 .fini = &evergreen_hpd_fini,
1427                 .sense = &evergreen_hpd_sense,
1428                 .set_polarity = &evergreen_hpd_set_polarity,
1429         },
1430         .pm = {
1431                 .misc = &evergreen_pm_misc,
1432                 .prepare = &evergreen_pm_prepare,
1433                 .finish = &evergreen_pm_finish,
1434                 .init_profile = &sumo_pm_init_profile,
1435                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1436                 .get_engine_clock = &radeon_atom_get_engine_clock,
1437                 .set_engine_clock = &radeon_atom_set_engine_clock,
1438                 .get_memory_clock = NULL,
1439                 .set_memory_clock = NULL,
1440                 .get_pcie_lanes = NULL,
1441                 .set_pcie_lanes = NULL,
1442                 .set_clock_gating = NULL,
1443                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1444                 .get_temperature = &sumo_get_temp,
1445         },
1446         .dpm = {
1447                 .init = &sumo_dpm_init,
1448                 .setup_asic = &sumo_dpm_setup_asic,
1449                 .enable = &sumo_dpm_enable,
1450                 .disable = &sumo_dpm_disable,
1451                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1452                 .set_power_state = &sumo_dpm_set_power_state,
1453                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1454                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1455                 .fini = &sumo_dpm_fini,
1456                 .get_sclk = &sumo_dpm_get_sclk,
1457                 .get_mclk = &sumo_dpm_get_mclk,
1458                 .print_power_state = &sumo_dpm_print_power_state,
1459                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1460                 .force_performance_level = &sumo_dpm_force_performance_level,
1461         },
1462         .pflip = {
1463                 .pre_page_flip = &evergreen_pre_page_flip,
1464                 .page_flip = &evergreen_page_flip,
1465                 .post_page_flip = &evergreen_post_page_flip,
1466         },
1467 };
1468
1469 static struct radeon_asic btc_asic = {
1470         .init = &evergreen_init,
1471         .fini = &evergreen_fini,
1472         .suspend = &evergreen_suspend,
1473         .resume = &evergreen_resume,
1474         .asic_reset = &evergreen_asic_reset,
1475         .vga_set_state = &r600_vga_set_state,
1476         .ioctl_wait_idle = r600_ioctl_wait_idle,
1477         .gui_idle = &r600_gui_idle,
1478         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1479         .get_xclk = &rv770_get_xclk,
1480         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1481         .gart = {
1482                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1483                 .set_page = &rs600_gart_set_page,
1484         },
1485         .ring = {
1486                 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1487                 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1488                 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1489         },
1490         .irq = {
1491                 .set = &evergreen_irq_set,
1492                 .process = &evergreen_irq_process,
1493         },
1494         .display = {
1495                 .bandwidth_update = &evergreen_bandwidth_update,
1496                 .get_vblank_counter = &evergreen_get_vblank_counter,
1497                 .wait_for_vblank = &dce4_wait_for_vblank,
1498                 .set_backlight_level = &atombios_set_backlight_level,
1499                 .get_backlight_level = &atombios_get_backlight_level,
1500                 .hdmi_enable = &evergreen_hdmi_enable,
1501                 .hdmi_setmode = &evergreen_hdmi_setmode,
1502         },
1503         .copy = {
1504                 .blit = &r600_copy_cpdma,
1505                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1506                 .dma = &evergreen_copy_dma,
1507                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1508                 .copy = &evergreen_copy_dma,
1509                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1510         },
1511         .surface = {
1512                 .set_reg = r600_set_surface_reg,
1513                 .clear_reg = r600_clear_surface_reg,
1514         },
1515         .hpd = {
1516                 .init = &evergreen_hpd_init,
1517                 .fini = &evergreen_hpd_fini,
1518                 .sense = &evergreen_hpd_sense,
1519                 .set_polarity = &evergreen_hpd_set_polarity,
1520         },
1521         .pm = {
1522                 .misc = &evergreen_pm_misc,
1523                 .prepare = &evergreen_pm_prepare,
1524                 .finish = &evergreen_pm_finish,
1525                 .init_profile = &btc_pm_init_profile,
1526                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1527                 .get_engine_clock = &radeon_atom_get_engine_clock,
1528                 .set_engine_clock = &radeon_atom_set_engine_clock,
1529                 .get_memory_clock = &radeon_atom_get_memory_clock,
1530                 .set_memory_clock = &radeon_atom_set_memory_clock,
1531                 .get_pcie_lanes = &r600_get_pcie_lanes,
1532                 .set_pcie_lanes = &r600_set_pcie_lanes,
1533                 .set_clock_gating = NULL,
1534                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1535                 .get_temperature = &evergreen_get_temp,
1536         },
1537         .dpm = {
1538                 .init = &btc_dpm_init,
1539                 .setup_asic = &btc_dpm_setup_asic,
1540                 .enable = &btc_dpm_enable,
1541                 .disable = &btc_dpm_disable,
1542                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1543                 .set_power_state = &btc_dpm_set_power_state,
1544                 .post_set_power_state = &btc_dpm_post_set_power_state,
1545                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1546                 .fini = &btc_dpm_fini,
1547                 .get_sclk = &btc_dpm_get_sclk,
1548                 .get_mclk = &btc_dpm_get_mclk,
1549                 .print_power_state = &rv770_dpm_print_power_state,
1550                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1551                 .force_performance_level = &rv770_dpm_force_performance_level,
1552                 .vblank_too_short = &btc_dpm_vblank_too_short,
1553         },
1554         .pflip = {
1555                 .pre_page_flip = &evergreen_pre_page_flip,
1556                 .page_flip = &evergreen_page_flip,
1557                 .post_page_flip = &evergreen_post_page_flip,
1558         },
1559 };
1560
1561 static struct radeon_asic_ring cayman_gfx_ring = {
1562         .ib_execute = &cayman_ring_ib_execute,
1563         .ib_parse = &evergreen_ib_parse,
1564         .emit_fence = &cayman_fence_ring_emit,
1565         .emit_semaphore = &r600_semaphore_ring_emit,
1566         .cs_parse = &evergreen_cs_parse,
1567         .ring_test = &r600_ring_test,
1568         .ib_test = &r600_ib_test,
1569         .is_lockup = &cayman_gfx_is_lockup,
1570         .vm_flush = &cayman_vm_flush,
1571         .get_rptr = &radeon_ring_generic_get_rptr,
1572         .get_wptr = &radeon_ring_generic_get_wptr,
1573         .set_wptr = &radeon_ring_generic_set_wptr,
1574 };
1575
1576 static struct radeon_asic_ring cayman_dma_ring = {
1577         .ib_execute = &cayman_dma_ring_ib_execute,
1578         .ib_parse = &evergreen_dma_ib_parse,
1579         .emit_fence = &evergreen_dma_fence_ring_emit,
1580         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1581         .cs_parse = &evergreen_dma_cs_parse,
1582         .ring_test = &r600_dma_ring_test,
1583         .ib_test = &r600_dma_ib_test,
1584         .is_lockup = &cayman_dma_is_lockup,
1585         .vm_flush = &cayman_dma_vm_flush,
1586         .get_rptr = &r600_dma_get_rptr,
1587         .get_wptr = &r600_dma_get_wptr,
1588         .set_wptr = &r600_dma_set_wptr
1589 };
1590
1591 static struct radeon_asic_ring cayman_uvd_ring = {
1592         .ib_execute = &uvd_v1_0_ib_execute,
1593         .emit_fence = &uvd_v2_2_fence_emit,
1594         .emit_semaphore = &uvd_v3_1_semaphore_emit,
1595         .cs_parse = &radeon_uvd_cs_parse,
1596         .ring_test = &uvd_v1_0_ring_test,
1597         .ib_test = &uvd_v1_0_ib_test,
1598         .is_lockup = &radeon_ring_test_lockup,
1599         .get_rptr = &uvd_v1_0_get_rptr,
1600         .get_wptr = &uvd_v1_0_get_wptr,
1601         .set_wptr = &uvd_v1_0_set_wptr,
1602 };
1603
1604 static struct radeon_asic cayman_asic = {
1605         .init = &cayman_init,
1606         .fini = &cayman_fini,
1607         .suspend = &cayman_suspend,
1608         .resume = &cayman_resume,
1609         .asic_reset = &cayman_asic_reset,
1610         .vga_set_state = &r600_vga_set_state,
1611         .ioctl_wait_idle = r600_ioctl_wait_idle,
1612         .gui_idle = &r600_gui_idle,
1613         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1614         .get_xclk = &rv770_get_xclk,
1615         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1616         .gart = {
1617                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1618                 .set_page = &rs600_gart_set_page,
1619         },
1620         .vm = {
1621                 .init = &cayman_vm_init,
1622                 .fini = &cayman_vm_fini,
1623                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1624                 .set_page = &cayman_vm_set_page,
1625         },
1626         .ring = {
1627                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1628                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1629                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1630                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1631                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1632                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1633         },
1634         .irq = {
1635                 .set = &evergreen_irq_set,
1636                 .process = &evergreen_irq_process,
1637         },
1638         .display = {
1639                 .bandwidth_update = &evergreen_bandwidth_update,
1640                 .get_vblank_counter = &evergreen_get_vblank_counter,
1641                 .wait_for_vblank = &dce4_wait_for_vblank,
1642                 .set_backlight_level = &atombios_set_backlight_level,
1643                 .get_backlight_level = &atombios_get_backlight_level,
1644                 .hdmi_enable = &evergreen_hdmi_enable,
1645                 .hdmi_setmode = &evergreen_hdmi_setmode,
1646         },
1647         .copy = {
1648                 .blit = &r600_copy_cpdma,
1649                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1650                 .dma = &evergreen_copy_dma,
1651                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1652                 .copy = &evergreen_copy_dma,
1653                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1654         },
1655         .surface = {
1656                 .set_reg = r600_set_surface_reg,
1657                 .clear_reg = r600_clear_surface_reg,
1658         },
1659         .hpd = {
1660                 .init = &evergreen_hpd_init,
1661                 .fini = &evergreen_hpd_fini,
1662                 .sense = &evergreen_hpd_sense,
1663                 .set_polarity = &evergreen_hpd_set_polarity,
1664         },
1665         .pm = {
1666                 .misc = &evergreen_pm_misc,
1667                 .prepare = &evergreen_pm_prepare,
1668                 .finish = &evergreen_pm_finish,
1669                 .init_profile = &btc_pm_init_profile,
1670                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1671                 .get_engine_clock = &radeon_atom_get_engine_clock,
1672                 .set_engine_clock = &radeon_atom_set_engine_clock,
1673                 .get_memory_clock = &radeon_atom_get_memory_clock,
1674                 .set_memory_clock = &radeon_atom_set_memory_clock,
1675                 .get_pcie_lanes = &r600_get_pcie_lanes,
1676                 .set_pcie_lanes = &r600_set_pcie_lanes,
1677                 .set_clock_gating = NULL,
1678                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1679                 .get_temperature = &evergreen_get_temp,
1680         },
1681         .dpm = {
1682                 .init = &ni_dpm_init,
1683                 .setup_asic = &ni_dpm_setup_asic,
1684                 .enable = &ni_dpm_enable,
1685                 .disable = &ni_dpm_disable,
1686                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1687                 .set_power_state = &ni_dpm_set_power_state,
1688                 .post_set_power_state = &ni_dpm_post_set_power_state,
1689                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1690                 .fini = &ni_dpm_fini,
1691                 .get_sclk = &ni_dpm_get_sclk,
1692                 .get_mclk = &ni_dpm_get_mclk,
1693                 .print_power_state = &ni_dpm_print_power_state,
1694                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1695                 .force_performance_level = &ni_dpm_force_performance_level,
1696                 .vblank_too_short = &ni_dpm_vblank_too_short,
1697         },
1698         .pflip = {
1699                 .pre_page_flip = &evergreen_pre_page_flip,
1700                 .page_flip = &evergreen_page_flip,
1701                 .post_page_flip = &evergreen_post_page_flip,
1702         },
1703 };
1704
1705 static struct radeon_asic trinity_asic = {
1706         .init = &cayman_init,
1707         .fini = &cayman_fini,
1708         .suspend = &cayman_suspend,
1709         .resume = &cayman_resume,
1710         .asic_reset = &cayman_asic_reset,
1711         .vga_set_state = &r600_vga_set_state,
1712         .ioctl_wait_idle = r600_ioctl_wait_idle,
1713         .gui_idle = &r600_gui_idle,
1714         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1715         .get_xclk = &r600_get_xclk,
1716         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1717         .gart = {
1718                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1719                 .set_page = &rs600_gart_set_page,
1720         },
1721         .vm = {
1722                 .init = &cayman_vm_init,
1723                 .fini = &cayman_vm_fini,
1724                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1725                 .set_page = &cayman_vm_set_page,
1726         },
1727         .ring = {
1728                 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1729                 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1730                 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1731                 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1732                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1733                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1734         },
1735         .irq = {
1736                 .set = &evergreen_irq_set,
1737                 .process = &evergreen_irq_process,
1738         },
1739         .display = {
1740                 .bandwidth_update = &dce6_bandwidth_update,
1741                 .get_vblank_counter = &evergreen_get_vblank_counter,
1742                 .wait_for_vblank = &dce4_wait_for_vblank,
1743                 .set_backlight_level = &atombios_set_backlight_level,
1744                 .get_backlight_level = &atombios_get_backlight_level,
1745                 .hdmi_enable = &evergreen_hdmi_enable,
1746                 .hdmi_setmode = &evergreen_hdmi_setmode,
1747         },
1748         .copy = {
1749                 .blit = &r600_copy_cpdma,
1750                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1751                 .dma = &evergreen_copy_dma,
1752                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1753                 .copy = &evergreen_copy_dma,
1754                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1755         },
1756         .surface = {
1757                 .set_reg = r600_set_surface_reg,
1758                 .clear_reg = r600_clear_surface_reg,
1759         },
1760         .hpd = {
1761                 .init = &evergreen_hpd_init,
1762                 .fini = &evergreen_hpd_fini,
1763                 .sense = &evergreen_hpd_sense,
1764                 .set_polarity = &evergreen_hpd_set_polarity,
1765         },
1766         .pm = {
1767                 .misc = &evergreen_pm_misc,
1768                 .prepare = &evergreen_pm_prepare,
1769                 .finish = &evergreen_pm_finish,
1770                 .init_profile = &sumo_pm_init_profile,
1771                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1772                 .get_engine_clock = &radeon_atom_get_engine_clock,
1773                 .set_engine_clock = &radeon_atom_set_engine_clock,
1774                 .get_memory_clock = NULL,
1775                 .set_memory_clock = NULL,
1776                 .get_pcie_lanes = NULL,
1777                 .set_pcie_lanes = NULL,
1778                 .set_clock_gating = NULL,
1779                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1780                 .get_temperature = &tn_get_temp,
1781         },
1782         .dpm = {
1783                 .init = &trinity_dpm_init,
1784                 .setup_asic = &trinity_dpm_setup_asic,
1785                 .enable = &trinity_dpm_enable,
1786                 .disable = &trinity_dpm_disable,
1787                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1788                 .set_power_state = &trinity_dpm_set_power_state,
1789                 .post_set_power_state = &trinity_dpm_post_set_power_state,
1790                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1791                 .fini = &trinity_dpm_fini,
1792                 .get_sclk = &trinity_dpm_get_sclk,
1793                 .get_mclk = &trinity_dpm_get_mclk,
1794                 .print_power_state = &trinity_dpm_print_power_state,
1795                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1796                 .force_performance_level = &trinity_dpm_force_performance_level,
1797                 .enable_bapm = &trinity_dpm_enable_bapm,
1798         },
1799         .pflip = {
1800                 .pre_page_flip = &evergreen_pre_page_flip,
1801                 .page_flip = &evergreen_page_flip,
1802                 .post_page_flip = &evergreen_post_page_flip,
1803         },
1804 };
1805
1806 static struct radeon_asic_ring si_gfx_ring = {
1807         .ib_execute = &si_ring_ib_execute,
1808         .ib_parse = &si_ib_parse,
1809         .emit_fence = &si_fence_ring_emit,
1810         .emit_semaphore = &r600_semaphore_ring_emit,
1811         .cs_parse = NULL,
1812         .ring_test = &r600_ring_test,
1813         .ib_test = &r600_ib_test,
1814         .is_lockup = &si_gfx_is_lockup,
1815         .vm_flush = &si_vm_flush,
1816         .get_rptr = &radeon_ring_generic_get_rptr,
1817         .get_wptr = &radeon_ring_generic_get_wptr,
1818         .set_wptr = &radeon_ring_generic_set_wptr,
1819 };
1820
1821 static struct radeon_asic_ring si_dma_ring = {
1822         .ib_execute = &cayman_dma_ring_ib_execute,
1823         .ib_parse = &evergreen_dma_ib_parse,
1824         .emit_fence = &evergreen_dma_fence_ring_emit,
1825         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1826         .cs_parse = NULL,
1827         .ring_test = &r600_dma_ring_test,
1828         .ib_test = &r600_dma_ib_test,
1829         .is_lockup = &si_dma_is_lockup,
1830         .vm_flush = &si_dma_vm_flush,
1831         .get_rptr = &r600_dma_get_rptr,
1832         .get_wptr = &r600_dma_get_wptr,
1833         .set_wptr = &r600_dma_set_wptr,
1834 };
1835
1836 static struct radeon_asic si_asic = {
1837         .init = &si_init,
1838         .fini = &si_fini,
1839         .suspend = &si_suspend,
1840         .resume = &si_resume,
1841         .asic_reset = &si_asic_reset,
1842         .vga_set_state = &r600_vga_set_state,
1843         .ioctl_wait_idle = r600_ioctl_wait_idle,
1844         .gui_idle = &r600_gui_idle,
1845         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1846         .get_xclk = &si_get_xclk,
1847         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1848         .gart = {
1849                 .tlb_flush = &si_pcie_gart_tlb_flush,
1850                 .set_page = &rs600_gart_set_page,
1851         },
1852         .vm = {
1853                 .init = &si_vm_init,
1854                 .fini = &si_vm_fini,
1855                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1856                 .set_page = &si_vm_set_page,
1857         },
1858         .ring = {
1859                 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1860                 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1861                 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1862                 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1863                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1864                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1865         },
1866         .irq = {
1867                 .set = &si_irq_set,
1868                 .process = &si_irq_process,
1869         },
1870         .display = {
1871                 .bandwidth_update = &dce6_bandwidth_update,
1872                 .get_vblank_counter = &evergreen_get_vblank_counter,
1873                 .wait_for_vblank = &dce4_wait_for_vblank,
1874                 .set_backlight_level = &atombios_set_backlight_level,
1875                 .get_backlight_level = &atombios_get_backlight_level,
1876                 .hdmi_enable = &evergreen_hdmi_enable,
1877                 .hdmi_setmode = &evergreen_hdmi_setmode,
1878         },
1879         .copy = {
1880                 .blit = NULL,
1881                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1882                 .dma = &si_copy_dma,
1883                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1884                 .copy = &si_copy_dma,
1885                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1886         },
1887         .surface = {
1888                 .set_reg = r600_set_surface_reg,
1889                 .clear_reg = r600_clear_surface_reg,
1890         },
1891         .hpd = {
1892                 .init = &evergreen_hpd_init,
1893                 .fini = &evergreen_hpd_fini,
1894                 .sense = &evergreen_hpd_sense,
1895                 .set_polarity = &evergreen_hpd_set_polarity,
1896         },
1897         .pm = {
1898                 .misc = &evergreen_pm_misc,
1899                 .prepare = &evergreen_pm_prepare,
1900                 .finish = &evergreen_pm_finish,
1901                 .init_profile = &sumo_pm_init_profile,
1902                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1903                 .get_engine_clock = &radeon_atom_get_engine_clock,
1904                 .set_engine_clock = &radeon_atom_set_engine_clock,
1905                 .get_memory_clock = &radeon_atom_get_memory_clock,
1906                 .set_memory_clock = &radeon_atom_set_memory_clock,
1907                 .get_pcie_lanes = &r600_get_pcie_lanes,
1908                 .set_pcie_lanes = &r600_set_pcie_lanes,
1909                 .set_clock_gating = NULL,
1910                 .set_uvd_clocks = &si_set_uvd_clocks,
1911                 .get_temperature = &si_get_temp,
1912         },
1913         .dpm = {
1914                 .init = &si_dpm_init,
1915                 .setup_asic = &si_dpm_setup_asic,
1916                 .enable = &si_dpm_enable,
1917                 .disable = &si_dpm_disable,
1918                 .pre_set_power_state = &si_dpm_pre_set_power_state,
1919                 .set_power_state = &si_dpm_set_power_state,
1920                 .post_set_power_state = &si_dpm_post_set_power_state,
1921                 .display_configuration_changed = &si_dpm_display_configuration_changed,
1922                 .fini = &si_dpm_fini,
1923                 .get_sclk = &ni_dpm_get_sclk,
1924                 .get_mclk = &ni_dpm_get_mclk,
1925                 .print_power_state = &ni_dpm_print_power_state,
1926                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
1927                 .force_performance_level = &si_dpm_force_performance_level,
1928                 .vblank_too_short = &ni_dpm_vblank_too_short,
1929         },
1930         .pflip = {
1931                 .pre_page_flip = &evergreen_pre_page_flip,
1932                 .page_flip = &evergreen_page_flip,
1933                 .post_page_flip = &evergreen_post_page_flip,
1934         },
1935 };
1936
1937 static struct radeon_asic_ring ci_gfx_ring = {
1938         .ib_execute = &cik_ring_ib_execute,
1939         .ib_parse = &cik_ib_parse,
1940         .emit_fence = &cik_fence_gfx_ring_emit,
1941         .emit_semaphore = &cik_semaphore_ring_emit,
1942         .cs_parse = NULL,
1943         .ring_test = &cik_ring_test,
1944         .ib_test = &cik_ib_test,
1945         .is_lockup = &cik_gfx_is_lockup,
1946         .vm_flush = &cik_vm_flush,
1947         .get_rptr = &radeon_ring_generic_get_rptr,
1948         .get_wptr = &radeon_ring_generic_get_wptr,
1949         .set_wptr = &radeon_ring_generic_set_wptr,
1950 };
1951
1952 static struct radeon_asic_ring ci_cp_ring = {
1953         .ib_execute = &cik_ring_ib_execute,
1954         .ib_parse = &cik_ib_parse,
1955         .emit_fence = &cik_fence_compute_ring_emit,
1956         .emit_semaphore = &cik_semaphore_ring_emit,
1957         .cs_parse = NULL,
1958         .ring_test = &cik_ring_test,
1959         .ib_test = &cik_ib_test,
1960         .is_lockup = &cik_gfx_is_lockup,
1961         .vm_flush = &cik_vm_flush,
1962         .get_rptr = &cik_compute_ring_get_rptr,
1963         .get_wptr = &cik_compute_ring_get_wptr,
1964         .set_wptr = &cik_compute_ring_set_wptr,
1965 };
1966
1967 static struct radeon_asic_ring ci_dma_ring = {
1968         .ib_execute = &cik_sdma_ring_ib_execute,
1969         .ib_parse = &cik_ib_parse,
1970         .emit_fence = &cik_sdma_fence_ring_emit,
1971         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1972         .cs_parse = NULL,
1973         .ring_test = &cik_sdma_ring_test,
1974         .ib_test = &cik_sdma_ib_test,
1975         .is_lockup = &cik_sdma_is_lockup,
1976         .vm_flush = &cik_dma_vm_flush,
1977         .get_rptr = &r600_dma_get_rptr,
1978         .get_wptr = &r600_dma_get_wptr,
1979         .set_wptr = &r600_dma_set_wptr,
1980 };
1981
1982 static struct radeon_asic ci_asic = {
1983         .init = &cik_init,
1984         .fini = &cik_fini,
1985         .suspend = &cik_suspend,
1986         .resume = &cik_resume,
1987         .asic_reset = &cik_asic_reset,
1988         .vga_set_state = &r600_vga_set_state,
1989         .ioctl_wait_idle = NULL,
1990         .gui_idle = &r600_gui_idle,
1991         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1992         .get_xclk = &cik_get_xclk,
1993         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1994         .gart = {
1995                 .tlb_flush = &cik_pcie_gart_tlb_flush,
1996                 .set_page = &rs600_gart_set_page,
1997         },
1998         .vm = {
1999                 .init = &cik_vm_init,
2000                 .fini = &cik_vm_fini,
2001                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2002                 .set_page = &cik_vm_set_page,
2003         },
2004         .ring = {
2005                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2006                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2007                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2008                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2009                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2010                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2011         },
2012         .irq = {
2013                 .set = &cik_irq_set,
2014                 .process = &cik_irq_process,
2015         },
2016         .display = {
2017                 .bandwidth_update = &dce8_bandwidth_update,
2018                 .get_vblank_counter = &evergreen_get_vblank_counter,
2019                 .wait_for_vblank = &dce4_wait_for_vblank,
2020                 .hdmi_enable = &evergreen_hdmi_enable,
2021                 .hdmi_setmode = &evergreen_hdmi_setmode,
2022         },
2023         .copy = {
2024                 .blit = NULL,
2025                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2026                 .dma = &cik_copy_dma,
2027                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2028                 .copy = &cik_copy_dma,
2029                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2030         },
2031         .surface = {
2032                 .set_reg = r600_set_surface_reg,
2033                 .clear_reg = r600_clear_surface_reg,
2034         },
2035         .hpd = {
2036                 .init = &evergreen_hpd_init,
2037                 .fini = &evergreen_hpd_fini,
2038                 .sense = &evergreen_hpd_sense,
2039                 .set_polarity = &evergreen_hpd_set_polarity,
2040         },
2041         .pm = {
2042                 .misc = &evergreen_pm_misc,
2043                 .prepare = &evergreen_pm_prepare,
2044                 .finish = &evergreen_pm_finish,
2045                 .init_profile = &sumo_pm_init_profile,
2046                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2047                 .get_engine_clock = &radeon_atom_get_engine_clock,
2048                 .set_engine_clock = &radeon_atom_set_engine_clock,
2049                 .get_memory_clock = &radeon_atom_get_memory_clock,
2050                 .set_memory_clock = &radeon_atom_set_memory_clock,
2051                 .get_pcie_lanes = NULL,
2052                 .set_pcie_lanes = NULL,
2053                 .set_clock_gating = NULL,
2054                 .set_uvd_clocks = &cik_set_uvd_clocks,
2055                 .get_temperature = &ci_get_temp,
2056         },
2057         .dpm = {
2058                 .init = &ci_dpm_init,
2059                 .setup_asic = &ci_dpm_setup_asic,
2060                 .enable = &ci_dpm_enable,
2061                 .disable = &ci_dpm_disable,
2062                 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2063                 .set_power_state = &ci_dpm_set_power_state,
2064                 .post_set_power_state = &ci_dpm_post_set_power_state,
2065                 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2066                 .fini = &ci_dpm_fini,
2067                 .get_sclk = &ci_dpm_get_sclk,
2068                 .get_mclk = &ci_dpm_get_mclk,
2069                 .print_power_state = &ci_dpm_print_power_state,
2070                 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2071                 .force_performance_level = &ci_dpm_force_performance_level,
2072                 .vblank_too_short = &ci_dpm_vblank_too_short,
2073                 .powergate_uvd = &ci_dpm_powergate_uvd,
2074         },
2075         .pflip = {
2076                 .pre_page_flip = &evergreen_pre_page_flip,
2077                 .page_flip = &evergreen_page_flip,
2078                 .post_page_flip = &evergreen_post_page_flip,
2079         },
2080 };
2081
2082 static struct radeon_asic kv_asic = {
2083         .init = &cik_init,
2084         .fini = &cik_fini,
2085         .suspend = &cik_suspend,
2086         .resume = &cik_resume,
2087         .asic_reset = &cik_asic_reset,
2088         .vga_set_state = &r600_vga_set_state,
2089         .ioctl_wait_idle = NULL,
2090         .gui_idle = &r600_gui_idle,
2091         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2092         .get_xclk = &cik_get_xclk,
2093         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2094         .gart = {
2095                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2096                 .set_page = &rs600_gart_set_page,
2097         },
2098         .vm = {
2099                 .init = &cik_vm_init,
2100                 .fini = &cik_vm_fini,
2101                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2102                 .set_page = &cik_vm_set_page,
2103         },
2104         .ring = {
2105                 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2106                 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2107                 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2108                 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2109                 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2110                 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2111         },
2112         .irq = {
2113                 .set = &cik_irq_set,
2114                 .process = &cik_irq_process,
2115         },
2116         .display = {
2117                 .bandwidth_update = &dce8_bandwidth_update,
2118                 .get_vblank_counter = &evergreen_get_vblank_counter,
2119                 .wait_for_vblank = &dce4_wait_for_vblank,
2120                 .hdmi_enable = &evergreen_hdmi_enable,
2121                 .hdmi_setmode = &evergreen_hdmi_setmode,
2122         },
2123         .copy = {
2124                 .blit = NULL,
2125                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2126                 .dma = &cik_copy_dma,
2127                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2128                 .copy = &cik_copy_dma,
2129                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2130         },
2131         .surface = {
2132                 .set_reg = r600_set_surface_reg,
2133                 .clear_reg = r600_clear_surface_reg,
2134         },
2135         .hpd = {
2136                 .init = &evergreen_hpd_init,
2137                 .fini = &evergreen_hpd_fini,
2138                 .sense = &evergreen_hpd_sense,
2139                 .set_polarity = &evergreen_hpd_set_polarity,
2140         },
2141         .pm = {
2142                 .misc = &evergreen_pm_misc,
2143                 .prepare = &evergreen_pm_prepare,
2144                 .finish = &evergreen_pm_finish,
2145                 .init_profile = &sumo_pm_init_profile,
2146                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2147                 .get_engine_clock = &radeon_atom_get_engine_clock,
2148                 .set_engine_clock = &radeon_atom_set_engine_clock,
2149                 .get_memory_clock = &radeon_atom_get_memory_clock,
2150                 .set_memory_clock = &radeon_atom_set_memory_clock,
2151                 .get_pcie_lanes = NULL,
2152                 .set_pcie_lanes = NULL,
2153                 .set_clock_gating = NULL,
2154                 .set_uvd_clocks = &cik_set_uvd_clocks,
2155                 .get_temperature = &kv_get_temp,
2156         },
2157         .dpm = {
2158                 .init = &kv_dpm_init,
2159                 .setup_asic = &kv_dpm_setup_asic,
2160                 .enable = &kv_dpm_enable,
2161                 .disable = &kv_dpm_disable,
2162                 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2163                 .set_power_state = &kv_dpm_set_power_state,
2164                 .post_set_power_state = &kv_dpm_post_set_power_state,
2165                 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2166                 .fini = &kv_dpm_fini,
2167                 .get_sclk = &kv_dpm_get_sclk,
2168                 .get_mclk = &kv_dpm_get_mclk,
2169                 .print_power_state = &kv_dpm_print_power_state,
2170                 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2171                 .force_performance_level = &kv_dpm_force_performance_level,
2172                 .powergate_uvd = &kv_dpm_powergate_uvd,
2173                 .enable_bapm = &kv_dpm_enable_bapm,
2174         },
2175         .pflip = {
2176                 .pre_page_flip = &evergreen_pre_page_flip,
2177                 .page_flip = &evergreen_page_flip,
2178                 .post_page_flip = &evergreen_post_page_flip,
2179         },
2180 };
2181
2182 /**
2183  * radeon_asic_init - register asic specific callbacks
2184  *
2185  * @rdev: radeon device pointer
2186  *
2187  * Registers the appropriate asic specific callbacks for each
2188  * chip family.  Also sets other asics specific info like the number
2189  * of crtcs and the register aperture accessors (all asics).
2190  * Returns 0 for success.
2191  */
2192 int radeon_asic_init(struct radeon_device *rdev)
2193 {
2194         radeon_register_accessor_init(rdev);
2195
2196         /* set the number of crtcs */
2197         if (rdev->flags & RADEON_SINGLE_CRTC)
2198                 rdev->num_crtc = 1;
2199         else
2200                 rdev->num_crtc = 2;
2201
2202         rdev->has_uvd = false;
2203
2204         switch (rdev->family) {
2205         case CHIP_R100:
2206         case CHIP_RV100:
2207         case CHIP_RS100:
2208         case CHIP_RV200:
2209         case CHIP_RS200:
2210                 rdev->asic = &r100_asic;
2211                 break;
2212         case CHIP_R200:
2213         case CHIP_RV250:
2214         case CHIP_RS300:
2215         case CHIP_RV280:
2216                 rdev->asic = &r200_asic;
2217                 break;
2218         case CHIP_R300:
2219         case CHIP_R350:
2220         case CHIP_RV350:
2221         case CHIP_RV380:
2222                 if (rdev->flags & RADEON_IS_PCIE)
2223                         rdev->asic = &r300_asic_pcie;
2224                 else
2225                         rdev->asic = &r300_asic;
2226                 break;
2227         case CHIP_R420:
2228         case CHIP_R423:
2229         case CHIP_RV410:
2230                 rdev->asic = &r420_asic;
2231                 /* handle macs */
2232                 if (rdev->bios == NULL) {
2233                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2234                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2235                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2236                         rdev->asic->pm.set_memory_clock = NULL;
2237                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2238                 }
2239                 break;
2240         case CHIP_RS400:
2241         case CHIP_RS480:
2242                 rdev->asic = &rs400_asic;
2243                 break;
2244         case CHIP_RS600:
2245                 rdev->asic = &rs600_asic;
2246                 break;
2247         case CHIP_RS690:
2248         case CHIP_RS740:
2249                 rdev->asic = &rs690_asic;
2250                 break;
2251         case CHIP_RV515:
2252                 rdev->asic = &rv515_asic;
2253                 break;
2254         case CHIP_R520:
2255         case CHIP_RV530:
2256         case CHIP_RV560:
2257         case CHIP_RV570:
2258         case CHIP_R580:
2259                 rdev->asic = &r520_asic;
2260                 break;
2261         case CHIP_R600:
2262                 rdev->asic = &r600_asic;
2263                 break;
2264         case CHIP_RV610:
2265         case CHIP_RV630:
2266         case CHIP_RV620:
2267         case CHIP_RV635:
2268         case CHIP_RV670:
2269                 rdev->asic = &rv6xx_asic;
2270                 rdev->has_uvd = true;
2271                 break;
2272         case CHIP_RS780:
2273         case CHIP_RS880:
2274                 rdev->asic = &rs780_asic;
2275                 rdev->has_uvd = true;
2276                 break;
2277         case CHIP_RV770:
2278         case CHIP_RV730:
2279         case CHIP_RV710:
2280         case CHIP_RV740:
2281                 rdev->asic = &rv770_asic;
2282                 rdev->has_uvd = true;
2283                 break;
2284         case CHIP_CEDAR:
2285         case CHIP_REDWOOD:
2286         case CHIP_JUNIPER:
2287         case CHIP_CYPRESS:
2288         case CHIP_HEMLOCK:
2289                 /* set num crtcs */
2290                 if (rdev->family == CHIP_CEDAR)
2291                         rdev->num_crtc = 4;
2292                 else
2293                         rdev->num_crtc = 6;
2294                 rdev->asic = &evergreen_asic;
2295                 rdev->has_uvd = true;
2296                 break;
2297         case CHIP_PALM:
2298         case CHIP_SUMO:
2299         case CHIP_SUMO2:
2300                 rdev->asic = &sumo_asic;
2301                 rdev->has_uvd = true;
2302                 break;
2303         case CHIP_BARTS:
2304         case CHIP_TURKS:
2305         case CHIP_CAICOS:
2306                 /* set num crtcs */
2307                 if (rdev->family == CHIP_CAICOS)
2308                         rdev->num_crtc = 4;
2309                 else
2310                         rdev->num_crtc = 6;
2311                 rdev->asic = &btc_asic;
2312                 rdev->has_uvd = true;
2313                 break;
2314         case CHIP_CAYMAN:
2315                 rdev->asic = &cayman_asic;
2316                 /* set num crtcs */
2317                 rdev->num_crtc = 6;
2318                 rdev->has_uvd = true;
2319                 break;
2320         case CHIP_ARUBA:
2321                 rdev->asic = &trinity_asic;
2322                 /* set num crtcs */
2323                 rdev->num_crtc = 4;
2324                 rdev->has_uvd = true;
2325                 break;
2326         case CHIP_TAHITI:
2327         case CHIP_PITCAIRN:
2328         case CHIP_VERDE:
2329         case CHIP_OLAND:
2330         case CHIP_HAINAN:
2331                 rdev->asic = &si_asic;
2332                 /* set num crtcs */
2333                 if (rdev->family == CHIP_HAINAN)
2334                         rdev->num_crtc = 0;
2335                 else if (rdev->family == CHIP_OLAND)
2336                         rdev->num_crtc = 2;
2337                 else
2338                         rdev->num_crtc = 6;
2339                 if (rdev->family == CHIP_HAINAN)
2340                         rdev->has_uvd = false;
2341                 else
2342                         rdev->has_uvd = true;
2343                 switch (rdev->family) {
2344                 case CHIP_TAHITI:
2345                         rdev->cg_flags =
2346                                 RADEON_CG_SUPPORT_GFX_MGCG |
2347                                 RADEON_CG_SUPPORT_GFX_MGLS |
2348                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2349                                 RADEON_CG_SUPPORT_GFX_CGLS |
2350                                 RADEON_CG_SUPPORT_GFX_CGTS |
2351                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2352                                 RADEON_CG_SUPPORT_MC_MGCG |
2353                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2354                                 RADEON_CG_SUPPORT_BIF_LS |
2355                                 RADEON_CG_SUPPORT_VCE_MGCG |
2356                                 RADEON_CG_SUPPORT_UVD_MGCG |
2357                                 RADEON_CG_SUPPORT_HDP_LS |
2358                                 RADEON_CG_SUPPORT_HDP_MGCG;
2359                         rdev->pg_flags = 0;
2360                         break;
2361                 case CHIP_PITCAIRN:
2362                         rdev->cg_flags =
2363                                 RADEON_CG_SUPPORT_GFX_MGCG |
2364                                 RADEON_CG_SUPPORT_GFX_MGLS |
2365                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2366                                 RADEON_CG_SUPPORT_GFX_CGLS |
2367                                 RADEON_CG_SUPPORT_GFX_CGTS |
2368                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2369                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2370                                 RADEON_CG_SUPPORT_MC_LS |
2371                                 RADEON_CG_SUPPORT_MC_MGCG |
2372                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2373                                 RADEON_CG_SUPPORT_BIF_LS |
2374                                 RADEON_CG_SUPPORT_VCE_MGCG |
2375                                 RADEON_CG_SUPPORT_UVD_MGCG |
2376                                 RADEON_CG_SUPPORT_HDP_LS |
2377                                 RADEON_CG_SUPPORT_HDP_MGCG;
2378                         rdev->pg_flags = 0;
2379                         break;
2380                 case CHIP_VERDE:
2381                         rdev->cg_flags =
2382                                 RADEON_CG_SUPPORT_GFX_MGCG |
2383                                 RADEON_CG_SUPPORT_GFX_MGLS |
2384                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2385                                 RADEON_CG_SUPPORT_GFX_CGLS |
2386                                 RADEON_CG_SUPPORT_GFX_CGTS |
2387                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2388                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2389                                 RADEON_CG_SUPPORT_MC_LS |
2390                                 RADEON_CG_SUPPORT_MC_MGCG |
2391                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2392                                 RADEON_CG_SUPPORT_BIF_LS |
2393                                 RADEON_CG_SUPPORT_VCE_MGCG |
2394                                 RADEON_CG_SUPPORT_UVD_MGCG |
2395                                 RADEON_CG_SUPPORT_HDP_LS |
2396                                 RADEON_CG_SUPPORT_HDP_MGCG;
2397                         rdev->pg_flags = 0 |
2398                                 /*RADEON_PG_SUPPORT_GFX_PG | */
2399                                 RADEON_PG_SUPPORT_SDMA;
2400                         break;
2401                 case CHIP_OLAND:
2402                         rdev->cg_flags =
2403                                 RADEON_CG_SUPPORT_GFX_MGCG |
2404                                 RADEON_CG_SUPPORT_GFX_MGLS |
2405                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2406                                 RADEON_CG_SUPPORT_GFX_CGLS |
2407                                 RADEON_CG_SUPPORT_GFX_CGTS |
2408                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2409                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2410                                 RADEON_CG_SUPPORT_MC_LS |
2411                                 RADEON_CG_SUPPORT_MC_MGCG |
2412                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2413                                 RADEON_CG_SUPPORT_BIF_LS |
2414                                 RADEON_CG_SUPPORT_UVD_MGCG |
2415                                 RADEON_CG_SUPPORT_HDP_LS |
2416                                 RADEON_CG_SUPPORT_HDP_MGCG;
2417                         rdev->pg_flags = 0;
2418                         break;
2419                 case CHIP_HAINAN:
2420                         rdev->cg_flags =
2421                                 RADEON_CG_SUPPORT_GFX_MGCG |
2422                                 RADEON_CG_SUPPORT_GFX_MGLS |
2423                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2424                                 RADEON_CG_SUPPORT_GFX_CGLS |
2425                                 RADEON_CG_SUPPORT_GFX_CGTS |
2426                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2427                                 RADEON_CG_SUPPORT_GFX_RLC_LS |
2428                                 RADEON_CG_SUPPORT_MC_LS |
2429                                 RADEON_CG_SUPPORT_MC_MGCG |
2430                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2431                                 RADEON_CG_SUPPORT_BIF_LS |
2432                                 RADEON_CG_SUPPORT_HDP_LS |
2433                                 RADEON_CG_SUPPORT_HDP_MGCG;
2434                         rdev->pg_flags = 0;
2435                         break;
2436                 default:
2437                         rdev->cg_flags = 0;
2438                         rdev->pg_flags = 0;
2439                         break;
2440                 }
2441                 break;
2442         case CHIP_BONAIRE:
2443                 rdev->asic = &ci_asic;
2444                 rdev->num_crtc = 6;
2445                 rdev->has_uvd = true;
2446                 rdev->cg_flags =
2447                         RADEON_CG_SUPPORT_GFX_MGCG |
2448                         RADEON_CG_SUPPORT_GFX_MGLS |
2449                         /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2450                         RADEON_CG_SUPPORT_GFX_CGLS |
2451                         RADEON_CG_SUPPORT_GFX_CGTS |
2452                         RADEON_CG_SUPPORT_GFX_CGTS_LS |
2453                         RADEON_CG_SUPPORT_GFX_CP_LS |
2454                         RADEON_CG_SUPPORT_MC_LS |
2455                         RADEON_CG_SUPPORT_MC_MGCG |
2456                         RADEON_CG_SUPPORT_SDMA_MGCG |
2457                         RADEON_CG_SUPPORT_SDMA_LS |
2458                         RADEON_CG_SUPPORT_BIF_LS |
2459                         RADEON_CG_SUPPORT_VCE_MGCG |
2460                         RADEON_CG_SUPPORT_UVD_MGCG |
2461                         RADEON_CG_SUPPORT_HDP_LS |
2462                         RADEON_CG_SUPPORT_HDP_MGCG;
2463                 rdev->pg_flags = 0;
2464                 break;
2465         case CHIP_KAVERI:
2466         case CHIP_KABINI:
2467                 rdev->asic = &kv_asic;
2468                 /* set num crtcs */
2469                 if (rdev->family == CHIP_KAVERI) {
2470                         rdev->num_crtc = 4;
2471                         rdev->cg_flags =
2472                                 RADEON_CG_SUPPORT_GFX_MGCG |
2473                                 RADEON_CG_SUPPORT_GFX_MGLS |
2474                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2475                                 RADEON_CG_SUPPORT_GFX_CGLS |
2476                                 RADEON_CG_SUPPORT_GFX_CGTS |
2477                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2478                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2479                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2480                                 RADEON_CG_SUPPORT_SDMA_LS |
2481                                 RADEON_CG_SUPPORT_BIF_LS |
2482                                 RADEON_CG_SUPPORT_VCE_MGCG |
2483                                 RADEON_CG_SUPPORT_UVD_MGCG |
2484                                 RADEON_CG_SUPPORT_HDP_LS |
2485                                 RADEON_CG_SUPPORT_HDP_MGCG;
2486                         rdev->pg_flags = 0;
2487                                 /*RADEON_PG_SUPPORT_GFX_PG |
2488                                 RADEON_PG_SUPPORT_GFX_SMG |
2489                                 RADEON_PG_SUPPORT_GFX_DMG |
2490                                 RADEON_PG_SUPPORT_UVD |
2491                                 RADEON_PG_SUPPORT_VCE |
2492                                 RADEON_PG_SUPPORT_CP |
2493                                 RADEON_PG_SUPPORT_GDS |
2494                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2495                                 RADEON_PG_SUPPORT_ACP |
2496                                 RADEON_PG_SUPPORT_SAMU;*/
2497                 } else {
2498                         rdev->num_crtc = 2;
2499                         rdev->cg_flags =
2500                                 RADEON_CG_SUPPORT_GFX_MGCG |
2501                                 RADEON_CG_SUPPORT_GFX_MGLS |
2502                                 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2503                                 RADEON_CG_SUPPORT_GFX_CGLS |
2504                                 RADEON_CG_SUPPORT_GFX_CGTS |
2505                                 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2506                                 RADEON_CG_SUPPORT_GFX_CP_LS |
2507                                 RADEON_CG_SUPPORT_SDMA_MGCG |
2508                                 RADEON_CG_SUPPORT_SDMA_LS |
2509                                 RADEON_CG_SUPPORT_BIF_LS |
2510                                 RADEON_CG_SUPPORT_VCE_MGCG |
2511                                 RADEON_CG_SUPPORT_UVD_MGCG |
2512                                 RADEON_CG_SUPPORT_HDP_LS |
2513                                 RADEON_CG_SUPPORT_HDP_MGCG;
2514                         rdev->pg_flags = 0;
2515                                 /*RADEON_PG_SUPPORT_GFX_PG |
2516                                 RADEON_PG_SUPPORT_GFX_SMG |
2517                                 RADEON_PG_SUPPORT_UVD |
2518                                 RADEON_PG_SUPPORT_VCE |
2519                                 RADEON_PG_SUPPORT_CP |
2520                                 RADEON_PG_SUPPORT_GDS |
2521                                 RADEON_PG_SUPPORT_RLC_SMU_HS |
2522                                 RADEON_PG_SUPPORT_SAMU;*/
2523                 }
2524                 rdev->has_uvd = true;
2525                 break;
2526         default:
2527                 /* FIXME: not supported yet */
2528                 return -EINVAL;
2529         }
2530
2531         if (rdev->flags & RADEON_IS_IGP) {
2532                 rdev->asic->pm.get_memory_clock = NULL;
2533                 rdev->asic->pm.set_memory_clock = NULL;
2534         }
2535
2536         return 0;
2537 }
2538