drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if (rdev->family >= CHIP_R600) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .ring = {
 142                 [RADEON_RING_TYPE_GFX_INDEX] = {
 143                         .ib_execute = &r100_ring_ib_execute,
 144                         .emit_fence = &r100_fence_ring_emit,
 145                         .emit_semaphore = &r100_semaphore_ring_emit,
 146                         .cs_parse = &r100_cs_parse,
 147                         .ring_start = &r100_ring_start,
 148                         .ring_test = &r100_ring_test,
 149                         .ib_test = &r100_ib_test,
 150                 }
 151         },
 152         .irq = {
 153                 .set = &r100_irq_set,
 154                 .process = &r100_irq_process,
 155         },
 156         .get_vblank_counter = &r100_get_vblank_counter,
 157         .copy = {
 158                 .blit = &r100_copy_blit,
 159                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 160                 .dma = NULL,
 161                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 162                 .copy = &r100_copy_blit,
 163                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 164         },
 165         .get_engine_clock = &radeon_legacy_get_engine_clock,
 166         .set_engine_clock = &radeon_legacy_set_engine_clock,
 167         .get_memory_clock = &radeon_legacy_get_memory_clock,
 168         .set_memory_clock = NULL,
 169         .get_pcie_lanes = NULL,
 170         .set_pcie_lanes = NULL,
 171         .set_clock_gating = &radeon_legacy_set_clock_gating,
 172         .set_surface_reg = r100_set_surface_reg,
 173         .clear_surface_reg = r100_clear_surface_reg,
 174         .bandwidth_update = &r100_bandwidth_update,
 175         .hpd = {
 176                 .init = &r100_hpd_init,
 177                 .fini = &r100_hpd_fini,
 178                 .sense = &r100_hpd_sense,
 179                 .set_polarity = &r100_hpd_set_polarity,
 180         },
 181         .ioctl_wait_idle = NULL,
 182         .gui_idle = &r100_gui_idle,
 183         .pm = {
 184                 .misc = &r100_pm_misc,
 185                 .prepare = &r100_pm_prepare,
 186                 .finish = &r100_pm_finish,
 187                 .init_profile = &r100_pm_init_profile,
 188                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 189         },
 190         .pflip = {
 191                 .pre_page_flip = &r100_pre_page_flip,
 192                 .page_flip = &r100_page_flip,
 193                 .post_page_flip = &r100_post_page_flip,
 194         },
 195         .wait_for_vblank = &r100_wait_for_vblank,
 196         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 197 };
 198
 199 static struct radeon_asic r200_asic = {
 200         .init = &r100_init,
 201         .fini = &r100_fini,
 202         .suspend = &r100_suspend,
 203         .resume = &r100_resume,
 204         .vga_set_state = &r100_vga_set_state,
 205         .gpu_is_lockup = &r100_gpu_is_lockup,
 206         .asic_reset = &r100_asic_reset,
 207         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 208         .gart_set_page = &r100_pci_gart_set_page,
 209         .ring = {
 210                 [RADEON_RING_TYPE_GFX_INDEX] = {
 211                         .ib_execute = &r100_ring_ib_execute,
 212                         .emit_fence = &r100_fence_ring_emit,
 213                         .emit_semaphore = &r100_semaphore_ring_emit,
 214                         .cs_parse = &r100_cs_parse,
 215                         .ring_start = &r100_ring_start,
 216                         .ring_test = &r100_ring_test,
 217                         .ib_test = &r100_ib_test,
 218                 }
 219         },
 220         .irq = {
 221                 .set = &r100_irq_set,
 222                 .process = &r100_irq_process,
 223         },
 224         .get_vblank_counter = &r100_get_vblank_counter,
 225         .copy = {
 226                 .blit = &r100_copy_blit,
 227                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 228                 .dma = &r200_copy_dma,
 229                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 230                 .copy = &r100_copy_blit,
 231                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 232         },
 233         .get_engine_clock = &radeon_legacy_get_engine_clock,
 234         .set_engine_clock = &radeon_legacy_set_engine_clock,
 235         .get_memory_clock = &radeon_legacy_get_memory_clock,
 236         .set_memory_clock = NULL,
 237         .set_pcie_lanes = NULL,
 238         .set_clock_gating = &radeon_legacy_set_clock_gating,
 239         .set_surface_reg = r100_set_surface_reg,
 240         .clear_surface_reg = r100_clear_surface_reg,
 241         .bandwidth_update = &r100_bandwidth_update,
 242         .hpd = {
 243                 .init = &r100_hpd_init,
 244                 .fini = &r100_hpd_fini,
 245                 .sense = &r100_hpd_sense,
 246                 .set_polarity = &r100_hpd_set_polarity,
 247         },
 248         .ioctl_wait_idle = NULL,
 249         .gui_idle = &r100_gui_idle,
 250         .pm = {
 251                 .misc = &r100_pm_misc,
 252                 .prepare = &r100_pm_prepare,
 253                 .finish = &r100_pm_finish,
 254                 .init_profile = &r100_pm_init_profile,
 255                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 256         },
 257         .pflip = {
 258                 .pre_page_flip = &r100_pre_page_flip,
 259                 .page_flip = &r100_page_flip,
 260                 .post_page_flip = &r100_post_page_flip,
 261         },
 262         .wait_for_vblank = &r100_wait_for_vblank,
 263         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 264 };
 265
 266 static struct radeon_asic r300_asic = {
 267         .init = &r300_init,
 268         .fini = &r300_fini,
 269         .suspend = &r300_suspend,
 270         .resume = &r300_resume,
 271         .vga_set_state = &r100_vga_set_state,
 272         .gpu_is_lockup = &r300_gpu_is_lockup,
 273         .asic_reset = &r300_asic_reset,
 274         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 275         .gart_set_page = &r100_pci_gart_set_page,
 276         .ring = {
 277                 [RADEON_RING_TYPE_GFX_INDEX] = {
 278                         .ib_execute = &r100_ring_ib_execute,
 279                         .emit_fence = &r300_fence_ring_emit,
 280                         .emit_semaphore = &r100_semaphore_ring_emit,
 281                         .cs_parse = &r300_cs_parse,
 282                         .ring_start = &r300_ring_start,
 283                         .ring_test = &r100_ring_test,
 284                         .ib_test = &r100_ib_test,
 285                 }
 286         },
 287         .irq = {
 288                 .set = &r100_irq_set,
 289                 .process = &r100_irq_process,
 290         },
 291         .get_vblank_counter = &r100_get_vblank_counter,
 292         .copy = {
 293                 .blit = &r100_copy_blit,
 294                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 295                 .dma = &r200_copy_dma,
 296                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 297                 .copy = &r100_copy_blit,
 298                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 299         },
 300         .get_engine_clock = &radeon_legacy_get_engine_clock,
 301         .set_engine_clock = &radeon_legacy_set_engine_clock,
 302         .get_memory_clock = &radeon_legacy_get_memory_clock,
 303         .set_memory_clock = NULL,
 304         .get_pcie_lanes = &rv370_get_pcie_lanes,
 305         .set_pcie_lanes = &rv370_set_pcie_lanes,
 306         .set_clock_gating = &radeon_legacy_set_clock_gating,
 307         .set_surface_reg = r100_set_surface_reg,
 308         .clear_surface_reg = r100_clear_surface_reg,
 309         .bandwidth_update = &r100_bandwidth_update,
 310         .hpd = {
 311                 .init = &r100_hpd_init,
 312                 .fini = &r100_hpd_fini,
 313                 .sense = &r100_hpd_sense,
 314                 .set_polarity = &r100_hpd_set_polarity,
 315         },
 316         .ioctl_wait_idle = NULL,
 317         .gui_idle = &r100_gui_idle,
 318         .pm = {
 319                 .misc = &r100_pm_misc,
 320                 .prepare = &r100_pm_prepare,
 321                 .finish = &r100_pm_finish,
 322                 .init_profile = &r100_pm_init_profile,
 323                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 324         },
 325         .pflip = {
 326                 .pre_page_flip = &r100_pre_page_flip,
 327                 .page_flip = &r100_page_flip,
 328                 .post_page_flip = &r100_post_page_flip,
 329         },
 330         .wait_for_vblank = &r100_wait_for_vblank,
 331         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 332 };
 333
 334 static struct radeon_asic r300_asic_pcie = {
 335         .init = &r300_init,
 336         .fini = &r300_fini,
 337         .suspend = &r300_suspend,
 338         .resume = &r300_resume,
 339         .vga_set_state = &r100_vga_set_state,
 340         .gpu_is_lockup = &r300_gpu_is_lockup,
 341         .asic_reset = &r300_asic_reset,
 342         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 343         .gart_set_page = &rv370_pcie_gart_set_page,
 344         .ring = {
 345                 [RADEON_RING_TYPE_GFX_INDEX] = {
 346                         .ib_execute = &r100_ring_ib_execute,
 347                         .emit_fence = &r300_fence_ring_emit,
 348                         .emit_semaphore = &r100_semaphore_ring_emit,
 349                         .cs_parse = &r300_cs_parse,
 350                         .ring_start = &r300_ring_start,
 351                         .ring_test = &r100_ring_test,
 352                         .ib_test = &r100_ib_test,
 353                 }
 354         },
 355         .irq = {
 356                 .set = &r100_irq_set,
 357                 .process = &r100_irq_process,
 358         },
 359         .get_vblank_counter = &r100_get_vblank_counter,
 360         .copy = {
 361                 .blit = &r100_copy_blit,
 362                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 363                 .dma = &r200_copy_dma,
 364                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 365                 .copy = &r100_copy_blit,
 366                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 367         },
 368         .get_engine_clock = &radeon_legacy_get_engine_clock,
 369         .set_engine_clock = &radeon_legacy_set_engine_clock,
 370         .get_memory_clock = &radeon_legacy_get_memory_clock,
 371         .set_memory_clock = NULL,
 372         .set_pcie_lanes = &rv370_set_pcie_lanes,
 373         .set_clock_gating = &radeon_legacy_set_clock_gating,
 374         .set_surface_reg = r100_set_surface_reg,
 375         .clear_surface_reg = r100_clear_surface_reg,
 376         .bandwidth_update = &r100_bandwidth_update,
 377         .hpd = {
 378                 .init = &r100_hpd_init,
 379                 .fini = &r100_hpd_fini,
 380                 .sense = &r100_hpd_sense,
 381                 .set_polarity = &r100_hpd_set_polarity,
 382         },
 383         .ioctl_wait_idle = NULL,
 384         .gui_idle = &r100_gui_idle,
 385         .pm = {
 386                 .misc = &r100_pm_misc,
 387                 .prepare = &r100_pm_prepare,
 388                 .finish = &r100_pm_finish,
 389                 .init_profile = &r100_pm_init_profile,
 390                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 391         },
 392         .pflip = {
 393                 .pre_page_flip = &r100_pre_page_flip,
 394                 .page_flip = &r100_page_flip,
 395                 .post_page_flip = &r100_post_page_flip,
 396         },
 397         .wait_for_vblank = &r100_wait_for_vblank,
 398         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 399 };
 400
 401 static struct radeon_asic r420_asic = {
 402         .init = &r420_init,
 403         .fini = &r420_fini,
 404         .suspend = &r420_suspend,
 405         .resume = &r420_resume,
 406         .vga_set_state = &r100_vga_set_state,
 407         .gpu_is_lockup = &r300_gpu_is_lockup,
 408         .asic_reset = &r300_asic_reset,
 409         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 410         .gart_set_page = &rv370_pcie_gart_set_page,
 411         .ring = {
 412                 [RADEON_RING_TYPE_GFX_INDEX] = {
 413                         .ib_execute = &r100_ring_ib_execute,
 414                         .emit_fence = &r300_fence_ring_emit,
 415                         .emit_semaphore = &r100_semaphore_ring_emit,
 416                         .cs_parse = &r300_cs_parse,
 417                         .ring_start = &r300_ring_start,
 418                         .ring_test = &r100_ring_test,
 419                         .ib_test = &r100_ib_test,
 420                 }
 421         },
 422         .irq = {
 423                 .set = &r100_irq_set,
 424                 .process = &r100_irq_process,
 425         },
 426         .get_vblank_counter = &r100_get_vblank_counter,
 427         .copy = {
 428                 .blit = &r100_copy_blit,
 429                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 430                 .dma = &r200_copy_dma,
 431                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 432                 .copy = &r100_copy_blit,
 433                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 434         },
 435         .get_engine_clock = &radeon_atom_get_engine_clock,
 436         .set_engine_clock = &radeon_atom_set_engine_clock,
 437         .get_memory_clock = &radeon_atom_get_memory_clock,
 438         .set_memory_clock = &radeon_atom_set_memory_clock,
 439         .get_pcie_lanes = &rv370_get_pcie_lanes,
 440         .set_pcie_lanes = &rv370_set_pcie_lanes,
 441         .set_clock_gating = &radeon_atom_set_clock_gating,
 442         .set_surface_reg = r100_set_surface_reg,
 443         .clear_surface_reg = r100_clear_surface_reg,
 444         .bandwidth_update = &r100_bandwidth_update,
 445         .hpd = {
 446                 .init = &r100_hpd_init,
 447                 .fini = &r100_hpd_fini,
 448                 .sense = &r100_hpd_sense,
 449                 .set_polarity = &r100_hpd_set_polarity,
 450         },
 451         .ioctl_wait_idle = NULL,
 452         .gui_idle = &r100_gui_idle,
 453         .pm = {
 454                 .misc = &r100_pm_misc,
 455                 .prepare = &r100_pm_prepare,
 456                 .finish = &r100_pm_finish,
 457                 .init_profile = &r420_pm_init_profile,
 458                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 459         },
 460         .pflip = {
 461                 .pre_page_flip = &r100_pre_page_flip,
 462                 .page_flip = &r100_page_flip,
 463                 .post_page_flip = &r100_post_page_flip,
 464         },
 465         .wait_for_vblank = &r100_wait_for_vblank,
 466         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 467 };
 468
 469 static struct radeon_asic rs400_asic = {
 470         .init = &rs400_init,
 471         .fini = &rs400_fini,
 472         .suspend = &rs400_suspend,
 473         .resume = &rs400_resume,
 474         .vga_set_state = &r100_vga_set_state,
 475         .gpu_is_lockup = &r300_gpu_is_lockup,
 476         .asic_reset = &r300_asic_reset,
 477         .gart_tlb_flush = &rs400_gart_tlb_flush,
 478         .gart_set_page = &rs400_gart_set_page,
 479         .ring = {
 480                 [RADEON_RING_TYPE_GFX_INDEX] = {
 481                         .ib_execute = &r100_ring_ib_execute,
 482                         .emit_fence = &r300_fence_ring_emit,
 483                         .emit_semaphore = &r100_semaphore_ring_emit,
 484                         .cs_parse = &r300_cs_parse,
 485                         .ring_start = &r300_ring_start,
 486                         .ring_test = &r100_ring_test,
 487                         .ib_test = &r100_ib_test,
 488                 }
 489         },
 490         .irq = {
 491                 .set = &r100_irq_set,
 492                 .process = &r100_irq_process,
 493         },
 494         .get_vblank_counter = &r100_get_vblank_counter,
 495         .copy = {
 496                 .blit = &r100_copy_blit,
 497                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 498                 .dma = &r200_copy_dma,
 499                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 500                 .copy = &r100_copy_blit,
 501                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 502         },
 503         .get_engine_clock = &radeon_legacy_get_engine_clock,
 504         .set_engine_clock = &radeon_legacy_set_engine_clock,
 505         .get_memory_clock = &radeon_legacy_get_memory_clock,
 506         .set_memory_clock = NULL,
 507         .get_pcie_lanes = NULL,
 508         .set_pcie_lanes = NULL,
 509         .set_clock_gating = &radeon_legacy_set_clock_gating,
 510         .set_surface_reg = r100_set_surface_reg,
 511         .clear_surface_reg = r100_clear_surface_reg,
 512         .bandwidth_update = &r100_bandwidth_update,
 513         .hpd = {
 514                 .init = &r100_hpd_init,
 515                 .fini = &r100_hpd_fini,
 516                 .sense = &r100_hpd_sense,
 517                 .set_polarity = &r100_hpd_set_polarity,
 518         },
 519         .ioctl_wait_idle = NULL,
 520         .gui_idle = &r100_gui_idle,
 521         .pm = {
 522                 .misc = &r100_pm_misc,
 523                 .prepare = &r100_pm_prepare,
 524                 .finish = &r100_pm_finish,
 525                 .init_profile = &r100_pm_init_profile,
 526                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 527         },
 528         .pflip = {
 529                 .pre_page_flip = &r100_pre_page_flip,
 530                 .page_flip = &r100_page_flip,
 531                 .post_page_flip = &r100_post_page_flip,
 532         },
 533         .wait_for_vblank = &r100_wait_for_vblank,
 534         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 535 };
 536
 537 static struct radeon_asic rs600_asic = {
 538         .init = &rs600_init,
 539         .fini = &rs600_fini,
 540         .suspend = &rs600_suspend,
 541         .resume = &rs600_resume,
 542         .vga_set_state = &r100_vga_set_state,
 543         .gpu_is_lockup = &r300_gpu_is_lockup,
 544         .asic_reset = &rs600_asic_reset,
 545         .gart_tlb_flush = &rs600_gart_tlb_flush,
 546         .gart_set_page = &rs600_gart_set_page,
 547         .ring = {
 548                 [RADEON_RING_TYPE_GFX_INDEX] = {
 549                         .ib_execute = &r100_ring_ib_execute,
 550                         .emit_fence = &r300_fence_ring_emit,
 551                         .emit_semaphore = &r100_semaphore_ring_emit,
 552                         .cs_parse = &r300_cs_parse,
 553                         .ring_start = &r300_ring_start,
 554                         .ring_test = &r100_ring_test,
 555                         .ib_test = &r100_ib_test,
 556                 }
 557         },
 558         .irq = {
 559                 .set = &rs600_irq_set,
 560                 .process = &rs600_irq_process,
 561         },
 562         .get_vblank_counter = &rs600_get_vblank_counter,
 563         .copy = {
 564                 .blit = &r100_copy_blit,
 565                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 566                 .dma = &r200_copy_dma,
 567                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 568                 .copy = &r100_copy_blit,
 569                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 570         },
 571         .get_engine_clock = &radeon_atom_get_engine_clock,
 572         .set_engine_clock = &radeon_atom_set_engine_clock,
 573         .get_memory_clock = &radeon_atom_get_memory_clock,
 574         .set_memory_clock = &radeon_atom_set_memory_clock,
 575         .get_pcie_lanes = NULL,
 576         .set_pcie_lanes = NULL,
 577         .set_clock_gating = &radeon_atom_set_clock_gating,
 578         .set_surface_reg = r100_set_surface_reg,
 579         .clear_surface_reg = r100_clear_surface_reg,
 580         .bandwidth_update = &rs600_bandwidth_update,
 581         .hpd = {
 582                 .init = &rs600_hpd_init,
 583                 .fini = &rs600_hpd_fini,
 584                 .sense = &rs600_hpd_sense,
 585                 .set_polarity = &rs600_hpd_set_polarity,
 586         },
 587         .ioctl_wait_idle = NULL,
 588         .gui_idle = &r100_gui_idle,
 589         .pm = {
 590                 .misc = &rs600_pm_misc,
 591                 .prepare = &rs600_pm_prepare,
 592                 .finish = &rs600_pm_finish,
 593                 .init_profile = &r420_pm_init_profile,
 594                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 595         },
 596         .pflip = {
 597                 .pre_page_flip = &rs600_pre_page_flip,
 598                 .page_flip = &rs600_page_flip,
 599                 .post_page_flip = &rs600_post_page_flip,
 600         },
 601         .wait_for_vblank = &avivo_wait_for_vblank,
 602         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 603 };
 604
 605 static struct radeon_asic rs690_asic = {
 606         .init = &rs690_init,
 607         .fini = &rs690_fini,
 608         .suspend = &rs690_suspend,
 609         .resume = &rs690_resume,
 610         .vga_set_state = &r100_vga_set_state,
 611         .gpu_is_lockup = &r300_gpu_is_lockup,
 612         .asic_reset = &rs600_asic_reset,
 613         .gart_tlb_flush = &rs400_gart_tlb_flush,
 614         .gart_set_page = &rs400_gart_set_page,
 615         .ring = {
 616                 [RADEON_RING_TYPE_GFX_INDEX] = {
 617                         .ib_execute = &r100_ring_ib_execute,
 618                         .emit_fence = &r300_fence_ring_emit,
 619                         .emit_semaphore = &r100_semaphore_ring_emit,
 620                         .cs_parse = &r300_cs_parse,
 621                         .ring_start = &r300_ring_start,
 622                         .ring_test = &r100_ring_test,
 623                         .ib_test = &r100_ib_test,
 624                 }
 625         },
 626         .irq = {
 627                 .set = &rs600_irq_set,
 628                 .process = &rs600_irq_process,
 629         },
 630         .get_vblank_counter = &rs600_get_vblank_counter,
 631         .copy = {
 632                 .blit = &r100_copy_blit,
 633                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 634                 .dma = &r200_copy_dma,
 635                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 636                 .copy = &r200_copy_dma,
 637                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 638         },
 639         .get_engine_clock = &radeon_atom_get_engine_clock,
 640         .set_engine_clock = &radeon_atom_set_engine_clock,
 641         .get_memory_clock = &radeon_atom_get_memory_clock,
 642         .set_memory_clock = &radeon_atom_set_memory_clock,
 643         .get_pcie_lanes = NULL,
 644         .set_pcie_lanes = NULL,
 645         .set_clock_gating = &radeon_atom_set_clock_gating,
 646         .set_surface_reg = r100_set_surface_reg,
 647         .clear_surface_reg = r100_clear_surface_reg,
 648         .bandwidth_update = &rs690_bandwidth_update,
 649         .hpd = {
 650                 .init = &rs600_hpd_init,
 651                 .fini = &rs600_hpd_fini,
 652                 .sense = &rs600_hpd_sense,
 653                 .set_polarity = &rs600_hpd_set_polarity,
 654         },
 655         .ioctl_wait_idle = NULL,
 656         .gui_idle = &r100_gui_idle,
 657         .pm = {
 658                 .misc = &rs600_pm_misc,
 659                 .prepare = &rs600_pm_prepare,
 660                 .finish = &rs600_pm_finish,
 661                 .init_profile = &r420_pm_init_profile,
 662                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 663         },
 664         .pflip = {
 665                 .pre_page_flip = &rs600_pre_page_flip,
 666                 .page_flip = &rs600_page_flip,
 667                 .post_page_flip = &rs600_post_page_flip,
 668         },
 669         .wait_for_vblank = &avivo_wait_for_vblank,
 670         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 671 };
 672
 673 static struct radeon_asic rv515_asic = {
 674         .init = &rv515_init,
 675         .fini = &rv515_fini,
 676         .suspend = &rv515_suspend,
 677         .resume = &rv515_resume,
 678         .vga_set_state = &r100_vga_set_state,
 679         .gpu_is_lockup = &r300_gpu_is_lockup,
 680         .asic_reset = &rs600_asic_reset,
 681         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 682         .gart_set_page = &rv370_pcie_gart_set_page,
 683         .ring = {
 684                 [RADEON_RING_TYPE_GFX_INDEX] = {
 685                         .ib_execute = &r100_ring_ib_execute,
 686                         .emit_fence = &r300_fence_ring_emit,
 687                         .emit_semaphore = &r100_semaphore_ring_emit,
 688                         .cs_parse = &r300_cs_parse,
 689                         .ring_start = &rv515_ring_start,
 690                         .ring_test = &r100_ring_test,
 691                         .ib_test = &r100_ib_test,
 692                 }
 693         },
 694         .irq = {
 695                 .set = &rs600_irq_set,
 696                 .process = &rs600_irq_process,
 697         },
 698         .get_vblank_counter = &rs600_get_vblank_counter,
 699         .copy = {
 700                 .blit = &r100_copy_blit,
 701                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 702                 .dma = &r200_copy_dma,
 703                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 704                 .copy = &r100_copy_blit,
 705                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 706         },
 707         .get_engine_clock = &radeon_atom_get_engine_clock,
 708         .set_engine_clock = &radeon_atom_set_engine_clock,
 709         .get_memory_clock = &radeon_atom_get_memory_clock,
 710         .set_memory_clock = &radeon_atom_set_memory_clock,
 711         .get_pcie_lanes = &rv370_get_pcie_lanes,
 712         .set_pcie_lanes = &rv370_set_pcie_lanes,
 713         .set_clock_gating = &radeon_atom_set_clock_gating,
 714         .set_surface_reg = r100_set_surface_reg,
 715         .clear_surface_reg = r100_clear_surface_reg,
 716         .bandwidth_update = &rv515_bandwidth_update,
 717         .hpd = {
 718                 .init = &rs600_hpd_init,
 719                 .fini = &rs600_hpd_fini,
 720                 .sense = &rs600_hpd_sense,
 721                 .set_polarity = &rs600_hpd_set_polarity,
 722         },
 723         .ioctl_wait_idle = NULL,
 724         .gui_idle = &r100_gui_idle,
 725         .pm = {
 726                 .misc = &rs600_pm_misc,
 727                 .prepare = &rs600_pm_prepare,
 728                 .finish = &rs600_pm_finish,
 729                 .init_profile = &r420_pm_init_profile,
 730                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 731         },
 732         .pflip = {
 733                 .pre_page_flip = &rs600_pre_page_flip,
 734                 .page_flip = &rs600_page_flip,
 735                 .post_page_flip = &rs600_post_page_flip,
 736         },
 737         .wait_for_vblank = &avivo_wait_for_vblank,
 738         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 739 };
 740
 741 static struct radeon_asic r520_asic = {
 742         .init = &r520_init,
 743         .fini = &rv515_fini,
 744         .suspend = &rv515_suspend,
 745         .resume = &r520_resume,
 746         .vga_set_state = &r100_vga_set_state,
 747         .gpu_is_lockup = &r300_gpu_is_lockup,
 748         .asic_reset = &rs600_asic_reset,
 749         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 750         .gart_set_page = &rv370_pcie_gart_set_page,
 751         .ring = {
 752                 [RADEON_RING_TYPE_GFX_INDEX] = {
 753                         .ib_execute = &r100_ring_ib_execute,
 754                         .emit_fence = &r300_fence_ring_emit,
 755                         .emit_semaphore = &r100_semaphore_ring_emit,
 756                         .cs_parse = &r300_cs_parse,
 757                         .ring_start = &rv515_ring_start,
 758                         .ring_test = &r100_ring_test,
 759                         .ib_test = &r100_ib_test,
 760                 }
 761         },
 762         .irq = {
 763                 .set = &rs600_irq_set,
 764                 .process = &rs600_irq_process,
 765         },
 766         .get_vblank_counter = &rs600_get_vblank_counter,
 767         .copy = {
 768                 .blit = &r100_copy_blit,
 769                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 770                 .dma = &r200_copy_dma,
 771                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 772                 .copy = &r100_copy_blit,
 773                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 774         },
 775         .get_engine_clock = &radeon_atom_get_engine_clock,
 776         .set_engine_clock = &radeon_atom_set_engine_clock,
 777         .get_memory_clock = &radeon_atom_get_memory_clock,
 778         .set_memory_clock = &radeon_atom_set_memory_clock,
 779         .get_pcie_lanes = &rv370_get_pcie_lanes,
 780         .set_pcie_lanes = &rv370_set_pcie_lanes,
 781         .set_clock_gating = &radeon_atom_set_clock_gating,
 782         .set_surface_reg = r100_set_surface_reg,
 783         .clear_surface_reg = r100_clear_surface_reg,
 784         .bandwidth_update = &rv515_bandwidth_update,
 785         .hpd = {
 786                 .init = &rs600_hpd_init,
 787                 .fini = &rs600_hpd_fini,
 788                 .sense = &rs600_hpd_sense,
 789                 .set_polarity = &rs600_hpd_set_polarity,
 790         },
 791         .ioctl_wait_idle = NULL,
 792         .gui_idle = &r100_gui_idle,
 793         .pm = {
 794                 .misc = &rs600_pm_misc,
 795                 .prepare = &rs600_pm_prepare,
 796                 .finish = &rs600_pm_finish,
 797                 .init_profile = &r420_pm_init_profile,
 798                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 799         },
 800         .pflip = {
 801                 .pre_page_flip = &rs600_pre_page_flip,
 802                 .page_flip = &rs600_page_flip,
 803                 .post_page_flip = &rs600_post_page_flip,
 804         },
 805         .wait_for_vblank = &avivo_wait_for_vblank,
 806         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 807 };
 808
 809 static struct radeon_asic r600_asic = {
 810         .init = &r600_init,
 811         .fini = &r600_fini,
 812         .suspend = &r600_suspend,
 813         .resume = &r600_resume,
 814         .vga_set_state = &r600_vga_set_state,
 815         .gpu_is_lockup = &r600_gpu_is_lockup,
 816         .asic_reset = &r600_asic_reset,
 817         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 818         .gart_set_page = &rs600_gart_set_page,
 819         .ring = {
 820                 [RADEON_RING_TYPE_GFX_INDEX] = {
 821                         .ib_execute = &r600_ring_ib_execute,
 822                         .emit_fence = &r600_fence_ring_emit,
 823                         .emit_semaphore = &r600_semaphore_ring_emit,
 824                         .cs_parse = &r600_cs_parse,
 825                         .ring_test = &r600_ring_test,
 826                         .ib_test = &r600_ib_test,
 827                 }
 828         },
 829         .irq = {
 830                 .set = &r600_irq_set,
 831                 .process = &r600_irq_process,
 832         },
 833         .get_vblank_counter = &rs600_get_vblank_counter,
 834         .copy = {
 835                 .blit = &r600_copy_blit,
 836                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 837                 .dma = NULL,
 838                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 839                 .copy = &r600_copy_blit,
 840                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 841         },
 842         .get_engine_clock = &radeon_atom_get_engine_clock,
 843         .set_engine_clock = &radeon_atom_set_engine_clock,
 844         .get_memory_clock = &radeon_atom_get_memory_clock,
 845         .set_memory_clock = &radeon_atom_set_memory_clock,
 846         .get_pcie_lanes = &r600_get_pcie_lanes,
 847         .set_pcie_lanes = &r600_set_pcie_lanes,
 848         .set_clock_gating = NULL,
 849         .set_surface_reg = r600_set_surface_reg,
 850         .clear_surface_reg = r600_clear_surface_reg,
 851         .bandwidth_update = &rv515_bandwidth_update,
 852         .hpd = {
 853                 .init = &r600_hpd_init,
 854                 .fini = &r600_hpd_fini,
 855                 .sense = &r600_hpd_sense,
 856                 .set_polarity = &r600_hpd_set_polarity,
 857         },
 858         .ioctl_wait_idle = r600_ioctl_wait_idle,
 859         .gui_idle = &r600_gui_idle,
 860         .pm = {
 861                 .misc = &r600_pm_misc,
 862                 .prepare = &rs600_pm_prepare,
 863                 .finish = &rs600_pm_finish,
 864                 .init_profile = &r600_pm_init_profile,
 865                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 866         },
 867         .pflip = {
 868                 .pre_page_flip = &rs600_pre_page_flip,
 869                 .page_flip = &rs600_page_flip,
 870                 .post_page_flip = &rs600_post_page_flip,
 871         },
 872         .wait_for_vblank = &avivo_wait_for_vblank,
 873         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 874 };
 875
 876 static struct radeon_asic rs780_asic = {
 877         .init = &r600_init,
 878         .fini = &r600_fini,
 879         .suspend = &r600_suspend,
 880         .resume = &r600_resume,
 881         .gpu_is_lockup = &r600_gpu_is_lockup,
 882         .vga_set_state = &r600_vga_set_state,
 883         .asic_reset = &r600_asic_reset,
 884         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 885         .gart_set_page = &rs600_gart_set_page,
 886         .ring = {
 887                 [RADEON_RING_TYPE_GFX_INDEX] = {
 888                         .ib_execute = &r600_ring_ib_execute,
 889                         .emit_fence = &r600_fence_ring_emit,
 890                         .emit_semaphore = &r600_semaphore_ring_emit,
 891                         .cs_parse = &r600_cs_parse,
 892                         .ring_test = &r600_ring_test,
 893                         .ib_test = &r600_ib_test,
 894                 }
 895         },
 896         .irq = {
 897                 .set = &r600_irq_set,
 898                 .process = &r600_irq_process,
 899         },
 900         .get_vblank_counter = &rs600_get_vblank_counter,
 901         .copy = {
 902                 .blit = &r600_copy_blit,
 903                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 904                 .dma = NULL,
 905                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 906                 .copy = &r600_copy_blit,
 907                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 908         },
 909         .get_engine_clock = &radeon_atom_get_engine_clock,
 910         .set_engine_clock = &radeon_atom_set_engine_clock,
 911         .get_memory_clock = NULL,
 912         .set_memory_clock = NULL,
 913         .get_pcie_lanes = NULL,
 914         .set_pcie_lanes = NULL,
 915         .set_clock_gating = NULL,
 916         .set_surface_reg = r600_set_surface_reg,
 917         .clear_surface_reg = r600_clear_surface_reg,
 918         .bandwidth_update = &rs690_bandwidth_update,
 919         .hpd = {
 920                 .init = &r600_hpd_init,
 921                 .fini = &r600_hpd_fini,
 922                 .sense = &r600_hpd_sense,
 923                 .set_polarity = &r600_hpd_set_polarity,
 924         },
 925         .ioctl_wait_idle = r600_ioctl_wait_idle,
 926         .gui_idle = &r600_gui_idle,
 927         .pm = {
 928                 .misc = &r600_pm_misc,
 929                 .prepare = &rs600_pm_prepare,
 930                 .finish = &rs600_pm_finish,
 931                 .init_profile = &rs780_pm_init_profile,
 932                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 933         },
 934         .pflip = {
 935                 .pre_page_flip = &rs600_pre_page_flip,
 936                 .page_flip = &rs600_page_flip,
 937                 .post_page_flip = &rs600_post_page_flip,
 938         },
 939         .wait_for_vblank = &avivo_wait_for_vblank,
 940         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 941 };
 942
 943 static struct radeon_asic rv770_asic = {
 944         .init = &rv770_init,
 945         .fini = &rv770_fini,
 946         .suspend = &rv770_suspend,
 947         .resume = &rv770_resume,
 948         .asic_reset = &r600_asic_reset,
 949         .gpu_is_lockup = &r600_gpu_is_lockup,
 950         .vga_set_state = &r600_vga_set_state,
 951         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 952         .gart_set_page = &rs600_gart_set_page,
 953         .ring = {
 954                 [RADEON_RING_TYPE_GFX_INDEX] = {
 955                         .ib_execute = &r600_ring_ib_execute,
 956                         .emit_fence = &r600_fence_ring_emit,
 957                         .emit_semaphore = &r600_semaphore_ring_emit,
 958                         .cs_parse = &r600_cs_parse,
 959                         .ring_test = &r600_ring_test,
 960                         .ib_test = &r600_ib_test,
 961                 }
 962         },
 963         .irq = {
 964                 .set = &r600_irq_set,
 965                 .process = &r600_irq_process,
 966         },
 967         .get_vblank_counter = &rs600_get_vblank_counter,
 968         .copy = {
 969                 .blit = &r600_copy_blit,
 970                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 971                 .dma = NULL,
 972                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 973                 .copy = &r600_copy_blit,
 974                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 975         },
 976         .get_engine_clock = &radeon_atom_get_engine_clock,
 977         .set_engine_clock = &radeon_atom_set_engine_clock,
 978         .get_memory_clock = &radeon_atom_get_memory_clock,
 979         .set_memory_clock = &radeon_atom_set_memory_clock,
 980         .get_pcie_lanes = &r600_get_pcie_lanes,
 981         .set_pcie_lanes = &r600_set_pcie_lanes,
 982         .set_clock_gating = &radeon_atom_set_clock_gating,
 983         .set_surface_reg = r600_set_surface_reg,
 984         .clear_surface_reg = r600_clear_surface_reg,
 985         .bandwidth_update = &rv515_bandwidth_update,
 986         .hpd = {
 987                 .init = &r600_hpd_init,
 988                 .fini = &r600_hpd_fini,
 989                 .sense = &r600_hpd_sense,
 990                 .set_polarity = &r600_hpd_set_polarity,
 991         },
 992         .ioctl_wait_idle = r600_ioctl_wait_idle,
 993         .gui_idle = &r600_gui_idle,
 994         .pm = {
 995                 .misc = &rv770_pm_misc,
 996                 .prepare = &rs600_pm_prepare,
 997                 .finish = &rs600_pm_finish,
 998                 .init_profile = &r600_pm_init_profile,
 999                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1000         },
1001         .pflip = {
1002                 .pre_page_flip = &rs600_pre_page_flip,
1003                 .page_flip = &rv770_page_flip,
1004                 .post_page_flip = &rs600_post_page_flip,
1005         },
1006         .wait_for_vblank = &avivo_wait_for_vblank,
1007         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1008 };
1009
1010 static struct radeon_asic evergreen_asic = {
1011         .init = &evergreen_init,
1012         .fini = &evergreen_fini,
1013         .suspend = &evergreen_suspend,
1014         .resume = &evergreen_resume,
1015         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1016         .asic_reset = &evergreen_asic_reset,
1017         .vga_set_state = &r600_vga_set_state,
1018         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1019         .gart_set_page = &rs600_gart_set_page,
1020         .ring = {
1021                 [RADEON_RING_TYPE_GFX_INDEX] = {
1022                         .ib_execute = &evergreen_ring_ib_execute,
1023                         .emit_fence = &r600_fence_ring_emit,
1024                         .emit_semaphore = &r600_semaphore_ring_emit,
1025                         .cs_parse = &evergreen_cs_parse,
1026                         .ring_test = &r600_ring_test,
1027                         .ib_test = &r600_ib_test,
1028                 }
1029         },
1030         .irq = {
1031                 .set = &evergreen_irq_set,
1032                 .process = &evergreen_irq_process,
1033         },
1034         .get_vblank_counter = &evergreen_get_vblank_counter,
1035         .copy = {
1036                 .blit = &r600_copy_blit,
1037                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1038                 .dma = NULL,
1039                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1040                 .copy = &r600_copy_blit,
1041                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1042         },
1043         .get_engine_clock = &radeon_atom_get_engine_clock,
1044         .set_engine_clock = &radeon_atom_set_engine_clock,
1045         .get_memory_clock = &radeon_atom_get_memory_clock,
1046         .set_memory_clock = &radeon_atom_set_memory_clock,
1047         .get_pcie_lanes = &r600_get_pcie_lanes,
1048         .set_pcie_lanes = &r600_set_pcie_lanes,
1049         .set_clock_gating = NULL,
1050         .set_surface_reg = r600_set_surface_reg,
1051         .clear_surface_reg = r600_clear_surface_reg,
1052         .bandwidth_update = &evergreen_bandwidth_update,
1053         .hpd = {
1054                 .init = &evergreen_hpd_init,
1055                 .fini = &evergreen_hpd_fini,
1056                 .sense = &evergreen_hpd_sense,
1057                 .set_polarity = &evergreen_hpd_set_polarity,
1058         },
1059         .ioctl_wait_idle = r600_ioctl_wait_idle,
1060         .gui_idle = &r600_gui_idle,
1061         .pm = {
1062                 .misc = &evergreen_pm_misc,
1063                 .prepare = &evergreen_pm_prepare,
1064                 .finish = &evergreen_pm_finish,
1065                 .init_profile = &r600_pm_init_profile,
1066                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1067         },
1068         .pflip = {
1069                 .pre_page_flip = &evergreen_pre_page_flip,
1070                 .page_flip = &evergreen_page_flip,
1071                 .post_page_flip = &evergreen_post_page_flip,
1072         },
1073         .wait_for_vblank = &dce4_wait_for_vblank,
1074         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1075 };
1076
1077 static struct radeon_asic sumo_asic = {
1078         .init = &evergreen_init,
1079         .fini = &evergreen_fini,
1080         .suspend = &evergreen_suspend,
1081         .resume = &evergreen_resume,
1082         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1083         .asic_reset = &evergreen_asic_reset,
1084         .vga_set_state = &r600_vga_set_state,
1085         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1086         .gart_set_page = &rs600_gart_set_page,
1087         .ring = {
1088                 [RADEON_RING_TYPE_GFX_INDEX] = {
1089                         .ib_execute = &evergreen_ring_ib_execute,
1090                         .emit_fence = &r600_fence_ring_emit,
1091                         .emit_semaphore = &r600_semaphore_ring_emit,
1092                         .cs_parse = &evergreen_cs_parse,
1093                         .ring_test = &r600_ring_test,
1094                         .ib_test = &r600_ib_test,
1095                 },
1096         },
1097         .irq = {
1098                 .set = &evergreen_irq_set,
1099                 .process = &evergreen_irq_process,
1100         },
1101         .get_vblank_counter = &evergreen_get_vblank_counter,
1102         .copy = {
1103                 .blit = &r600_copy_blit,
1104                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1105                 .dma = NULL,
1106                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1107                 .copy = &r600_copy_blit,
1108                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1109         },
1110         .get_engine_clock = &radeon_atom_get_engine_clock,
1111         .set_engine_clock = &radeon_atom_set_engine_clock,
1112         .get_memory_clock = NULL,
1113         .set_memory_clock = NULL,
1114         .get_pcie_lanes = NULL,
1115         .set_pcie_lanes = NULL,
1116         .set_clock_gating = NULL,
1117         .set_surface_reg = r600_set_surface_reg,
1118         .clear_surface_reg = r600_clear_surface_reg,
1119         .bandwidth_update = &evergreen_bandwidth_update,
1120         .hpd = {
1121                 .init = &evergreen_hpd_init,
1122                 .fini = &evergreen_hpd_fini,
1123                 .sense = &evergreen_hpd_sense,
1124                 .set_polarity = &evergreen_hpd_set_polarity,
1125         },
1126         .ioctl_wait_idle = r600_ioctl_wait_idle,
1127         .gui_idle = &r600_gui_idle,
1128         .pm = {
1129                 .misc = &evergreen_pm_misc,
1130                 .prepare = &evergreen_pm_prepare,
1131                 .finish = &evergreen_pm_finish,
1132                 .init_profile = &sumo_pm_init_profile,
1133                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1134         },
1135         .pflip = {
1136                 .pre_page_flip = &evergreen_pre_page_flip,
1137                 .page_flip = &evergreen_page_flip,
1138                 .post_page_flip = &evergreen_post_page_flip,
1139         },
1140         .wait_for_vblank = &dce4_wait_for_vblank,
1141         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1142 };
1143
1144 static struct radeon_asic btc_asic = {
1145         .init = &evergreen_init,
1146         .fini = &evergreen_fini,
1147         .suspend = &evergreen_suspend,
1148         .resume = &evergreen_resume,
1149         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1150         .asic_reset = &evergreen_asic_reset,
1151         .vga_set_state = &r600_vga_set_state,
1152         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1153         .gart_set_page = &rs600_gart_set_page,
1154         .ring = {
1155                 [RADEON_RING_TYPE_GFX_INDEX] = {
1156                         .ib_execute = &evergreen_ring_ib_execute,
1157                         .emit_fence = &r600_fence_ring_emit,
1158                         .emit_semaphore = &r600_semaphore_ring_emit,
1159                         .cs_parse = &evergreen_cs_parse,
1160                         .ring_test = &r600_ring_test,
1161                         .ib_test = &r600_ib_test,
1162                 }
1163         },
1164         .irq = {
1165                 .set = &evergreen_irq_set,
1166                 .process = &evergreen_irq_process,
1167         },
1168         .get_vblank_counter = &evergreen_get_vblank_counter,
1169         .copy = {
1170                 .blit = &r600_copy_blit,
1171                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1172                 .dma = NULL,
1173                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1174                 .copy = &r600_copy_blit,
1175                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1176         },
1177         .get_engine_clock = &radeon_atom_get_engine_clock,
1178         .set_engine_clock = &radeon_atom_set_engine_clock,
1179         .get_memory_clock = &radeon_atom_get_memory_clock,
1180         .set_memory_clock = &radeon_atom_set_memory_clock,
1181         .get_pcie_lanes = NULL,
1182         .set_pcie_lanes = NULL,
1183         .set_clock_gating = NULL,
1184         .set_surface_reg = r600_set_surface_reg,
1185         .clear_surface_reg = r600_clear_surface_reg,
1186         .bandwidth_update = &evergreen_bandwidth_update,
1187         .hpd = {
1188                 .init = &evergreen_hpd_init,
1189                 .fini = &evergreen_hpd_fini,
1190                 .sense = &evergreen_hpd_sense,
1191                 .set_polarity = &evergreen_hpd_set_polarity,
1192         },
1193         .ioctl_wait_idle = r600_ioctl_wait_idle,
1194         .gui_idle = &r600_gui_idle,
1195         .pm = {
1196                 .misc = &evergreen_pm_misc,
1197                 .prepare = &evergreen_pm_prepare,
1198                 .finish = &evergreen_pm_finish,
1199                 .init_profile = &r600_pm_init_profile,
1200                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1201         },
1202         .pflip = {
1203                 .pre_page_flip = &evergreen_pre_page_flip,
1204                 .page_flip = &evergreen_page_flip,
1205                 .post_page_flip = &evergreen_post_page_flip,
1206         },
1207         .wait_for_vblank = &dce4_wait_for_vblank,
1208         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1209 };
1210
1211 static const struct radeon_vm_funcs cayman_vm_funcs = {
1212         .init = &cayman_vm_init,
1213         .fini = &cayman_vm_fini,
1214         .bind = &cayman_vm_bind,
1215         .unbind = &cayman_vm_unbind,
1216         .tlb_flush = &cayman_vm_tlb_flush,
1217         .page_flags = &cayman_vm_page_flags,
1218         .set_page = &cayman_vm_set_page,
1219 };
1220
1221 static struct radeon_asic cayman_asic = {
1222         .init = &cayman_init,
1223         .fini = &cayman_fini,
1224         .suspend = &cayman_suspend,
1225         .resume = &cayman_resume,
1226         .gpu_is_lockup = &cayman_gpu_is_lockup,
1227         .asic_reset = &cayman_asic_reset,
1228         .vga_set_state = &r600_vga_set_state,
1229         .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
1230         .gart_set_page = &rs600_gart_set_page,
1231         .ring = {
1232                 [RADEON_RING_TYPE_GFX_INDEX] = {
1233                         .ib_execute = &cayman_ring_ib_execute,
1234                         .ib_parse = &evergreen_ib_parse,
1235                         .emit_fence = &cayman_fence_ring_emit,
1236                         .emit_semaphore = &r600_semaphore_ring_emit,
1237                         .cs_parse = &evergreen_cs_parse,
1238                         .ring_test = &r600_ring_test,
1239                         .ib_test = &r600_ib_test,
1240                 },
1241                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1242                         .ib_execute = &cayman_ring_ib_execute,
1243                         .ib_parse = &evergreen_ib_parse,
1244                         .emit_fence = &cayman_fence_ring_emit,
1245                         .emit_semaphore = &r600_semaphore_ring_emit,
1246                         .cs_parse = &evergreen_cs_parse,
1247                         .ring_test = &r600_ring_test,
1248                         .ib_test = &r600_ib_test,
1249                 },
1250                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1251                         .ib_execute = &cayman_ring_ib_execute,
1252                         .ib_parse = &evergreen_ib_parse,
1253                         .emit_fence = &cayman_fence_ring_emit,
1254                         .emit_semaphore = &r600_semaphore_ring_emit,
1255                         .cs_parse = &evergreen_cs_parse,
1256                         .ring_test = &r600_ring_test,
1257                         .ib_test = &r600_ib_test,
1258                 }
1259         },
1260         .irq = {
1261                 .set = &evergreen_irq_set,
1262                 .process = &evergreen_irq_process,
1263         },
1264         .get_vblank_counter = &evergreen_get_vblank_counter,
1265         .copy = {
1266                 .blit = &r600_copy_blit,
1267                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1268                 .dma = NULL,
1269                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1270                 .copy = &r600_copy_blit,
1271                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1272         },
1273         .get_engine_clock = &radeon_atom_get_engine_clock,
1274         .set_engine_clock = &radeon_atom_set_engine_clock,
1275         .get_memory_clock = &radeon_atom_get_memory_clock,
1276         .set_memory_clock = &radeon_atom_set_memory_clock,
1277         .get_pcie_lanes = NULL,
1278         .set_pcie_lanes = NULL,
1279         .set_clock_gating = NULL,
1280         .set_surface_reg = r600_set_surface_reg,
1281         .clear_surface_reg = r600_clear_surface_reg,
1282         .bandwidth_update = &evergreen_bandwidth_update,
1283         .hpd = {
1284                 .init = &evergreen_hpd_init,
1285                 .fini = &evergreen_hpd_fini,
1286                 .sense = &evergreen_hpd_sense,
1287                 .set_polarity = &evergreen_hpd_set_polarity,
1288         },
1289         .ioctl_wait_idle = r600_ioctl_wait_idle,
1290         .gui_idle = &r600_gui_idle,
1291         .pm = {
1292                 .misc = &evergreen_pm_misc,
1293                 .prepare = &evergreen_pm_prepare,
1294                 .finish = &evergreen_pm_finish,
1295                 .init_profile = &r600_pm_init_profile,
1296                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1297         },
1298         .pflip = {
1299                 .pre_page_flip = &evergreen_pre_page_flip,
1300                 .page_flip = &evergreen_page_flip,
1301                 .post_page_flip = &evergreen_post_page_flip,
1302         },
1303         .wait_for_vblank = &dce4_wait_for_vblank,
1304         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1305 };
1306
1307 int radeon_asic_init(struct radeon_device *rdev)
1308 {
1309         radeon_register_accessor_init(rdev);
1310
1311         /* set the number of crtcs */
1312         if (rdev->flags & RADEON_SINGLE_CRTC)
1313                 rdev->num_crtc = 1;
1314         else
1315                 rdev->num_crtc = 2;
1316
1317         switch (rdev->family) {
1318         case CHIP_R100:
1319         case CHIP_RV100:
1320         case CHIP_RS100:
1321         case CHIP_RV200:
1322         case CHIP_RS200:
1323                 rdev->asic = &r100_asic;
1324                 break;
1325         case CHIP_R200:
1326         case CHIP_RV250:
1327         case CHIP_RS300:
1328         case CHIP_RV280:
1329                 rdev->asic = &r200_asic;
1330                 break;
1331         case CHIP_R300:
1332         case CHIP_R350:
1333         case CHIP_RV350:
1334         case CHIP_RV380:
1335                 if (rdev->flags & RADEON_IS_PCIE)
1336                         rdev->asic = &r300_asic_pcie;
1337                 else
1338                         rdev->asic = &r300_asic;
1339                 break;
1340         case CHIP_R420:
1341         case CHIP_R423:
1342         case CHIP_RV410:
1343                 rdev->asic = &r420_asic;
1344                 /* handle macs */
1345                 if (rdev->bios == NULL) {
1346                         rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
1347                         rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
1348                         rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
1349                         rdev->asic->set_memory_clock = NULL;
1350                 }
1351                 break;
1352         case CHIP_RS400:
1353         case CHIP_RS480:
1354                 rdev->asic = &rs400_asic;
1355                 break;
1356         case CHIP_RS600:
1357                 rdev->asic = &rs600_asic;
1358                 break;
1359         case CHIP_RS690:
1360         case CHIP_RS740:
1361                 rdev->asic = &rs690_asic;
1362                 break;
1363         case CHIP_RV515:
1364                 rdev->asic = &rv515_asic;
1365                 break;
1366         case CHIP_R520:
1367         case CHIP_RV530:
1368         case CHIP_RV560:
1369         case CHIP_RV570:
1370         case CHIP_R580:
1371                 rdev->asic = &r520_asic;
1372                 break;
1373         case CHIP_R600:
1374         case CHIP_RV610:
1375         case CHIP_RV630:
1376         case CHIP_RV620:
1377         case CHIP_RV635:
1378         case CHIP_RV670:
1379                 rdev->asic = &r600_asic;
1380                 break;
1381         case CHIP_RS780:
1382         case CHIP_RS880:
1383                 rdev->asic = &rs780_asic;
1384                 break;
1385         case CHIP_RV770:
1386         case CHIP_RV730:
1387         case CHIP_RV710:
1388         case CHIP_RV740:
1389                 rdev->asic = &rv770_asic;
1390                 break;
1391         case CHIP_CEDAR:
1392         case CHIP_REDWOOD:
1393         case CHIP_JUNIPER:
1394         case CHIP_CYPRESS:
1395         case CHIP_HEMLOCK:
1396                 /* set num crtcs */
1397                 if (rdev->family == CHIP_CEDAR)
1398                         rdev->num_crtc = 4;
1399                 else
1400                         rdev->num_crtc = 6;
1401                 rdev->asic = &evergreen_asic;
1402                 break;
1403         case CHIP_PALM:
1404         case CHIP_SUMO:
1405         case CHIP_SUMO2:
1406                 rdev->asic = &sumo_asic;
1407                 break;
1408         case CHIP_BARTS:
1409         case CHIP_TURKS:
1410         case CHIP_CAICOS:
1411                 /* set num crtcs */
1412                 if (rdev->family == CHIP_CAICOS)
1413                         rdev->num_crtc = 4;
1414                 else
1415                         rdev->num_crtc = 6;
1416                 rdev->asic = &btc_asic;
1417                 break;
1418         case CHIP_CAYMAN:
1419                 rdev->asic = &cayman_asic;
1420                 /* set num crtcs */
1421                 rdev->num_crtc = 6;
1422                 rdev->vm_manager.funcs = &cayman_vm_funcs;
1423                 break;
1424         default:
1425                 /* FIXME: not supported yet */
1426                 return -EINVAL;
1427         }
1428
1429         if (rdev->flags & RADEON_IS_IGP) {
1430                 rdev->asic->get_memory_clock = NULL;
1431                 rdev->asic->set_memory_clock = NULL;
1432         }
1433
1434         return 0;
1435 }
1436