drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if (rdev->family >= CHIP_R600) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .cp_commit = &r100_cp_commit,
 142         .ring_start = &r100_ring_start,
 143         .ring_test = &r100_ring_test,
 144         .ring_ib_execute = &r100_ring_ib_execute,
 145         .irq_set = &r100_irq_set,
 146         .irq_process = &r100_irq_process,
 147         .get_vblank_counter = &r100_get_vblank_counter,
 148         .fence_ring_emit = &r100_fence_ring_emit,
 149         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 150         .cs_parse = &r100_cs_parse,
 151         .copy_blit = &r100_copy_blit,
 152         .copy_dma = NULL,
 153         .copy = &r100_copy_blit,
 154         .get_engine_clock = &radeon_legacy_get_engine_clock,
 155         .set_engine_clock = &radeon_legacy_set_engine_clock,
 156         .get_memory_clock = &radeon_legacy_get_memory_clock,
 157         .set_memory_clock = NULL,
 158         .get_pcie_lanes = NULL,
 159         .set_pcie_lanes = NULL,
 160         .set_clock_gating = &radeon_legacy_set_clock_gating,
 161         .set_surface_reg = r100_set_surface_reg,
 162         .clear_surface_reg = r100_clear_surface_reg,
 163         .bandwidth_update = &r100_bandwidth_update,
 164         .hpd_init = &r100_hpd_init,
 165         .hpd_fini = &r100_hpd_fini,
 166         .hpd_sense = &r100_hpd_sense,
 167         .hpd_set_polarity = &r100_hpd_set_polarity,
 168         .ioctl_wait_idle = NULL,
 169         .gui_idle = &r100_gui_idle,
 170         .pm_misc = &r100_pm_misc,
 171         .pm_prepare = &r100_pm_prepare,
 172         .pm_finish = &r100_pm_finish,
 173         .pm_init_profile = &r100_pm_init_profile,
 174         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 175         .pre_page_flip = &r100_pre_page_flip,
 176         .page_flip = &r100_page_flip,
 177         .post_page_flip = &r100_post_page_flip,
 178 };
 179
 180 static struct radeon_asic r200_asic = {
 181         .init = &r100_init,
 182         .fini = &r100_fini,
 183         .suspend = &r100_suspend,
 184         .resume = &r100_resume,
 185         .vga_set_state = &r100_vga_set_state,
 186         .gpu_is_lockup = &r100_gpu_is_lockup,
 187         .asic_reset = &r100_asic_reset,
 188         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 189         .gart_set_page = &r100_pci_gart_set_page,
 190         .cp_commit = &r100_cp_commit,
 191         .ring_start = &r100_ring_start,
 192         .ring_test = &r100_ring_test,
 193         .ring_ib_execute = &r100_ring_ib_execute,
 194         .irq_set = &r100_irq_set,
 195         .irq_process = &r100_irq_process,
 196         .get_vblank_counter = &r100_get_vblank_counter,
 197         .fence_ring_emit = &r100_fence_ring_emit,
 198         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 199         .cs_parse = &r100_cs_parse,
 200         .copy_blit = &r100_copy_blit,
 201         .copy_dma = &r200_copy_dma,
 202         .copy = &r100_copy_blit,
 203         .get_engine_clock = &radeon_legacy_get_engine_clock,
 204         .set_engine_clock = &radeon_legacy_set_engine_clock,
 205         .get_memory_clock = &radeon_legacy_get_memory_clock,
 206         .set_memory_clock = NULL,
 207         .set_pcie_lanes = NULL,
 208         .set_clock_gating = &radeon_legacy_set_clock_gating,
 209         .set_surface_reg = r100_set_surface_reg,
 210         .clear_surface_reg = r100_clear_surface_reg,
 211         .bandwidth_update = &r100_bandwidth_update,
 212         .hpd_init = &r100_hpd_init,
 213         .hpd_fini = &r100_hpd_fini,
 214         .hpd_sense = &r100_hpd_sense,
 215         .hpd_set_polarity = &r100_hpd_set_polarity,
 216         .ioctl_wait_idle = NULL,
 217         .gui_idle = &r100_gui_idle,
 218         .pm_misc = &r100_pm_misc,
 219         .pm_prepare = &r100_pm_prepare,
 220         .pm_finish = &r100_pm_finish,
 221         .pm_init_profile = &r100_pm_init_profile,
 222         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 223         .pre_page_flip = &r100_pre_page_flip,
 224         .page_flip = &r100_page_flip,
 225         .post_page_flip = &r100_post_page_flip,
 226 };
 227
 228 static struct radeon_asic r300_asic = {
 229         .init = &r300_init,
 230         .fini = &r300_fini,
 231         .suspend = &r300_suspend,
 232         .resume = &r300_resume,
 233         .vga_set_state = &r100_vga_set_state,
 234         .gpu_is_lockup = &r300_gpu_is_lockup,
 235         .asic_reset = &r300_asic_reset,
 236         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 237         .gart_set_page = &r100_pci_gart_set_page,
 238         .cp_commit = &r100_cp_commit,
 239         .ring_start = &r300_ring_start,
 240         .ring_test = &r100_ring_test,
 241         .ring_ib_execute = &r100_ring_ib_execute,
 242         .irq_set = &r100_irq_set,
 243         .irq_process = &r100_irq_process,
 244         .get_vblank_counter = &r100_get_vblank_counter,
 245         .fence_ring_emit = &r300_fence_ring_emit,
 246         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 247         .cs_parse = &r300_cs_parse,
 248         .copy_blit = &r100_copy_blit,
 249         .copy_dma = &r200_copy_dma,
 250         .copy = &r100_copy_blit,
 251         .get_engine_clock = &radeon_legacy_get_engine_clock,
 252         .set_engine_clock = &radeon_legacy_set_engine_clock,
 253         .get_memory_clock = &radeon_legacy_get_memory_clock,
 254         .set_memory_clock = NULL,
 255         .get_pcie_lanes = &rv370_get_pcie_lanes,
 256         .set_pcie_lanes = &rv370_set_pcie_lanes,
 257         .set_clock_gating = &radeon_legacy_set_clock_gating,
 258         .set_surface_reg = r100_set_surface_reg,
 259         .clear_surface_reg = r100_clear_surface_reg,
 260         .bandwidth_update = &r100_bandwidth_update,
 261         .hpd_init = &r100_hpd_init,
 262         .hpd_fini = &r100_hpd_fini,
 263         .hpd_sense = &r100_hpd_sense,
 264         .hpd_set_polarity = &r100_hpd_set_polarity,
 265         .ioctl_wait_idle = NULL,
 266         .gui_idle = &r100_gui_idle,
 267         .pm_misc = &r100_pm_misc,
 268         .pm_prepare = &r100_pm_prepare,
 269         .pm_finish = &r100_pm_finish,
 270         .pm_init_profile = &r100_pm_init_profile,
 271         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 272         .pre_page_flip = &r100_pre_page_flip,
 273         .page_flip = &r100_page_flip,
 274         .post_page_flip = &r100_post_page_flip,
 275 };
 276
 277 static struct radeon_asic r300_asic_pcie = {
 278         .init = &r300_init,
 279         .fini = &r300_fini,
 280         .suspend = &r300_suspend,
 281         .resume = &r300_resume,
 282         .vga_set_state = &r100_vga_set_state,
 283         .gpu_is_lockup = &r300_gpu_is_lockup,
 284         .asic_reset = &r300_asic_reset,
 285         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 286         .gart_set_page = &rv370_pcie_gart_set_page,
 287         .cp_commit = &r100_cp_commit,
 288         .ring_start = &r300_ring_start,
 289         .ring_test = &r100_ring_test,
 290         .ring_ib_execute = &r100_ring_ib_execute,
 291         .irq_set = &r100_irq_set,
 292         .irq_process = &r100_irq_process,
 293         .get_vblank_counter = &r100_get_vblank_counter,
 294         .fence_ring_emit = &r300_fence_ring_emit,
 295         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 296         .cs_parse = &r300_cs_parse,
 297         .copy_blit = &r100_copy_blit,
 298         .copy_dma = &r200_copy_dma,
 299         .copy = &r100_copy_blit,
 300         .get_engine_clock = &radeon_legacy_get_engine_clock,
 301         .set_engine_clock = &radeon_legacy_set_engine_clock,
 302         .get_memory_clock = &radeon_legacy_get_memory_clock,
 303         .set_memory_clock = NULL,
 304         .set_pcie_lanes = &rv370_set_pcie_lanes,
 305         .set_clock_gating = &radeon_legacy_set_clock_gating,
 306         .set_surface_reg = r100_set_surface_reg,
 307         .clear_surface_reg = r100_clear_surface_reg,
 308         .bandwidth_update = &r100_bandwidth_update,
 309         .hpd_init = &r100_hpd_init,
 310         .hpd_fini = &r100_hpd_fini,
 311         .hpd_sense = &r100_hpd_sense,
 312         .hpd_set_polarity = &r100_hpd_set_polarity,
 313         .ioctl_wait_idle = NULL,
 314         .gui_idle = &r100_gui_idle,
 315         .pm_misc = &r100_pm_misc,
 316         .pm_prepare = &r100_pm_prepare,
 317         .pm_finish = &r100_pm_finish,
 318         .pm_init_profile = &r100_pm_init_profile,
 319         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 320         .pre_page_flip = &r100_pre_page_flip,
 321         .page_flip = &r100_page_flip,
 322         .post_page_flip = &r100_post_page_flip,
 323 };
 324
 325 static struct radeon_asic r420_asic = {
 326         .init = &r420_init,
 327         .fini = &r420_fini,
 328         .suspend = &r420_suspend,
 329         .resume = &r420_resume,
 330         .vga_set_state = &r100_vga_set_state,
 331         .gpu_is_lockup = &r300_gpu_is_lockup,
 332         .asic_reset = &r300_asic_reset,
 333         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 334         .gart_set_page = &rv370_pcie_gart_set_page,
 335         .cp_commit = &r100_cp_commit,
 336         .ring_start = &r300_ring_start,
 337         .ring_test = &r100_ring_test,
 338         .ring_ib_execute = &r100_ring_ib_execute,
 339         .irq_set = &r100_irq_set,
 340         .irq_process = &r100_irq_process,
 341         .get_vblank_counter = &r100_get_vblank_counter,
 342         .fence_ring_emit = &r300_fence_ring_emit,
 343         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 344         .cs_parse = &r300_cs_parse,
 345         .copy_blit = &r100_copy_blit,
 346         .copy_dma = &r200_copy_dma,
 347         .copy = &r100_copy_blit,
 348         .get_engine_clock = &radeon_atom_get_engine_clock,
 349         .set_engine_clock = &radeon_atom_set_engine_clock,
 350         .get_memory_clock = &radeon_atom_get_memory_clock,
 351         .set_memory_clock = &radeon_atom_set_memory_clock,
 352         .get_pcie_lanes = &rv370_get_pcie_lanes,
 353         .set_pcie_lanes = &rv370_set_pcie_lanes,
 354         .set_clock_gating = &radeon_atom_set_clock_gating,
 355         .set_surface_reg = r100_set_surface_reg,
 356         .clear_surface_reg = r100_clear_surface_reg,
 357         .bandwidth_update = &r100_bandwidth_update,
 358         .hpd_init = &r100_hpd_init,
 359         .hpd_fini = &r100_hpd_fini,
 360         .hpd_sense = &r100_hpd_sense,
 361         .hpd_set_polarity = &r100_hpd_set_polarity,
 362         .ioctl_wait_idle = NULL,
 363         .gui_idle = &r100_gui_idle,
 364         .pm_misc = &r100_pm_misc,
 365         .pm_prepare = &r100_pm_prepare,
 366         .pm_finish = &r100_pm_finish,
 367         .pm_init_profile = &r420_pm_init_profile,
 368         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 369         .pre_page_flip = &r100_pre_page_flip,
 370         .page_flip = &r100_page_flip,
 371         .post_page_flip = &r100_post_page_flip,
 372 };
 373
 374 static struct radeon_asic rs400_asic = {
 375         .init = &rs400_init,
 376         .fini = &rs400_fini,
 377         .suspend = &rs400_suspend,
 378         .resume = &rs400_resume,
 379         .vga_set_state = &r100_vga_set_state,
 380         .gpu_is_lockup = &r300_gpu_is_lockup,
 381         .asic_reset = &r300_asic_reset,
 382         .gart_tlb_flush = &rs400_gart_tlb_flush,
 383         .gart_set_page = &rs400_gart_set_page,
 384         .cp_commit = &r100_cp_commit,
 385         .ring_start = &r300_ring_start,
 386         .ring_test = &r100_ring_test,
 387         .ring_ib_execute = &r100_ring_ib_execute,
 388         .irq_set = &r100_irq_set,
 389         .irq_process = &r100_irq_process,
 390         .get_vblank_counter = &r100_get_vblank_counter,
 391         .fence_ring_emit = &r300_fence_ring_emit,
 392         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 393         .cs_parse = &r300_cs_parse,
 394         .copy_blit = &r100_copy_blit,
 395         .copy_dma = &r200_copy_dma,
 396         .copy = &r100_copy_blit,
 397         .get_engine_clock = &radeon_legacy_get_engine_clock,
 398         .set_engine_clock = &radeon_legacy_set_engine_clock,
 399         .get_memory_clock = &radeon_legacy_get_memory_clock,
 400         .set_memory_clock = NULL,
 401         .get_pcie_lanes = NULL,
 402         .set_pcie_lanes = NULL,
 403         .set_clock_gating = &radeon_legacy_set_clock_gating,
 404         .set_surface_reg = r100_set_surface_reg,
 405         .clear_surface_reg = r100_clear_surface_reg,
 406         .bandwidth_update = &r100_bandwidth_update,
 407         .hpd_init = &r100_hpd_init,
 408         .hpd_fini = &r100_hpd_fini,
 409         .hpd_sense = &r100_hpd_sense,
 410         .hpd_set_polarity = &r100_hpd_set_polarity,
 411         .ioctl_wait_idle = NULL,
 412         .gui_idle = &r100_gui_idle,
 413         .pm_misc = &r100_pm_misc,
 414         .pm_prepare = &r100_pm_prepare,
 415         .pm_finish = &r100_pm_finish,
 416         .pm_init_profile = &r100_pm_init_profile,
 417         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 418         .pre_page_flip = &r100_pre_page_flip,
 419         .page_flip = &r100_page_flip,
 420         .post_page_flip = &r100_post_page_flip,
 421 };
 422
 423 static struct radeon_asic rs600_asic = {
 424         .init = &rs600_init,
 425         .fini = &rs600_fini,
 426         .suspend = &rs600_suspend,
 427         .resume = &rs600_resume,
 428         .vga_set_state = &r100_vga_set_state,
 429         .gpu_is_lockup = &r300_gpu_is_lockup,
 430         .asic_reset = &rs600_asic_reset,
 431         .gart_tlb_flush = &rs600_gart_tlb_flush,
 432         .gart_set_page = &rs600_gart_set_page,
 433         .cp_commit = &r100_cp_commit,
 434         .ring_start = &r300_ring_start,
 435         .ring_test = &r100_ring_test,
 436         .ring_ib_execute = &r100_ring_ib_execute,
 437         .irq_set = &rs600_irq_set,
 438         .irq_process = &rs600_irq_process,
 439         .get_vblank_counter = &rs600_get_vblank_counter,
 440         .fence_ring_emit = &r300_fence_ring_emit,
 441         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 442         .cs_parse = &r300_cs_parse,
 443         .copy_blit = &r100_copy_blit,
 444         .copy_dma = &r200_copy_dma,
 445         .copy = &r100_copy_blit,
 446         .get_engine_clock = &radeon_atom_get_engine_clock,
 447         .set_engine_clock = &radeon_atom_set_engine_clock,
 448         .get_memory_clock = &radeon_atom_get_memory_clock,
 449         .set_memory_clock = &radeon_atom_set_memory_clock,
 450         .get_pcie_lanes = NULL,
 451         .set_pcie_lanes = NULL,
 452         .set_clock_gating = &radeon_atom_set_clock_gating,
 453         .set_surface_reg = r100_set_surface_reg,
 454         .clear_surface_reg = r100_clear_surface_reg,
 455         .bandwidth_update = &rs600_bandwidth_update,
 456         .hpd_init = &rs600_hpd_init,
 457         .hpd_fini = &rs600_hpd_fini,
 458         .hpd_sense = &rs600_hpd_sense,
 459         .hpd_set_polarity = &rs600_hpd_set_polarity,
 460         .ioctl_wait_idle = NULL,
 461         .gui_idle = &r100_gui_idle,
 462         .pm_misc = &rs600_pm_misc,
 463         .pm_prepare = &rs600_pm_prepare,
 464         .pm_finish = &rs600_pm_finish,
 465         .pm_init_profile = &r420_pm_init_profile,
 466         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 467         .pre_page_flip = &rs600_pre_page_flip,
 468         .page_flip = &rs600_page_flip,
 469         .post_page_flip = &rs600_post_page_flip,
 470 };
 471
 472 static struct radeon_asic rs690_asic = {
 473         .init = &rs690_init,
 474         .fini = &rs690_fini,
 475         .suspend = &rs690_suspend,
 476         .resume = &rs690_resume,
 477         .vga_set_state = &r100_vga_set_state,
 478         .gpu_is_lockup = &r300_gpu_is_lockup,
 479         .asic_reset = &rs600_asic_reset,
 480         .gart_tlb_flush = &rs400_gart_tlb_flush,
 481         .gart_set_page = &rs400_gart_set_page,
 482         .cp_commit = &r100_cp_commit,
 483         .ring_start = &r300_ring_start,
 484         .ring_test = &r100_ring_test,
 485         .ring_ib_execute = &r100_ring_ib_execute,
 486         .irq_set = &rs600_irq_set,
 487         .irq_process = &rs600_irq_process,
 488         .get_vblank_counter = &rs600_get_vblank_counter,
 489         .fence_ring_emit = &r300_fence_ring_emit,
 490         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 491         .cs_parse = &r300_cs_parse,
 492         .copy_blit = &r100_copy_blit,
 493         .copy_dma = &r200_copy_dma,
 494         .copy = &r200_copy_dma,
 495         .get_engine_clock = &radeon_atom_get_engine_clock,
 496         .set_engine_clock = &radeon_atom_set_engine_clock,
 497         .get_memory_clock = &radeon_atom_get_memory_clock,
 498         .set_memory_clock = &radeon_atom_set_memory_clock,
 499         .get_pcie_lanes = NULL,
 500         .set_pcie_lanes = NULL,
 501         .set_clock_gating = &radeon_atom_set_clock_gating,
 502         .set_surface_reg = r100_set_surface_reg,
 503         .clear_surface_reg = r100_clear_surface_reg,
 504         .bandwidth_update = &rs690_bandwidth_update,
 505         .hpd_init = &rs600_hpd_init,
 506         .hpd_fini = &rs600_hpd_fini,
 507         .hpd_sense = &rs600_hpd_sense,
 508         .hpd_set_polarity = &rs600_hpd_set_polarity,
 509         .ioctl_wait_idle = NULL,
 510         .gui_idle = &r100_gui_idle,
 511         .pm_misc = &rs600_pm_misc,
 512         .pm_prepare = &rs600_pm_prepare,
 513         .pm_finish = &rs600_pm_finish,
 514         .pm_init_profile = &r420_pm_init_profile,
 515         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 516         .pre_page_flip = &rs600_pre_page_flip,
 517         .page_flip = &rs600_page_flip,
 518         .post_page_flip = &rs600_post_page_flip,
 519 };
 520
 521 static struct radeon_asic rv515_asic = {
 522         .init = &rv515_init,
 523         .fini = &rv515_fini,
 524         .suspend = &rv515_suspend,
 525         .resume = &rv515_resume,
 526         .vga_set_state = &r100_vga_set_state,
 527         .gpu_is_lockup = &r300_gpu_is_lockup,
 528         .asic_reset = &rs600_asic_reset,
 529         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 530         .gart_set_page = &rv370_pcie_gart_set_page,
 531         .cp_commit = &r100_cp_commit,
 532         .ring_start = &rv515_ring_start,
 533         .ring_test = &r100_ring_test,
 534         .ring_ib_execute = &r100_ring_ib_execute,
 535         .irq_set = &rs600_irq_set,
 536         .irq_process = &rs600_irq_process,
 537         .get_vblank_counter = &rs600_get_vblank_counter,
 538         .fence_ring_emit = &r300_fence_ring_emit,
 539         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 540         .cs_parse = &r300_cs_parse,
 541         .copy_blit = &r100_copy_blit,
 542         .copy_dma = &r200_copy_dma,
 543         .copy = &r100_copy_blit,
 544         .get_engine_clock = &radeon_atom_get_engine_clock,
 545         .set_engine_clock = &radeon_atom_set_engine_clock,
 546         .get_memory_clock = &radeon_atom_get_memory_clock,
 547         .set_memory_clock = &radeon_atom_set_memory_clock,
 548         .get_pcie_lanes = &rv370_get_pcie_lanes,
 549         .set_pcie_lanes = &rv370_set_pcie_lanes,
 550         .set_clock_gating = &radeon_atom_set_clock_gating,
 551         .set_surface_reg = r100_set_surface_reg,
 552         .clear_surface_reg = r100_clear_surface_reg,
 553         .bandwidth_update = &rv515_bandwidth_update,
 554         .hpd_init = &rs600_hpd_init,
 555         .hpd_fini = &rs600_hpd_fini,
 556         .hpd_sense = &rs600_hpd_sense,
 557         .hpd_set_polarity = &rs600_hpd_set_polarity,
 558         .ioctl_wait_idle = NULL,
 559         .gui_idle = &r100_gui_idle,
 560         .pm_misc = &rs600_pm_misc,
 561         .pm_prepare = &rs600_pm_prepare,
 562         .pm_finish = &rs600_pm_finish,
 563         .pm_init_profile = &r420_pm_init_profile,
 564         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 565         .pre_page_flip = &rs600_pre_page_flip,
 566         .page_flip = &rs600_page_flip,
 567         .post_page_flip = &rs600_post_page_flip,
 568 };
 569
 570 static struct radeon_asic r520_asic = {
 571         .init = &r520_init,
 572         .fini = &rv515_fini,
 573         .suspend = &rv515_suspend,
 574         .resume = &r520_resume,
 575         .vga_set_state = &r100_vga_set_state,
 576         .gpu_is_lockup = &r300_gpu_is_lockup,
 577         .asic_reset = &rs600_asic_reset,
 578         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 579         .gart_set_page = &rv370_pcie_gart_set_page,
 580         .cp_commit = &r100_cp_commit,
 581         .ring_start = &rv515_ring_start,
 582         .ring_test = &r100_ring_test,
 583         .ring_ib_execute = &r100_ring_ib_execute,
 584         .irq_set = &rs600_irq_set,
 585         .irq_process = &rs600_irq_process,
 586         .get_vblank_counter = &rs600_get_vblank_counter,
 587         .fence_ring_emit = &r300_fence_ring_emit,
 588         .semaphore_ring_emit = &r100_semaphore_ring_emit,
 589         .cs_parse = &r300_cs_parse,
 590         .copy_blit = &r100_copy_blit,
 591         .copy_dma = &r200_copy_dma,
 592         .copy = &r100_copy_blit,
 593         .get_engine_clock = &radeon_atom_get_engine_clock,
 594         .set_engine_clock = &radeon_atom_set_engine_clock,
 595         .get_memory_clock = &radeon_atom_get_memory_clock,
 596         .set_memory_clock = &radeon_atom_set_memory_clock,
 597         .get_pcie_lanes = &rv370_get_pcie_lanes,
 598         .set_pcie_lanes = &rv370_set_pcie_lanes,
 599         .set_clock_gating = &radeon_atom_set_clock_gating,
 600         .set_surface_reg = r100_set_surface_reg,
 601         .clear_surface_reg = r100_clear_surface_reg,
 602         .bandwidth_update = &rv515_bandwidth_update,
 603         .hpd_init = &rs600_hpd_init,
 604         .hpd_fini = &rs600_hpd_fini,
 605         .hpd_sense = &rs600_hpd_sense,
 606         .hpd_set_polarity = &rs600_hpd_set_polarity,
 607         .ioctl_wait_idle = NULL,
 608         .gui_idle = &r100_gui_idle,
 609         .pm_misc = &rs600_pm_misc,
 610         .pm_prepare = &rs600_pm_prepare,
 611         .pm_finish = &rs600_pm_finish,
 612         .pm_init_profile = &r420_pm_init_profile,
 613         .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
 614         .pre_page_flip = &rs600_pre_page_flip,
 615         .page_flip = &rs600_page_flip,
 616         .post_page_flip = &rs600_post_page_flip,
 617 };
 618
 619 static struct radeon_asic r600_asic = {
 620         .init = &r600_init,
 621         .fini = &r600_fini,
 622         .suspend = &r600_suspend,
 623         .resume = &r600_resume,
 624         .cp_commit = &r600_cp_commit,
 625         .vga_set_state = &r600_vga_set_state,
 626         .gpu_is_lockup = &r600_gpu_is_lockup,
 627         .asic_reset = &r600_asic_reset,
 628         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 629         .gart_set_page = &rs600_gart_set_page,
 630         .ring_test = &r600_ring_test,
 631         .ring_ib_execute = &r600_ring_ib_execute,
 632         .irq_set = &r600_irq_set,
 633         .irq_process = &r600_irq_process,
 634         .get_vblank_counter = &rs600_get_vblank_counter,
 635         .fence_ring_emit = &r600_fence_ring_emit,
 636         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 637         .cs_parse = &r600_cs_parse,
 638         .copy_blit = &r600_copy_blit,
 639         .copy_dma = NULL,
 640         .copy = &r600_copy_blit,
 641         .get_engine_clock = &radeon_atom_get_engine_clock,
 642         .set_engine_clock = &radeon_atom_set_engine_clock,
 643         .get_memory_clock = &radeon_atom_get_memory_clock,
 644         .set_memory_clock = &radeon_atom_set_memory_clock,
 645         .get_pcie_lanes = &r600_get_pcie_lanes,
 646         .set_pcie_lanes = &r600_set_pcie_lanes,
 647         .set_clock_gating = NULL,
 648         .set_surface_reg = r600_set_surface_reg,
 649         .clear_surface_reg = r600_clear_surface_reg,
 650         .bandwidth_update = &rv515_bandwidth_update,
 651         .hpd_init = &r600_hpd_init,
 652         .hpd_fini = &r600_hpd_fini,
 653         .hpd_sense = &r600_hpd_sense,
 654         .hpd_set_polarity = &r600_hpd_set_polarity,
 655         .ioctl_wait_idle = r600_ioctl_wait_idle,
 656         .gui_idle = &r600_gui_idle,
 657         .pm_misc = &r600_pm_misc,
 658         .pm_prepare = &rs600_pm_prepare,
 659         .pm_finish = &rs600_pm_finish,
 660         .pm_init_profile = &r600_pm_init_profile,
 661         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 662         .pre_page_flip = &rs600_pre_page_flip,
 663         .page_flip = &rs600_page_flip,
 664         .post_page_flip = &rs600_post_page_flip,
 665 };
 666
 667 static struct radeon_asic rs780_asic = {
 668         .init = &r600_init,
 669         .fini = &r600_fini,
 670         .suspend = &r600_suspend,
 671         .resume = &r600_resume,
 672         .cp_commit = &r600_cp_commit,
 673         .gpu_is_lockup = &r600_gpu_is_lockup,
 674         .vga_set_state = &r600_vga_set_state,
 675         .asic_reset = &r600_asic_reset,
 676         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 677         .gart_set_page = &rs600_gart_set_page,
 678         .ring_test = &r600_ring_test,
 679         .ring_ib_execute = &r600_ring_ib_execute,
 680         .irq_set = &r600_irq_set,
 681         .irq_process = &r600_irq_process,
 682         .get_vblank_counter = &rs600_get_vblank_counter,
 683         .fence_ring_emit = &r600_fence_ring_emit,
 684         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 685         .cs_parse = &r600_cs_parse,
 686         .copy_blit = &r600_copy_blit,
 687         .copy_dma = NULL,
 688         .copy = &r600_copy_blit,
 689         .get_engine_clock = &radeon_atom_get_engine_clock,
 690         .set_engine_clock = &radeon_atom_set_engine_clock,
 691         .get_memory_clock = NULL,
 692         .set_memory_clock = NULL,
 693         .get_pcie_lanes = NULL,
 694         .set_pcie_lanes = NULL,
 695         .set_clock_gating = NULL,
 696         .set_surface_reg = r600_set_surface_reg,
 697         .clear_surface_reg = r600_clear_surface_reg,
 698         .bandwidth_update = &rs690_bandwidth_update,
 699         .hpd_init = &r600_hpd_init,
 700         .hpd_fini = &r600_hpd_fini,
 701         .hpd_sense = &r600_hpd_sense,
 702         .hpd_set_polarity = &r600_hpd_set_polarity,
 703         .ioctl_wait_idle = r600_ioctl_wait_idle,
 704         .gui_idle = &r600_gui_idle,
 705         .pm_misc = &r600_pm_misc,
 706         .pm_prepare = &rs600_pm_prepare,
 707         .pm_finish = &rs600_pm_finish,
 708         .pm_init_profile = &rs780_pm_init_profile,
 709         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 710         .pre_page_flip = &rs600_pre_page_flip,
 711         .page_flip = &rs600_page_flip,
 712         .post_page_flip = &rs600_post_page_flip,
 713 };
 714
 715 static struct radeon_asic rv770_asic = {
 716         .init = &rv770_init,
 717         .fini = &rv770_fini,
 718         .suspend = &rv770_suspend,
 719         .resume = &rv770_resume,
 720         .cp_commit = &r600_cp_commit,
 721         .asic_reset = &r600_asic_reset,
 722         .gpu_is_lockup = &r600_gpu_is_lockup,
 723         .vga_set_state = &r600_vga_set_state,
 724         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 725         .gart_set_page = &rs600_gart_set_page,
 726         .ring_test = &r600_ring_test,
 727         .ring_ib_execute = &r600_ring_ib_execute,
 728         .irq_set = &r600_irq_set,
 729         .irq_process = &r600_irq_process,
 730         .get_vblank_counter = &rs600_get_vblank_counter,
 731         .fence_ring_emit = &r600_fence_ring_emit,
 732         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 733         .cs_parse = &r600_cs_parse,
 734         .copy_blit = &r600_copy_blit,
 735         .copy_dma = NULL,
 736         .copy = &r600_copy_blit,
 737         .get_engine_clock = &radeon_atom_get_engine_clock,
 738         .set_engine_clock = &radeon_atom_set_engine_clock,
 739         .get_memory_clock = &radeon_atom_get_memory_clock,
 740         .set_memory_clock = &radeon_atom_set_memory_clock,
 741         .get_pcie_lanes = &r600_get_pcie_lanes,
 742         .set_pcie_lanes = &r600_set_pcie_lanes,
 743         .set_clock_gating = &radeon_atom_set_clock_gating,
 744         .set_surface_reg = r600_set_surface_reg,
 745         .clear_surface_reg = r600_clear_surface_reg,
 746         .bandwidth_update = &rv515_bandwidth_update,
 747         .hpd_init = &r600_hpd_init,
 748         .hpd_fini = &r600_hpd_fini,
 749         .hpd_sense = &r600_hpd_sense,
 750         .hpd_set_polarity = &r600_hpd_set_polarity,
 751         .ioctl_wait_idle = r600_ioctl_wait_idle,
 752         .gui_idle = &r600_gui_idle,
 753         .pm_misc = &rv770_pm_misc,
 754         .pm_prepare = &rs600_pm_prepare,
 755         .pm_finish = &rs600_pm_finish,
 756         .pm_init_profile = &r600_pm_init_profile,
 757         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 758         .pre_page_flip = &rs600_pre_page_flip,
 759         .page_flip = &rv770_page_flip,
 760         .post_page_flip = &rs600_post_page_flip,
 761 };
 762
 763 static struct radeon_asic evergreen_asic = {
 764         .init = &evergreen_init,
 765         .fini = &evergreen_fini,
 766         .suspend = &evergreen_suspend,
 767         .resume = &evergreen_resume,
 768         .cp_commit = &r600_cp_commit,
 769         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 770         .asic_reset = &evergreen_asic_reset,
 771         .vga_set_state = &r600_vga_set_state,
 772         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 773         .gart_set_page = &rs600_gart_set_page,
 774         .ring_test = &r600_ring_test,
 775         .ring_ib_execute = &evergreen_ring_ib_execute,
 776         .irq_set = &evergreen_irq_set,
 777         .irq_process = &evergreen_irq_process,
 778         .get_vblank_counter = &evergreen_get_vblank_counter,
 779         .fence_ring_emit = &r600_fence_ring_emit,
 780         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 781         .cs_parse = &evergreen_cs_parse,
 782         .copy_blit = &r600_copy_blit,
 783         .copy_dma = NULL,
 784         .copy = &r600_copy_blit,
 785         .get_engine_clock = &radeon_atom_get_engine_clock,
 786         .set_engine_clock = &radeon_atom_set_engine_clock,
 787         .get_memory_clock = &radeon_atom_get_memory_clock,
 788         .set_memory_clock = &radeon_atom_set_memory_clock,
 789         .get_pcie_lanes = &r600_get_pcie_lanes,
 790         .set_pcie_lanes = &r600_set_pcie_lanes,
 791         .set_clock_gating = NULL,
 792         .set_surface_reg = r600_set_surface_reg,
 793         .clear_surface_reg = r600_clear_surface_reg,
 794         .bandwidth_update = &evergreen_bandwidth_update,
 795         .hpd_init = &evergreen_hpd_init,
 796         .hpd_fini = &evergreen_hpd_fini,
 797         .hpd_sense = &evergreen_hpd_sense,
 798         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 799         .ioctl_wait_idle = r600_ioctl_wait_idle,
 800         .gui_idle = &r600_gui_idle,
 801         .pm_misc = &evergreen_pm_misc,
 802         .pm_prepare = &evergreen_pm_prepare,
 803         .pm_finish = &evergreen_pm_finish,
 804         .pm_init_profile = &r600_pm_init_profile,
 805         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 806         .pre_page_flip = &evergreen_pre_page_flip,
 807         .page_flip = &evergreen_page_flip,
 808         .post_page_flip = &evergreen_post_page_flip,
 809 };
 810
 811 static struct radeon_asic sumo_asic = {
 812         .init = &evergreen_init,
 813         .fini = &evergreen_fini,
 814         .suspend = &evergreen_suspend,
 815         .resume = &evergreen_resume,
 816         .cp_commit = &r600_cp_commit,
 817         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 818         .asic_reset = &evergreen_asic_reset,
 819         .vga_set_state = &r600_vga_set_state,
 820         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 821         .gart_set_page = &rs600_gart_set_page,
 822         .ring_test = &r600_ring_test,
 823         .ring_ib_execute = &evergreen_ring_ib_execute,
 824         .irq_set = &evergreen_irq_set,
 825         .irq_process = &evergreen_irq_process,
 826         .get_vblank_counter = &evergreen_get_vblank_counter,
 827         .fence_ring_emit = &r600_fence_ring_emit,
 828         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 829         .cs_parse = &evergreen_cs_parse,
 830         .copy_blit = &r600_copy_blit,
 831         .copy_dma = NULL,
 832         .copy = &r600_copy_blit,
 833         .get_engine_clock = &radeon_atom_get_engine_clock,
 834         .set_engine_clock = &radeon_atom_set_engine_clock,
 835         .get_memory_clock = NULL,
 836         .set_memory_clock = NULL,
 837         .get_pcie_lanes = NULL,
 838         .set_pcie_lanes = NULL,
 839         .set_clock_gating = NULL,
 840         .set_surface_reg = r600_set_surface_reg,
 841         .clear_surface_reg = r600_clear_surface_reg,
 842         .bandwidth_update = &evergreen_bandwidth_update,
 843         .hpd_init = &evergreen_hpd_init,
 844         .hpd_fini = &evergreen_hpd_fini,
 845         .hpd_sense = &evergreen_hpd_sense,
 846         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 847         .ioctl_wait_idle = r600_ioctl_wait_idle,
 848         .gui_idle = &r600_gui_idle,
 849         .pm_misc = &evergreen_pm_misc,
 850         .pm_prepare = &evergreen_pm_prepare,
 851         .pm_finish = &evergreen_pm_finish,
 852         .pm_init_profile = &sumo_pm_init_profile,
 853         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 854         .pre_page_flip = &evergreen_pre_page_flip,
 855         .page_flip = &evergreen_page_flip,
 856         .post_page_flip = &evergreen_post_page_flip,
 857 };
 858
 859 static struct radeon_asic btc_asic = {
 860         .init = &evergreen_init,
 861         .fini = &evergreen_fini,
 862         .suspend = &evergreen_suspend,
 863         .resume = &evergreen_resume,
 864         .cp_commit = &r600_cp_commit,
 865         .gpu_is_lockup = &evergreen_gpu_is_lockup,
 866         .asic_reset = &evergreen_asic_reset,
 867         .vga_set_state = &r600_vga_set_state,
 868         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
 869         .gart_set_page = &rs600_gart_set_page,
 870         .ring_test = &r600_ring_test,
 871         .ring_ib_execute = &evergreen_ring_ib_execute,
 872         .irq_set = &evergreen_irq_set,
 873         .irq_process = &evergreen_irq_process,
 874         .get_vblank_counter = &evergreen_get_vblank_counter,
 875         .fence_ring_emit = &r600_fence_ring_emit,
 876         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 877         .cs_parse = &evergreen_cs_parse,
 878         .copy_blit = &r600_copy_blit,
 879         .copy_dma = NULL,
 880         .copy = &r600_copy_blit,
 881         .get_engine_clock = &radeon_atom_get_engine_clock,
 882         .set_engine_clock = &radeon_atom_set_engine_clock,
 883         .get_memory_clock = &radeon_atom_get_memory_clock,
 884         .set_memory_clock = &radeon_atom_set_memory_clock,
 885         .get_pcie_lanes = NULL,
 886         .set_pcie_lanes = NULL,
 887         .set_clock_gating = NULL,
 888         .set_surface_reg = r600_set_surface_reg,
 889         .clear_surface_reg = r600_clear_surface_reg,
 890         .bandwidth_update = &evergreen_bandwidth_update,
 891         .hpd_init = &evergreen_hpd_init,
 892         .hpd_fini = &evergreen_hpd_fini,
 893         .hpd_sense = &evergreen_hpd_sense,
 894         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 895         .ioctl_wait_idle = r600_ioctl_wait_idle,
 896         .gui_idle = &r600_gui_idle,
 897         .pm_misc = &evergreen_pm_misc,
 898         .pm_prepare = &evergreen_pm_prepare,
 899         .pm_finish = &evergreen_pm_finish,
 900         .pm_init_profile = &r600_pm_init_profile,
 901         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 902         .pre_page_flip = &evergreen_pre_page_flip,
 903         .page_flip = &evergreen_page_flip,
 904         .post_page_flip = &evergreen_post_page_flip,
 905 };
 906
 907 static struct radeon_asic cayman_asic = {
 908         .init = &cayman_init,
 909         .fini = &cayman_fini,
 910         .suspend = &cayman_suspend,
 911         .resume = &cayman_resume,
 912         .cp_commit = &r600_cp_commit,
 913         .gpu_is_lockup = &cayman_gpu_is_lockup,
 914         .asic_reset = &cayman_asic_reset,
 915         .vga_set_state = &r600_vga_set_state,
 916         .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
 917         .gart_set_page = &rs600_gart_set_page,
 918         .ring_test = &r600_ring_test,
 919         .ring_ib_execute = &evergreen_ring_ib_execute,
 920         .irq_set = &evergreen_irq_set,
 921         .irq_process = &evergreen_irq_process,
 922         .get_vblank_counter = &evergreen_get_vblank_counter,
 923         .fence_ring_emit = &r600_fence_ring_emit,
 924         .semaphore_ring_emit = &r600_semaphore_ring_emit,
 925         .cs_parse = &evergreen_cs_parse,
 926         .copy_blit = &r600_copy_blit,
 927         .copy_dma = NULL,
 928         .copy = &r600_copy_blit,
 929         .get_engine_clock = &radeon_atom_get_engine_clock,
 930         .set_engine_clock = &radeon_atom_set_engine_clock,
 931         .get_memory_clock = &radeon_atom_get_memory_clock,
 932         .set_memory_clock = &radeon_atom_set_memory_clock,
 933         .get_pcie_lanes = NULL,
 934         .set_pcie_lanes = NULL,
 935         .set_clock_gating = NULL,
 936         .set_surface_reg = r600_set_surface_reg,
 937         .clear_surface_reg = r600_clear_surface_reg,
 938         .bandwidth_update = &evergreen_bandwidth_update,
 939         .hpd_init = &evergreen_hpd_init,
 940         .hpd_fini = &evergreen_hpd_fini,
 941         .hpd_sense = &evergreen_hpd_sense,
 942         .hpd_set_polarity = &evergreen_hpd_set_polarity,
 943         .ioctl_wait_idle = r600_ioctl_wait_idle,
 944         .gui_idle = &r600_gui_idle,
 945         .pm_misc = &evergreen_pm_misc,
 946         .pm_prepare = &evergreen_pm_prepare,
 947         .pm_finish = &evergreen_pm_finish,
 948         .pm_init_profile = &r600_pm_init_profile,
 949         .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 950         .pre_page_flip = &evergreen_pre_page_flip,
 951         .page_flip = &evergreen_page_flip,
 952         .post_page_flip = &evergreen_post_page_flip,
 953 };
 954
 955 int radeon_asic_init(struct radeon_device *rdev)
 956 {
 957         radeon_register_accessor_init(rdev);
 958
 959         /* set the number of crtcs */
 960         if (rdev->flags & RADEON_SINGLE_CRTC)
 961                 rdev->num_crtc = 1;
 962         else
 963                 rdev->num_crtc = 2;
 964
 965         switch (rdev->family) {
 966         case CHIP_R100:
 967         case CHIP_RV100:
 968         case CHIP_RS100:
 969         case CHIP_RV200:
 970         case CHIP_RS200:
 971                 rdev->asic = &r100_asic;
 972                 break;
 973         case CHIP_R200:
 974         case CHIP_RV250:
 975         case CHIP_RS300:
 976         case CHIP_RV280:
 977                 rdev->asic = &r200_asic;
 978                 break;
 979         case CHIP_R300:
 980         case CHIP_R350:
 981         case CHIP_RV350:
 982         case CHIP_RV380:
 983                 if (rdev->flags & RADEON_IS_PCIE)
 984                         rdev->asic = &r300_asic_pcie;
 985                 else
 986                         rdev->asic = &r300_asic;
 987                 break;
 988         case CHIP_R420:
 989         case CHIP_R423:
 990         case CHIP_RV410:
 991                 rdev->asic = &r420_asic;
 992                 /* handle macs */
 993                 if (rdev->bios == NULL) {
 994                         rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
 995                         rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
 996                         rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
 997                         rdev->asic->set_memory_clock = NULL;
 998                 }
 999                 break;
1000         case CHIP_RS400:
1001         case CHIP_RS480:
1002                 rdev->asic = &rs400_asic;
1003                 break;
1004         case CHIP_RS600:
1005                 rdev->asic = &rs600_asic;
1006                 break;
1007         case CHIP_RS690:
1008         case CHIP_RS740:
1009                 rdev->asic = &rs690_asic;
1010                 break;
1011         case CHIP_RV515:
1012                 rdev->asic = &rv515_asic;
1013                 break;
1014         case CHIP_R520:
1015         case CHIP_RV530:
1016         case CHIP_RV560:
1017         case CHIP_RV570:
1018         case CHIP_R580:
1019                 rdev->asic = &r520_asic;
1020                 break;
1021         case CHIP_R600:
1022         case CHIP_RV610:
1023         case CHIP_RV630:
1024         case CHIP_RV620:
1025         case CHIP_RV635:
1026         case CHIP_RV670:
1027                 rdev->asic = &r600_asic;
1028                 break;
1029         case CHIP_RS780:
1030         case CHIP_RS880:
1031                 rdev->asic = &rs780_asic;
1032                 break;
1033         case CHIP_RV770:
1034         case CHIP_RV730:
1035         case CHIP_RV710:
1036         case CHIP_RV740:
1037                 rdev->asic = &rv770_asic;
1038                 break;
1039         case CHIP_CEDAR:
1040         case CHIP_REDWOOD:
1041         case CHIP_JUNIPER:
1042         case CHIP_CYPRESS:
1043         case CHIP_HEMLOCK:
1044                 /* set num crtcs */
1045                 if (rdev->family == CHIP_CEDAR)
1046                         rdev->num_crtc = 4;
1047                 else
1048                         rdev->num_crtc = 6;
1049                 rdev->asic = &evergreen_asic;
1050                 break;
1051         case CHIP_PALM:
1052         case CHIP_SUMO:
1053         case CHIP_SUMO2:
1054                 rdev->asic = &sumo_asic;
1055                 break;
1056         case CHIP_BARTS:
1057         case CHIP_TURKS:
1058         case CHIP_CAICOS:
1059                 /* set num crtcs */
1060                 if (rdev->family == CHIP_CAICOS)
1061                         rdev->num_crtc = 4;
1062                 else
1063                         rdev->num_crtc = 6;
1064                 rdev->asic = &btc_asic;
1065                 break;
1066         case CHIP_CAYMAN:
1067                 rdev->asic = &cayman_asic;
1068                 /* set num crtcs */
1069                 rdev->num_crtc = 6;
1070                 break;
1071         default:
1072                 /* FIXME: not supported yet */
1073                 return -EINVAL;
1074         }
1075
1076         if (rdev->flags & RADEON_IS_IGP) {
1077                 rdev->asic->get_memory_clock = NULL;
1078                 rdev->asic->set_memory_clock = NULL;
1079         }
1080
1081         return 0;
1082 }
1083