drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  44 {
  45         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  46         BUG_ON(1);
  47         return 0;
  48 }
  49
  50 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  51 {
  52         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  53                   reg, v);
  54         BUG_ON(1);
  55 }
  56
  57 static void radeon_register_accessor_init(struct radeon_device *rdev)
  58 {
  59         rdev->mc_rreg = &radeon_invalid_rreg;
  60         rdev->mc_wreg = &radeon_invalid_wreg;
  61         rdev->pll_rreg = &radeon_invalid_rreg;
  62         rdev->pll_wreg = &radeon_invalid_wreg;
  63         rdev->pciep_rreg = &radeon_invalid_rreg;
  64         rdev->pciep_wreg = &radeon_invalid_wreg;
  65
  66         /* Don't change order as we are overridding accessor. */
  67         if (rdev->family < CHIP_RV515) {
  68                 rdev->pcie_reg_mask = 0xff;
  69         } else {
  70                 rdev->pcie_reg_mask = 0x7ff;
  71         }
  72         /* FIXME: not sure here */
  73         if (rdev->family <= CHIP_R580) {
  74                 rdev->pll_rreg = &r100_pll_rreg;
  75                 rdev->pll_wreg = &r100_pll_wreg;
  76         }
  77         if (rdev->family >= CHIP_R420) {
  78                 rdev->mc_rreg = &r420_mc_rreg;
  79                 rdev->mc_wreg = &r420_mc_wreg;
  80         }
  81         if (rdev->family >= CHIP_RV515) {
  82                 rdev->mc_rreg = &rv515_mc_rreg;
  83                 rdev->mc_wreg = &rv515_mc_wreg;
  84         }
  85         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  86                 rdev->mc_rreg = &rs400_mc_rreg;
  87                 rdev->mc_wreg = &rs400_mc_wreg;
  88         }
  89         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  90                 rdev->mc_rreg = &rs690_mc_rreg;
  91                 rdev->mc_wreg = &rs690_mc_wreg;
  92         }
  93         if (rdev->family == CHIP_RS600) {
  94                 rdev->mc_rreg = &rs600_mc_rreg;
  95                 rdev->mc_wreg = &rs600_mc_wreg;
  96         }
  97         if (rdev->family >= CHIP_R600) {
  98                 rdev->pciep_rreg = &r600_pciep_rreg;
  99                 rdev->pciep_wreg = &r600_pciep_wreg;
 100         }
 101 }
 102
 103
 104 /* helper to disable agp */
 105 void radeon_agp_disable(struct radeon_device *rdev)
 106 {
 107         rdev->flags &= ~RADEON_IS_AGP;
 108         if (rdev->family >= CHIP_R600) {
 109                 DRM_INFO("Forcing AGP to PCIE mode\n");
 110                 rdev->flags |= RADEON_IS_PCIE;
 111         } else if (rdev->family >= CHIP_RV515 ||
 112                         rdev->family == CHIP_RV380 ||
 113                         rdev->family == CHIP_RV410 ||
 114                         rdev->family == CHIP_R423) {
 115                 DRM_INFO("Forcing AGP to PCIE mode\n");
 116                 rdev->flags |= RADEON_IS_PCIE;
 117                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
 118                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 119         } else {
 120                 DRM_INFO("Forcing AGP to PCI mode\n");
 121                 rdev->flags |= RADEON_IS_PCI;
 122                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 123                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 124         }
 125         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 126 }
 127
 128 /*
 129  * ASIC
 130  */
 131 static struct radeon_asic r100_asic = {
 132         .init = &r100_init,
 133         .fini = &r100_fini,
 134         .suspend = &r100_suspend,
 135         .resume = &r100_resume,
 136         .vga_set_state = &r100_vga_set_state,
 137         .gpu_is_lockup = &r100_gpu_is_lockup,
 138         .asic_reset = &r100_asic_reset,
 139         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 140         .gart_set_page = &r100_pci_gart_set_page,
 141         .ring_start = &r100_ring_start,
 142         .ring_test = &r100_ring_test,
 143         .ring = {
 144                 [RADEON_RING_TYPE_GFX_INDEX] = {
 145                         .ib_execute = &r100_ring_ib_execute,
 146                         .emit_fence = &r100_fence_ring_emit,
 147                         .emit_semaphore = &r100_semaphore_ring_emit,
 148                         .cs_parse = &r100_cs_parse,
 149                 }
 150         },
 151         .irq = {
 152                 .set = &r100_irq_set,
 153                 .process = &r100_irq_process,
 154         },
 155         .get_vblank_counter = &r100_get_vblank_counter,
 156         .copy = {
 157                 .blit = &r100_copy_blit,
 158                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 159                 .dma = NULL,
 160                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 161                 .copy = &r100_copy_blit,
 162                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 163         },
 164         .get_engine_clock = &radeon_legacy_get_engine_clock,
 165         .set_engine_clock = &radeon_legacy_set_engine_clock,
 166         .get_memory_clock = &radeon_legacy_get_memory_clock,
 167         .set_memory_clock = NULL,
 168         .get_pcie_lanes = NULL,
 169         .set_pcie_lanes = NULL,
 170         .set_clock_gating = &radeon_legacy_set_clock_gating,
 171         .set_surface_reg = r100_set_surface_reg,
 172         .clear_surface_reg = r100_clear_surface_reg,
 173         .bandwidth_update = &r100_bandwidth_update,
 174         .hpd = {
 175                 .init = &r100_hpd_init,
 176                 .fini = &r100_hpd_fini,
 177                 .sense = &r100_hpd_sense,
 178                 .set_polarity = &r100_hpd_set_polarity,
 179         },
 180         .ioctl_wait_idle = NULL,
 181         .gui_idle = &r100_gui_idle,
 182         .pm = {
 183                 .misc = &r100_pm_misc,
 184                 .prepare = &r100_pm_prepare,
 185                 .finish = &r100_pm_finish,
 186                 .init_profile = &r100_pm_init_profile,
 187                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 188         },
 189         .pflip = {
 190                 .pre_page_flip = &r100_pre_page_flip,
 191                 .page_flip = &r100_page_flip,
 192                 .post_page_flip = &r100_post_page_flip,
 193         },
 194         .wait_for_vblank = &r100_wait_for_vblank,
 195         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 196 };
 197
 198 static struct radeon_asic r200_asic = {
 199         .init = &r100_init,
 200         .fini = &r100_fini,
 201         .suspend = &r100_suspend,
 202         .resume = &r100_resume,
 203         .vga_set_state = &r100_vga_set_state,
 204         .gpu_is_lockup = &r100_gpu_is_lockup,
 205         .asic_reset = &r100_asic_reset,
 206         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 207         .gart_set_page = &r100_pci_gart_set_page,
 208         .ring_start = &r100_ring_start,
 209         .ring_test = &r100_ring_test,
 210         .ring = {
 211                 [RADEON_RING_TYPE_GFX_INDEX] = {
 212                         .ib_execute = &r100_ring_ib_execute,
 213                         .emit_fence = &r100_fence_ring_emit,
 214                         .emit_semaphore = &r100_semaphore_ring_emit,
 215                         .cs_parse = &r100_cs_parse,
 216                 }
 217         },
 218         .irq = {
 219                 .set = &r100_irq_set,
 220                 .process = &r100_irq_process,
 221         },
 222         .get_vblank_counter = &r100_get_vblank_counter,
 223         .copy = {
 224                 .blit = &r100_copy_blit,
 225                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 226                 .dma = &r200_copy_dma,
 227                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 228                 .copy = &r100_copy_blit,
 229                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 230         },
 231         .get_engine_clock = &radeon_legacy_get_engine_clock,
 232         .set_engine_clock = &radeon_legacy_set_engine_clock,
 233         .get_memory_clock = &radeon_legacy_get_memory_clock,
 234         .set_memory_clock = NULL,
 235         .set_pcie_lanes = NULL,
 236         .set_clock_gating = &radeon_legacy_set_clock_gating,
 237         .set_surface_reg = r100_set_surface_reg,
 238         .clear_surface_reg = r100_clear_surface_reg,
 239         .bandwidth_update = &r100_bandwidth_update,
 240         .hpd = {
 241                 .init = &r100_hpd_init,
 242                 .fini = &r100_hpd_fini,
 243                 .sense = &r100_hpd_sense,
 244                 .set_polarity = &r100_hpd_set_polarity,
 245         },
 246         .ioctl_wait_idle = NULL,
 247         .gui_idle = &r100_gui_idle,
 248         .pm = {
 249                 .misc = &r100_pm_misc,
 250                 .prepare = &r100_pm_prepare,
 251                 .finish = &r100_pm_finish,
 252                 .init_profile = &r100_pm_init_profile,
 253                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 254         },
 255         .pflip = {
 256                 .pre_page_flip = &r100_pre_page_flip,
 257                 .page_flip = &r100_page_flip,
 258                 .post_page_flip = &r100_post_page_flip,
 259         },
 260         .wait_for_vblank = &r100_wait_for_vblank,
 261         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 262 };
 263
 264 static struct radeon_asic r300_asic = {
 265         .init = &r300_init,
 266         .fini = &r300_fini,
 267         .suspend = &r300_suspend,
 268         .resume = &r300_resume,
 269         .vga_set_state = &r100_vga_set_state,
 270         .gpu_is_lockup = &r300_gpu_is_lockup,
 271         .asic_reset = &r300_asic_reset,
 272         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 273         .gart_set_page = &r100_pci_gart_set_page,
 274         .ring_start = &r300_ring_start,
 275         .ring_test = &r100_ring_test,
 276         .ring = {
 277                 [RADEON_RING_TYPE_GFX_INDEX] = {
 278                         .ib_execute = &r100_ring_ib_execute,
 279                         .emit_fence = &r300_fence_ring_emit,
 280                         .emit_semaphore = &r100_semaphore_ring_emit,
 281                         .cs_parse = &r300_cs_parse,
 282                 }
 283         },
 284         .irq = {
 285                 .set = &r100_irq_set,
 286                 .process = &r100_irq_process,
 287         },
 288         .get_vblank_counter = &r100_get_vblank_counter,
 289         .copy = {
 290                 .blit = &r100_copy_blit,
 291                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 292                 .dma = &r200_copy_dma,
 293                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 294                 .copy = &r100_copy_blit,
 295                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 296         },
 297         .get_engine_clock = &radeon_legacy_get_engine_clock,
 298         .set_engine_clock = &radeon_legacy_set_engine_clock,
 299         .get_memory_clock = &radeon_legacy_get_memory_clock,
 300         .set_memory_clock = NULL,
 301         .get_pcie_lanes = &rv370_get_pcie_lanes,
 302         .set_pcie_lanes = &rv370_set_pcie_lanes,
 303         .set_clock_gating = &radeon_legacy_set_clock_gating,
 304         .set_surface_reg = r100_set_surface_reg,
 305         .clear_surface_reg = r100_clear_surface_reg,
 306         .bandwidth_update = &r100_bandwidth_update,
 307         .hpd = {
 308                 .init = &r100_hpd_init,
 309                 .fini = &r100_hpd_fini,
 310                 .sense = &r100_hpd_sense,
 311                 .set_polarity = &r100_hpd_set_polarity,
 312         },
 313         .ioctl_wait_idle = NULL,
 314         .gui_idle = &r100_gui_idle,
 315         .pm = {
 316                 .misc = &r100_pm_misc,
 317                 .prepare = &r100_pm_prepare,
 318                 .finish = &r100_pm_finish,
 319                 .init_profile = &r100_pm_init_profile,
 320                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 321         },
 322         .pflip = {
 323                 .pre_page_flip = &r100_pre_page_flip,
 324                 .page_flip = &r100_page_flip,
 325                 .post_page_flip = &r100_post_page_flip,
 326         },
 327         .wait_for_vblank = &r100_wait_for_vblank,
 328         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 329 };
 330
 331 static struct radeon_asic r300_asic_pcie = {
 332         .init = &r300_init,
 333         .fini = &r300_fini,
 334         .suspend = &r300_suspend,
 335         .resume = &r300_resume,
 336         .vga_set_state = &r100_vga_set_state,
 337         .gpu_is_lockup = &r300_gpu_is_lockup,
 338         .asic_reset = &r300_asic_reset,
 339         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 340         .gart_set_page = &rv370_pcie_gart_set_page,
 341         .ring_start = &r300_ring_start,
 342         .ring_test = &r100_ring_test,
 343         .ring = {
 344                 [RADEON_RING_TYPE_GFX_INDEX] = {
 345                         .ib_execute = &r100_ring_ib_execute,
 346                         .emit_fence = &r300_fence_ring_emit,
 347                         .emit_semaphore = &r100_semaphore_ring_emit,
 348                         .cs_parse = &r300_cs_parse,
 349                 }
 350         },
 351         .irq = {
 352                 .set = &r100_irq_set,
 353                 .process = &r100_irq_process,
 354         },
 355         .get_vblank_counter = &r100_get_vblank_counter,
 356         .copy = {
 357                 .blit = &r100_copy_blit,
 358                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 359                 .dma = &r200_copy_dma,
 360                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 361                 .copy = &r100_copy_blit,
 362                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 363         },
 364         .get_engine_clock = &radeon_legacy_get_engine_clock,
 365         .set_engine_clock = &radeon_legacy_set_engine_clock,
 366         .get_memory_clock = &radeon_legacy_get_memory_clock,
 367         .set_memory_clock = NULL,
 368         .set_pcie_lanes = &rv370_set_pcie_lanes,
 369         .set_clock_gating = &radeon_legacy_set_clock_gating,
 370         .set_surface_reg = r100_set_surface_reg,
 371         .clear_surface_reg = r100_clear_surface_reg,
 372         .bandwidth_update = &r100_bandwidth_update,
 373         .hpd = {
 374                 .init = &r100_hpd_init,
 375                 .fini = &r100_hpd_fini,
 376                 .sense = &r100_hpd_sense,
 377                 .set_polarity = &r100_hpd_set_polarity,
 378         },
 379         .ioctl_wait_idle = NULL,
 380         .gui_idle = &r100_gui_idle,
 381         .pm = {
 382                 .misc = &r100_pm_misc,
 383                 .prepare = &r100_pm_prepare,
 384                 .finish = &r100_pm_finish,
 385                 .init_profile = &r100_pm_init_profile,
 386                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 387         },
 388         .pflip = {
 389                 .pre_page_flip = &r100_pre_page_flip,
 390                 .page_flip = &r100_page_flip,
 391                 .post_page_flip = &r100_post_page_flip,
 392         },
 393         .wait_for_vblank = &r100_wait_for_vblank,
 394         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 395 };
 396
 397 static struct radeon_asic r420_asic = {
 398         .init = &r420_init,
 399         .fini = &r420_fini,
 400         .suspend = &r420_suspend,
 401         .resume = &r420_resume,
 402         .vga_set_state = &r100_vga_set_state,
 403         .gpu_is_lockup = &r300_gpu_is_lockup,
 404         .asic_reset = &r300_asic_reset,
 405         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 406         .gart_set_page = &rv370_pcie_gart_set_page,
 407         .ring_start = &r300_ring_start,
 408         .ring_test = &r100_ring_test,
 409         .ring = {
 410                 [RADEON_RING_TYPE_GFX_INDEX] = {
 411                         .ib_execute = &r100_ring_ib_execute,
 412                         .emit_fence = &r300_fence_ring_emit,
 413                         .emit_semaphore = &r100_semaphore_ring_emit,
 414                         .cs_parse = &r300_cs_parse,
 415                 }
 416         },
 417         .irq = {
 418                 .set = &r100_irq_set,
 419                 .process = &r100_irq_process,
 420         },
 421         .get_vblank_counter = &r100_get_vblank_counter,
 422         .copy = {
 423                 .blit = &r100_copy_blit,
 424                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 425                 .dma = &r200_copy_dma,
 426                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 427                 .copy = &r100_copy_blit,
 428                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 429         },
 430         .get_engine_clock = &radeon_atom_get_engine_clock,
 431         .set_engine_clock = &radeon_atom_set_engine_clock,
 432         .get_memory_clock = &radeon_atom_get_memory_clock,
 433         .set_memory_clock = &radeon_atom_set_memory_clock,
 434         .get_pcie_lanes = &rv370_get_pcie_lanes,
 435         .set_pcie_lanes = &rv370_set_pcie_lanes,
 436         .set_clock_gating = &radeon_atom_set_clock_gating,
 437         .set_surface_reg = r100_set_surface_reg,
 438         .clear_surface_reg = r100_clear_surface_reg,
 439         .bandwidth_update = &r100_bandwidth_update,
 440         .hpd = {
 441                 .init = &r100_hpd_init,
 442                 .fini = &r100_hpd_fini,
 443                 .sense = &r100_hpd_sense,
 444                 .set_polarity = &r100_hpd_set_polarity,
 445         },
 446         .ioctl_wait_idle = NULL,
 447         .gui_idle = &r100_gui_idle,
 448         .pm = {
 449                 .misc = &r100_pm_misc,
 450                 .prepare = &r100_pm_prepare,
 451                 .finish = &r100_pm_finish,
 452                 .init_profile = &r420_pm_init_profile,
 453                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 454         },
 455         .pflip = {
 456                 .pre_page_flip = &r100_pre_page_flip,
 457                 .page_flip = &r100_page_flip,
 458                 .post_page_flip = &r100_post_page_flip,
 459         },
 460         .wait_for_vblank = &r100_wait_for_vblank,
 461         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 462 };
 463
 464 static struct radeon_asic rs400_asic = {
 465         .init = &rs400_init,
 466         .fini = &rs400_fini,
 467         .suspend = &rs400_suspend,
 468         .resume = &rs400_resume,
 469         .vga_set_state = &r100_vga_set_state,
 470         .gpu_is_lockup = &r300_gpu_is_lockup,
 471         .asic_reset = &r300_asic_reset,
 472         .gart_tlb_flush = &rs400_gart_tlb_flush,
 473         .gart_set_page = &rs400_gart_set_page,
 474         .ring_start = &r300_ring_start,
 475         .ring_test = &r100_ring_test,
 476         .ring = {
 477                 [RADEON_RING_TYPE_GFX_INDEX] = {
 478                         .ib_execute = &r100_ring_ib_execute,
 479                         .emit_fence = &r300_fence_ring_emit,
 480                         .emit_semaphore = &r100_semaphore_ring_emit,
 481                         .cs_parse = &r300_cs_parse,
 482                 }
 483         },
 484         .irq = {
 485                 .set = &r100_irq_set,
 486                 .process = &r100_irq_process,
 487         },
 488         .get_vblank_counter = &r100_get_vblank_counter,
 489         .copy = {
 490                 .blit = &r100_copy_blit,
 491                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 492                 .dma = &r200_copy_dma,
 493                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 494                 .copy = &r100_copy_blit,
 495                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 496         },
 497         .get_engine_clock = &radeon_legacy_get_engine_clock,
 498         .set_engine_clock = &radeon_legacy_set_engine_clock,
 499         .get_memory_clock = &radeon_legacy_get_memory_clock,
 500         .set_memory_clock = NULL,
 501         .get_pcie_lanes = NULL,
 502         .set_pcie_lanes = NULL,
 503         .set_clock_gating = &radeon_legacy_set_clock_gating,
 504         .set_surface_reg = r100_set_surface_reg,
 505         .clear_surface_reg = r100_clear_surface_reg,
 506         .bandwidth_update = &r100_bandwidth_update,
 507         .hpd = {
 508                 .init = &r100_hpd_init,
 509                 .fini = &r100_hpd_fini,
 510                 .sense = &r100_hpd_sense,
 511                 .set_polarity = &r100_hpd_set_polarity,
 512         },
 513         .ioctl_wait_idle = NULL,
 514         .gui_idle = &r100_gui_idle,
 515         .pm = {
 516                 .misc = &r100_pm_misc,
 517                 .prepare = &r100_pm_prepare,
 518                 .finish = &r100_pm_finish,
 519                 .init_profile = &r100_pm_init_profile,
 520                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 521         },
 522         .pflip = {
 523                 .pre_page_flip = &r100_pre_page_flip,
 524                 .page_flip = &r100_page_flip,
 525                 .post_page_flip = &r100_post_page_flip,
 526         },
 527         .wait_for_vblank = &r100_wait_for_vblank,
 528         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 529 };
 530
 531 static struct radeon_asic rs600_asic = {
 532         .init = &rs600_init,
 533         .fini = &rs600_fini,
 534         .suspend = &rs600_suspend,
 535         .resume = &rs600_resume,
 536         .vga_set_state = &r100_vga_set_state,
 537         .gpu_is_lockup = &r300_gpu_is_lockup,
 538         .asic_reset = &rs600_asic_reset,
 539         .gart_tlb_flush = &rs600_gart_tlb_flush,
 540         .gart_set_page = &rs600_gart_set_page,
 541         .ring_start = &r300_ring_start,
 542         .ring_test = &r100_ring_test,
 543         .ring = {
 544                 [RADEON_RING_TYPE_GFX_INDEX] = {
 545                         .ib_execute = &r100_ring_ib_execute,
 546                         .emit_fence = &r300_fence_ring_emit,
 547                         .emit_semaphore = &r100_semaphore_ring_emit,
 548                         .cs_parse = &r300_cs_parse,
 549                 }
 550         },
 551         .irq = {
 552                 .set = &rs600_irq_set,
 553                 .process = &rs600_irq_process,
 554         },
 555         .get_vblank_counter = &rs600_get_vblank_counter,
 556         .copy = {
 557                 .blit = &r100_copy_blit,
 558                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 559                 .dma = &r200_copy_dma,
 560                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 561                 .copy = &r100_copy_blit,
 562                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 563         },
 564         .get_engine_clock = &radeon_atom_get_engine_clock,
 565         .set_engine_clock = &radeon_atom_set_engine_clock,
 566         .get_memory_clock = &radeon_atom_get_memory_clock,
 567         .set_memory_clock = &radeon_atom_set_memory_clock,
 568         .get_pcie_lanes = NULL,
 569         .set_pcie_lanes = NULL,
 570         .set_clock_gating = &radeon_atom_set_clock_gating,
 571         .set_surface_reg = r100_set_surface_reg,
 572         .clear_surface_reg = r100_clear_surface_reg,
 573         .bandwidth_update = &rs600_bandwidth_update,
 574         .hpd = {
 575                 .init = &rs600_hpd_init,
 576                 .fini = &rs600_hpd_fini,
 577                 .sense = &rs600_hpd_sense,
 578                 .set_polarity = &rs600_hpd_set_polarity,
 579         },
 580         .ioctl_wait_idle = NULL,
 581         .gui_idle = &r100_gui_idle,
 582         .pm = {
 583                 .misc = &rs600_pm_misc,
 584                 .prepare = &rs600_pm_prepare,
 585                 .finish = &rs600_pm_finish,
 586                 .init_profile = &r420_pm_init_profile,
 587                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 588         },
 589         .pflip = {
 590                 .pre_page_flip = &rs600_pre_page_flip,
 591                 .page_flip = &rs600_page_flip,
 592                 .post_page_flip = &rs600_post_page_flip,
 593         },
 594         .wait_for_vblank = &avivo_wait_for_vblank,
 595         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 596 };
 597
 598 static struct radeon_asic rs690_asic = {
 599         .init = &rs690_init,
 600         .fini = &rs690_fini,
 601         .suspend = &rs690_suspend,
 602         .resume = &rs690_resume,
 603         .vga_set_state = &r100_vga_set_state,
 604         .gpu_is_lockup = &r300_gpu_is_lockup,
 605         .asic_reset = &rs600_asic_reset,
 606         .gart_tlb_flush = &rs400_gart_tlb_flush,
 607         .gart_set_page = &rs400_gart_set_page,
 608         .ring_start = &r300_ring_start,
 609         .ring_test = &r100_ring_test,
 610         .ring = {
 611                 [RADEON_RING_TYPE_GFX_INDEX] = {
 612                         .ib_execute = &r100_ring_ib_execute,
 613                         .emit_fence = &r300_fence_ring_emit,
 614                         .emit_semaphore = &r100_semaphore_ring_emit,
 615                         .cs_parse = &r300_cs_parse,
 616                 }
 617         },
 618         .irq = {
 619                 .set = &rs600_irq_set,
 620                 .process = &rs600_irq_process,
 621         },
 622         .get_vblank_counter = &rs600_get_vblank_counter,
 623         .copy = {
 624                 .blit = &r100_copy_blit,
 625                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 626                 .dma = &r200_copy_dma,
 627                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 628                 .copy = &r200_copy_dma,
 629                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 630         },
 631         .get_engine_clock = &radeon_atom_get_engine_clock,
 632         .set_engine_clock = &radeon_atom_set_engine_clock,
 633         .get_memory_clock = &radeon_atom_get_memory_clock,
 634         .set_memory_clock = &radeon_atom_set_memory_clock,
 635         .get_pcie_lanes = NULL,
 636         .set_pcie_lanes = NULL,
 637         .set_clock_gating = &radeon_atom_set_clock_gating,
 638         .set_surface_reg = r100_set_surface_reg,
 639         .clear_surface_reg = r100_clear_surface_reg,
 640         .bandwidth_update = &rs690_bandwidth_update,
 641         .hpd = {
 642                 .init = &rs600_hpd_init,
 643                 .fini = &rs600_hpd_fini,
 644                 .sense = &rs600_hpd_sense,
 645                 .set_polarity = &rs600_hpd_set_polarity,
 646         },
 647         .ioctl_wait_idle = NULL,
 648         .gui_idle = &r100_gui_idle,
 649         .pm = {
 650                 .misc = &rs600_pm_misc,
 651                 .prepare = &rs600_pm_prepare,
 652                 .finish = &rs600_pm_finish,
 653                 .init_profile = &r420_pm_init_profile,
 654                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 655         },
 656         .pflip = {
 657                 .pre_page_flip = &rs600_pre_page_flip,
 658                 .page_flip = &rs600_page_flip,
 659                 .post_page_flip = &rs600_post_page_flip,
 660         },
 661         .wait_for_vblank = &avivo_wait_for_vblank,
 662         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 663 };
 664
 665 static struct radeon_asic rv515_asic = {
 666         .init = &rv515_init,
 667         .fini = &rv515_fini,
 668         .suspend = &rv515_suspend,
 669         .resume = &rv515_resume,
 670         .vga_set_state = &r100_vga_set_state,
 671         .gpu_is_lockup = &r300_gpu_is_lockup,
 672         .asic_reset = &rs600_asic_reset,
 673         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 674         .gart_set_page = &rv370_pcie_gart_set_page,
 675         .ring_start = &rv515_ring_start,
 676         .ring_test = &r100_ring_test,
 677         .ring = {
 678                 [RADEON_RING_TYPE_GFX_INDEX] = {
 679                         .ib_execute = &r100_ring_ib_execute,
 680                         .emit_fence = &r300_fence_ring_emit,
 681                         .emit_semaphore = &r100_semaphore_ring_emit,
 682                         .cs_parse = &r300_cs_parse,
 683                 }
 684         },
 685         .irq = {
 686                 .set = &rs600_irq_set,
 687                 .process = &rs600_irq_process,
 688         },
 689         .get_vblank_counter = &rs600_get_vblank_counter,
 690         .copy = {
 691                 .blit = &r100_copy_blit,
 692                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 693                 .dma = &r200_copy_dma,
 694                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 695                 .copy = &r100_copy_blit,
 696                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 697         },
 698         .get_engine_clock = &radeon_atom_get_engine_clock,
 699         .set_engine_clock = &radeon_atom_set_engine_clock,
 700         .get_memory_clock = &radeon_atom_get_memory_clock,
 701         .set_memory_clock = &radeon_atom_set_memory_clock,
 702         .get_pcie_lanes = &rv370_get_pcie_lanes,
 703         .set_pcie_lanes = &rv370_set_pcie_lanes,
 704         .set_clock_gating = &radeon_atom_set_clock_gating,
 705         .set_surface_reg = r100_set_surface_reg,
 706         .clear_surface_reg = r100_clear_surface_reg,
 707         .bandwidth_update = &rv515_bandwidth_update,
 708         .hpd = {
 709                 .init = &rs600_hpd_init,
 710                 .fini = &rs600_hpd_fini,
 711                 .sense = &rs600_hpd_sense,
 712                 .set_polarity = &rs600_hpd_set_polarity,
 713         },
 714         .ioctl_wait_idle = NULL,
 715         .gui_idle = &r100_gui_idle,
 716         .pm = {
 717                 .misc = &rs600_pm_misc,
 718                 .prepare = &rs600_pm_prepare,
 719                 .finish = &rs600_pm_finish,
 720                 .init_profile = &r420_pm_init_profile,
 721                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 722         },
 723         .pflip = {
 724                 .pre_page_flip = &rs600_pre_page_flip,
 725                 .page_flip = &rs600_page_flip,
 726                 .post_page_flip = &rs600_post_page_flip,
 727         },
 728         .wait_for_vblank = &avivo_wait_for_vblank,
 729         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 730 };
 731
 732 static struct radeon_asic r520_asic = {
 733         .init = &r520_init,
 734         .fini = &rv515_fini,
 735         .suspend = &rv515_suspend,
 736         .resume = &r520_resume,
 737         .vga_set_state = &r100_vga_set_state,
 738         .gpu_is_lockup = &r300_gpu_is_lockup,
 739         .asic_reset = &rs600_asic_reset,
 740         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 741         .gart_set_page = &rv370_pcie_gart_set_page,
 742         .ring_start = &rv515_ring_start,
 743         .ring_test = &r100_ring_test,
 744         .ring = {
 745                 [RADEON_RING_TYPE_GFX_INDEX] = {
 746                         .ib_execute = &r100_ring_ib_execute,
 747                         .emit_fence = &r300_fence_ring_emit,
 748                         .emit_semaphore = &r100_semaphore_ring_emit,
 749                         .cs_parse = &r300_cs_parse,
 750                 }
 751         },
 752         .irq = {
 753                 .set = &rs600_irq_set,
 754                 .process = &rs600_irq_process,
 755         },
 756         .get_vblank_counter = &rs600_get_vblank_counter,
 757         .copy = {
 758                 .blit = &r100_copy_blit,
 759                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 760                 .dma = &r200_copy_dma,
 761                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 762                 .copy = &r100_copy_blit,
 763                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 764         },
 765         .get_engine_clock = &radeon_atom_get_engine_clock,
 766         .set_engine_clock = &radeon_atom_set_engine_clock,
 767         .get_memory_clock = &radeon_atom_get_memory_clock,
 768         .set_memory_clock = &radeon_atom_set_memory_clock,
 769         .get_pcie_lanes = &rv370_get_pcie_lanes,
 770         .set_pcie_lanes = &rv370_set_pcie_lanes,
 771         .set_clock_gating = &radeon_atom_set_clock_gating,
 772         .set_surface_reg = r100_set_surface_reg,
 773         .clear_surface_reg = r100_clear_surface_reg,
 774         .bandwidth_update = &rv515_bandwidth_update,
 775         .hpd = {
 776                 .init = &rs600_hpd_init,
 777                 .fini = &rs600_hpd_fini,
 778                 .sense = &rs600_hpd_sense,
 779                 .set_polarity = &rs600_hpd_set_polarity,
 780         },
 781         .ioctl_wait_idle = NULL,
 782         .gui_idle = &r100_gui_idle,
 783         .pm = {
 784                 .misc = &rs600_pm_misc,
 785                 .prepare = &rs600_pm_prepare,
 786                 .finish = &rs600_pm_finish,
 787                 .init_profile = &r420_pm_init_profile,
 788                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 789         },
 790         .pflip = {
 791                 .pre_page_flip = &rs600_pre_page_flip,
 792                 .page_flip = &rs600_page_flip,
 793                 .post_page_flip = &rs600_post_page_flip,
 794         },
 795         .wait_for_vblank = &avivo_wait_for_vblank,
 796         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 797 };
 798
 799 static struct radeon_asic r600_asic = {
 800         .init = &r600_init,
 801         .fini = &r600_fini,
 802         .suspend = &r600_suspend,
 803         .resume = &r600_resume,
 804         .vga_set_state = &r600_vga_set_state,
 805         .gpu_is_lockup = &r600_gpu_is_lockup,
 806         .asic_reset = &r600_asic_reset,
 807         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 808         .gart_set_page = &rs600_gart_set_page,
 809         .ring_test = &r600_ring_test,
 810         .ring = {
 811                 [RADEON_RING_TYPE_GFX_INDEX] = {
 812                         .ib_execute = &r600_ring_ib_execute,
 813                         .emit_fence = &r600_fence_ring_emit,
 814                         .emit_semaphore = &r600_semaphore_ring_emit,
 815                         .cs_parse = &r600_cs_parse,
 816                 }
 817         },
 818         .irq = {
 819                 .set = &r600_irq_set,
 820                 .process = &r600_irq_process,
 821         },
 822         .get_vblank_counter = &rs600_get_vblank_counter,
 823         .copy = {
 824                 .blit = &r600_copy_blit,
 825                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 826                 .dma = NULL,
 827                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 828                 .copy = &r600_copy_blit,
 829                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 830         },
 831         .get_engine_clock = &radeon_atom_get_engine_clock,
 832         .set_engine_clock = &radeon_atom_set_engine_clock,
 833         .get_memory_clock = &radeon_atom_get_memory_clock,
 834         .set_memory_clock = &radeon_atom_set_memory_clock,
 835         .get_pcie_lanes = &r600_get_pcie_lanes,
 836         .set_pcie_lanes = &r600_set_pcie_lanes,
 837         .set_clock_gating = NULL,
 838         .set_surface_reg = r600_set_surface_reg,
 839         .clear_surface_reg = r600_clear_surface_reg,
 840         .bandwidth_update = &rv515_bandwidth_update,
 841         .hpd = {
 842                 .init = &r600_hpd_init,
 843                 .fini = &r600_hpd_fini,
 844                 .sense = &r600_hpd_sense,
 845                 .set_polarity = &r600_hpd_set_polarity,
 846         },
 847         .ioctl_wait_idle = r600_ioctl_wait_idle,
 848         .gui_idle = &r600_gui_idle,
 849         .pm = {
 850                 .misc = &r600_pm_misc,
 851                 .prepare = &rs600_pm_prepare,
 852                 .finish = &rs600_pm_finish,
 853                 .init_profile = &r600_pm_init_profile,
 854                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 855         },
 856         .pflip = {
 857                 .pre_page_flip = &rs600_pre_page_flip,
 858                 .page_flip = &rs600_page_flip,
 859                 .post_page_flip = &rs600_post_page_flip,
 860         },
 861         .wait_for_vblank = &avivo_wait_for_vblank,
 862         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 863 };
 864
 865 static struct radeon_asic rs780_asic = {
 866         .init = &r600_init,
 867         .fini = &r600_fini,
 868         .suspend = &r600_suspend,
 869         .resume = &r600_resume,
 870         .gpu_is_lockup = &r600_gpu_is_lockup,
 871         .vga_set_state = &r600_vga_set_state,
 872         .asic_reset = &r600_asic_reset,
 873         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 874         .gart_set_page = &rs600_gart_set_page,
 875         .ring_test = &r600_ring_test,
 876         .ring = {
 877                 [RADEON_RING_TYPE_GFX_INDEX] = {
 878                         .ib_execute = &r600_ring_ib_execute,
 879                         .emit_fence = &r600_fence_ring_emit,
 880                         .emit_semaphore = &r600_semaphore_ring_emit,
 881                         .cs_parse = &r600_cs_parse,
 882                 }
 883         },
 884         .irq = {
 885                 .set = &r600_irq_set,
 886                 .process = &r600_irq_process,
 887         },
 888         .get_vblank_counter = &rs600_get_vblank_counter,
 889         .copy = {
 890                 .blit = &r600_copy_blit,
 891                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 892                 .dma = NULL,
 893                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 894                 .copy = &r600_copy_blit,
 895                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 896         },
 897         .get_engine_clock = &radeon_atom_get_engine_clock,
 898         .set_engine_clock = &radeon_atom_set_engine_clock,
 899         .get_memory_clock = NULL,
 900         .set_memory_clock = NULL,
 901         .get_pcie_lanes = NULL,
 902         .set_pcie_lanes = NULL,
 903         .set_clock_gating = NULL,
 904         .set_surface_reg = r600_set_surface_reg,
 905         .clear_surface_reg = r600_clear_surface_reg,
 906         .bandwidth_update = &rs690_bandwidth_update,
 907         .hpd = {
 908                 .init = &r600_hpd_init,
 909                 .fini = &r600_hpd_fini,
 910                 .sense = &r600_hpd_sense,
 911                 .set_polarity = &r600_hpd_set_polarity,
 912         },
 913         .ioctl_wait_idle = r600_ioctl_wait_idle,
 914         .gui_idle = &r600_gui_idle,
 915         .pm = {
 916                 .misc = &r600_pm_misc,
 917                 .prepare = &rs600_pm_prepare,
 918                 .finish = &rs600_pm_finish,
 919                 .init_profile = &rs780_pm_init_profile,
 920                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 921         },
 922         .pflip = {
 923                 .pre_page_flip = &rs600_pre_page_flip,
 924                 .page_flip = &rs600_page_flip,
 925                 .post_page_flip = &rs600_post_page_flip,
 926         },
 927         .wait_for_vblank = &avivo_wait_for_vblank,
 928         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 929 };
 930
 931 static struct radeon_asic rv770_asic = {
 932         .init = &rv770_init,
 933         .fini = &rv770_fini,
 934         .suspend = &rv770_suspend,
 935         .resume = &rv770_resume,
 936         .asic_reset = &r600_asic_reset,
 937         .gpu_is_lockup = &r600_gpu_is_lockup,
 938         .vga_set_state = &r600_vga_set_state,
 939         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
 940         .gart_set_page = &rs600_gart_set_page,
 941         .ring_test = &r600_ring_test,
 942         .ring = {
 943                 [RADEON_RING_TYPE_GFX_INDEX] = {
 944                         .ib_execute = &r600_ring_ib_execute,
 945                         .emit_fence = &r600_fence_ring_emit,
 946                         .emit_semaphore = &r600_semaphore_ring_emit,
 947                         .cs_parse = &r600_cs_parse,
 948                 }
 949         },
 950         .irq = {
 951                 .set = &r600_irq_set,
 952                 .process = &r600_irq_process,
 953         },
 954         .get_vblank_counter = &rs600_get_vblank_counter,
 955         .copy = {
 956                 .blit = &r600_copy_blit,
 957                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 958                 .dma = NULL,
 959                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 960                 .copy = &r600_copy_blit,
 961                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 962         },
 963         .get_engine_clock = &radeon_atom_get_engine_clock,
 964         .set_engine_clock = &radeon_atom_set_engine_clock,
 965         .get_memory_clock = &radeon_atom_get_memory_clock,
 966         .set_memory_clock = &radeon_atom_set_memory_clock,
 967         .get_pcie_lanes = &r600_get_pcie_lanes,
 968         .set_pcie_lanes = &r600_set_pcie_lanes,
 969         .set_clock_gating = &radeon_atom_set_clock_gating,
 970         .set_surface_reg = r600_set_surface_reg,
 971         .clear_surface_reg = r600_clear_surface_reg,
 972         .bandwidth_update = &rv515_bandwidth_update,
 973         .hpd = {
 974                 .init = &r600_hpd_init,
 975                 .fini = &r600_hpd_fini,
 976                 .sense = &r600_hpd_sense,
 977                 .set_polarity = &r600_hpd_set_polarity,
 978         },
 979         .ioctl_wait_idle = r600_ioctl_wait_idle,
 980         .gui_idle = &r600_gui_idle,
 981         .pm = {
 982                 .misc = &rv770_pm_misc,
 983                 .prepare = &rs600_pm_prepare,
 984                 .finish = &rs600_pm_finish,
 985                 .init_profile = &r600_pm_init_profile,
 986                 .get_dynpm_state = &r600_pm_get_dynpm_state,
 987         },
 988         .pflip = {
 989                 .pre_page_flip = &rs600_pre_page_flip,
 990                 .page_flip = &rv770_page_flip,
 991                 .post_page_flip = &rs600_post_page_flip,
 992         },
 993         .wait_for_vblank = &avivo_wait_for_vblank,
 994         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 995 };
 996
 997 static struct radeon_asic evergreen_asic = {
 998         .init = &evergreen_init,
 999         .fini = &evergreen_fini,
1000         .suspend = &evergreen_suspend,
1001         .resume = &evergreen_resume,
1002         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1003         .asic_reset = &evergreen_asic_reset,
1004         .vga_set_state = &r600_vga_set_state,
1005         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1006         .gart_set_page = &rs600_gart_set_page,
1007         .ring_test = &r600_ring_test,
1008         .ring = {
1009                 [RADEON_RING_TYPE_GFX_INDEX] = {
1010                         .ib_execute = &evergreen_ring_ib_execute,
1011                         .emit_fence = &r600_fence_ring_emit,
1012                         .emit_semaphore = &r600_semaphore_ring_emit,
1013                         .cs_parse = &evergreen_cs_parse,
1014                 }
1015         },
1016         .irq = {
1017                 .set = &evergreen_irq_set,
1018                 .process = &evergreen_irq_process,
1019         },
1020         .get_vblank_counter = &evergreen_get_vblank_counter,
1021         .copy = {
1022                 .blit = &r600_copy_blit,
1023                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1024                 .dma = NULL,
1025                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1026                 .copy = &r600_copy_blit,
1027                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1028         },
1029         .get_engine_clock = &radeon_atom_get_engine_clock,
1030         .set_engine_clock = &radeon_atom_set_engine_clock,
1031         .get_memory_clock = &radeon_atom_get_memory_clock,
1032         .set_memory_clock = &radeon_atom_set_memory_clock,
1033         .get_pcie_lanes = &r600_get_pcie_lanes,
1034         .set_pcie_lanes = &r600_set_pcie_lanes,
1035         .set_clock_gating = NULL,
1036         .set_surface_reg = r600_set_surface_reg,
1037         .clear_surface_reg = r600_clear_surface_reg,
1038         .bandwidth_update = &evergreen_bandwidth_update,
1039         .hpd = {
1040                 .init = &evergreen_hpd_init,
1041                 .fini = &evergreen_hpd_fini,
1042                 .sense = &evergreen_hpd_sense,
1043                 .set_polarity = &evergreen_hpd_set_polarity,
1044         },
1045         .ioctl_wait_idle = r600_ioctl_wait_idle,
1046         .gui_idle = &r600_gui_idle,
1047         .pm = {
1048                 .misc = &evergreen_pm_misc,
1049                 .prepare = &evergreen_pm_prepare,
1050                 .finish = &evergreen_pm_finish,
1051                 .init_profile = &r600_pm_init_profile,
1052                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1053         },
1054         .pflip = {
1055                 .pre_page_flip = &evergreen_pre_page_flip,
1056                 .page_flip = &evergreen_page_flip,
1057                 .post_page_flip = &evergreen_post_page_flip,
1058         },
1059         .wait_for_vblank = &dce4_wait_for_vblank,
1060         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1061 };
1062
1063 static struct radeon_asic sumo_asic = {
1064         .init = &evergreen_init,
1065         .fini = &evergreen_fini,
1066         .suspend = &evergreen_suspend,
1067         .resume = &evergreen_resume,
1068         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1069         .asic_reset = &evergreen_asic_reset,
1070         .vga_set_state = &r600_vga_set_state,
1071         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1072         .gart_set_page = &rs600_gart_set_page,
1073         .ring_test = &r600_ring_test,
1074         .ring = {
1075                 [RADEON_RING_TYPE_GFX_INDEX] = {
1076                         .ib_execute = &evergreen_ring_ib_execute,
1077                         .emit_fence = &r600_fence_ring_emit,
1078                         .emit_semaphore = &r600_semaphore_ring_emit,
1079                         .cs_parse = &evergreen_cs_parse,
1080                 },
1081         },
1082         .irq = {
1083                 .set = &evergreen_irq_set,
1084                 .process = &evergreen_irq_process,
1085         },
1086         .get_vblank_counter = &evergreen_get_vblank_counter,
1087         .copy = {
1088                 .blit = &r600_copy_blit,
1089                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1090                 .dma = NULL,
1091                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1092                 .copy = &r600_copy_blit,
1093                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1094         },
1095         .get_engine_clock = &radeon_atom_get_engine_clock,
1096         .set_engine_clock = &radeon_atom_set_engine_clock,
1097         .get_memory_clock = NULL,
1098         .set_memory_clock = NULL,
1099         .get_pcie_lanes = NULL,
1100         .set_pcie_lanes = NULL,
1101         .set_clock_gating = NULL,
1102         .set_surface_reg = r600_set_surface_reg,
1103         .clear_surface_reg = r600_clear_surface_reg,
1104         .bandwidth_update = &evergreen_bandwidth_update,
1105         .hpd = {
1106                 .init = &evergreen_hpd_init,
1107                 .fini = &evergreen_hpd_fini,
1108                 .sense = &evergreen_hpd_sense,
1109                 .set_polarity = &evergreen_hpd_set_polarity,
1110         },
1111         .ioctl_wait_idle = r600_ioctl_wait_idle,
1112         .gui_idle = &r600_gui_idle,
1113         .pm = {
1114                 .misc = &evergreen_pm_misc,
1115                 .prepare = &evergreen_pm_prepare,
1116                 .finish = &evergreen_pm_finish,
1117                 .init_profile = &sumo_pm_init_profile,
1118                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1119         },
1120         .pflip = {
1121                 .pre_page_flip = &evergreen_pre_page_flip,
1122                 .page_flip = &evergreen_page_flip,
1123                 .post_page_flip = &evergreen_post_page_flip,
1124         },
1125         .wait_for_vblank = &dce4_wait_for_vblank,
1126         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1127 };
1128
1129 static struct radeon_asic btc_asic = {
1130         .init = &evergreen_init,
1131         .fini = &evergreen_fini,
1132         .suspend = &evergreen_suspend,
1133         .resume = &evergreen_resume,
1134         .gpu_is_lockup = &evergreen_gpu_is_lockup,
1135         .asic_reset = &evergreen_asic_reset,
1136         .vga_set_state = &r600_vga_set_state,
1137         .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1138         .gart_set_page = &rs600_gart_set_page,
1139         .ring_test = &r600_ring_test,
1140         .ring = {
1141                 [RADEON_RING_TYPE_GFX_INDEX] = {
1142                         .ib_execute = &evergreen_ring_ib_execute,
1143                         .emit_fence = &r600_fence_ring_emit,
1144                         .emit_semaphore = &r600_semaphore_ring_emit,
1145                         .cs_parse = &evergreen_cs_parse,
1146                 }
1147         },
1148         .irq = {
1149                 .set = &evergreen_irq_set,
1150                 .process = &evergreen_irq_process,
1151         },
1152         .get_vblank_counter = &evergreen_get_vblank_counter,
1153         .copy = {
1154                 .blit = &r600_copy_blit,
1155                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1156                 .dma = NULL,
1157                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1158                 .copy = &r600_copy_blit,
1159                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1160         },
1161         .get_engine_clock = &radeon_atom_get_engine_clock,
1162         .set_engine_clock = &radeon_atom_set_engine_clock,
1163         .get_memory_clock = &radeon_atom_get_memory_clock,
1164         .set_memory_clock = &radeon_atom_set_memory_clock,
1165         .get_pcie_lanes = NULL,
1166         .set_pcie_lanes = NULL,
1167         .set_clock_gating = NULL,
1168         .set_surface_reg = r600_set_surface_reg,
1169         .clear_surface_reg = r600_clear_surface_reg,
1170         .bandwidth_update = &evergreen_bandwidth_update,
1171         .hpd = {
1172                 .init = &evergreen_hpd_init,
1173                 .fini = &evergreen_hpd_fini,
1174                 .sense = &evergreen_hpd_sense,
1175                 .set_polarity = &evergreen_hpd_set_polarity,
1176         },
1177         .ioctl_wait_idle = r600_ioctl_wait_idle,
1178         .gui_idle = &r600_gui_idle,
1179         .pm = {
1180                 .misc = &evergreen_pm_misc,
1181                 .prepare = &evergreen_pm_prepare,
1182                 .finish = &evergreen_pm_finish,
1183                 .init_profile = &r600_pm_init_profile,
1184                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1185         },
1186         .pflip = {
1187                 .pre_page_flip = &evergreen_pre_page_flip,
1188                 .page_flip = &evergreen_page_flip,
1189                 .post_page_flip = &evergreen_post_page_flip,
1190         },
1191         .wait_for_vblank = &dce4_wait_for_vblank,
1192         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1193 };
1194
1195 static const struct radeon_vm_funcs cayman_vm_funcs = {
1196         .init = &cayman_vm_init,
1197         .fini = &cayman_vm_fini,
1198         .bind = &cayman_vm_bind,
1199         .unbind = &cayman_vm_unbind,
1200         .tlb_flush = &cayman_vm_tlb_flush,
1201         .page_flags = &cayman_vm_page_flags,
1202         .set_page = &cayman_vm_set_page,
1203 };
1204
1205 static struct radeon_asic cayman_asic = {
1206         .init = &cayman_init,
1207         .fini = &cayman_fini,
1208         .suspend = &cayman_suspend,
1209         .resume = &cayman_resume,
1210         .gpu_is_lockup = &cayman_gpu_is_lockup,
1211         .asic_reset = &cayman_asic_reset,
1212         .vga_set_state = &r600_vga_set_state,
1213         .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
1214         .gart_set_page = &rs600_gart_set_page,
1215         .ring_test = &r600_ring_test,
1216         .ring = {
1217                 [RADEON_RING_TYPE_GFX_INDEX] = {
1218                         .ib_execute = &cayman_ring_ib_execute,
1219                         .ib_parse = &evergreen_ib_parse,
1220                         .emit_fence = &cayman_fence_ring_emit,
1221                         .emit_semaphore = &r600_semaphore_ring_emit,
1222                         .cs_parse = &evergreen_cs_parse,
1223                 },
1224                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1225                         .ib_execute = &cayman_ring_ib_execute,
1226                         .ib_parse = &evergreen_ib_parse,
1227                         .emit_fence = &cayman_fence_ring_emit,
1228                         .emit_semaphore = &r600_semaphore_ring_emit,
1229                         .cs_parse = &evergreen_cs_parse,
1230                 },
1231                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1232                         .ib_execute = &cayman_ring_ib_execute,
1233                         .ib_parse = &evergreen_ib_parse,
1234                         .emit_fence = &cayman_fence_ring_emit,
1235                         .emit_semaphore = &r600_semaphore_ring_emit,
1236                         .cs_parse = &evergreen_cs_parse,
1237                 }
1238         },
1239         .irq = {
1240                 .set = &evergreen_irq_set,
1241                 .process = &evergreen_irq_process,
1242         },
1243         .get_vblank_counter = &evergreen_get_vblank_counter,
1244         .copy = {
1245                 .blit = &r600_copy_blit,
1246                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1247                 .dma = NULL,
1248                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1249                 .copy = &r600_copy_blit,
1250                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1251         },
1252         .get_engine_clock = &radeon_atom_get_engine_clock,
1253         .set_engine_clock = &radeon_atom_set_engine_clock,
1254         .get_memory_clock = &radeon_atom_get_memory_clock,
1255         .set_memory_clock = &radeon_atom_set_memory_clock,
1256         .get_pcie_lanes = NULL,
1257         .set_pcie_lanes = NULL,
1258         .set_clock_gating = NULL,
1259         .set_surface_reg = r600_set_surface_reg,
1260         .clear_surface_reg = r600_clear_surface_reg,
1261         .bandwidth_update = &evergreen_bandwidth_update,
1262         .hpd = {
1263                 .init = &evergreen_hpd_init,
1264                 .fini = &evergreen_hpd_fini,
1265                 .sense = &evergreen_hpd_sense,
1266                 .set_polarity = &evergreen_hpd_set_polarity,
1267         },
1268         .ioctl_wait_idle = r600_ioctl_wait_idle,
1269         .gui_idle = &r600_gui_idle,
1270         .pm = {
1271                 .misc = &evergreen_pm_misc,
1272                 .prepare = &evergreen_pm_prepare,
1273                 .finish = &evergreen_pm_finish,
1274                 .init_profile = &r600_pm_init_profile,
1275                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1276         },
1277         .pflip = {
1278                 .pre_page_flip = &evergreen_pre_page_flip,
1279                 .page_flip = &evergreen_page_flip,
1280                 .post_page_flip = &evergreen_post_page_flip,
1281         },
1282         .wait_for_vblank = &dce4_wait_for_vblank,
1283         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1284 };
1285
1286 int radeon_asic_init(struct radeon_device *rdev)
1287 {
1288         radeon_register_accessor_init(rdev);
1289
1290         /* set the number of crtcs */
1291         if (rdev->flags & RADEON_SINGLE_CRTC)
1292                 rdev->num_crtc = 1;
1293         else
1294                 rdev->num_crtc = 2;
1295
1296         switch (rdev->family) {
1297         case CHIP_R100:
1298         case CHIP_RV100:
1299         case CHIP_RS100:
1300         case CHIP_RV200:
1301         case CHIP_RS200:
1302                 rdev->asic = &r100_asic;
1303                 break;
1304         case CHIP_R200:
1305         case CHIP_RV250:
1306         case CHIP_RS300:
1307         case CHIP_RV280:
1308                 rdev->asic = &r200_asic;
1309                 break;
1310         case CHIP_R300:
1311         case CHIP_R350:
1312         case CHIP_RV350:
1313         case CHIP_RV380:
1314                 if (rdev->flags & RADEON_IS_PCIE)
1315                         rdev->asic = &r300_asic_pcie;
1316                 else
1317                         rdev->asic = &r300_asic;
1318                 break;
1319         case CHIP_R420:
1320         case CHIP_R423:
1321         case CHIP_RV410:
1322                 rdev->asic = &r420_asic;
1323                 /* handle macs */
1324                 if (rdev->bios == NULL) {
1325                         rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
1326                         rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
1327                         rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
1328                         rdev->asic->set_memory_clock = NULL;
1329                 }
1330                 break;
1331         case CHIP_RS400:
1332         case CHIP_RS480:
1333                 rdev->asic = &rs400_asic;
1334                 break;
1335         case CHIP_RS600:
1336                 rdev->asic = &rs600_asic;
1337                 break;
1338         case CHIP_RS690:
1339         case CHIP_RS740:
1340                 rdev->asic = &rs690_asic;
1341                 break;
1342         case CHIP_RV515:
1343                 rdev->asic = &rv515_asic;
1344                 break;
1345         case CHIP_R520:
1346         case CHIP_RV530:
1347         case CHIP_RV560:
1348         case CHIP_RV570:
1349         case CHIP_R580:
1350                 rdev->asic = &r520_asic;
1351                 break;
1352         case CHIP_R600:
1353         case CHIP_RV610:
1354         case CHIP_RV630:
1355         case CHIP_RV620:
1356         case CHIP_RV635:
1357         case CHIP_RV670:
1358                 rdev->asic = &r600_asic;
1359                 break;
1360         case CHIP_RS780:
1361         case CHIP_RS880:
1362                 rdev->asic = &rs780_asic;
1363                 break;
1364         case CHIP_RV770:
1365         case CHIP_RV730:
1366         case CHIP_RV710:
1367         case CHIP_RV740:
1368                 rdev->asic = &rv770_asic;
1369                 break;
1370         case CHIP_CEDAR:
1371         case CHIP_REDWOOD:
1372         case CHIP_JUNIPER:
1373         case CHIP_CYPRESS:
1374         case CHIP_HEMLOCK:
1375                 /* set num crtcs */
1376                 if (rdev->family == CHIP_CEDAR)
1377                         rdev->num_crtc = 4;
1378                 else
1379                         rdev->num_crtc = 6;
1380                 rdev->asic = &evergreen_asic;
1381                 break;
1382         case CHIP_PALM:
1383         case CHIP_SUMO:
1384         case CHIP_SUMO2:
1385                 rdev->asic = &sumo_asic;
1386                 break;
1387         case CHIP_BARTS:
1388         case CHIP_TURKS:
1389         case CHIP_CAICOS:
1390                 /* set num crtcs */
1391                 if (rdev->family == CHIP_CAICOS)
1392                         rdev->num_crtc = 4;
1393                 else
1394                         rdev->num_crtc = 6;
1395                 rdev->asic = &btc_asic;
1396                 break;
1397         case CHIP_CAYMAN:
1398                 rdev->asic = &cayman_asic;
1399                 /* set num crtcs */
1400                 rdev->num_crtc = 6;
1401                 rdev->vm_manager.funcs = &cayman_vm_funcs;
1402                 break;
1403         default:
1404                 /* FIXME: not supported yet */
1405                 return -EINVAL;
1406         }
1407
1408         if (rdev->flags & RADEON_IS_IGP) {
1409                 rdev->asic->get_memory_clock = NULL;
1410                 rdev->asic->set_memory_clock = NULL;
1411         }
1412
1413         return 0;
1414 }
1415