2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset, size;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84 for (i = 0; i < num_indices; i++) {
85 gpio = &i2c_info->asGPIO_Info[i];
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
108 i2c.hw_capable = false;
110 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 struct radeon_gpio_rec gpio;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
132 struct _ATOM_GPIO_PIN_LUT *gpio_info;
133 ATOM_GPIO_PIN_ASSIGNMENT *pin;
134 u16 data_offset, size;
137 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
146 for (i = 0; i < num_indices; i++) {
147 pin = &gpio_info->asGPIO_Pin[i];
148 if (id == pin->ucGPIO_ID) {
149 gpio.id = pin->ucGPIO_ID;
150 gpio.reg = pin->usGpioPin_AIndex * 4;
151 gpio.mask = (1 << pin->ucGpioPinBitShift);
161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
162 struct radeon_gpio_rec *gpio)
164 struct radeon_hpd hpd;
167 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A;
170 reg = AVIVO_DC_GPIO_HPD_A;
173 if (gpio->reg == reg) {
176 hpd.hpd = RADEON_HPD_1;
179 hpd.hpd = RADEON_HPD_2;
182 hpd.hpd = RADEON_HPD_3;
185 hpd.hpd = RADEON_HPD_4;
188 hpd.hpd = RADEON_HPD_5;
191 hpd.hpd = RADEON_HPD_6;
194 hpd.hpd = RADEON_HPD_NONE;
198 hpd.hpd = RADEON_HPD_NONE;
202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
203 uint32_t supported_device,
205 struct radeon_i2c_bus_rec *i2c_bus,
207 struct radeon_hpd *hpd)
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) &&
212 (dev->pdev->subsystem_vendor == 0x1043) &&
213 (dev->pdev->subsystem_device == 0x826d)) {
214 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
215 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
216 *connector_type = DRM_MODE_CONNECTOR_DVID;
219 /* Asrock RS600 board lists the DVI port as HDMI */
220 if ((dev->pdev->device == 0x7941) &&
221 (dev->pdev->subsystem_vendor == 0x1849) &&
222 (dev->pdev->subsystem_device == 0x7941)) {
223 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
224 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
225 *connector_type = DRM_MODE_CONNECTOR_DVID;
228 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
229 if ((dev->pdev->device == 0x7941) &&
230 (dev->pdev->subsystem_vendor == 0x147b) &&
231 (dev->pdev->subsystem_device == 0x2412)) {
232 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
236 /* Falcon NW laptop lists vga ddc line for LVDS */
237 if ((dev->pdev->device == 0x5653) &&
238 (dev->pdev->subsystem_vendor == 0x1462) &&
239 (dev->pdev->subsystem_device == 0x0291)) {
240 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
241 i2c_bus->valid = false;
246 /* HIS X1300 is DVI+VGA, not DVI+DVI */
247 if ((dev->pdev->device == 0x7146) &&
248 (dev->pdev->subsystem_vendor == 0x17af) &&
249 (dev->pdev->subsystem_device == 0x2058)) {
250 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
254 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
255 if ((dev->pdev->device == 0x7142) &&
256 (dev->pdev->subsystem_vendor == 0x1458) &&
257 (dev->pdev->subsystem_device == 0x2134)) {
258 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
264 if ((dev->pdev->device == 0x71C5) &&
265 (dev->pdev->subsystem_vendor == 0x106b) &&
266 (dev->pdev->subsystem_device == 0x0080)) {
267 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
268 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
270 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
274 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
275 if ((dev->pdev->device == 0x9598) &&
276 (dev->pdev->subsystem_vendor == 0x1043) &&
277 (dev->pdev->subsystem_device == 0x01da)) {
278 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
279 *connector_type = DRM_MODE_CONNECTOR_DVII;
283 /* ASUS HD 3600 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x9598) &&
285 (dev->pdev->subsystem_vendor == 0x1043) &&
286 (dev->pdev->subsystem_device == 0x01e4)) {
287 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
288 *connector_type = DRM_MODE_CONNECTOR_DVII;
292 /* ASUS HD 3450 board lists the DVI port as HDMI */
293 if ((dev->pdev->device == 0x95C5) &&
294 (dev->pdev->subsystem_vendor == 0x1043) &&
295 (dev->pdev->subsystem_device == 0x01e2)) {
296 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
297 *connector_type = DRM_MODE_CONNECTOR_DVII;
301 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
302 * HDMI + VGA reporting as HDMI
304 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
305 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
306 *connector_type = DRM_MODE_CONNECTOR_VGA;
311 /* Acer laptop reports DVI-D as DVI-I */
312 if ((dev->pdev->device == 0x95c4) &&
313 (dev->pdev->subsystem_vendor == 0x1025) &&
314 (dev->pdev->subsystem_device == 0x013c)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
316 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
320 /* XFX Pine Group device rv730 reports no VGA DDC lines
321 * even though they are wired up to record 0x93
323 if ((dev->pdev->device == 0x9498) &&
324 (dev->pdev->subsystem_vendor == 0x1682) &&
325 (dev->pdev->subsystem_device == 0x2452)) {
326 struct radeon_device *rdev = dev->dev_private;
327 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
332 const int supported_devices_connector_convert[] = {
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_VGA,
335 DRM_MODE_CONNECTOR_DVII,
336 DRM_MODE_CONNECTOR_DVID,
337 DRM_MODE_CONNECTOR_DVIA,
338 DRM_MODE_CONNECTOR_SVIDEO,
339 DRM_MODE_CONNECTOR_Composite,
340 DRM_MODE_CONNECTOR_LVDS,
341 DRM_MODE_CONNECTOR_Unknown,
342 DRM_MODE_CONNECTOR_Unknown,
343 DRM_MODE_CONNECTOR_HDMIA,
344 DRM_MODE_CONNECTOR_HDMIB,
345 DRM_MODE_CONNECTOR_Unknown,
346 DRM_MODE_CONNECTOR_Unknown,
347 DRM_MODE_CONNECTOR_9PinDIN,
348 DRM_MODE_CONNECTOR_DisplayPort
351 const uint16_t supported_devices_connector_object_id_convert[] = {
352 CONNECTOR_OBJECT_ID_NONE,
353 CONNECTOR_OBJECT_ID_VGA,
354 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
355 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
356 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
357 CONNECTOR_OBJECT_ID_COMPOSITE,
358 CONNECTOR_OBJECT_ID_SVIDEO,
359 CONNECTOR_OBJECT_ID_LVDS,
360 CONNECTOR_OBJECT_ID_9PIN_DIN,
361 CONNECTOR_OBJECT_ID_9PIN_DIN,
362 CONNECTOR_OBJECT_ID_DISPLAYPORT,
363 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
364 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
365 CONNECTOR_OBJECT_ID_SVIDEO
368 const int object_connector_convert[] = {
369 DRM_MODE_CONNECTOR_Unknown,
370 DRM_MODE_CONNECTOR_DVII,
371 DRM_MODE_CONNECTOR_DVII,
372 DRM_MODE_CONNECTOR_DVID,
373 DRM_MODE_CONNECTOR_DVID,
374 DRM_MODE_CONNECTOR_VGA,
375 DRM_MODE_CONNECTOR_Composite,
376 DRM_MODE_CONNECTOR_SVIDEO,
377 DRM_MODE_CONNECTOR_Unknown,
378 DRM_MODE_CONNECTOR_Unknown,
379 DRM_MODE_CONNECTOR_9PinDIN,
380 DRM_MODE_CONNECTOR_Unknown,
381 DRM_MODE_CONNECTOR_HDMIA,
382 DRM_MODE_CONNECTOR_HDMIB,
383 DRM_MODE_CONNECTOR_LVDS,
384 DRM_MODE_CONNECTOR_9PinDIN,
385 DRM_MODE_CONNECTOR_Unknown,
386 DRM_MODE_CONNECTOR_Unknown,
387 DRM_MODE_CONNECTOR_Unknown,
388 DRM_MODE_CONNECTOR_DisplayPort,
389 DRM_MODE_CONNECTOR_eDP,
390 DRM_MODE_CONNECTOR_Unknown
393 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_mode_info *mode_info = &rdev->mode_info;
397 struct atom_context *ctx = mode_info->atom_context;
398 int index = GetIndexIntoMasterTable(DATA, Object_Header);
399 u16 size, data_offset;
401 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
402 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
403 ATOM_OBJECT_HEADER *obj_header;
404 int i, j, path_size, device_support;
406 u16 igp_lane_info, conn_id, connector_object_id;
408 struct radeon_i2c_bus_rec ddc_bus;
409 struct radeon_gpio_rec gpio;
410 struct radeon_hpd hpd;
412 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
418 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
419 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
420 (ctx->bios + data_offset +
421 le16_to_cpu(obj_header->usDisplayPathTableOffset));
422 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
423 (ctx->bios + data_offset +
424 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
425 device_support = le16_to_cpu(obj_header->usDeviceSupport);
428 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
429 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
430 ATOM_DISPLAY_OBJECT_PATH *path;
432 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
433 path_size += le16_to_cpu(path->usSize);
435 if (device_support & le16_to_cpu(path->usDeviceTag)) {
436 uint8_t con_obj_id, con_obj_num, con_obj_type;
439 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
442 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
445 (le16_to_cpu(path->usConnObjectId) &
446 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
448 /* TODO CV support */
449 if (le16_to_cpu(path->usDeviceTag) ==
450 ATOM_DEVICE_CV_SUPPORT)
454 if ((rdev->flags & RADEON_IS_IGP) &&
456 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
457 uint16_t igp_offset = 0;
458 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
461 GetIndexIntoMasterTable(DATA,
462 IntegratedSystemInfo);
464 if (atom_parse_data_header(ctx, index, &size, &frev,
465 &crev, &igp_offset)) {
469 (ATOM_INTEGRATED_SYSTEM_INFO_V2
470 *) (ctx->bios + igp_offset);
473 uint32_t slot_config, ct;
475 if (con_obj_num == 1)
484 ct = (slot_config >> 16) & 0xff;
486 object_connector_convert
488 connector_object_id = ct;
490 slot_config & 0xffff;
498 object_connector_convert[con_obj_id];
499 connector_object_id = con_obj_id;
504 object_connector_convert[con_obj_id];
505 connector_object_id = con_obj_id;
508 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
511 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
513 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
516 (le16_to_cpu(path->usGraphicObjIds[j]) &
517 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
519 (le16_to_cpu(path->usGraphicObjIds[j]) &
520 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
522 (le16_to_cpu(path->usGraphicObjIds[j]) &
523 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
525 /* FIXME: add support for router objects */
526 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
527 if (enc_obj_num == 2)
532 radeon_add_atom_encoder(dev,
541 /* look up gpio for ddc, hpd */
542 ddc_bus.valid = false;
543 hpd.hpd = RADEON_HPD_NONE;
544 if ((le16_to_cpu(path->usDeviceTag) &
545 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
546 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
547 if (le16_to_cpu(path->usConnObjectId) ==
548 le16_to_cpu(con_obj->asObjects[j].
550 ATOM_COMMON_RECORD_HEADER
552 (ATOM_COMMON_RECORD_HEADER
554 (ctx->bios + data_offset +
555 le16_to_cpu(con_obj->
558 ATOM_I2C_RECORD *i2c_record;
559 ATOM_HPD_INT_RECORD *hpd_record;
560 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
562 while (record->ucRecordType > 0
565 ATOM_MAX_OBJECT_RECORD_NUMBER) {
566 switch (record->ucRecordType) {
567 case ATOM_I2C_RECORD_TYPE:
572 (ATOM_I2C_ID_CONFIG_ACCESS *)
573 &i2c_record->sucI2cId;
574 ddc_bus = radeon_lookup_i2c_gpio(rdev,
578 case ATOM_HPD_INT_RECORD_TYPE:
580 (ATOM_HPD_INT_RECORD *)
582 gpio = radeon_lookup_gpio(rdev,
583 hpd_record->ucHPDIntGPIOID);
584 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
585 hpd.plugged_state = hpd_record->ucPlugged_PinState;
589 (ATOM_COMMON_RECORD_HEADER
600 /* needed for aux chan transactions */
601 ddc_bus.hpd = hpd.hpd;
603 conn_id = le16_to_cpu(path->usConnObjectId);
605 if (!radeon_atom_apply_quirks
606 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
607 &ddc_bus, &conn_id, &hpd))
610 radeon_add_atom_connector(dev,
614 connector_type, &ddc_bus,
615 linkb, igp_lane_info,
622 radeon_link_encoder_connector(dev);
627 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
631 struct radeon_device *rdev = dev->dev_private;
633 if (rdev->flags & RADEON_IS_IGP) {
634 return supported_devices_connector_object_id_convert
636 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
637 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
638 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
639 struct radeon_mode_info *mode_info = &rdev->mode_info;
640 struct atom_context *ctx = mode_info->atom_context;
641 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
642 uint16_t size, data_offset;
644 ATOM_XTMDS_INFO *xtmds;
646 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
647 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
649 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
650 if (connector_type == DRM_MODE_CONNECTOR_DVII)
651 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
653 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
655 if (connector_type == DRM_MODE_CONNECTOR_DVII)
656 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
658 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
661 return supported_devices_connector_object_id_convert
664 return supported_devices_connector_object_id_convert
669 struct bios_connector {
674 struct radeon_i2c_bus_rec ddc_bus;
675 struct radeon_hpd hpd;
678 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
682 struct radeon_device *rdev = dev->dev_private;
683 struct radeon_mode_info *mode_info = &rdev->mode_info;
684 struct atom_context *ctx = mode_info->atom_context;
685 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
686 uint16_t size, data_offset;
688 uint16_t device_support;
690 union atom_supported_devices *supported_devices;
691 int i, j, max_device;
692 struct bios_connector *bios_connectors;
693 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
695 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
696 if (!bios_connectors)
699 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
701 kfree(bios_connectors);
706 (union atom_supported_devices *)(ctx->bios + data_offset);
708 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
711 max_device = ATOM_MAX_SUPPORTED_DEVICE;
713 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
715 for (i = 0; i < max_device; i++) {
716 ATOM_CONNECTOR_INFO_I2C ci =
717 supported_devices->info.asConnInfo[i];
719 bios_connectors[i].valid = false;
721 if (!(device_support & (1 << i))) {
725 if (i == ATOM_DEVICE_CV_INDEX) {
726 DRM_DEBUG("Skipping Component Video\n");
730 bios_connectors[i].connector_type =
731 supported_devices_connector_convert[ci.sucConnectorInfo.
735 if (bios_connectors[i].connector_type ==
736 DRM_MODE_CONNECTOR_Unknown)
739 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
741 bios_connectors[i].line_mux =
742 ci.sucI2cId.ucAccess;
744 /* give tv unique connector ids */
745 if (i == ATOM_DEVICE_TV1_INDEX) {
746 bios_connectors[i].ddc_bus.valid = false;
747 bios_connectors[i].line_mux = 50;
748 } else if (i == ATOM_DEVICE_TV2_INDEX) {
749 bios_connectors[i].ddc_bus.valid = false;
750 bios_connectors[i].line_mux = 51;
751 } else if (i == ATOM_DEVICE_CV_INDEX) {
752 bios_connectors[i].ddc_bus.valid = false;
753 bios_connectors[i].line_mux = 52;
755 bios_connectors[i].ddc_bus =
756 radeon_lookup_i2c_gpio(rdev,
757 bios_connectors[i].line_mux);
759 if ((crev > 1) && (frev > 1)) {
760 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
763 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
766 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
769 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
773 if (i == ATOM_DEVICE_DFP1_INDEX)
774 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
775 else if (i == ATOM_DEVICE_DFP2_INDEX)
776 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
778 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
781 /* Always set the connector type to VGA for CRT1/CRT2. if they are
782 * shared with a DVI port, we'll pick up the DVI connector when we
783 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
785 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
786 bios_connectors[i].connector_type =
787 DRM_MODE_CONNECTOR_VGA;
789 if (!radeon_atom_apply_quirks
790 (dev, (1 << i), &bios_connectors[i].connector_type,
791 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
792 &bios_connectors[i].hpd))
795 bios_connectors[i].valid = true;
796 bios_connectors[i].devices = (1 << i);
798 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
799 radeon_add_atom_encoder(dev,
800 radeon_get_encoder_id(dev,
805 radeon_add_legacy_encoder(dev,
806 radeon_get_encoder_id(dev,
812 /* combine shared connectors */
813 for (i = 0; i < max_device; i++) {
814 if (bios_connectors[i].valid) {
815 for (j = 0; j < max_device; j++) {
816 if (bios_connectors[j].valid && (i != j)) {
817 if (bios_connectors[i].line_mux ==
818 bios_connectors[j].line_mux) {
819 /* make sure not to combine LVDS */
820 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
821 bios_connectors[i].line_mux = 53;
822 bios_connectors[i].ddc_bus.valid = false;
825 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
826 bios_connectors[j].line_mux = 53;
827 bios_connectors[j].ddc_bus.valid = false;
830 /* combine analog and digital for DVI-I */
831 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
832 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
833 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
834 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
835 bios_connectors[i].devices |=
836 bios_connectors[j].devices;
837 bios_connectors[i].connector_type =
838 DRM_MODE_CONNECTOR_DVII;
839 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
840 bios_connectors[i].hpd =
841 bios_connectors[j].hpd;
842 bios_connectors[j].valid = false;
850 /* add the connectors */
851 for (i = 0; i < max_device; i++) {
852 if (bios_connectors[i].valid) {
853 uint16_t connector_object_id =
854 atombios_get_connector_object_id(dev,
855 bios_connectors[i].connector_type,
856 bios_connectors[i].devices);
857 radeon_add_atom_connector(dev,
858 bios_connectors[i].line_mux,
859 bios_connectors[i].devices,
862 &bios_connectors[i].ddc_bus,
865 &bios_connectors[i].hpd);
869 radeon_link_encoder_connector(dev);
871 kfree(bios_connectors);
875 union firmware_info {
876 ATOM_FIRMWARE_INFO info;
877 ATOM_FIRMWARE_INFO_V1_2 info_12;
878 ATOM_FIRMWARE_INFO_V1_3 info_13;
879 ATOM_FIRMWARE_INFO_V1_4 info_14;
880 ATOM_FIRMWARE_INFO_V2_1 info_21;
883 bool radeon_atom_get_clock_info(struct drm_device *dev)
885 struct radeon_device *rdev = dev->dev_private;
886 struct radeon_mode_info *mode_info = &rdev->mode_info;
887 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
888 union firmware_info *firmware_info;
890 struct radeon_pll *p1pll = &rdev->clock.p1pll;
891 struct radeon_pll *p2pll = &rdev->clock.p2pll;
892 struct radeon_pll *dcpll = &rdev->clock.dcpll;
893 struct radeon_pll *spll = &rdev->clock.spll;
894 struct radeon_pll *mpll = &rdev->clock.mpll;
895 uint16_t data_offset;
897 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
898 &frev, &crev, &data_offset)) {
900 (union firmware_info *)(mode_info->atom_context->bios +
903 p1pll->reference_freq =
904 le16_to_cpu(firmware_info->info.usReferenceClock);
905 p1pll->reference_div = 0;
909 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
912 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
914 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
917 p1pll->lcd_pll_out_min =
918 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
919 if (p1pll->lcd_pll_out_min == 0)
920 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
921 p1pll->lcd_pll_out_max =
922 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
923 if (p1pll->lcd_pll_out_max == 0)
924 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
926 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
927 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
930 if (p1pll->pll_out_min == 0) {
931 if (ASIC_IS_AVIVO(rdev))
932 p1pll->pll_out_min = 64800;
934 p1pll->pll_out_min = 20000;
935 } else if (p1pll->pll_out_min > 64800) {
936 /* Limiting the pll output range is a good thing generally as
937 * it limits the number of possible pll combinations for a given
938 * frequency presumably to the ones that work best on each card.
939 * However, certain duallink DVI monitors seem to like
940 * pll combinations that would be limited by this at least on
941 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
945 p1pll->pll_out_min = 64800;
949 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
951 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
956 spll->reference_freq =
957 le16_to_cpu(firmware_info->info.usReferenceClock);
958 spll->reference_div = 0;
961 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
963 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
966 if (spll->pll_out_min == 0) {
967 if (ASIC_IS_AVIVO(rdev))
968 spll->pll_out_min = 64800;
970 spll->pll_out_min = 20000;
974 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
976 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
979 mpll->reference_freq =
980 le16_to_cpu(firmware_info->info.usReferenceClock);
981 mpll->reference_div = 0;
984 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
986 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
989 if (mpll->pll_out_min == 0) {
990 if (ASIC_IS_AVIVO(rdev))
991 mpll->pll_out_min = 64800;
993 mpll->pll_out_min = 20000;
997 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
999 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1001 rdev->clock.default_sclk =
1002 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1003 rdev->clock.default_mclk =
1004 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1006 if (ASIC_IS_DCE4(rdev)) {
1007 rdev->clock.default_dispclk =
1008 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1009 if (rdev->clock.default_dispclk == 0)
1010 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1011 rdev->clock.dp_extclk =
1012 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1023 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1024 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1027 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1029 struct radeon_mode_info *mode_info = &rdev->mode_info;
1030 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1031 union igp_info *igp_info;
1035 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1036 &frev, &crev, &data_offset)) {
1037 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1042 if ((rdev->family == CHIP_RS690) ||
1043 (rdev->family == CHIP_RS740)) {
1044 if (igp_info->info.ulBootUpMemoryClock)
1047 if (igp_info->info.ucMemoryType & 0xf0)
1052 if (igp_info->info_2.ucMemoryType & 0x0f)
1056 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1063 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1064 struct radeon_encoder_int_tmds *tmds)
1066 struct drm_device *dev = encoder->base.dev;
1067 struct radeon_device *rdev = dev->dev_private;
1068 struct radeon_mode_info *mode_info = &rdev->mode_info;
1069 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1070 uint16_t data_offset;
1071 struct _ATOM_TMDS_INFO *tmds_info;
1076 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1077 &frev, &crev, &data_offset)) {
1079 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1082 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1083 for (i = 0; i < 4; i++) {
1084 tmds->tmds_pll[i].freq =
1085 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1086 tmds->tmds_pll[i].value =
1087 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1088 tmds->tmds_pll[i].value |=
1089 (tmds_info->asMiscInfo[i].
1090 ucPLL_VCO_Gain & 0x3f) << 6;
1091 tmds->tmds_pll[i].value |=
1092 (tmds_info->asMiscInfo[i].
1093 ucPLL_DutyCycle & 0xf) << 12;
1094 tmds->tmds_pll[i].value |=
1095 (tmds_info->asMiscInfo[i].
1096 ucPLL_VoltageSwing & 0xf) << 16;
1098 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1099 tmds->tmds_pll[i].freq,
1100 tmds->tmds_pll[i].value);
1102 if (maxfreq == tmds->tmds_pll[i].freq) {
1103 tmds->tmds_pll[i].freq = 0xffffffff;
1112 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1117 struct drm_device *dev = encoder->base.dev;
1118 struct radeon_device *rdev = dev->dev_private;
1119 struct radeon_mode_info *mode_info = &rdev->mode_info;
1120 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1121 uint16_t data_offset;
1122 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1124 struct radeon_atom_ss *ss = NULL;
1127 if (id > ATOM_MAX_SS_ENTRY)
1130 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1131 &frev, &crev, &data_offset)) {
1133 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1136 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1141 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1142 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1144 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1145 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1146 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1147 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1148 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1149 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1158 struct _ATOM_LVDS_INFO info;
1159 struct _ATOM_LVDS_INFO_V12 info_12;
1162 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1166 struct drm_device *dev = encoder->base.dev;
1167 struct radeon_device *rdev = dev->dev_private;
1168 struct radeon_mode_info *mode_info = &rdev->mode_info;
1169 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1170 uint16_t data_offset, misc;
1171 union lvds_info *lvds_info;
1173 struct radeon_encoder_atom_dig *lvds = NULL;
1175 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1176 &frev, &crev, &data_offset)) {
1178 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1180 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1185 lvds->native_mode.clock =
1186 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1187 lvds->native_mode.hdisplay =
1188 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1189 lvds->native_mode.vdisplay =
1190 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1191 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1192 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1193 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1194 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1195 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1196 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1197 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1198 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1199 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1200 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1201 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1202 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1203 lvds->panel_pwr_delay =
1204 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1205 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1207 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1208 if (misc & ATOM_VSYNC_POLARITY)
1209 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1210 if (misc & ATOM_HSYNC_POLARITY)
1211 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1212 if (misc & ATOM_COMPOSITESYNC)
1213 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1214 if (misc & ATOM_INTERLACE)
1215 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1216 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1217 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1219 /* set crtc values */
1220 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1222 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1224 if (ASIC_IS_AVIVO(rdev)) {
1225 if (radeon_new_pll == 0)
1226 lvds->pll_algo = PLL_ALGO_LEGACY;
1228 lvds->pll_algo = PLL_ALGO_NEW;
1230 if (radeon_new_pll == 1)
1231 lvds->pll_algo = PLL_ALGO_NEW;
1233 lvds->pll_algo = PLL_ALGO_LEGACY;
1236 encoder->native_mode = lvds->native_mode;
1241 struct radeon_encoder_primary_dac *
1242 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1244 struct drm_device *dev = encoder->base.dev;
1245 struct radeon_device *rdev = dev->dev_private;
1246 struct radeon_mode_info *mode_info = &rdev->mode_info;
1247 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1248 uint16_t data_offset;
1249 struct _COMPASSIONATE_DATA *dac_info;
1252 struct radeon_encoder_primary_dac *p_dac = NULL;
1254 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1255 &frev, &crev, &data_offset)) {
1256 dac_info = (struct _COMPASSIONATE_DATA *)
1257 (mode_info->atom_context->bios + data_offset);
1259 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1264 bg = dac_info->ucDAC1_BG_Adjustment;
1265 dac = dac_info->ucDAC1_DAC_Adjustment;
1266 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1272 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1273 struct drm_display_mode *mode)
1275 struct radeon_mode_info *mode_info = &rdev->mode_info;
1276 ATOM_ANALOG_TV_INFO *tv_info;
1277 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1278 ATOM_DTD_FORMAT *dtd_timings;
1279 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1281 u16 data_offset, misc;
1283 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1284 &frev, &crev, &data_offset))
1289 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1290 if (index >= MAX_SUPPORTED_TV_TIMING)
1293 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1294 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1295 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1296 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1297 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1299 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1300 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1301 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1302 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1303 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1306 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1307 if (misc & ATOM_VSYNC_POLARITY)
1308 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1309 if (misc & ATOM_HSYNC_POLARITY)
1310 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1311 if (misc & ATOM_COMPOSITESYNC)
1312 mode->flags |= DRM_MODE_FLAG_CSYNC;
1313 if (misc & ATOM_INTERLACE)
1314 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1315 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1316 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1318 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1321 /* PAL timings appear to have wrong values for totals */
1322 mode->crtc_htotal -= 1;
1323 mode->crtc_vtotal -= 1;
1327 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1328 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1331 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1332 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1333 le16_to_cpu(dtd_timings->usHBlanking_Time);
1334 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1335 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1336 le16_to_cpu(dtd_timings->usHSyncOffset);
1337 mode->crtc_hsync_end = mode->crtc_hsync_start +
1338 le16_to_cpu(dtd_timings->usHSyncWidth);
1340 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1341 le16_to_cpu(dtd_timings->usVBlanking_Time);
1342 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1343 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1344 le16_to_cpu(dtd_timings->usVSyncOffset);
1345 mode->crtc_vsync_end = mode->crtc_vsync_start +
1346 le16_to_cpu(dtd_timings->usVSyncWidth);
1349 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1350 if (misc & ATOM_VSYNC_POLARITY)
1351 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1352 if (misc & ATOM_HSYNC_POLARITY)
1353 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1354 if (misc & ATOM_COMPOSITESYNC)
1355 mode->flags |= DRM_MODE_FLAG_CSYNC;
1356 if (misc & ATOM_INTERLACE)
1357 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1358 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1359 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1361 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1368 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1370 struct radeon_mode_info *mode_info = &rdev->mode_info;
1371 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1372 uint16_t data_offset;
1374 struct _ATOM_ANALOG_TV_INFO *tv_info;
1375 enum radeon_tv_std tv_std = TV_STD_NTSC;
1377 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1378 &frev, &crev, &data_offset)) {
1380 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1381 (mode_info->atom_context->bios + data_offset);
1383 switch (tv_info->ucTV_BootUpDefaultStandard) {
1385 tv_std = TV_STD_NTSC;
1386 DRM_INFO("Default TV standard: NTSC\n");
1389 tv_std = TV_STD_NTSC_J;
1390 DRM_INFO("Default TV standard: NTSC-J\n");
1393 tv_std = TV_STD_PAL;
1394 DRM_INFO("Default TV standard: PAL\n");
1397 tv_std = TV_STD_PAL_M;
1398 DRM_INFO("Default TV standard: PAL-M\n");
1401 tv_std = TV_STD_PAL_N;
1402 DRM_INFO("Default TV standard: PAL-N\n");
1405 tv_std = TV_STD_PAL_CN;
1406 DRM_INFO("Default TV standard: PAL-CN\n");
1409 tv_std = TV_STD_PAL_60;
1410 DRM_INFO("Default TV standard: PAL-60\n");
1413 tv_std = TV_STD_SECAM;
1414 DRM_INFO("Default TV standard: SECAM\n");
1417 tv_std = TV_STD_NTSC;
1418 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1425 struct radeon_encoder_tv_dac *
1426 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1428 struct drm_device *dev = encoder->base.dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_mode_info *mode_info = &rdev->mode_info;
1431 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1432 uint16_t data_offset;
1433 struct _COMPASSIONATE_DATA *dac_info;
1436 struct radeon_encoder_tv_dac *tv_dac = NULL;
1438 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1439 &frev, &crev, &data_offset)) {
1441 dac_info = (struct _COMPASSIONATE_DATA *)
1442 (mode_info->atom_context->bios + data_offset);
1444 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1449 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1450 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1451 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1453 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1454 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1455 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1457 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1458 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1459 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1461 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1466 static const char *thermal_controller_names[] = {
1477 static const char *pp_lib_thermal_controller_names[] = {
1490 "adt7473 with internal",
1495 struct _ATOM_POWERPLAY_INFO info;
1496 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1497 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1498 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1501 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1503 struct radeon_mode_info *mode_info = &rdev->mode_info;
1504 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1507 u32 misc, misc2 = 0, sclk, mclk;
1508 union power_info *power_info;
1509 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1510 struct _ATOM_PPLIB_STATE *power_state;
1511 int num_modes = 0, i, j;
1512 int state_index = 0, mode_index = 0;
1513 struct radeon_i2c_bus_rec i2c_bus;
1515 rdev->pm.default_power_state_index = -1;
1517 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1518 &frev, &crev, &data_offset)) {
1519 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1521 /* add the i2c bus for thermal/fan chip */
1522 if (power_info->info.ucOverdriveThermalController > 0) {
1523 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1524 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1525 power_info->info.ucOverdriveControllerAddress >> 1);
1526 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1527 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1528 if (rdev->pm.i2c_bus) {
1529 struct i2c_board_info info = { };
1530 const char *name = thermal_controller_names[power_info->info.
1531 ucOverdriveThermalController];
1532 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1533 strlcpy(info.type, name, sizeof(info.type));
1534 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1537 num_modes = power_info->info.ucNumOfPowerModeEntries;
1538 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1539 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1540 /* last mode is usually default, array is low to high */
1541 for (i = 0; i < num_modes; i++) {
1542 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1545 rdev->pm.power_state[state_index].num_clock_modes = 1;
1546 rdev->pm.power_state[state_index].clock_info[0].mclk =
1547 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1548 rdev->pm.power_state[state_index].clock_info[0].sclk =
1549 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1550 /* skip invalid modes */
1551 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1552 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1554 rdev->pm.power_state[state_index].pcie_lanes =
1555 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1556 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1557 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1558 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1559 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1561 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1562 radeon_lookup_gpio(rdev,
1563 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1564 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1565 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1568 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1570 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1571 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1573 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1574 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1576 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1577 rdev->pm.power_state[state_index].misc = misc;
1578 /* order matters! */
1579 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1580 rdev->pm.power_state[state_index].type =
1581 POWER_STATE_TYPE_POWERSAVE;
1582 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1583 rdev->pm.power_state[state_index].type =
1584 POWER_STATE_TYPE_BATTERY;
1585 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1586 rdev->pm.power_state[state_index].type =
1587 POWER_STATE_TYPE_BATTERY;
1588 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1589 rdev->pm.power_state[state_index].type =
1590 POWER_STATE_TYPE_BALANCED;
1591 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1592 rdev->pm.power_state[state_index].type =
1593 POWER_STATE_TYPE_PERFORMANCE;
1594 rdev->pm.power_state[state_index].flags &=
1595 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1597 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1598 rdev->pm.power_state[state_index].type =
1599 POWER_STATE_TYPE_DEFAULT;
1600 rdev->pm.default_power_state_index = state_index;
1601 rdev->pm.power_state[state_index].default_clock_mode =
1602 &rdev->pm.power_state[state_index].clock_info[0];
1603 rdev->pm.power_state[state_index].flags &=
1604 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1605 } else if (state_index == 0) {
1606 rdev->pm.power_state[state_index].clock_info[0].flags |=
1607 RADEON_PM_MODE_NO_DISPLAY;
1612 rdev->pm.power_state[state_index].num_clock_modes = 1;
1613 rdev->pm.power_state[state_index].clock_info[0].mclk =
1614 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1615 rdev->pm.power_state[state_index].clock_info[0].sclk =
1616 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1617 /* skip invalid modes */
1618 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1619 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1621 rdev->pm.power_state[state_index].pcie_lanes =
1622 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1623 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1624 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1625 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1626 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1627 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1629 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1630 radeon_lookup_gpio(rdev,
1631 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1632 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1633 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1636 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1638 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1639 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1641 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1642 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1644 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1645 rdev->pm.power_state[state_index].misc = misc;
1646 rdev->pm.power_state[state_index].misc2 = misc2;
1647 /* order matters! */
1648 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1649 rdev->pm.power_state[state_index].type =
1650 POWER_STATE_TYPE_POWERSAVE;
1651 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1652 rdev->pm.power_state[state_index].type =
1653 POWER_STATE_TYPE_BATTERY;
1654 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1655 rdev->pm.power_state[state_index].type =
1656 POWER_STATE_TYPE_BATTERY;
1657 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1658 rdev->pm.power_state[state_index].type =
1659 POWER_STATE_TYPE_BALANCED;
1660 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1661 rdev->pm.power_state[state_index].type =
1662 POWER_STATE_TYPE_PERFORMANCE;
1663 rdev->pm.power_state[state_index].flags &=
1664 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1666 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1667 rdev->pm.power_state[state_index].type =
1668 POWER_STATE_TYPE_BALANCED;
1669 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1670 rdev->pm.power_state[state_index].flags &=
1671 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1672 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1673 rdev->pm.power_state[state_index].type =
1674 POWER_STATE_TYPE_DEFAULT;
1675 rdev->pm.default_power_state_index = state_index;
1676 rdev->pm.power_state[state_index].default_clock_mode =
1677 &rdev->pm.power_state[state_index].clock_info[0];
1678 rdev->pm.power_state[state_index].flags &=
1679 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1680 } else if (state_index == 0) {
1681 rdev->pm.power_state[state_index].clock_info[0].flags |=
1682 RADEON_PM_MODE_NO_DISPLAY;
1687 rdev->pm.power_state[state_index].num_clock_modes = 1;
1688 rdev->pm.power_state[state_index].clock_info[0].mclk =
1689 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1690 rdev->pm.power_state[state_index].clock_info[0].sclk =
1691 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1692 /* skip invalid modes */
1693 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1694 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1696 rdev->pm.power_state[state_index].pcie_lanes =
1697 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1698 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1699 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1700 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1701 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1702 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1704 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1705 radeon_lookup_gpio(rdev,
1706 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1707 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1708 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1711 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1713 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1714 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1716 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1717 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1718 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1719 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1721 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1722 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1725 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1726 rdev->pm.power_state[state_index].misc = misc;
1727 rdev->pm.power_state[state_index].misc2 = misc2;
1728 /* order matters! */
1729 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1730 rdev->pm.power_state[state_index].type =
1731 POWER_STATE_TYPE_POWERSAVE;
1732 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1733 rdev->pm.power_state[state_index].type =
1734 POWER_STATE_TYPE_BATTERY;
1735 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1736 rdev->pm.power_state[state_index].type =
1737 POWER_STATE_TYPE_BATTERY;
1738 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1739 rdev->pm.power_state[state_index].type =
1740 POWER_STATE_TYPE_BALANCED;
1741 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1742 rdev->pm.power_state[state_index].type =
1743 POWER_STATE_TYPE_PERFORMANCE;
1744 rdev->pm.power_state[state_index].flags &=
1745 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1747 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1748 rdev->pm.power_state[state_index].type =
1749 POWER_STATE_TYPE_BALANCED;
1750 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1751 rdev->pm.power_state[state_index].type =
1752 POWER_STATE_TYPE_DEFAULT;
1753 rdev->pm.default_power_state_index = state_index;
1754 rdev->pm.power_state[state_index].default_clock_mode =
1755 &rdev->pm.power_state[state_index].clock_info[0];
1756 } else if (state_index == 0) {
1757 rdev->pm.power_state[state_index].clock_info[0].flags |=
1758 RADEON_PM_MODE_NO_DISPLAY;
1764 /* last mode is usually default */
1765 if (rdev->pm.default_power_state_index == -1) {
1766 rdev->pm.power_state[state_index - 1].type =
1767 POWER_STATE_TYPE_DEFAULT;
1768 rdev->pm.default_power_state_index = state_index - 1;
1769 rdev->pm.power_state[state_index - 1].default_clock_mode =
1770 &rdev->pm.power_state[state_index - 1].clock_info[0];
1771 rdev->pm.power_state[state_index].flags &=
1772 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1773 rdev->pm.power_state[state_index].misc = 0;
1774 rdev->pm.power_state[state_index].misc2 = 0;
1777 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1778 uint8_t fw_frev, fw_crev;
1779 uint16_t fw_data_offset, vddc = 0;
1780 union firmware_info *firmware_info;
1781 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1783 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1784 &fw_frev, &fw_crev, &fw_data_offset)) {
1786 (union firmware_info *)(mode_info->atom_context->bios +
1788 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1791 /* add the i2c bus for thermal/fan chip */
1792 /* no support for internal controller yet */
1793 if (controller->ucType > 0) {
1794 if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1795 (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
1796 (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
1797 DRM_INFO("Internal thermal controller %s fan control\n",
1798 (controller->ucFanParameters &
1799 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1800 } else if ((controller->ucType ==
1801 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1802 (controller->ucType ==
1803 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1804 DRM_INFO("Special thermal controller config\n");
1806 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1807 pp_lib_thermal_controller_names[controller->ucType],
1808 controller->ucI2cAddress >> 1,
1809 (controller->ucFanParameters &
1810 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1811 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1812 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1813 if (rdev->pm.i2c_bus) {
1814 struct i2c_board_info info = { };
1815 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1816 info.addr = controller->ucI2cAddress >> 1;
1817 strlcpy(info.type, name, sizeof(info.type));
1818 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1823 /* first mode is usually default, followed by low to high */
1824 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1826 power_state = (struct _ATOM_PPLIB_STATE *)
1827 (mode_info->atom_context->bios +
1829 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1830 i * power_info->info_4.ucStateEntrySize);
1831 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1832 (mode_info->atom_context->bios +
1834 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1835 (power_state->ucNonClockStateIndex *
1836 power_info->info_4.ucNonClockSize));
1837 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1838 if (rdev->flags & RADEON_IS_IGP) {
1839 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1840 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1841 (mode_info->atom_context->bios +
1843 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1844 (power_state->ucClockStateIndices[j] *
1845 power_info->info_4.ucClockInfoSize));
1846 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1847 sclk |= clock_info->ucLowEngineClockHigh << 16;
1848 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1849 /* skip invalid modes */
1850 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1852 /* voltage works differently on IGPs */
1854 } else if (ASIC_IS_DCE4(rdev)) {
1855 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1856 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1857 (mode_info->atom_context->bios +
1859 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1860 (power_state->ucClockStateIndices[j] *
1861 power_info->info_4.ucClockInfoSize));
1862 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1863 sclk |= clock_info->ucEngineClockHigh << 16;
1864 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1865 mclk |= clock_info->ucMemoryClockHigh << 16;
1866 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1867 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1868 /* skip invalid modes */
1869 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1870 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1872 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1874 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1879 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1880 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1881 (mode_info->atom_context->bios +
1883 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1884 (power_state->ucClockStateIndices[j] *
1885 power_info->info_4.ucClockInfoSize));
1886 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1887 sclk |= clock_info->ucEngineClockHigh << 16;
1888 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1889 mclk |= clock_info->ucMemoryClockHigh << 16;
1890 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1891 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1892 /* skip invalid modes */
1893 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1894 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1896 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1898 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1903 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1905 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1906 misc2 = le16_to_cpu(non_clock_info->usClassification);
1907 rdev->pm.power_state[state_index].misc = misc;
1908 rdev->pm.power_state[state_index].misc2 = misc2;
1909 rdev->pm.power_state[state_index].pcie_lanes =
1910 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1911 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1912 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1913 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1914 rdev->pm.power_state[state_index].type =
1915 POWER_STATE_TYPE_BATTERY;
1917 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1918 rdev->pm.power_state[state_index].type =
1919 POWER_STATE_TYPE_BALANCED;
1921 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1922 rdev->pm.power_state[state_index].type =
1923 POWER_STATE_TYPE_PERFORMANCE;
1926 rdev->pm.power_state[state_index].flags = 0;
1927 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1928 rdev->pm.power_state[state_index].flags |=
1929 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1930 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1931 rdev->pm.power_state[state_index].type =
1932 POWER_STATE_TYPE_DEFAULT;
1933 rdev->pm.default_power_state_index = state_index;
1934 rdev->pm.power_state[state_index].default_clock_mode =
1935 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1936 /* patch the table values with the default slck/mclk from firmware info */
1937 for (j = 0; j < mode_index; j++) {
1938 rdev->pm.power_state[state_index].clock_info[j].mclk =
1939 rdev->clock.default_mclk;
1940 rdev->pm.power_state[state_index].clock_info[j].sclk =
1941 rdev->clock.default_sclk;
1943 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
1950 /* if multiple clock modes, mark the lowest as no display */
1951 for (i = 0; i < state_index; i++) {
1952 if (rdev->pm.power_state[i].num_clock_modes > 1)
1953 rdev->pm.power_state[i].clock_info[0].flags |=
1954 RADEON_PM_MODE_NO_DISPLAY;
1956 /* first mode is usually default */
1957 if (rdev->pm.default_power_state_index == -1) {
1958 rdev->pm.power_state[0].type =
1959 POWER_STATE_TYPE_DEFAULT;
1960 rdev->pm.default_power_state_index = 0;
1961 rdev->pm.power_state[0].default_clock_mode =
1962 &rdev->pm.power_state[0].clock_info[0];
1966 /* add the default mode */
1967 rdev->pm.power_state[state_index].type =
1968 POWER_STATE_TYPE_DEFAULT;
1969 rdev->pm.power_state[state_index].num_clock_modes = 1;
1970 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1971 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1972 rdev->pm.power_state[state_index].default_clock_mode =
1973 &rdev->pm.power_state[state_index].clock_info[0];
1974 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1975 rdev->pm.power_state[state_index].pcie_lanes = 16;
1976 rdev->pm.default_power_state_index = state_index;
1977 rdev->pm.power_state[state_index].flags = 0;
1981 rdev->pm.num_power_states = state_index;
1983 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1984 rdev->pm.current_clock_mode_index = 0;
1985 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1988 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1990 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1991 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1993 args.ucEnable = enable;
1995 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1998 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2000 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2001 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2003 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2004 return args.ulReturnEngineClock;
2007 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2009 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2010 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2013 return args.ulReturnMemoryClock;
2016 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2019 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2020 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2022 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2027 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2030 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2031 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2033 if (rdev->flags & RADEON_IS_IGP)
2036 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2038 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2042 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2043 struct _SET_VOLTAGE_PARAMETERS v1;
2044 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2047 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2049 union set_voltage args;
2050 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2051 u8 frev, crev, volt_index = level;
2053 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2058 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2059 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2060 args.v1.ucVoltageIndex = volt_index;
2063 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2064 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2065 args.v2.usVoltageLevel = cpu_to_le16(level);
2068 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2077 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2079 struct radeon_device *rdev = dev->dev_private;
2080 uint32_t bios_2_scratch, bios_6_scratch;
2082 if (rdev->family >= CHIP_R600) {
2083 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2084 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2086 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2087 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2090 /* let the bios control the backlight */
2091 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2093 /* tell the bios not to handle mode switching */
2094 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2096 if (rdev->family >= CHIP_R600) {
2097 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2098 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2100 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2101 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2106 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2108 uint32_t scratch_reg;
2111 if (rdev->family >= CHIP_R600)
2112 scratch_reg = R600_BIOS_0_SCRATCH;
2114 scratch_reg = RADEON_BIOS_0_SCRATCH;
2116 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2117 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2120 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2122 uint32_t scratch_reg;
2125 if (rdev->family >= CHIP_R600)
2126 scratch_reg = R600_BIOS_0_SCRATCH;
2128 scratch_reg = RADEON_BIOS_0_SCRATCH;
2130 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2131 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2134 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2136 struct drm_device *dev = encoder->dev;
2137 struct radeon_device *rdev = dev->dev_private;
2138 uint32_t bios_6_scratch;
2140 if (rdev->family >= CHIP_R600)
2141 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2143 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2146 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2148 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2150 if (rdev->family >= CHIP_R600)
2151 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2153 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2156 /* at some point we may want to break this out into individual functions */
2158 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2159 struct drm_encoder *encoder,
2162 struct drm_device *dev = connector->dev;
2163 struct radeon_device *rdev = dev->dev_private;
2164 struct radeon_connector *radeon_connector =
2165 to_radeon_connector(connector);
2166 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2167 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2169 if (rdev->family >= CHIP_R600) {
2170 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2171 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2172 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2174 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2175 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2176 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2179 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2180 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2182 DRM_DEBUG("TV1 connected\n");
2183 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2184 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2186 DRM_DEBUG("TV1 disconnected\n");
2187 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2188 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2189 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2192 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2193 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2195 DRM_DEBUG("CV connected\n");
2196 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2197 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2199 DRM_DEBUG("CV disconnected\n");
2200 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2201 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2202 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2205 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2206 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2208 DRM_DEBUG("LCD1 connected\n");
2209 bios_0_scratch |= ATOM_S0_LCD1;
2210 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2211 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2213 DRM_DEBUG("LCD1 disconnected\n");
2214 bios_0_scratch &= ~ATOM_S0_LCD1;
2215 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2216 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2219 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2220 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2222 DRM_DEBUG("CRT1 connected\n");
2223 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2224 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2225 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2227 DRM_DEBUG("CRT1 disconnected\n");
2228 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2229 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2230 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2233 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2234 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2236 DRM_DEBUG("CRT2 connected\n");
2237 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2238 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2239 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2241 DRM_DEBUG("CRT2 disconnected\n");
2242 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2243 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2244 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2247 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2248 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2250 DRM_DEBUG("DFP1 connected\n");
2251 bios_0_scratch |= ATOM_S0_DFP1;
2252 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2253 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2255 DRM_DEBUG("DFP1 disconnected\n");
2256 bios_0_scratch &= ~ATOM_S0_DFP1;
2257 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2258 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2261 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2262 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2264 DRM_DEBUG("DFP2 connected\n");
2265 bios_0_scratch |= ATOM_S0_DFP2;
2266 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2267 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2269 DRM_DEBUG("DFP2 disconnected\n");
2270 bios_0_scratch &= ~ATOM_S0_DFP2;
2271 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2272 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2275 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2276 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2278 DRM_DEBUG("DFP3 connected\n");
2279 bios_0_scratch |= ATOM_S0_DFP3;
2280 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2281 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2283 DRM_DEBUG("DFP3 disconnected\n");
2284 bios_0_scratch &= ~ATOM_S0_DFP3;
2285 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2286 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2289 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2290 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2292 DRM_DEBUG("DFP4 connected\n");
2293 bios_0_scratch |= ATOM_S0_DFP4;
2294 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2295 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2297 DRM_DEBUG("DFP4 disconnected\n");
2298 bios_0_scratch &= ~ATOM_S0_DFP4;
2299 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2300 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2303 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2304 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2306 DRM_DEBUG("DFP5 connected\n");
2307 bios_0_scratch |= ATOM_S0_DFP5;
2308 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2309 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2311 DRM_DEBUG("DFP5 disconnected\n");
2312 bios_0_scratch &= ~ATOM_S0_DFP5;
2313 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2314 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2318 if (rdev->family >= CHIP_R600) {
2319 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2320 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2321 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2323 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2324 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2325 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2330 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2332 struct drm_device *dev = encoder->dev;
2333 struct radeon_device *rdev = dev->dev_private;
2334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2335 uint32_t bios_3_scratch;
2337 if (rdev->family >= CHIP_R600)
2338 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2340 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2342 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2343 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2344 bios_3_scratch |= (crtc << 18);
2346 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2347 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2348 bios_3_scratch |= (crtc << 24);
2350 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2351 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2352 bios_3_scratch |= (crtc << 16);
2354 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2355 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2356 bios_3_scratch |= (crtc << 20);
2358 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2359 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2360 bios_3_scratch |= (crtc << 17);
2362 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2363 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2364 bios_3_scratch |= (crtc << 19);
2366 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2367 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2368 bios_3_scratch |= (crtc << 23);
2370 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2371 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2372 bios_3_scratch |= (crtc << 25);
2375 if (rdev->family >= CHIP_R600)
2376 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2378 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2382 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2384 struct drm_device *dev = encoder->dev;
2385 struct radeon_device *rdev = dev->dev_private;
2386 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2387 uint32_t bios_2_scratch;
2389 if (rdev->family >= CHIP_R600)
2390 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2392 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2394 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2396 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2398 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2400 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2402 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2404 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2406 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2408 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2410 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2412 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2414 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2416 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2418 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2420 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2422 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2424 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2426 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2428 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2430 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2432 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2434 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2436 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2438 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2440 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2442 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2444 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2446 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2448 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2450 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2452 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2455 if (rdev->family >= CHIP_R600)
2456 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2458 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);