2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
66 ATOM_GPIO_I2C_ASSIGMENT *gpio,
69 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
70 if ((rdev->family == CHIP_R420) ||
71 (rdev->family == CHIP_R423) ||
72 (rdev->family == CHIP_RV410)) {
73 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
74 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
76 gpio->ucClkMaskShift = 0x19;
77 gpio->ucDataMaskShift = 0x18;
81 /* some evergreen boards have bad data for this entry */
82 if (ASIC_IS_DCE4(rdev)) {
84 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
85 (gpio->sucI2cId.ucAccess == 0)) {
86 gpio->sucI2cId.ucAccess = 0x97;
87 gpio->ucDataMaskShift = 8;
88 gpio->ucDataEnShift = 8;
89 gpio->ucDataY_Shift = 8;
90 gpio->ucDataA_Shift = 8;
94 /* some DCE3 boards have bad data for this entry */
95 if (ASIC_IS_DCE3(rdev)) {
97 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
98 (gpio->sucI2cId.ucAccess == 0x94))
99 gpio->sucI2cId.ucAccess = 0x14;
103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
105 struct radeon_i2c_bus_rec i2c;
107 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
109 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
110 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
111 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
112 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
113 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
114 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
115 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
116 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
117 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
118 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
119 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
120 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
121 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
122 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
123 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
124 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
127 i2c.hw_capable = true;
129 i2c.hw_capable = false;
131 if (gpio->sucI2cId.ucAccess == 0xa0)
136 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138 if (i2c.mask_clk_reg)
146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
149 struct atom_context *ctx = rdev->mode_info.atom_context;
150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
151 struct radeon_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
154 uint16_t data_offset, size;
157 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
160 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
161 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
163 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
164 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
166 for (i = 0; i < num_indices; i++) {
167 gpio = &i2c_info->asGPIO_Info[i];
169 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
171 if (gpio->sucI2cId.ucAccess == id) {
172 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
181 void radeon_atombios_i2c_init(struct radeon_device *rdev)
183 struct atom_context *ctx = rdev->mode_info.atom_context;
184 ATOM_GPIO_I2C_ASSIGMENT *gpio;
185 struct radeon_i2c_bus_rec i2c;
186 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
187 struct _ATOM_GPIO_I2C_INFO *i2c_info;
188 uint16_t data_offset, size;
192 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
193 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
195 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
196 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
198 for (i = 0; i < num_indices; i++) {
199 gpio = &i2c_info->asGPIO_Info[i];
201 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
203 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
206 sprintf(stmp, "0x%x", i2c.i2c_id);
207 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
213 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
216 struct atom_context *ctx = rdev->mode_info.atom_context;
217 struct radeon_gpio_rec gpio;
218 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
219 struct _ATOM_GPIO_PIN_LUT *gpio_info;
220 ATOM_GPIO_PIN_ASSIGNMENT *pin;
221 u16 data_offset, size;
224 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
227 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
228 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
230 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
231 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
233 for (i = 0; i < num_indices; i++) {
234 pin = &gpio_info->asGPIO_Pin[i];
235 if (id == pin->ucGPIO_ID) {
236 gpio.id = pin->ucGPIO_ID;
237 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
238 gpio.mask = (1 << pin->ucGpioPinBitShift);
248 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
249 struct radeon_gpio_rec *gpio)
251 struct radeon_hpd hpd;
254 memset(&hpd, 0, sizeof(struct radeon_hpd));
256 if (ASIC_IS_DCE4(rdev))
257 reg = EVERGREEN_DC_GPIO_HPD_A;
259 reg = AVIVO_DC_GPIO_HPD_A;
262 if (gpio->reg == reg) {
265 hpd.hpd = RADEON_HPD_1;
268 hpd.hpd = RADEON_HPD_2;
271 hpd.hpd = RADEON_HPD_3;
274 hpd.hpd = RADEON_HPD_4;
277 hpd.hpd = RADEON_HPD_5;
280 hpd.hpd = RADEON_HPD_6;
283 hpd.hpd = RADEON_HPD_NONE;
287 hpd.hpd = RADEON_HPD_NONE;
291 static bool radeon_atom_apply_quirks(struct drm_device *dev,
292 uint32_t supported_device,
294 struct radeon_i2c_bus_rec *i2c_bus,
296 struct radeon_hpd *hpd)
299 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
300 if ((dev->pdev->device == 0x791e) &&
301 (dev->pdev->subsystem_vendor == 0x1043) &&
302 (dev->pdev->subsystem_device == 0x826d)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
308 /* Asrock RS600 board lists the DVI port as HDMI */
309 if ((dev->pdev->device == 0x7941) &&
310 (dev->pdev->subsystem_vendor == 0x1849) &&
311 (dev->pdev->subsystem_device == 0x7941)) {
312 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 *connector_type = DRM_MODE_CONNECTOR_DVID;
317 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
318 if ((dev->pdev->device == 0x796e) &&
319 (dev->pdev->subsystem_vendor == 0x1462) &&
320 (dev->pdev->subsystem_device == 0x7302)) {
321 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x147b) &&
329 (dev->pdev->subsystem_device == 0x2412)) {
330 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
334 /* Falcon NW laptop lists vga ddc line for LVDS */
335 if ((dev->pdev->device == 0x5653) &&
336 (dev->pdev->subsystem_vendor == 0x1462) &&
337 (dev->pdev->subsystem_device == 0x0291)) {
338 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
339 i2c_bus->valid = false;
344 /* HIS X1300 is DVI+VGA, not DVI+DVI */
345 if ((dev->pdev->device == 0x7146) &&
346 (dev->pdev->subsystem_vendor == 0x17af) &&
347 (dev->pdev->subsystem_device == 0x2058)) {
348 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
353 if ((dev->pdev->device == 0x7142) &&
354 (dev->pdev->subsystem_vendor == 0x1458) &&
355 (dev->pdev->subsystem_device == 0x2134)) {
356 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
362 if ((dev->pdev->device == 0x71C5) &&
363 (dev->pdev->subsystem_vendor == 0x106b) &&
364 (dev->pdev->subsystem_device == 0x0080)) {
365 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
366 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
368 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
372 /* mac rv630, rv730, others */
373 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
374 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
375 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
376 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
379 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
380 if ((dev->pdev->device == 0x9598) &&
381 (dev->pdev->subsystem_vendor == 0x1043) &&
382 (dev->pdev->subsystem_device == 0x01da)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
388 /* ASUS HD 3600 board lists the DVI port as HDMI */
389 if ((dev->pdev->device == 0x9598) &&
390 (dev->pdev->subsystem_vendor == 0x1043) &&
391 (dev->pdev->subsystem_device == 0x01e4)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
397 /* ASUS HD 3450 board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x95C5) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01e2)) {
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 *connector_type = DRM_MODE_CONNECTOR_DVII;
406 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
407 * HDMI + VGA reporting as HDMI
409 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
410 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
411 *connector_type = DRM_MODE_CONNECTOR_VGA;
416 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
417 * on the laptop and a DVI port on the docking station and
418 * both share the same encoder, hpd pin, and ddc line.
419 * So while the bios table is technically correct,
420 * we drop the DVI port here since xrandr has no concept of
421 * encoders and will try and drive both connectors
422 * with different crtcs which isn't possible on the hardware
423 * side and leaves no crtcs for LVDS or VGA.
425 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
426 (dev->pdev->subsystem_vendor == 0x1025) &&
427 (dev->pdev->subsystem_device == 0x013c)) {
428 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
429 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
430 /* actually it's a DVI-D port not DVI-I */
431 *connector_type = DRM_MODE_CONNECTOR_DVID;
436 /* XFX Pine Group device rv730 reports no VGA DDC lines
437 * even though they are wired up to record 0x93
439 if ((dev->pdev->device == 0x9498) &&
440 (dev->pdev->subsystem_vendor == 0x1682) &&
441 (dev->pdev->subsystem_device == 0x2452)) {
442 struct radeon_device *rdev = dev->dev_private;
443 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
448 const int supported_devices_connector_convert[] = {
449 DRM_MODE_CONNECTOR_Unknown,
450 DRM_MODE_CONNECTOR_VGA,
451 DRM_MODE_CONNECTOR_DVII,
452 DRM_MODE_CONNECTOR_DVID,
453 DRM_MODE_CONNECTOR_DVIA,
454 DRM_MODE_CONNECTOR_SVIDEO,
455 DRM_MODE_CONNECTOR_Composite,
456 DRM_MODE_CONNECTOR_LVDS,
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_HDMIA,
460 DRM_MODE_CONNECTOR_HDMIB,
461 DRM_MODE_CONNECTOR_Unknown,
462 DRM_MODE_CONNECTOR_Unknown,
463 DRM_MODE_CONNECTOR_9PinDIN,
464 DRM_MODE_CONNECTOR_DisplayPort
467 const uint16_t supported_devices_connector_object_id_convert[] = {
468 CONNECTOR_OBJECT_ID_NONE,
469 CONNECTOR_OBJECT_ID_VGA,
470 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
471 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
472 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
473 CONNECTOR_OBJECT_ID_COMPOSITE,
474 CONNECTOR_OBJECT_ID_SVIDEO,
475 CONNECTOR_OBJECT_ID_LVDS,
476 CONNECTOR_OBJECT_ID_9PIN_DIN,
477 CONNECTOR_OBJECT_ID_9PIN_DIN,
478 CONNECTOR_OBJECT_ID_DISPLAYPORT,
479 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
480 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
481 CONNECTOR_OBJECT_ID_SVIDEO
484 const int object_connector_convert[] = {
485 DRM_MODE_CONNECTOR_Unknown,
486 DRM_MODE_CONNECTOR_DVII,
487 DRM_MODE_CONNECTOR_DVII,
488 DRM_MODE_CONNECTOR_DVID,
489 DRM_MODE_CONNECTOR_DVID,
490 DRM_MODE_CONNECTOR_VGA,
491 DRM_MODE_CONNECTOR_Composite,
492 DRM_MODE_CONNECTOR_SVIDEO,
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_Unknown,
495 DRM_MODE_CONNECTOR_9PinDIN,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_HDMIA,
498 DRM_MODE_CONNECTOR_HDMIB,
499 DRM_MODE_CONNECTOR_LVDS,
500 DRM_MODE_CONNECTOR_9PinDIN,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DisplayPort,
505 DRM_MODE_CONNECTOR_eDP,
506 DRM_MODE_CONNECTOR_Unknown
509 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
511 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_mode_info *mode_info = &rdev->mode_info;
513 struct atom_context *ctx = mode_info->atom_context;
514 int index = GetIndexIntoMasterTable(DATA, Object_Header);
515 u16 size, data_offset;
517 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
518 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
519 ATOM_OBJECT_TABLE *router_obj;
520 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
521 ATOM_OBJECT_HEADER *obj_header;
522 int i, j, k, path_size, device_support;
524 u16 igp_lane_info, conn_id, connector_object_id;
525 struct radeon_i2c_bus_rec ddc_bus;
526 struct radeon_router router;
527 struct radeon_gpio_rec gpio;
528 struct radeon_hpd hpd;
530 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
536 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
537 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
538 (ctx->bios + data_offset +
539 le16_to_cpu(obj_header->usDisplayPathTableOffset));
540 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
541 (ctx->bios + data_offset +
542 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
543 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
544 (ctx->bios + data_offset +
545 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
546 router_obj = (ATOM_OBJECT_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usRouterObjectTableOffset));
549 device_support = le16_to_cpu(obj_header->usDeviceSupport);
552 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
553 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
554 ATOM_DISPLAY_OBJECT_PATH *path;
556 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
557 path_size += le16_to_cpu(path->usSize);
559 if (device_support & le16_to_cpu(path->usDeviceTag)) {
560 uint8_t con_obj_id, con_obj_num, con_obj_type;
563 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
566 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
569 (le16_to_cpu(path->usConnObjectId) &
570 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
572 /* TODO CV support */
573 if (le16_to_cpu(path->usDeviceTag) ==
574 ATOM_DEVICE_CV_SUPPORT)
578 if ((rdev->flags & RADEON_IS_IGP) &&
580 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
581 uint16_t igp_offset = 0;
582 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
585 GetIndexIntoMasterTable(DATA,
586 IntegratedSystemInfo);
588 if (atom_parse_data_header(ctx, index, &size, &frev,
589 &crev, &igp_offset)) {
593 (ATOM_INTEGRATED_SYSTEM_INFO_V2
594 *) (ctx->bios + igp_offset);
597 uint32_t slot_config, ct;
599 if (con_obj_num == 1)
608 ct = (slot_config >> 16) & 0xff;
610 object_connector_convert
612 connector_object_id = ct;
614 slot_config & 0xffff;
622 object_connector_convert[con_obj_id];
623 connector_object_id = con_obj_id;
628 object_connector_convert[con_obj_id];
629 connector_object_id = con_obj_id;
632 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
635 router.ddc_valid = false;
636 router.cd_valid = false;
637 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
638 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
641 (le16_to_cpu(path->usGraphicObjIds[j]) &
642 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
644 (le16_to_cpu(path->usGraphicObjIds[j]) &
645 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
647 (le16_to_cpu(path->usGraphicObjIds[j]) &
648 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
650 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
651 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
652 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
653 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
654 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
655 (ctx->bios + data_offset +
656 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
657 ATOM_ENCODER_CAP_RECORD *cap_record;
660 while (record->ucRecordSize > 0 &&
661 record->ucRecordType > 0 &&
662 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
663 switch (record->ucRecordType) {
664 case ATOM_ENCODER_CAP_RECORD_TYPE:
665 cap_record =(ATOM_ENCODER_CAP_RECORD *)
667 caps = le16_to_cpu(cap_record->usEncoderCap);
670 record = (ATOM_COMMON_RECORD_HEADER *)
671 ((char *)record + record->ucRecordSize);
673 radeon_add_atom_encoder(dev,
681 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
682 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
683 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
684 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
685 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
686 (ctx->bios + data_offset +
687 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
688 ATOM_I2C_RECORD *i2c_record;
689 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
690 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
691 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
692 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
693 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
694 (ctx->bios + data_offset +
695 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
698 router.router_id = router_obj_id;
699 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
701 if (le16_to_cpu(path->usConnObjectId) ==
702 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
706 while (record->ucRecordSize > 0 &&
707 record->ucRecordType > 0 &&
708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
709 switch (record->ucRecordType) {
710 case ATOM_I2C_RECORD_TYPE:
715 (ATOM_I2C_ID_CONFIG_ACCESS *)
716 &i2c_record->sucI2cId;
718 radeon_lookup_i2c_gpio(rdev,
721 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
726 router.ddc_valid = true;
727 router.ddc_mux_type = ddc_path->ucMuxType;
728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
734 router.cd_valid = true;
735 router.cd_mux_type = cd_path->ucMuxType;
736 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
737 router.cd_mux_state = cd_path->ucMuxState[enum_id];
740 record = (ATOM_COMMON_RECORD_HEADER *)
741 ((char *)record + record->ucRecordSize);
748 /* look up gpio for ddc, hpd */
749 ddc_bus.valid = false;
750 hpd.hpd = RADEON_HPD_NONE;
751 if ((le16_to_cpu(path->usDeviceTag) &
752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
754 if (le16_to_cpu(path->usConnObjectId) ==
755 le16_to_cpu(con_obj->asObjects[j].
757 ATOM_COMMON_RECORD_HEADER
759 (ATOM_COMMON_RECORD_HEADER
761 (ctx->bios + data_offset +
762 le16_to_cpu(con_obj->
765 ATOM_I2C_RECORD *i2c_record;
766 ATOM_HPD_INT_RECORD *hpd_record;
767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
769 while (record->ucRecordSize > 0 &&
770 record->ucRecordType > 0 &&
771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
772 switch (record->ucRecordType) {
773 case ATOM_I2C_RECORD_TYPE:
778 (ATOM_I2C_ID_CONFIG_ACCESS *)
779 &i2c_record->sucI2cId;
780 ddc_bus = radeon_lookup_i2c_gpio(rdev,
784 case ATOM_HPD_INT_RECORD_TYPE:
786 (ATOM_HPD_INT_RECORD *)
788 gpio = radeon_lookup_gpio(rdev,
789 hpd_record->ucHPDIntGPIOID);
790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
791 hpd.plugged_state = hpd_record->ucPlugged_PinState;
795 (ATOM_COMMON_RECORD_HEADER
806 /* needed for aux chan transactions */
807 ddc_bus.hpd = hpd.hpd;
809 conn_id = le16_to_cpu(path->usConnObjectId);
811 if (!radeon_atom_apply_quirks
812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
813 &ddc_bus, &conn_id, &hpd))
816 radeon_add_atom_connector(dev,
820 connector_type, &ddc_bus,
829 radeon_link_encoder_connector(dev);
834 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
838 struct radeon_device *rdev = dev->dev_private;
840 if (rdev->flags & RADEON_IS_IGP) {
841 return supported_devices_connector_object_id_convert
843 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
844 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
845 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
846 struct radeon_mode_info *mode_info = &rdev->mode_info;
847 struct atom_context *ctx = mode_info->atom_context;
848 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
849 uint16_t size, data_offset;
851 ATOM_XTMDS_INFO *xtmds;
853 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
854 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
856 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
857 if (connector_type == DRM_MODE_CONNECTOR_DVII)
858 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
860 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
862 if (connector_type == DRM_MODE_CONNECTOR_DVII)
863 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
865 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
868 return supported_devices_connector_object_id_convert
871 return supported_devices_connector_object_id_convert
876 struct bios_connector {
881 struct radeon_i2c_bus_rec ddc_bus;
882 struct radeon_hpd hpd;
885 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
889 struct radeon_device *rdev = dev->dev_private;
890 struct radeon_mode_info *mode_info = &rdev->mode_info;
891 struct atom_context *ctx = mode_info->atom_context;
892 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
893 uint16_t size, data_offset;
895 uint16_t device_support;
897 union atom_supported_devices *supported_devices;
898 int i, j, max_device;
899 struct bios_connector *bios_connectors;
900 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
901 struct radeon_router router;
903 router.ddc_valid = false;
904 router.cd_valid = false;
906 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
907 if (!bios_connectors)
910 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
912 kfree(bios_connectors);
917 (union atom_supported_devices *)(ctx->bios + data_offset);
919 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
922 max_device = ATOM_MAX_SUPPORTED_DEVICE;
924 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
926 for (i = 0; i < max_device; i++) {
927 ATOM_CONNECTOR_INFO_I2C ci =
928 supported_devices->info.asConnInfo[i];
930 bios_connectors[i].valid = false;
932 if (!(device_support & (1 << i))) {
936 if (i == ATOM_DEVICE_CV_INDEX) {
937 DRM_DEBUG_KMS("Skipping Component Video\n");
941 bios_connectors[i].connector_type =
942 supported_devices_connector_convert[ci.sucConnectorInfo.
946 if (bios_connectors[i].connector_type ==
947 DRM_MODE_CONNECTOR_Unknown)
950 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
952 bios_connectors[i].line_mux =
953 ci.sucI2cId.ucAccess;
955 /* give tv unique connector ids */
956 if (i == ATOM_DEVICE_TV1_INDEX) {
957 bios_connectors[i].ddc_bus.valid = false;
958 bios_connectors[i].line_mux = 50;
959 } else if (i == ATOM_DEVICE_TV2_INDEX) {
960 bios_connectors[i].ddc_bus.valid = false;
961 bios_connectors[i].line_mux = 51;
962 } else if (i == ATOM_DEVICE_CV_INDEX) {
963 bios_connectors[i].ddc_bus.valid = false;
964 bios_connectors[i].line_mux = 52;
966 bios_connectors[i].ddc_bus =
967 radeon_lookup_i2c_gpio(rdev,
968 bios_connectors[i].line_mux);
970 if ((crev > 1) && (frev > 1)) {
971 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
974 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
977 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
980 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
984 if (i == ATOM_DEVICE_DFP1_INDEX)
985 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
986 else if (i == ATOM_DEVICE_DFP2_INDEX)
987 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
989 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
992 /* Always set the connector type to VGA for CRT1/CRT2. if they are
993 * shared with a DVI port, we'll pick up the DVI connector when we
994 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
996 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
997 bios_connectors[i].connector_type =
998 DRM_MODE_CONNECTOR_VGA;
1000 if (!radeon_atom_apply_quirks
1001 (dev, (1 << i), &bios_connectors[i].connector_type,
1002 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1003 &bios_connectors[i].hpd))
1006 bios_connectors[i].valid = true;
1007 bios_connectors[i].devices = (1 << i);
1009 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1010 radeon_add_atom_encoder(dev,
1011 radeon_get_encoder_enum(dev,
1017 radeon_add_legacy_encoder(dev,
1018 radeon_get_encoder_enum(dev,
1024 /* combine shared connectors */
1025 for (i = 0; i < max_device; i++) {
1026 if (bios_connectors[i].valid) {
1027 for (j = 0; j < max_device; j++) {
1028 if (bios_connectors[j].valid && (i != j)) {
1029 if (bios_connectors[i].line_mux ==
1030 bios_connectors[j].line_mux) {
1031 /* make sure not to combine LVDS */
1032 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033 bios_connectors[i].line_mux = 53;
1034 bios_connectors[i].ddc_bus.valid = false;
1037 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1038 bios_connectors[j].line_mux = 53;
1039 bios_connectors[j].ddc_bus.valid = false;
1042 /* combine analog and digital for DVI-I */
1043 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1045 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1046 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1047 bios_connectors[i].devices |=
1048 bios_connectors[j].devices;
1049 bios_connectors[i].connector_type =
1050 DRM_MODE_CONNECTOR_DVII;
1051 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1052 bios_connectors[i].hpd =
1053 bios_connectors[j].hpd;
1054 bios_connectors[j].valid = false;
1062 /* add the connectors */
1063 for (i = 0; i < max_device; i++) {
1064 if (bios_connectors[i].valid) {
1065 uint16_t connector_object_id =
1066 atombios_get_connector_object_id(dev,
1067 bios_connectors[i].connector_type,
1068 bios_connectors[i].devices);
1069 radeon_add_atom_connector(dev,
1070 bios_connectors[i].line_mux,
1071 bios_connectors[i].devices,
1074 &bios_connectors[i].ddc_bus,
1076 connector_object_id,
1077 &bios_connectors[i].hpd,
1082 radeon_link_encoder_connector(dev);
1084 kfree(bios_connectors);
1088 union firmware_info {
1089 ATOM_FIRMWARE_INFO info;
1090 ATOM_FIRMWARE_INFO_V1_2 info_12;
1091 ATOM_FIRMWARE_INFO_V1_3 info_13;
1092 ATOM_FIRMWARE_INFO_V1_4 info_14;
1093 ATOM_FIRMWARE_INFO_V2_1 info_21;
1094 ATOM_FIRMWARE_INFO_V2_2 info_22;
1097 bool radeon_atom_get_clock_info(struct drm_device *dev)
1099 struct radeon_device *rdev = dev->dev_private;
1100 struct radeon_mode_info *mode_info = &rdev->mode_info;
1101 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1102 union firmware_info *firmware_info;
1104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1106 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1107 struct radeon_pll *spll = &rdev->clock.spll;
1108 struct radeon_pll *mpll = &rdev->clock.mpll;
1109 uint16_t data_offset;
1111 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1112 &frev, &crev, &data_offset)) {
1114 (union firmware_info *)(mode_info->atom_context->bios +
1117 p1pll->reference_freq =
1118 le16_to_cpu(firmware_info->info.usReferenceClock);
1119 p1pll->reference_div = 0;
1122 p1pll->pll_out_min =
1123 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1125 p1pll->pll_out_min =
1126 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1127 p1pll->pll_out_max =
1128 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1131 p1pll->lcd_pll_out_min =
1132 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1133 if (p1pll->lcd_pll_out_min == 0)
1134 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1135 p1pll->lcd_pll_out_max =
1136 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1137 if (p1pll->lcd_pll_out_max == 0)
1138 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1140 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1141 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1144 if (p1pll->pll_out_min == 0) {
1145 if (ASIC_IS_AVIVO(rdev))
1146 p1pll->pll_out_min = 64800;
1148 p1pll->pll_out_min = 20000;
1152 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1154 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1159 if (ASIC_IS_DCE4(rdev))
1160 spll->reference_freq =
1161 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1163 spll->reference_freq =
1164 le16_to_cpu(firmware_info->info.usReferenceClock);
1165 spll->reference_div = 0;
1168 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1170 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1173 if (spll->pll_out_min == 0) {
1174 if (ASIC_IS_AVIVO(rdev))
1175 spll->pll_out_min = 64800;
1177 spll->pll_out_min = 20000;
1181 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1183 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1186 if (ASIC_IS_DCE4(rdev))
1187 mpll->reference_freq =
1188 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1190 mpll->reference_freq =
1191 le16_to_cpu(firmware_info->info.usReferenceClock);
1192 mpll->reference_div = 0;
1195 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1197 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1200 if (mpll->pll_out_min == 0) {
1201 if (ASIC_IS_AVIVO(rdev))
1202 mpll->pll_out_min = 64800;
1204 mpll->pll_out_min = 20000;
1208 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1210 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1212 rdev->clock.default_sclk =
1213 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1214 rdev->clock.default_mclk =
1215 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1217 if (ASIC_IS_DCE4(rdev)) {
1218 rdev->clock.default_dispclk =
1219 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1220 if (rdev->clock.default_dispclk == 0) {
1221 if (ASIC_IS_DCE5(rdev))
1222 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1224 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1226 rdev->clock.dp_extclk =
1227 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1231 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1232 if (rdev->clock.max_pixel_clock == 0)
1233 rdev->clock.max_pixel_clock = 40000;
1242 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1243 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1246 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1248 struct radeon_mode_info *mode_info = &rdev->mode_info;
1249 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1250 union igp_info *igp_info;
1254 /* sideport is AMD only */
1255 if (rdev->family == CHIP_RS600)
1258 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1259 &frev, &crev, &data_offset)) {
1260 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1264 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1268 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1272 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1279 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1280 struct radeon_encoder_int_tmds *tmds)
1282 struct drm_device *dev = encoder->base.dev;
1283 struct radeon_device *rdev = dev->dev_private;
1284 struct radeon_mode_info *mode_info = &rdev->mode_info;
1285 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1286 uint16_t data_offset;
1287 struct _ATOM_TMDS_INFO *tmds_info;
1292 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1293 &frev, &crev, &data_offset)) {
1295 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1298 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1299 for (i = 0; i < 4; i++) {
1300 tmds->tmds_pll[i].freq =
1301 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1302 tmds->tmds_pll[i].value =
1303 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1304 tmds->tmds_pll[i].value |=
1305 (tmds_info->asMiscInfo[i].
1306 ucPLL_VCO_Gain & 0x3f) << 6;
1307 tmds->tmds_pll[i].value |=
1308 (tmds_info->asMiscInfo[i].
1309 ucPLL_DutyCycle & 0xf) << 12;
1310 tmds->tmds_pll[i].value |=
1311 (tmds_info->asMiscInfo[i].
1312 ucPLL_VoltageSwing & 0xf) << 16;
1314 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1315 tmds->tmds_pll[i].freq,
1316 tmds->tmds_pll[i].value);
1318 if (maxfreq == tmds->tmds_pll[i].freq) {
1319 tmds->tmds_pll[i].freq = 0xffffffff;
1328 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1329 struct radeon_atom_ss *ss,
1332 struct radeon_mode_info *mode_info = &rdev->mode_info;
1333 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1334 uint16_t data_offset, size;
1335 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1339 memset(ss, 0, sizeof(struct radeon_atom_ss));
1340 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1341 &frev, &crev, &data_offset)) {
1343 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1345 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1346 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1348 for (i = 0; i < num_indices; i++) {
1349 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1351 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1352 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1353 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1354 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1355 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1356 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1364 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1365 struct radeon_atom_ss *ss,
1368 struct radeon_mode_info *mode_info = &rdev->mode_info;
1369 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1370 u16 data_offset, size;
1371 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1373 u16 percentage = 0, rate = 0;
1375 /* get any igp specific overrides */
1376 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1377 &frev, &crev, &data_offset)) {
1378 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1379 (mode_info->atom_context->bios + data_offset);
1381 case ASIC_INTERNAL_SS_ON_TMDS:
1382 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1383 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1385 case ASIC_INTERNAL_SS_ON_HDMI:
1386 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1387 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1389 case ASIC_INTERNAL_SS_ON_LVDS:
1390 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1391 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1395 ss->percentage = percentage;
1401 union asic_ss_info {
1402 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1403 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1404 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1407 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1408 struct radeon_atom_ss *ss,
1411 struct radeon_mode_info *mode_info = &rdev->mode_info;
1412 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1413 uint16_t data_offset, size;
1414 union asic_ss_info *ss_info;
1418 memset(ss, 0, sizeof(struct radeon_atom_ss));
1419 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1420 &frev, &crev, &data_offset)) {
1423 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1427 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1428 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1430 for (i = 0; i < num_indices; i++) {
1431 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1432 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1434 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1435 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1436 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1442 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1443 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1444 for (i = 0; i < num_indices; i++) {
1445 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1446 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1448 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1449 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1450 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1456 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1457 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1458 for (i = 0; i < num_indices; i++) {
1459 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1460 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1462 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1463 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1464 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1465 if (rdev->flags & RADEON_IS_IGP)
1466 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1472 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1481 struct _ATOM_LVDS_INFO info;
1482 struct _ATOM_LVDS_INFO_V12 info_12;
1485 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1489 struct drm_device *dev = encoder->base.dev;
1490 struct radeon_device *rdev = dev->dev_private;
1491 struct radeon_mode_info *mode_info = &rdev->mode_info;
1492 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1493 uint16_t data_offset, misc;
1494 union lvds_info *lvds_info;
1496 struct radeon_encoder_atom_dig *lvds = NULL;
1497 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1499 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1500 &frev, &crev, &data_offset)) {
1502 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1504 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1509 lvds->native_mode.clock =
1510 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1511 lvds->native_mode.hdisplay =
1512 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1513 lvds->native_mode.vdisplay =
1514 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1515 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1516 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1517 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1518 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1519 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1520 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1521 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1522 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1523 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1524 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1525 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1526 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1527 lvds->panel_pwr_delay =
1528 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1529 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1531 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1532 if (misc & ATOM_VSYNC_POLARITY)
1533 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1534 if (misc & ATOM_HSYNC_POLARITY)
1535 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1536 if (misc & ATOM_COMPOSITESYNC)
1537 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1538 if (misc & ATOM_INTERLACE)
1539 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1540 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1541 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1543 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1544 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1546 /* set crtc values */
1547 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1549 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1551 encoder->native_mode = lvds->native_mode;
1553 if (encoder_enum == 2)
1556 lvds->linkb = false;
1558 /* parse the lcd record table */
1559 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1560 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1561 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1562 bool bad_record = false;
1565 if ((frev == 1) && (crev < 2))
1567 record = (u8 *)(mode_info->atom_context->bios +
1568 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1571 record = (u8 *)(mode_info->atom_context->bios +
1573 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1574 while (*record != ATOM_RECORD_END_TYPE) {
1576 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1577 record += sizeof(ATOM_PATCH_RECORD_MODE);
1579 case LCD_RTS_RECORD_TYPE:
1580 record += sizeof(ATOM_LCD_RTS_RECORD);
1582 case LCD_CAP_RECORD_TYPE:
1583 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1585 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1586 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1587 if (fake_edid_record->ucFakeEDIDLength) {
1590 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1591 edid = kmalloc(edid_size, GFP_KERNEL);
1593 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1594 fake_edid_record->ucFakeEDIDLength);
1596 if (drm_edid_is_valid(edid)) {
1597 rdev->mode_info.bios_hardcoded_edid = edid;
1598 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1603 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1605 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1606 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1607 lvds->native_mode.width_mm = panel_res_record->usHSize;
1608 lvds->native_mode.height_mm = panel_res_record->usVSize;
1609 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1612 DRM_ERROR("Bad LCD record %d\n", *record);
1624 struct radeon_encoder_primary_dac *
1625 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1627 struct drm_device *dev = encoder->base.dev;
1628 struct radeon_device *rdev = dev->dev_private;
1629 struct radeon_mode_info *mode_info = &rdev->mode_info;
1630 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1631 uint16_t data_offset;
1632 struct _COMPASSIONATE_DATA *dac_info;
1635 struct radeon_encoder_primary_dac *p_dac = NULL;
1637 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1638 &frev, &crev, &data_offset)) {
1639 dac_info = (struct _COMPASSIONATE_DATA *)
1640 (mode_info->atom_context->bios + data_offset);
1642 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1647 bg = dac_info->ucDAC1_BG_Adjustment;
1648 dac = dac_info->ucDAC1_DAC_Adjustment;
1649 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1655 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1656 struct drm_display_mode *mode)
1658 struct radeon_mode_info *mode_info = &rdev->mode_info;
1659 ATOM_ANALOG_TV_INFO *tv_info;
1660 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1661 ATOM_DTD_FORMAT *dtd_timings;
1662 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1664 u16 data_offset, misc;
1666 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1667 &frev, &crev, &data_offset))
1672 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1673 if (index >= MAX_SUPPORTED_TV_TIMING)
1676 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1677 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1678 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1679 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1680 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1682 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1683 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1684 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1685 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1686 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1689 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1690 if (misc & ATOM_VSYNC_POLARITY)
1691 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1692 if (misc & ATOM_HSYNC_POLARITY)
1693 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1694 if (misc & ATOM_COMPOSITESYNC)
1695 mode->flags |= DRM_MODE_FLAG_CSYNC;
1696 if (misc & ATOM_INTERLACE)
1697 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1698 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1699 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1701 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1704 /* PAL timings appear to have wrong values for totals */
1705 mode->crtc_htotal -= 1;
1706 mode->crtc_vtotal -= 1;
1710 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1711 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1714 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1715 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1716 le16_to_cpu(dtd_timings->usHBlanking_Time);
1717 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1718 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1719 le16_to_cpu(dtd_timings->usHSyncOffset);
1720 mode->crtc_hsync_end = mode->crtc_hsync_start +
1721 le16_to_cpu(dtd_timings->usHSyncWidth);
1723 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1724 le16_to_cpu(dtd_timings->usVBlanking_Time);
1725 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1726 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1727 le16_to_cpu(dtd_timings->usVSyncOffset);
1728 mode->crtc_vsync_end = mode->crtc_vsync_start +
1729 le16_to_cpu(dtd_timings->usVSyncWidth);
1732 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1733 if (misc & ATOM_VSYNC_POLARITY)
1734 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1735 if (misc & ATOM_HSYNC_POLARITY)
1736 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1737 if (misc & ATOM_COMPOSITESYNC)
1738 mode->flags |= DRM_MODE_FLAG_CSYNC;
1739 if (misc & ATOM_INTERLACE)
1740 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1741 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1742 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1744 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1751 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1753 struct radeon_mode_info *mode_info = &rdev->mode_info;
1754 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1755 uint16_t data_offset;
1757 struct _ATOM_ANALOG_TV_INFO *tv_info;
1758 enum radeon_tv_std tv_std = TV_STD_NTSC;
1760 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1761 &frev, &crev, &data_offset)) {
1763 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1764 (mode_info->atom_context->bios + data_offset);
1766 switch (tv_info->ucTV_BootUpDefaultStandard) {
1768 tv_std = TV_STD_NTSC;
1769 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1772 tv_std = TV_STD_NTSC_J;
1773 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1776 tv_std = TV_STD_PAL;
1777 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1780 tv_std = TV_STD_PAL_M;
1781 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1784 tv_std = TV_STD_PAL_N;
1785 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1788 tv_std = TV_STD_PAL_CN;
1789 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1792 tv_std = TV_STD_PAL_60;
1793 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1796 tv_std = TV_STD_SECAM;
1797 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1800 tv_std = TV_STD_NTSC;
1801 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1808 struct radeon_encoder_tv_dac *
1809 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1811 struct drm_device *dev = encoder->base.dev;
1812 struct radeon_device *rdev = dev->dev_private;
1813 struct radeon_mode_info *mode_info = &rdev->mode_info;
1814 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1815 uint16_t data_offset;
1816 struct _COMPASSIONATE_DATA *dac_info;
1819 struct radeon_encoder_tv_dac *tv_dac = NULL;
1821 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1822 &frev, &crev, &data_offset)) {
1824 dac_info = (struct _COMPASSIONATE_DATA *)
1825 (mode_info->atom_context->bios + data_offset);
1827 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1832 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1833 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1834 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1836 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1837 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1838 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1840 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1841 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1842 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1844 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1849 static const char *thermal_controller_names[] = {
1860 static const char *pp_lib_thermal_controller_names[] = {
1880 struct _ATOM_POWERPLAY_INFO info;
1881 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1882 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1883 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1884 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1885 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1888 union pplib_clock_info {
1889 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1890 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1891 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1892 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1895 union pplib_power_state {
1896 struct _ATOM_PPLIB_STATE v1;
1897 struct _ATOM_PPLIB_STATE_V2 v2;
1900 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1902 u32 misc, u32 misc2)
1904 rdev->pm.power_state[state_index].misc = misc;
1905 rdev->pm.power_state[state_index].misc2 = misc2;
1906 /* order matters! */
1907 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1908 rdev->pm.power_state[state_index].type =
1909 POWER_STATE_TYPE_POWERSAVE;
1910 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1911 rdev->pm.power_state[state_index].type =
1912 POWER_STATE_TYPE_BATTERY;
1913 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1914 rdev->pm.power_state[state_index].type =
1915 POWER_STATE_TYPE_BATTERY;
1916 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1917 rdev->pm.power_state[state_index].type =
1918 POWER_STATE_TYPE_BALANCED;
1919 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1920 rdev->pm.power_state[state_index].type =
1921 POWER_STATE_TYPE_PERFORMANCE;
1922 rdev->pm.power_state[state_index].flags &=
1923 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1925 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_BALANCED;
1928 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1929 rdev->pm.power_state[state_index].type =
1930 POWER_STATE_TYPE_DEFAULT;
1931 rdev->pm.default_power_state_index = state_index;
1932 rdev->pm.power_state[state_index].default_clock_mode =
1933 &rdev->pm.power_state[state_index].clock_info[0];
1934 } else if (state_index == 0) {
1935 rdev->pm.power_state[state_index].clock_info[0].flags |=
1936 RADEON_PM_MODE_NO_DISPLAY;
1940 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1942 struct radeon_mode_info *mode_info = &rdev->mode_info;
1943 u32 misc, misc2 = 0;
1944 int num_modes = 0, i;
1945 int state_index = 0;
1946 struct radeon_i2c_bus_rec i2c_bus;
1947 union power_info *power_info;
1948 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1952 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1953 &frev, &crev, &data_offset))
1955 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1957 /* add the i2c bus for thermal/fan chip */
1958 if (power_info->info.ucOverdriveThermalController > 0) {
1959 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1960 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1961 power_info->info.ucOverdriveControllerAddress >> 1);
1962 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1963 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1964 if (rdev->pm.i2c_bus) {
1965 struct i2c_board_info info = { };
1966 const char *name = thermal_controller_names[power_info->info.
1967 ucOverdriveThermalController];
1968 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1969 strlcpy(info.type, name, sizeof(info.type));
1970 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1973 num_modes = power_info->info.ucNumOfPowerModeEntries;
1974 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1975 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1976 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1977 if (!rdev->pm.power_state)
1979 /* last mode is usually default, array is low to high */
1980 for (i = 0; i < num_modes; i++) {
1981 rdev->pm.power_state[state_index].clock_info =
1982 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
1983 if (!rdev->pm.power_state[state_index].clock_info)
1985 rdev->pm.power_state[state_index].num_clock_modes = 1;
1986 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1989 rdev->pm.power_state[state_index].clock_info[0].mclk =
1990 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1991 rdev->pm.power_state[state_index].clock_info[0].sclk =
1992 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1993 /* skip invalid modes */
1994 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1995 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1997 rdev->pm.power_state[state_index].pcie_lanes =
1998 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1999 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2000 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2001 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2002 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2004 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2005 radeon_lookup_gpio(rdev,
2006 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2007 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2008 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2011 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2013 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2014 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2016 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2017 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2019 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2020 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2024 rdev->pm.power_state[state_index].clock_info[0].mclk =
2025 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2026 rdev->pm.power_state[state_index].clock_info[0].sclk =
2027 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2028 /* skip invalid modes */
2029 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2030 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2032 rdev->pm.power_state[state_index].pcie_lanes =
2033 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2034 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2035 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2036 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2037 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2038 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2041 radeon_lookup_gpio(rdev,
2042 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2043 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2044 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2047 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2049 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2050 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2053 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2055 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2056 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2060 rdev->pm.power_state[state_index].clock_info[0].mclk =
2061 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2062 rdev->pm.power_state[state_index].clock_info[0].sclk =
2063 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2064 /* skip invalid modes */
2065 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2066 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2068 rdev->pm.power_state[state_index].pcie_lanes =
2069 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2070 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2071 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2072 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2073 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2074 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2076 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2077 radeon_lookup_gpio(rdev,
2078 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2079 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2080 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2083 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2085 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2086 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2088 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2089 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2090 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2093 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2094 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2097 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2098 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2103 /* last mode is usually default */
2104 if (rdev->pm.default_power_state_index == -1) {
2105 rdev->pm.power_state[state_index - 1].type =
2106 POWER_STATE_TYPE_DEFAULT;
2107 rdev->pm.default_power_state_index = state_index - 1;
2108 rdev->pm.power_state[state_index - 1].default_clock_mode =
2109 &rdev->pm.power_state[state_index - 1].clock_info[0];
2110 rdev->pm.power_state[state_index].flags &=
2111 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2112 rdev->pm.power_state[state_index].misc = 0;
2113 rdev->pm.power_state[state_index].misc2 = 0;
2118 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2119 ATOM_PPLIB_THERMALCONTROLLER *controller)
2121 struct radeon_i2c_bus_rec i2c_bus;
2123 /* add the i2c bus for thermal/fan chip */
2124 if (controller->ucType > 0) {
2125 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2126 DRM_INFO("Internal thermal controller %s fan control\n",
2127 (controller->ucFanParameters &
2128 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2129 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2130 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2131 DRM_INFO("Internal thermal controller %s fan control\n",
2132 (controller->ucFanParameters &
2133 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2134 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2135 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2136 DRM_INFO("Internal thermal controller %s fan control\n",
2137 (controller->ucFanParameters &
2138 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2139 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2140 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2141 DRM_INFO("Internal thermal controller %s fan control\n",
2142 (controller->ucFanParameters &
2143 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2144 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2145 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2146 DRM_INFO("Internal thermal controller %s fan control\n",
2147 (controller->ucFanParameters &
2148 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2149 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2150 } else if ((controller->ucType ==
2151 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2152 (controller->ucType ==
2153 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2154 (controller->ucType ==
2155 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2156 DRM_INFO("Special thermal controller config\n");
2158 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2159 pp_lib_thermal_controller_names[controller->ucType],
2160 controller->ucI2cAddress >> 1,
2161 (controller->ucFanParameters &
2162 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2163 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2164 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2165 if (rdev->pm.i2c_bus) {
2166 struct i2c_board_info info = { };
2167 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2168 info.addr = controller->ucI2cAddress >> 1;
2169 strlcpy(info.type, name, sizeof(info.type));
2170 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2176 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2177 u16 *vddc, u16 *vddci)
2179 struct radeon_mode_info *mode_info = &rdev->mode_info;
2180 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2183 union firmware_info *firmware_info;
2188 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2189 &frev, &crev, &data_offset)) {
2191 (union firmware_info *)(mode_info->atom_context->bios +
2193 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2194 if ((frev == 2) && (crev >= 2))
2195 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2199 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2200 int state_index, int mode_index,
2201 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2204 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2205 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2208 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2210 rdev->pm.power_state[state_index].misc = misc;
2211 rdev->pm.power_state[state_index].misc2 = misc2;
2212 rdev->pm.power_state[state_index].pcie_lanes =
2213 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2214 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2215 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2216 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2217 rdev->pm.power_state[state_index].type =
2218 POWER_STATE_TYPE_BATTERY;
2220 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2221 rdev->pm.power_state[state_index].type =
2222 POWER_STATE_TYPE_BALANCED;
2224 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2225 rdev->pm.power_state[state_index].type =
2226 POWER_STATE_TYPE_PERFORMANCE;
2228 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2229 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2230 rdev->pm.power_state[state_index].type =
2231 POWER_STATE_TYPE_PERFORMANCE;
2234 rdev->pm.power_state[state_index].flags = 0;
2235 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2236 rdev->pm.power_state[state_index].flags |=
2237 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2238 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2239 rdev->pm.power_state[state_index].type =
2240 POWER_STATE_TYPE_DEFAULT;
2241 rdev->pm.default_power_state_index = state_index;
2242 rdev->pm.power_state[state_index].default_clock_mode =
2243 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2244 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2245 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2246 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2247 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2248 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2249 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2251 /* patch the table values with the default slck/mclk from firmware info */
2252 for (j = 0; j < mode_index; j++) {
2253 rdev->pm.power_state[state_index].clock_info[j].mclk =
2254 rdev->clock.default_mclk;
2255 rdev->pm.power_state[state_index].clock_info[j].sclk =
2256 rdev->clock.default_sclk;
2258 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2265 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2266 int state_index, int mode_index,
2267 union pplib_clock_info *clock_info)
2271 if (rdev->flags & RADEON_IS_IGP) {
2272 if (rdev->family >= CHIP_PALM) {
2273 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2274 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2275 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2277 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2278 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2279 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2281 } else if (ASIC_IS_DCE4(rdev)) {
2282 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2283 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2284 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2285 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2286 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2287 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2288 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2290 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2291 le16_to_cpu(clock_info->evergreen.usVDDC);
2292 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2293 le16_to_cpu(clock_info->evergreen.usVDDCI);
2295 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2296 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2297 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2298 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2299 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2300 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2301 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2303 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2304 le16_to_cpu(clock_info->r600.usVDDC);
2307 /* patch up vddc if necessary */
2308 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2311 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2312 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2315 if (rdev->flags & RADEON_IS_IGP) {
2316 /* skip invalid modes */
2317 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2320 /* skip invalid modes */
2321 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2322 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2328 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2330 struct radeon_mode_info *mode_info = &rdev->mode_info;
2331 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2332 union pplib_power_state *power_state;
2334 int state_index = 0, mode_index = 0;
2335 union pplib_clock_info *clock_info;
2337 union power_info *power_info;
2338 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2342 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2343 &frev, &crev, &data_offset))
2345 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2347 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2348 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2349 power_info->pplib.ucNumStates, GFP_KERNEL);
2350 if (!rdev->pm.power_state)
2352 /* first mode is usually default, followed by low to high */
2353 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2355 power_state = (union pplib_power_state *)
2356 (mode_info->atom_context->bios + data_offset +
2357 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2358 i * power_info->pplib.ucStateEntrySize);
2359 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2360 (mode_info->atom_context->bios + data_offset +
2361 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2362 (power_state->v1.ucNonClockStateIndex *
2363 power_info->pplib.ucNonClockSize));
2364 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2365 ((power_info->pplib.ucStateEntrySize - 1) ?
2366 (power_info->pplib.ucStateEntrySize - 1) : 1),
2368 if (!rdev->pm.power_state[i].clock_info)
2370 if (power_info->pplib.ucStateEntrySize - 1) {
2371 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2372 clock_info = (union pplib_clock_info *)
2373 (mode_info->atom_context->bios + data_offset +
2374 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2375 (power_state->v1.ucClockStateIndices[j] *
2376 power_info->pplib.ucClockInfoSize));
2377 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2378 state_index, mode_index,
2384 rdev->pm.power_state[state_index].clock_info[0].mclk =
2385 rdev->clock.default_mclk;
2386 rdev->pm.power_state[state_index].clock_info[0].sclk =
2387 rdev->clock.default_sclk;
2390 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2392 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2397 /* if multiple clock modes, mark the lowest as no display */
2398 for (i = 0; i < state_index; i++) {
2399 if (rdev->pm.power_state[i].num_clock_modes > 1)
2400 rdev->pm.power_state[i].clock_info[0].flags |=
2401 RADEON_PM_MODE_NO_DISPLAY;
2403 /* first mode is usually default */
2404 if (rdev->pm.default_power_state_index == -1) {
2405 rdev->pm.power_state[0].type =
2406 POWER_STATE_TYPE_DEFAULT;
2407 rdev->pm.default_power_state_index = 0;
2408 rdev->pm.power_state[0].default_clock_mode =
2409 &rdev->pm.power_state[0].clock_info[0];
2414 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2416 struct radeon_mode_info *mode_info = &rdev->mode_info;
2417 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2418 union pplib_power_state *power_state;
2419 int i, j, non_clock_array_index, clock_array_index;
2420 int state_index = 0, mode_index = 0;
2421 union pplib_clock_info *clock_info;
2422 struct StateArray *state_array;
2423 struct ClockInfoArray *clock_info_array;
2424 struct NonClockInfoArray *non_clock_info_array;
2426 union power_info *power_info;
2427 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2431 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2432 &frev, &crev, &data_offset))
2434 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2436 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2437 state_array = (struct StateArray *)
2438 (mode_info->atom_context->bios + data_offset +
2439 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2440 clock_info_array = (struct ClockInfoArray *)
2441 (mode_info->atom_context->bios + data_offset +
2442 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2443 non_clock_info_array = (struct NonClockInfoArray *)
2444 (mode_info->atom_context->bios + data_offset +
2445 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2446 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2447 state_array->ucNumEntries, GFP_KERNEL);
2448 if (!rdev->pm.power_state)
2450 for (i = 0; i < state_array->ucNumEntries; i++) {
2452 power_state = (union pplib_power_state *)&state_array->states[i];
2453 /* XXX this might be an inagua bug... */
2454 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2455 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2456 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2457 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2458 (power_state->v2.ucNumDPMLevels ?
2459 power_state->v2.ucNumDPMLevels : 1),
2461 if (!rdev->pm.power_state[i].clock_info)
2463 if (power_state->v2.ucNumDPMLevels) {
2464 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2465 clock_array_index = power_state->v2.clockInfoIndex[j];
2466 /* XXX this might be an inagua bug... */
2467 if (clock_array_index >= clock_info_array->ucNumEntries)
2469 clock_info = (union pplib_clock_info *)
2470 &clock_info_array->clockInfo[clock_array_index];
2471 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2472 state_index, mode_index,
2478 rdev->pm.power_state[state_index].clock_info[0].mclk =
2479 rdev->clock.default_mclk;
2480 rdev->pm.power_state[state_index].clock_info[0].sclk =
2481 rdev->clock.default_sclk;
2484 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2486 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2491 /* if multiple clock modes, mark the lowest as no display */
2492 for (i = 0; i < state_index; i++) {
2493 if (rdev->pm.power_state[i].num_clock_modes > 1)
2494 rdev->pm.power_state[i].clock_info[0].flags |=
2495 RADEON_PM_MODE_NO_DISPLAY;
2497 /* first mode is usually default */
2498 if (rdev->pm.default_power_state_index == -1) {
2499 rdev->pm.power_state[0].type =
2500 POWER_STATE_TYPE_DEFAULT;
2501 rdev->pm.default_power_state_index = 0;
2502 rdev->pm.power_state[0].default_clock_mode =
2503 &rdev->pm.power_state[0].clock_info[0];
2508 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2510 struct radeon_mode_info *mode_info = &rdev->mode_info;
2511 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2514 int state_index = 0;
2516 rdev->pm.default_power_state_index = -1;
2518 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2519 &frev, &crev, &data_offset)) {
2524 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2528 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2531 state_index = radeon_atombios_parse_power_table_6(rdev);
2537 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2538 if (rdev->pm.power_state) {
2539 rdev->pm.power_state[0].clock_info =
2540 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2541 if (rdev->pm.power_state[0].clock_info) {
2542 /* add the default mode */
2543 rdev->pm.power_state[state_index].type =
2544 POWER_STATE_TYPE_DEFAULT;
2545 rdev->pm.power_state[state_index].num_clock_modes = 1;
2546 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2547 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2548 rdev->pm.power_state[state_index].default_clock_mode =
2549 &rdev->pm.power_state[state_index].clock_info[0];
2550 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2551 rdev->pm.power_state[state_index].pcie_lanes = 16;
2552 rdev->pm.default_power_state_index = state_index;
2553 rdev->pm.power_state[state_index].flags = 0;
2559 rdev->pm.num_power_states = state_index;
2561 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2562 rdev->pm.current_clock_mode_index = 0;
2563 if (rdev->pm.default_power_state_index >= 0)
2564 rdev->pm.current_vddc =
2565 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2567 rdev->pm.current_vddc = 0;
2570 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2572 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2573 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2575 args.ucEnable = enable;
2577 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2580 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2582 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2583 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2585 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2586 return le32_to_cpu(args.ulReturnEngineClock);
2589 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2591 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2592 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2594 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2595 return le32_to_cpu(args.ulReturnMemoryClock);
2598 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2601 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2602 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2604 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2606 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2609 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2612 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2613 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2615 if (rdev->flags & RADEON_IS_IGP)
2618 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2624 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2625 struct _SET_VOLTAGE_PARAMETERS v1;
2626 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2629 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2631 union set_voltage args;
2632 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2633 u8 frev, crev, volt_index = voltage_level;
2635 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2638 /* 0xff01 is a flag rather then an actual voltage */
2639 if (voltage_level == 0xff01)
2644 args.v1.ucVoltageType = voltage_type;
2645 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2646 args.v1.ucVoltageIndex = volt_index;
2649 args.v2.ucVoltageType = voltage_type;
2650 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2651 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2654 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2658 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2661 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2664 union set_voltage args;
2665 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2668 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2675 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2676 args.v2.ucVoltageMode = 0;
2677 args.v2.usVoltageLevel = 0;
2679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2681 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2684 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2691 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2693 struct radeon_device *rdev = dev->dev_private;
2694 uint32_t bios_2_scratch, bios_6_scratch;
2696 if (rdev->family >= CHIP_R600) {
2697 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2698 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2700 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2701 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2704 /* let the bios control the backlight */
2705 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2707 /* tell the bios not to handle mode switching */
2708 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2710 if (rdev->family >= CHIP_R600) {
2711 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2712 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2714 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2715 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2720 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2722 uint32_t scratch_reg;
2725 if (rdev->family >= CHIP_R600)
2726 scratch_reg = R600_BIOS_0_SCRATCH;
2728 scratch_reg = RADEON_BIOS_0_SCRATCH;
2730 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2731 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2734 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2736 uint32_t scratch_reg;
2739 if (rdev->family >= CHIP_R600)
2740 scratch_reg = R600_BIOS_0_SCRATCH;
2742 scratch_reg = RADEON_BIOS_0_SCRATCH;
2744 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2745 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2748 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2750 struct drm_device *dev = encoder->dev;
2751 struct radeon_device *rdev = dev->dev_private;
2752 uint32_t bios_6_scratch;
2754 if (rdev->family >= CHIP_R600)
2755 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2757 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2760 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2761 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2763 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2764 bios_6_scratch |= ATOM_S6_ACC_MODE;
2767 if (rdev->family >= CHIP_R600)
2768 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2770 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2773 /* at some point we may want to break this out into individual functions */
2775 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2776 struct drm_encoder *encoder,
2779 struct drm_device *dev = connector->dev;
2780 struct radeon_device *rdev = dev->dev_private;
2781 struct radeon_connector *radeon_connector =
2782 to_radeon_connector(connector);
2783 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2784 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2786 if (rdev->family >= CHIP_R600) {
2787 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2788 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2789 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2791 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2792 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2793 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2796 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2797 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2799 DRM_DEBUG_KMS("TV1 connected\n");
2800 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2801 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2803 DRM_DEBUG_KMS("TV1 disconnected\n");
2804 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2805 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2806 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2809 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2810 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2812 DRM_DEBUG_KMS("CV connected\n");
2813 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2814 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2816 DRM_DEBUG_KMS("CV disconnected\n");
2817 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2818 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2819 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2822 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2823 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2825 DRM_DEBUG_KMS("LCD1 connected\n");
2826 bios_0_scratch |= ATOM_S0_LCD1;
2827 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2828 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2830 DRM_DEBUG_KMS("LCD1 disconnected\n");
2831 bios_0_scratch &= ~ATOM_S0_LCD1;
2832 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2833 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2836 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2837 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2839 DRM_DEBUG_KMS("CRT1 connected\n");
2840 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2841 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2842 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2844 DRM_DEBUG_KMS("CRT1 disconnected\n");
2845 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2846 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2847 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2850 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2851 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2853 DRM_DEBUG_KMS("CRT2 connected\n");
2854 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2855 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2856 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2858 DRM_DEBUG_KMS("CRT2 disconnected\n");
2859 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2860 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2861 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2864 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2865 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2867 DRM_DEBUG_KMS("DFP1 connected\n");
2868 bios_0_scratch |= ATOM_S0_DFP1;
2869 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2870 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2872 DRM_DEBUG_KMS("DFP1 disconnected\n");
2873 bios_0_scratch &= ~ATOM_S0_DFP1;
2874 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2875 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2878 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2879 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2881 DRM_DEBUG_KMS("DFP2 connected\n");
2882 bios_0_scratch |= ATOM_S0_DFP2;
2883 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2884 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2886 DRM_DEBUG_KMS("DFP2 disconnected\n");
2887 bios_0_scratch &= ~ATOM_S0_DFP2;
2888 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2889 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2892 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2893 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2895 DRM_DEBUG_KMS("DFP3 connected\n");
2896 bios_0_scratch |= ATOM_S0_DFP3;
2897 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2898 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2900 DRM_DEBUG_KMS("DFP3 disconnected\n");
2901 bios_0_scratch &= ~ATOM_S0_DFP3;
2902 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2903 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2906 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2907 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2909 DRM_DEBUG_KMS("DFP4 connected\n");
2910 bios_0_scratch |= ATOM_S0_DFP4;
2911 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2912 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2914 DRM_DEBUG_KMS("DFP4 disconnected\n");
2915 bios_0_scratch &= ~ATOM_S0_DFP4;
2916 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2917 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2920 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2921 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2923 DRM_DEBUG_KMS("DFP5 connected\n");
2924 bios_0_scratch |= ATOM_S0_DFP5;
2925 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2926 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2928 DRM_DEBUG_KMS("DFP5 disconnected\n");
2929 bios_0_scratch &= ~ATOM_S0_DFP5;
2930 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2931 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2934 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
2935 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
2937 DRM_DEBUG_KMS("DFP6 connected\n");
2938 bios_0_scratch |= ATOM_S0_DFP6;
2939 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
2940 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
2942 DRM_DEBUG_KMS("DFP6 disconnected\n");
2943 bios_0_scratch &= ~ATOM_S0_DFP6;
2944 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
2945 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
2949 if (rdev->family >= CHIP_R600) {
2950 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2951 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2952 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2954 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2955 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2956 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2961 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2963 struct drm_device *dev = encoder->dev;
2964 struct radeon_device *rdev = dev->dev_private;
2965 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2966 uint32_t bios_3_scratch;
2968 if (ASIC_IS_DCE4(rdev))
2971 if (rdev->family >= CHIP_R600)
2972 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2974 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2976 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2977 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2978 bios_3_scratch |= (crtc << 18);
2980 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2981 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2982 bios_3_scratch |= (crtc << 24);
2984 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2985 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2986 bios_3_scratch |= (crtc << 16);
2988 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2989 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2990 bios_3_scratch |= (crtc << 20);
2992 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2993 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2994 bios_3_scratch |= (crtc << 17);
2996 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2997 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2998 bios_3_scratch |= (crtc << 19);
3000 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3001 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3002 bios_3_scratch |= (crtc << 23);
3004 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3005 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3006 bios_3_scratch |= (crtc << 25);
3009 if (rdev->family >= CHIP_R600)
3010 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3012 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3016 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3018 struct drm_device *dev = encoder->dev;
3019 struct radeon_device *rdev = dev->dev_private;
3020 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3021 uint32_t bios_2_scratch;
3023 if (ASIC_IS_DCE4(rdev))
3026 if (rdev->family >= CHIP_R600)
3027 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3029 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3031 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3033 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3035 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3037 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3039 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3041 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3043 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3045 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3047 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3049 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3051 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3053 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3055 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3057 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3059 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3061 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3063 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3065 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3067 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3069 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3071 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3073 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3075 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3077 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3079 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3081 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3083 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3085 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3087 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3089 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3092 if (rdev->family >= CHIP_R600)
3093 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3095 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);