drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  66                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  67                                           u8 index)
  68 {
  69         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  70         if ((rdev->family == CHIP_R420) ||
  71             (rdev->family == CHIP_R423) ||
  72             (rdev->family == CHIP_RV410)) {
  73                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  74                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  75                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  76                         gpio->ucClkMaskShift = 0x19;
  77                         gpio->ucDataMaskShift = 0x18;
  78                 }
  79         }
  80
  81         /* some evergreen boards have bad data for this entry */
  82         if (ASIC_IS_DCE4(rdev)) {
  83                 if ((index == 7) &&
  84                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  85                     (gpio->sucI2cId.ucAccess == 0)) {
  86                         gpio->sucI2cId.ucAccess = 0x97;
  87                         gpio->ucDataMaskShift = 8;
  88                         gpio->ucDataEnShift = 8;
  89                         gpio->ucDataY_Shift = 8;
  90                         gpio->ucDataA_Shift = 8;
  91                 }
  92         }
  93
  94         /* some DCE3 boards have bad data for this entry */
  95         if (ASIC_IS_DCE3(rdev)) {
  96                 if ((index == 4) &&
  97                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  98                     (gpio->sucI2cId.ucAccess == 0x94))
  99                         gpio->sucI2cId.ucAccess = 0x14;
 100         }
 101 }
 102
 103 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 104 {
 105         struct radeon_i2c_bus_rec i2c;
 106
 107         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 108
 109         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 110         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 111         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 112         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 113         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 114         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 115         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 116         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 117         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 118         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 119         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 120         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 121         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 122         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 123         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 124         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 125
 126         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 127                 i2c.hw_capable = true;
 128         else
 129                 i2c.hw_capable = false;
 130
 131         if (gpio->sucI2cId.ucAccess == 0xa0)
 132                 i2c.mm_i2c = true;
 133         else
 134                 i2c.mm_i2c = false;
 135
 136         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 137
 138         if (i2c.mask_clk_reg)
 139                 i2c.valid = true;
 140         else
 141                 i2c.valid = false;
 142
 143         return i2c;
 144 }
 145
 146 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 147                                                                uint8_t id)
 148 {
 149         struct atom_context *ctx = rdev->mode_info.atom_context;
 150         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 151         struct radeon_i2c_bus_rec i2c;
 152         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 153         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 154         uint16_t data_offset, size;
 155         int i, num_indices;
 156
 157         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 158         i2c.valid = false;
 159
 160         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 161                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 162
 163                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 164                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 165
 166                 gpio = &i2c_info->asGPIO_Info[0];
 167                 for (i = 0; i < num_indices; i++) {
 168
 169                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 170
 171                         if (gpio->sucI2cId.ucAccess == id) {
 172                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 173                                 break;
 174                         }
 175                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 176                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 177                 }
 178         }
 179
 180         return i2c;
 181 }
 182
 183 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 184 {
 185         struct atom_context *ctx = rdev->mode_info.atom_context;
 186         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 187         struct radeon_i2c_bus_rec i2c;
 188         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 189         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 190         uint16_t data_offset, size;
 191         int i, num_indices;
 192         char stmp[32];
 193
 194         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 195                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 196
 197                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 198                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 199
 200                 gpio = &i2c_info->asGPIO_Info[0];
 201                 for (i = 0; i < num_indices; i++) {
 202                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 203
 204                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 205
 206                         if (i2c.valid) {
 207                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 208                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 209                         }
 210                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 211                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 212                 }
 213         }
 214 }
 215
 216 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 217                                                  u8 id)
 218 {
 219         struct atom_context *ctx = rdev->mode_info.atom_context;
 220         struct radeon_gpio_rec gpio;
 221         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 222         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 223         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 224         u16 data_offset, size;
 225         int i, num_indices;
 226
 227         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 228         gpio.valid = false;
 229
 230         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 231                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 232
 233                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 234                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 235
 236                 pin = gpio_info->asGPIO_Pin;
 237                 for (i = 0; i < num_indices; i++) {
 238                         if (id == pin->ucGPIO_ID) {
 239                                 gpio.id = pin->ucGPIO_ID;
 240                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 241                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 242                                 gpio.valid = true;
 243                                 break;
 244                         }
 245                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 246                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 247                 }
 248         }
 249
 250         return gpio;
 251 }
 252
 253 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 254                                                             struct radeon_gpio_rec *gpio)
 255 {
 256         struct radeon_hpd hpd;
 257         u32 reg;
 258
 259         memset(&hpd, 0, sizeof(struct radeon_hpd));
 260
 261         if (ASIC_IS_DCE6(rdev))
 262                 reg = SI_DC_GPIO_HPD_A;
 263         else if (ASIC_IS_DCE4(rdev))
 264                 reg = EVERGREEN_DC_GPIO_HPD_A;
 265         else
 266                 reg = AVIVO_DC_GPIO_HPD_A;
 267
 268         hpd.gpio = *gpio;
 269         if (gpio->reg == reg) {
 270                 switch(gpio->mask) {
 271                 case (1 << 0):
 272                         hpd.hpd = RADEON_HPD_1;
 273                         break;
 274                 case (1 << 8):
 275                         hpd.hpd = RADEON_HPD_2;
 276                         break;
 277                 case (1 << 16):
 278                         hpd.hpd = RADEON_HPD_3;
 279                         break;
 280                 case (1 << 24):
 281                         hpd.hpd = RADEON_HPD_4;
 282                         break;
 283                 case (1 << 26):
 284                         hpd.hpd = RADEON_HPD_5;
 285                         break;
 286                 case (1 << 28):
 287                         hpd.hpd = RADEON_HPD_6;
 288                         break;
 289                 default:
 290                         hpd.hpd = RADEON_HPD_NONE;
 291                         break;
 292                 }
 293         } else
 294                 hpd.hpd = RADEON_HPD_NONE;
 295         return hpd;
 296 }
 297
 298 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 299                                      uint32_t supported_device,
 300                                      int *connector_type,
 301                                      struct radeon_i2c_bus_rec *i2c_bus,
 302                                      uint16_t *line_mux,
 303                                      struct radeon_hpd *hpd)
 304 {
 305
 306         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 307         if ((dev->pdev->device == 0x791e) &&
 308             (dev->pdev->subsystem_vendor == 0x1043) &&
 309             (dev->pdev->subsystem_device == 0x826d)) {
 310                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 311                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 312                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 313         }
 314
 315         /* Asrock RS600 board lists the DVI port as HDMI */
 316         if ((dev->pdev->device == 0x7941) &&
 317             (dev->pdev->subsystem_vendor == 0x1849) &&
 318             (dev->pdev->subsystem_device == 0x7941)) {
 319                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 320                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 321                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 322         }
 323
 324         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 325         if ((dev->pdev->device == 0x796e) &&
 326             (dev->pdev->subsystem_vendor == 0x1462) &&
 327             (dev->pdev->subsystem_device == 0x7302)) {
 328                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 329                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 330                         return false;
 331         }
 332
 333         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 334         if ((dev->pdev->device == 0x7941) &&
 335             (dev->pdev->subsystem_vendor == 0x147b) &&
 336             (dev->pdev->subsystem_device == 0x2412)) {
 337                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 338                         return false;
 339         }
 340
 341         /* Falcon NW laptop lists vga ddc line for LVDS */
 342         if ((dev->pdev->device == 0x5653) &&
 343             (dev->pdev->subsystem_vendor == 0x1462) &&
 344             (dev->pdev->subsystem_device == 0x0291)) {
 345                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 346                         i2c_bus->valid = false;
 347                         *line_mux = 53;
 348                 }
 349         }
 350
 351         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 352         if ((dev->pdev->device == 0x7146) &&
 353             (dev->pdev->subsystem_vendor == 0x17af) &&
 354             (dev->pdev->subsystem_device == 0x2058)) {
 355                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 356                         return false;
 357         }
 358
 359         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 360         if ((dev->pdev->device == 0x7142) &&
 361             (dev->pdev->subsystem_vendor == 0x1458) &&
 362             (dev->pdev->subsystem_device == 0x2134)) {
 363                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 364                         return false;
 365         }
 366
 367
 368         /* Funky macbooks */
 369         if ((dev->pdev->device == 0x71C5) &&
 370             (dev->pdev->subsystem_vendor == 0x106b) &&
 371             (dev->pdev->subsystem_device == 0x0080)) {
 372                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 373                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 374                         return false;
 375                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 376                         *line_mux = 0x90;
 377         }
 378
 379         /* mac rv630, rv730, others */
 380         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 381             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 382                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 383                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 384         }
 385
 386         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 387         if ((dev->pdev->device == 0x9598) &&
 388             (dev->pdev->subsystem_vendor == 0x1043) &&
 389             (dev->pdev->subsystem_device == 0x01da)) {
 390                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 391                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 392                 }
 393         }
 394
 395         /* ASUS HD 3600 board lists the DVI port as HDMI */
 396         if ((dev->pdev->device == 0x9598) &&
 397             (dev->pdev->subsystem_vendor == 0x1043) &&
 398             (dev->pdev->subsystem_device == 0x01e4)) {
 399                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 400                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 401                 }
 402         }
 403
 404         /* ASUS HD 3450 board lists the DVI port as HDMI */
 405         if ((dev->pdev->device == 0x95C5) &&
 406             (dev->pdev->subsystem_vendor == 0x1043) &&
 407             (dev->pdev->subsystem_device == 0x01e2)) {
 408                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 409                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 410                 }
 411         }
 412
 413         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 414          * HDMI + VGA reporting as HDMI
 415          */
 416         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 417                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 418                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 419                         *line_mux = 0;
 420                 }
 421         }
 422
 423         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 424          * on the laptop and a DVI port on the docking station and
 425          * both share the same encoder, hpd pin, and ddc line.
 426          * So while the bios table is technically correct,
 427          * we drop the DVI port here since xrandr has no concept of
 428          * encoders and will try and drive both connectors
 429          * with different crtcs which isn't possible on the hardware
 430          * side and leaves no crtcs for LVDS or VGA.
 431          */
 432         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 433             (dev->pdev->subsystem_vendor == 0x1025) &&
 434             (dev->pdev->subsystem_device == 0x013c)) {
 435                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 436                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 437                         /* actually it's a DVI-D port not DVI-I */
 438                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 439                         return false;
 440                 }
 441         }
 442
 443         /* XFX Pine Group device rv730 reports no VGA DDC lines
 444          * even though they are wired up to record 0x93
 445          */
 446         if ((dev->pdev->device == 0x9498) &&
 447             (dev->pdev->subsystem_vendor == 0x1682) &&
 448             (dev->pdev->subsystem_device == 0x2452) &&
 449             (i2c_bus->valid == false) &&
 450             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 451                 struct radeon_device *rdev = dev->dev_private;
 452                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 453         }
 454
 455         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 456         if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
 457             (dev->pdev->subsystem_vendor == 0x1734) &&
 458             (dev->pdev->subsystem_device == 0x11bd)) {
 459                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 460                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 461                         *line_mux = 0x3103;
 462                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 463                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 464                 }
 465         }
 466
 467
 468         return true;
 469 }
 470
 471 const int supported_devices_connector_convert[] = {
 472         DRM_MODE_CONNECTOR_Unknown,
 473         DRM_MODE_CONNECTOR_VGA,
 474         DRM_MODE_CONNECTOR_DVII,
 475         DRM_MODE_CONNECTOR_DVID,
 476         DRM_MODE_CONNECTOR_DVIA,
 477         DRM_MODE_CONNECTOR_SVIDEO,
 478         DRM_MODE_CONNECTOR_Composite,
 479         DRM_MODE_CONNECTOR_LVDS,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_Unknown,
 482         DRM_MODE_CONNECTOR_HDMIA,
 483         DRM_MODE_CONNECTOR_HDMIB,
 484         DRM_MODE_CONNECTOR_Unknown,
 485         DRM_MODE_CONNECTOR_Unknown,
 486         DRM_MODE_CONNECTOR_9PinDIN,
 487         DRM_MODE_CONNECTOR_DisplayPort
 488 };
 489
 490 const uint16_t supported_devices_connector_object_id_convert[] = {
 491         CONNECTOR_OBJECT_ID_NONE,
 492         CONNECTOR_OBJECT_ID_VGA,
 493         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 494         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 495         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 496         CONNECTOR_OBJECT_ID_COMPOSITE,
 497         CONNECTOR_OBJECT_ID_SVIDEO,
 498         CONNECTOR_OBJECT_ID_LVDS,
 499         CONNECTOR_OBJECT_ID_9PIN_DIN,
 500         CONNECTOR_OBJECT_ID_9PIN_DIN,
 501         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 502         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 503         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 504         CONNECTOR_OBJECT_ID_SVIDEO
 505 };
 506
 507 const int object_connector_convert[] = {
 508         DRM_MODE_CONNECTOR_Unknown,
 509         DRM_MODE_CONNECTOR_DVII,
 510         DRM_MODE_CONNECTOR_DVII,
 511         DRM_MODE_CONNECTOR_DVID,
 512         DRM_MODE_CONNECTOR_DVID,
 513         DRM_MODE_CONNECTOR_VGA,
 514         DRM_MODE_CONNECTOR_Composite,
 515         DRM_MODE_CONNECTOR_SVIDEO,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_Unknown,
 518         DRM_MODE_CONNECTOR_9PinDIN,
 519         DRM_MODE_CONNECTOR_Unknown,
 520         DRM_MODE_CONNECTOR_HDMIA,
 521         DRM_MODE_CONNECTOR_HDMIB,
 522         DRM_MODE_CONNECTOR_LVDS,
 523         DRM_MODE_CONNECTOR_9PinDIN,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_Unknown,
 527         DRM_MODE_CONNECTOR_DisplayPort,
 528         DRM_MODE_CONNECTOR_eDP,
 529         DRM_MODE_CONNECTOR_Unknown
 530 };
 531
 532 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 533 {
 534         struct radeon_device *rdev = dev->dev_private;
 535         struct radeon_mode_info *mode_info = &rdev->mode_info;
 536         struct atom_context *ctx = mode_info->atom_context;
 537         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 538         u16 size, data_offset;
 539         u8 frev, crev;
 540         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 541         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 542         ATOM_OBJECT_TABLE *router_obj;
 543         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 544         ATOM_OBJECT_HEADER *obj_header;
 545         int i, j, k, path_size, device_support;
 546         int connector_type;
 547         u16 igp_lane_info, conn_id, connector_object_id;
 548         struct radeon_i2c_bus_rec ddc_bus;
 549         struct radeon_router router;
 550         struct radeon_gpio_rec gpio;
 551         struct radeon_hpd hpd;
 552
 553         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 554                 return false;
 555
 556         if (crev < 2)
 557                 return false;
 558
 559         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 560         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 561             (ctx->bios + data_offset +
 562              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 563         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 564             (ctx->bios + data_offset +
 565              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 566         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 567             (ctx->bios + data_offset +
 568              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 569         router_obj = (ATOM_OBJECT_TABLE *)
 570                 (ctx->bios + data_offset +
 571                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 572         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 573
 574         path_size = 0;
 575         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 576                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 577                 ATOM_DISPLAY_OBJECT_PATH *path;
 578                 addr += path_size;
 579                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 580                 path_size += le16_to_cpu(path->usSize);
 581
 582                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 583                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 584
 585                         con_obj_id =
 586                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 587                             >> OBJECT_ID_SHIFT;
 588                         con_obj_num =
 589                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 590                             >> ENUM_ID_SHIFT;
 591                         con_obj_type =
 592                             (le16_to_cpu(path->usConnObjectId) &
 593                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 594
 595                         /* TODO CV support */
 596                         if (le16_to_cpu(path->usDeviceTag) ==
 597                                 ATOM_DEVICE_CV_SUPPORT)
 598                                 continue;
 599
 600                         /* IGP chips */
 601                         if ((rdev->flags & RADEON_IS_IGP) &&
 602                             (con_obj_id ==
 603                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 604                                 uint16_t igp_offset = 0;
 605                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 606
 607                                 index =
 608                                     GetIndexIntoMasterTable(DATA,
 609                                                             IntegratedSystemInfo);
 610
 611                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 612                                                            &crev, &igp_offset)) {
 613
 614                                         if (crev >= 2) {
 615                                                 igp_obj =
 616                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 617                                                          *) (ctx->bios + igp_offset);
 618
 619                                                 if (igp_obj) {
 620                                                         uint32_t slot_config, ct;
 621
 622                                                         if (con_obj_num == 1)
 623                                                                 slot_config =
 624                                                                         igp_obj->
 625                                                                         ulDDISlot1Config;
 626                                                         else
 627                                                                 slot_config =
 628                                                                         igp_obj->
 629                                                                         ulDDISlot2Config;
 630
 631                                                         ct = (slot_config >> 16) & 0xff;
 632                                                         connector_type =
 633                                                                 object_connector_convert
 634                                                                 [ct];
 635                                                         connector_object_id = ct;
 636                                                         igp_lane_info =
 637                                                                 slot_config & 0xffff;
 638                                                 } else
 639                                                         continue;
 640                                         } else
 641                                                 continue;
 642                                 } else {
 643                                         igp_lane_info = 0;
 644                                         connector_type =
 645                                                 object_connector_convert[con_obj_id];
 646                                         connector_object_id = con_obj_id;
 647                                 }
 648                         } else {
 649                                 igp_lane_info = 0;
 650                                 connector_type =
 651                                     object_connector_convert[con_obj_id];
 652                                 connector_object_id = con_obj_id;
 653                         }
 654
 655                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 656                                 continue;
 657
 658                         router.ddc_valid = false;
 659                         router.cd_valid = false;
 660                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 661                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 662
 663                                 grph_obj_id =
 664                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 665                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 666                                 grph_obj_num =
 667                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 668                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 669                                 grph_obj_type =
 670                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 671                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 672
 673                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 674                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 675                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 676                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 677                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 678                                                                 (ctx->bios + data_offset +
 679                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 680                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 681                                                         u16 caps = 0;
 682
 683                                                         while (record->ucRecordSize > 0 &&
 684                                                                record->ucRecordType > 0 &&
 685                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 686                                                                 switch (record->ucRecordType) {
 687                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 688                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 689                                                                                 record;
 690                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 691                                                                         break;
 692                                                                 }
 693                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 694                                                                         ((char *)record + record->ucRecordSize);
 695                                                         }
 696                                                         radeon_add_atom_encoder(dev,
 697                                                                                 encoder_obj,
 698                                                                                 le16_to_cpu
 699                                                                                 (path->
 700                                                                                  usDeviceTag),
 701                                                                                 caps);
 702                                                 }
 703                                         }
 704                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 705                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 706                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 707                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 708                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 709                                                                 (ctx->bios + data_offset +
 710                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 711                                                         ATOM_I2C_RECORD *i2c_record;
 712                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 713                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 714                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 715                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 716                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 717                                                                 (ctx->bios + data_offset +
 718                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 719                                                         u8 *num_dst_objs = (u8 *)
 720                                                                 ((u8 *)router_src_dst_table + 1 +
 721                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 722                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 723                                                         int enum_id;
 724
 725                                                         router.router_id = router_obj_id;
 726                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 727                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 728                                                                     le16_to_cpu(dst_objs[enum_id]))
 729                                                                         break;
 730                                                         }
 731
 732                                                         while (record->ucRecordSize > 0 &&
 733                                                                record->ucRecordType > 0 &&
 734                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 735                                                                 switch (record->ucRecordType) {
 736                                                                 case ATOM_I2C_RECORD_TYPE:
 737                                                                         i2c_record =
 738                                                                                 (ATOM_I2C_RECORD *)
 739                                                                                 record;
 740                                                                         i2c_config =
 741                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 742                                                                                 &i2c_record->sucI2cId;
 743                                                                         router.i2c_info =
 744                                                                                 radeon_lookup_i2c_gpio(rdev,
 745                                                                                                        i2c_config->
 746                                                                                                        ucAccess);
 747                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 748                                                                         break;
 749                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 750                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 751                                                                                 record;
 752                                                                         router.ddc_valid = true;
 753                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 754                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 755                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 756                                                                         break;
 757                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 758                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 759                                                                                 record;
 760                                                                         router.cd_valid = true;
 761                                                                         router.cd_mux_type = cd_path->ucMuxType;
 762                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 763                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 764                                                                         break;
 765                                                                 }
 766                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 767                                                                         ((char *)record + record->ucRecordSize);
 768                                                         }
 769                                                 }
 770                                         }
 771                                 }
 772                         }
 773
 774                         /* look up gpio for ddc, hpd */
 775                         ddc_bus.valid = false;
 776                         hpd.hpd = RADEON_HPD_NONE;
 777                         if ((le16_to_cpu(path->usDeviceTag) &
 778                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 779                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 780                                         if (le16_to_cpu(path->usConnObjectId) ==
 781                                             le16_to_cpu(con_obj->asObjects[j].
 782                                                         usObjectID)) {
 783                                                 ATOM_COMMON_RECORD_HEADER
 784                                                     *record =
 785                                                     (ATOM_COMMON_RECORD_HEADER
 786                                                      *)
 787                                                     (ctx->bios + data_offset +
 788                                                      le16_to_cpu(con_obj->
 789                                                                  asObjects[j].
 790                                                                  usRecordOffset));
 791                                                 ATOM_I2C_RECORD *i2c_record;
 792                                                 ATOM_HPD_INT_RECORD *hpd_record;
 793                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 794
 795                                                 while (record->ucRecordSize > 0 &&
 796                                                        record->ucRecordType > 0 &&
 797                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 798                                                         switch (record->ucRecordType) {
 799                                                         case ATOM_I2C_RECORD_TYPE:
 800                                                                 i2c_record =
 801                                                                     (ATOM_I2C_RECORD *)
 802                                                                         record;
 803                                                                 i2c_config =
 804                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 805                                                                         &i2c_record->sucI2cId;
 806                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 807                                                                                                  i2c_config->
 808                                                                                                  ucAccess);
 809                                                                 break;
 810                                                         case ATOM_HPD_INT_RECORD_TYPE:
 811                                                                 hpd_record =
 812                                                                         (ATOM_HPD_INT_RECORD *)
 813                                                                         record;
 814                                                                 gpio = radeon_lookup_gpio(rdev,
 815                                                                                           hpd_record->ucHPDIntGPIOID);
 816                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 817                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 818                                                                 break;
 819                                                         }
 820                                                         record =
 821                                                             (ATOM_COMMON_RECORD_HEADER
 822                                                              *) ((char *)record
 823                                                                  +
 824                                                                  record->
 825                                                                  ucRecordSize);
 826                                                 }
 827                                                 break;
 828                                         }
 829                                 }
 830                         }
 831
 832                         /* needed for aux chan transactions */
 833                         ddc_bus.hpd = hpd.hpd;
 834
 835                         conn_id = le16_to_cpu(path->usConnObjectId);
 836
 837                         if (!radeon_atom_apply_quirks
 838                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 839                              &ddc_bus, &conn_id, &hpd))
 840                                 continue;
 841
 842                         radeon_add_atom_connector(dev,
 843                                                   conn_id,
 844                                                   le16_to_cpu(path->
 845                                                               usDeviceTag),
 846                                                   connector_type, &ddc_bus,
 847                                                   igp_lane_info,
 848                                                   connector_object_id,
 849                                                   &hpd,
 850                                                   &router);
 851
 852                 }
 853         }
 854
 855         radeon_link_encoder_connector(dev);
 856
 857         return true;
 858 }
 859
 860 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 861                                                  int connector_type,
 862                                                  uint16_t devices)
 863 {
 864         struct radeon_device *rdev = dev->dev_private;
 865
 866         if (rdev->flags & RADEON_IS_IGP) {
 867                 return supported_devices_connector_object_id_convert
 868                         [connector_type];
 869         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 870                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 871                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 872                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 873                 struct atom_context *ctx = mode_info->atom_context;
 874                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 875                 uint16_t size, data_offset;
 876                 uint8_t frev, crev;
 877                 ATOM_XTMDS_INFO *xtmds;
 878
 879                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 880                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 881
 882                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 883                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 884                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 885                                 else
 886                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 887                         } else {
 888                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 889                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 890                                 else
 891                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 892                         }
 893                 } else
 894                         return supported_devices_connector_object_id_convert
 895                                 [connector_type];
 896         } else {
 897                 return supported_devices_connector_object_id_convert
 898                         [connector_type];
 899         }
 900 }
 901
 902 struct bios_connector {
 903         bool valid;
 904         uint16_t line_mux;
 905         uint16_t devices;
 906         int connector_type;
 907         struct radeon_i2c_bus_rec ddc_bus;
 908         struct radeon_hpd hpd;
 909 };
 910
 911 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 912                                                                  drm_device
 913                                                                  *dev)
 914 {
 915         struct radeon_device *rdev = dev->dev_private;
 916         struct radeon_mode_info *mode_info = &rdev->mode_info;
 917         struct atom_context *ctx = mode_info->atom_context;
 918         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 919         uint16_t size, data_offset;
 920         uint8_t frev, crev;
 921         uint16_t device_support;
 922         uint8_t dac;
 923         union atom_supported_devices *supported_devices;
 924         int i, j, max_device;
 925         struct bios_connector *bios_connectors;
 926         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 927         struct radeon_router router;
 928
 929         router.ddc_valid = false;
 930         router.cd_valid = false;
 931
 932         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 933         if (!bios_connectors)
 934                 return false;
 935
 936         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 937                                     &data_offset)) {
 938                 kfree(bios_connectors);
 939                 return false;
 940         }
 941
 942         supported_devices =
 943             (union atom_supported_devices *)(ctx->bios + data_offset);
 944
 945         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 946
 947         if (frev > 1)
 948                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 949         else
 950                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 951
 952         for (i = 0; i < max_device; i++) {
 953                 ATOM_CONNECTOR_INFO_I2C ci =
 954                     supported_devices->info.asConnInfo[i];
 955
 956                 bios_connectors[i].valid = false;
 957
 958                 if (!(device_support & (1 << i))) {
 959                         continue;
 960                 }
 961
 962                 if (i == ATOM_DEVICE_CV_INDEX) {
 963                         DRM_DEBUG_KMS("Skipping Component Video\n");
 964                         continue;
 965                 }
 966
 967                 bios_connectors[i].connector_type =
 968                     supported_devices_connector_convert[ci.sucConnectorInfo.
 969                                                         sbfAccess.
 970                                                         bfConnectorType];
 971
 972                 if (bios_connectors[i].connector_type ==
 973                     DRM_MODE_CONNECTOR_Unknown)
 974                         continue;
 975
 976                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 977
 978                 bios_connectors[i].line_mux =
 979                         ci.sucI2cId.ucAccess;
 980
 981                 /* give tv unique connector ids */
 982                 if (i == ATOM_DEVICE_TV1_INDEX) {
 983                         bios_connectors[i].ddc_bus.valid = false;
 984                         bios_connectors[i].line_mux = 50;
 985                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 986                         bios_connectors[i].ddc_bus.valid = false;
 987                         bios_connectors[i].line_mux = 51;
 988                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 989                         bios_connectors[i].ddc_bus.valid = false;
 990                         bios_connectors[i].line_mux = 52;
 991                 } else
 992                         bios_connectors[i].ddc_bus =
 993                             radeon_lookup_i2c_gpio(rdev,
 994                                                    bios_connectors[i].line_mux);
 995
 996                 if ((crev > 1) && (frev > 1)) {
 997                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 998                         switch (isb) {
 999                         case 0x4:
1000                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1001                                 break;
1002                         case 0xa:
1003                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1004                                 break;
1005                         default:
1006                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1007                                 break;
1008                         }
1009                 } else {
1010                         if (i == ATOM_DEVICE_DFP1_INDEX)
1011                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1012                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1013                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1014                         else
1015                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1016                 }
1017
1018                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1019                  * shared with a DVI port, we'll pick up the DVI connector when we
1020                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1021                  */
1022                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1023                         bios_connectors[i].connector_type =
1024                             DRM_MODE_CONNECTOR_VGA;
1025
1026                 if (!radeon_atom_apply_quirks
1027                     (dev, (1 << i), &bios_connectors[i].connector_type,
1028                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1029                      &bios_connectors[i].hpd))
1030                         continue;
1031
1032                 bios_connectors[i].valid = true;
1033                 bios_connectors[i].devices = (1 << i);
1034
1035                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1036                         radeon_add_atom_encoder(dev,
1037                                                 radeon_get_encoder_enum(dev,
1038                                                                       (1 << i),
1039                                                                       dac),
1040                                                 (1 << i),
1041                                                 0);
1042                 else
1043                         radeon_add_legacy_encoder(dev,
1044                                                   radeon_get_encoder_enum(dev,
1045                                                                         (1 << i),
1046                                                                         dac),
1047                                                   (1 << i));
1048         }
1049
1050         /* combine shared connectors */
1051         for (i = 0; i < max_device; i++) {
1052                 if (bios_connectors[i].valid) {
1053                         for (j = 0; j < max_device; j++) {
1054                                 if (bios_connectors[j].valid && (i != j)) {
1055                                         if (bios_connectors[i].line_mux ==
1056                                             bios_connectors[j].line_mux) {
1057                                                 /* make sure not to combine LVDS */
1058                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1059                                                         bios_connectors[i].line_mux = 53;
1060                                                         bios_connectors[i].ddc_bus.valid = false;
1061                                                         continue;
1062                                                 }
1063                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1064                                                         bios_connectors[j].line_mux = 53;
1065                                                         bios_connectors[j].ddc_bus.valid = false;
1066                                                         continue;
1067                                                 }
1068                                                 /* combine analog and digital for DVI-I */
1069                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1070                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1071                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1072                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1073                                                         bios_connectors[i].devices |=
1074                                                                 bios_connectors[j].devices;
1075                                                         bios_connectors[i].connector_type =
1076                                                                 DRM_MODE_CONNECTOR_DVII;
1077                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1078                                                                 bios_connectors[i].hpd =
1079                                                                         bios_connectors[j].hpd;
1080                                                         bios_connectors[j].valid = false;
1081                                                 }
1082                                         }
1083                                 }
1084                         }
1085                 }
1086         }
1087
1088         /* add the connectors */
1089         for (i = 0; i < max_device; i++) {
1090                 if (bios_connectors[i].valid) {
1091                         uint16_t connector_object_id =
1092                                 atombios_get_connector_object_id(dev,
1093                                                       bios_connectors[i].connector_type,
1094                                                       bios_connectors[i].devices);
1095                         radeon_add_atom_connector(dev,
1096                                                   bios_connectors[i].line_mux,
1097                                                   bios_connectors[i].devices,
1098                                                   bios_connectors[i].
1099                                                   connector_type,
1100                                                   &bios_connectors[i].ddc_bus,
1101                                                   0,
1102                                                   connector_object_id,
1103                                                   &bios_connectors[i].hpd,
1104                                                   &router);
1105                 }
1106         }
1107
1108         radeon_link_encoder_connector(dev);
1109
1110         kfree(bios_connectors);
1111         return true;
1112 }
1113
1114 union firmware_info {
1115         ATOM_FIRMWARE_INFO info;
1116         ATOM_FIRMWARE_INFO_V1_2 info_12;
1117         ATOM_FIRMWARE_INFO_V1_3 info_13;
1118         ATOM_FIRMWARE_INFO_V1_4 info_14;
1119         ATOM_FIRMWARE_INFO_V2_1 info_21;
1120         ATOM_FIRMWARE_INFO_V2_2 info_22;
1121 };
1122
1123 bool radeon_atom_get_clock_info(struct drm_device *dev)
1124 {
1125         struct radeon_device *rdev = dev->dev_private;
1126         struct radeon_mode_info *mode_info = &rdev->mode_info;
1127         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1128         union firmware_info *firmware_info;
1129         uint8_t frev, crev;
1130         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1131         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1132         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1133         struct radeon_pll *spll = &rdev->clock.spll;
1134         struct radeon_pll *mpll = &rdev->clock.mpll;
1135         uint16_t data_offset;
1136
1137         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1138                                    &frev, &crev, &data_offset)) {
1139                 firmware_info =
1140                         (union firmware_info *)(mode_info->atom_context->bios +
1141                                                 data_offset);
1142                 /* pixel clocks */
1143                 p1pll->reference_freq =
1144                     le16_to_cpu(firmware_info->info.usReferenceClock);
1145                 p1pll->reference_div = 0;
1146
1147                 if (crev < 2)
1148                         p1pll->pll_out_min =
1149                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1150                 else
1151                         p1pll->pll_out_min =
1152                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1153                 p1pll->pll_out_max =
1154                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1155
1156                 if (crev >= 4) {
1157                         p1pll->lcd_pll_out_min =
1158                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1159                         if (p1pll->lcd_pll_out_min == 0)
1160                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1161                         p1pll->lcd_pll_out_max =
1162                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1163                         if (p1pll->lcd_pll_out_max == 0)
1164                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1165                 } else {
1166                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1167                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1168                 }
1169
1170                 if (p1pll->pll_out_min == 0) {
1171                         if (ASIC_IS_AVIVO(rdev))
1172                                 p1pll->pll_out_min = 64800;
1173                         else
1174                                 p1pll->pll_out_min = 20000;
1175                 }
1176
1177                 p1pll->pll_in_min =
1178                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1179                 p1pll->pll_in_max =
1180                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1181
1182                 *p2pll = *p1pll;
1183
1184                 /* system clock */
1185                 if (ASIC_IS_DCE4(rdev))
1186                         spll->reference_freq =
1187                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1188                 else
1189                         spll->reference_freq =
1190                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1191                 spll->reference_div = 0;
1192
1193                 spll->pll_out_min =
1194                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1195                 spll->pll_out_max =
1196                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1197
1198                 /* ??? */
1199                 if (spll->pll_out_min == 0) {
1200                         if (ASIC_IS_AVIVO(rdev))
1201                                 spll->pll_out_min = 64800;
1202                         else
1203                                 spll->pll_out_min = 20000;
1204                 }
1205
1206                 spll->pll_in_min =
1207                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1208                 spll->pll_in_max =
1209                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1210
1211                 /* memory clock */
1212                 if (ASIC_IS_DCE4(rdev))
1213                         mpll->reference_freq =
1214                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1215                 else
1216                         mpll->reference_freq =
1217                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1218                 mpll->reference_div = 0;
1219
1220                 mpll->pll_out_min =
1221                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1222                 mpll->pll_out_max =
1223                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1224
1225                 /* ??? */
1226                 if (mpll->pll_out_min == 0) {
1227                         if (ASIC_IS_AVIVO(rdev))
1228                                 mpll->pll_out_min = 64800;
1229                         else
1230                                 mpll->pll_out_min = 20000;
1231                 }
1232
1233                 mpll->pll_in_min =
1234                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1235                 mpll->pll_in_max =
1236                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1237
1238                 rdev->clock.default_sclk =
1239                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1240                 rdev->clock.default_mclk =
1241                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1242
1243                 if (ASIC_IS_DCE4(rdev)) {
1244                         rdev->clock.default_dispclk =
1245                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1246                         if (rdev->clock.default_dispclk == 0) {
1247                                 if (ASIC_IS_DCE5(rdev))
1248                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1249                                 else
1250                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1251                         }
1252                         rdev->clock.dp_extclk =
1253                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1254                         rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1255                 }
1256                 *dcpll = *p1pll;
1257
1258                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1259                 if (rdev->clock.max_pixel_clock == 0)
1260                         rdev->clock.max_pixel_clock = 40000;
1261
1262                 /* not technically a clock, but... */
1263                 rdev->mode_info.firmware_flags =
1264                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1265
1266                 return true;
1267         }
1268
1269         return false;
1270 }
1271
1272 union igp_info {
1273         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1274         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1275         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1276         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1277         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1278 };
1279
1280 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1281 {
1282         struct radeon_mode_info *mode_info = &rdev->mode_info;
1283         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1284         union igp_info *igp_info;
1285         u8 frev, crev;
1286         u16 data_offset;
1287
1288         /* sideport is AMD only */
1289         if (rdev->family == CHIP_RS600)
1290                 return false;
1291
1292         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1293                                    &frev, &crev, &data_offset)) {
1294                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1295                                       data_offset);
1296                 switch (crev) {
1297                 case 1:
1298                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1299                                 return true;
1300                         break;
1301                 case 2:
1302                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1303                                 return true;
1304                         break;
1305                 default:
1306                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1307                         break;
1308                 }
1309         }
1310         return false;
1311 }
1312
1313 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1314                                    struct radeon_encoder_int_tmds *tmds)
1315 {
1316         struct drm_device *dev = encoder->base.dev;
1317         struct radeon_device *rdev = dev->dev_private;
1318         struct radeon_mode_info *mode_info = &rdev->mode_info;
1319         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1320         uint16_t data_offset;
1321         struct _ATOM_TMDS_INFO *tmds_info;
1322         uint8_t frev, crev;
1323         uint16_t maxfreq;
1324         int i;
1325
1326         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1327                                    &frev, &crev, &data_offset)) {
1328                 tmds_info =
1329                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1330                                                    data_offset);
1331
1332                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1333                 for (i = 0; i < 4; i++) {
1334                         tmds->tmds_pll[i].freq =
1335                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1336                         tmds->tmds_pll[i].value =
1337                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1338                         tmds->tmds_pll[i].value |=
1339                             (tmds_info->asMiscInfo[i].
1340                              ucPLL_VCO_Gain & 0x3f) << 6;
1341                         tmds->tmds_pll[i].value |=
1342                             (tmds_info->asMiscInfo[i].
1343                              ucPLL_DutyCycle & 0xf) << 12;
1344                         tmds->tmds_pll[i].value |=
1345                             (tmds_info->asMiscInfo[i].
1346                              ucPLL_VoltageSwing & 0xf) << 16;
1347
1348                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1349                                   tmds->tmds_pll[i].freq,
1350                                   tmds->tmds_pll[i].value);
1351
1352                         if (maxfreq == tmds->tmds_pll[i].freq) {
1353                                 tmds->tmds_pll[i].freq = 0xffffffff;
1354                                 break;
1355                         }
1356                 }
1357                 return true;
1358         }
1359         return false;
1360 }
1361
1362 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1363                                       struct radeon_atom_ss *ss,
1364                                       int id)
1365 {
1366         struct radeon_mode_info *mode_info = &rdev->mode_info;
1367         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1368         uint16_t data_offset, size;
1369         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1370         uint8_t frev, crev;
1371         int i, num_indices;
1372
1373         memset(ss, 0, sizeof(struct radeon_atom_ss));
1374         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1375                                    &frev, &crev, &data_offset)) {
1376                 ss_info =
1377                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1378
1379                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1380                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1381
1382                 for (i = 0; i < num_indices; i++) {
1383                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1384                                 ss->percentage =
1385                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1386                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1387                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1388                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1389                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1390                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1391                                 return true;
1392                         }
1393                 }
1394         }
1395         return false;
1396 }
1397
1398 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1399                                                  struct radeon_atom_ss *ss,
1400                                                  int id)
1401 {
1402         struct radeon_mode_info *mode_info = &rdev->mode_info;
1403         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1404         u16 data_offset, size;
1405         union igp_info *igp_info;
1406         u8 frev, crev;
1407         u16 percentage = 0, rate = 0;
1408
1409         /* get any igp specific overrides */
1410         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1411                                    &frev, &crev, &data_offset)) {
1412                 igp_info = (union igp_info *)
1413                         (mode_info->atom_context->bios + data_offset);
1414                 switch (crev) {
1415                 case 6:
1416                         switch (id) {
1417                         case ASIC_INTERNAL_SS_ON_TMDS:
1418                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1419                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1420                                 break;
1421                         case ASIC_INTERNAL_SS_ON_HDMI:
1422                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1423                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1424                                 break;
1425                         case ASIC_INTERNAL_SS_ON_LVDS:
1426                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1427                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1428                                 break;
1429                         }
1430                         break;
1431                 case 7:
1432                         switch (id) {
1433                         case ASIC_INTERNAL_SS_ON_TMDS:
1434                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1435                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1436                                 break;
1437                         case ASIC_INTERNAL_SS_ON_HDMI:
1438                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1439                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1440                                 break;
1441                         case ASIC_INTERNAL_SS_ON_LVDS:
1442                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1443                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1444                                 break;
1445                         }
1446                         break;
1447                 case 8:
1448                         switch (id) {
1449                         case ASIC_INTERNAL_SS_ON_TMDS:
1450                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1451                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1452                                 break;
1453                         case ASIC_INTERNAL_SS_ON_HDMI:
1454                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1455                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1456                                 break;
1457                         case ASIC_INTERNAL_SS_ON_LVDS:
1458                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1459                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1460                                 break;
1461                         }
1462                         break;
1463                 default:
1464                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1465                         break;
1466                 }
1467                 if (percentage)
1468                         ss->percentage = percentage;
1469                 if (rate)
1470                         ss->rate = rate;
1471         }
1472 }
1473
1474 union asic_ss_info {
1475         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1476         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1477         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1478 };
1479
1480 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1481                                       struct radeon_atom_ss *ss,
1482                                       int id, u32 clock)
1483 {
1484         struct radeon_mode_info *mode_info = &rdev->mode_info;
1485         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1486         uint16_t data_offset, size;
1487         union asic_ss_info *ss_info;
1488         uint8_t frev, crev;
1489         int i, num_indices;
1490
1491         if (id == ASIC_INTERNAL_MEMORY_SS) {
1492                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1493                         return false;
1494         }
1495         if (id == ASIC_INTERNAL_ENGINE_SS) {
1496                 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1497                         return false;
1498         }
1499
1500         memset(ss, 0, sizeof(struct radeon_atom_ss));
1501         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1502                                    &frev, &crev, &data_offset)) {
1503
1504                 ss_info =
1505                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1506
1507                 switch (frev) {
1508                 case 1:
1509                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1510                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1511
1512                         for (i = 0; i < num_indices; i++) {
1513                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1514                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1515                                         ss->percentage =
1516                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1517                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1518                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1519                                         return true;
1520                                 }
1521                         }
1522                         break;
1523                 case 2:
1524                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1525                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1526                         for (i = 0; i < num_indices; i++) {
1527                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1528                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1529                                         ss->percentage =
1530                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1531                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1532                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1533                                         if ((crev == 2) &&
1534                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
1535                                              (id == ASIC_INTERNAL_MEMORY_SS)))
1536                                                 ss->rate /= 100;
1537                                         return true;
1538                                 }
1539                         }
1540                         break;
1541                 case 3:
1542                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1543                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1544                         for (i = 0; i < num_indices; i++) {
1545                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1546                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1547                                         ss->percentage =
1548                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1549                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1550                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1551                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1552                                             (id == ASIC_INTERNAL_MEMORY_SS))
1553                                                 ss->rate /= 100;
1554                                         if (rdev->flags & RADEON_IS_IGP)
1555                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1556                                         return true;
1557                                 }
1558                         }
1559                         break;
1560                 default:
1561                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1562                         break;
1563                 }
1564
1565         }
1566         return false;
1567 }
1568
1569 union lvds_info {
1570         struct _ATOM_LVDS_INFO info;
1571         struct _ATOM_LVDS_INFO_V12 info_12;
1572 };
1573
1574 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1575                                                               radeon_encoder
1576                                                               *encoder)
1577 {
1578         struct drm_device *dev = encoder->base.dev;
1579         struct radeon_device *rdev = dev->dev_private;
1580         struct radeon_mode_info *mode_info = &rdev->mode_info;
1581         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1582         uint16_t data_offset, misc;
1583         union lvds_info *lvds_info;
1584         uint8_t frev, crev;
1585         struct radeon_encoder_atom_dig *lvds = NULL;
1586         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1587
1588         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1589                                    &frev, &crev, &data_offset)) {
1590                 lvds_info =
1591                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1592                 lvds =
1593                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1594
1595                 if (!lvds)
1596                         return NULL;
1597
1598                 lvds->native_mode.clock =
1599                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1600                 lvds->native_mode.hdisplay =
1601                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1602                 lvds->native_mode.vdisplay =
1603                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1604                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1605                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1606                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1607                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1608                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1609                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1610                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1611                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1612                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1613                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1614                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1615                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1616                 lvds->panel_pwr_delay =
1617                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1618                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1619
1620                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1621                 if (misc & ATOM_VSYNC_POLARITY)
1622                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1623                 if (misc & ATOM_HSYNC_POLARITY)
1624                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1625                 if (misc & ATOM_COMPOSITESYNC)
1626                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1627                 if (misc & ATOM_INTERLACE)
1628                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1629                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1630                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1631
1632                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1633                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1634
1635                 /* set crtc values */
1636                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1637
1638                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1639
1640                 encoder->native_mode = lvds->native_mode;
1641
1642                 if (encoder_enum == 2)
1643                         lvds->linkb = true;
1644                 else
1645                         lvds->linkb = false;
1646
1647                 /* parse the lcd record table */
1648                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1649                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1650                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1651                         bool bad_record = false;
1652                         u8 *record;
1653
1654                         if ((frev == 1) && (crev < 2))
1655                                 /* absolute */
1656                                 record = (u8 *)(mode_info->atom_context->bios +
1657                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1658                         else
1659                                 /* relative */
1660                                 record = (u8 *)(mode_info->atom_context->bios +
1661                                                 data_offset +
1662                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1663                         while (*record != ATOM_RECORD_END_TYPE) {
1664                                 switch (*record) {
1665                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1666                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1667                                         break;
1668                                 case LCD_RTS_RECORD_TYPE:
1669                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1670                                         break;
1671                                 case LCD_CAP_RECORD_TYPE:
1672                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1673                                         break;
1674                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1675                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1676                                         if (fake_edid_record->ucFakeEDIDLength) {
1677                                                 struct edid *edid;
1678                                                 int edid_size =
1679                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1680                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1681                                                 if (edid) {
1682                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1683                                                                fake_edid_record->ucFakeEDIDLength);
1684
1685                                                         if (drm_edid_is_valid(edid)) {
1686                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1687                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1688                                                         } else
1689                                                                 kfree(edid);
1690                                                 }
1691                                         }
1692                                         record += fake_edid_record->ucFakeEDIDLength ?
1693                                                 fake_edid_record->ucFakeEDIDLength + 2 :
1694                                                 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1695                                         break;
1696                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1697                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1698                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1699                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1700                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1701                                         break;
1702                                 default:
1703                                         DRM_ERROR("Bad LCD record %d\n", *record);
1704                                         bad_record = true;
1705                                         break;
1706                                 }
1707                                 if (bad_record)
1708                                         break;
1709                         }
1710                 }
1711         }
1712         return lvds;
1713 }
1714
1715 struct radeon_encoder_primary_dac *
1716 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1717 {
1718         struct drm_device *dev = encoder->base.dev;
1719         struct radeon_device *rdev = dev->dev_private;
1720         struct radeon_mode_info *mode_info = &rdev->mode_info;
1721         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1722         uint16_t data_offset;
1723         struct _COMPASSIONATE_DATA *dac_info;
1724         uint8_t frev, crev;
1725         uint8_t bg, dac;
1726         struct radeon_encoder_primary_dac *p_dac = NULL;
1727
1728         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1729                                    &frev, &crev, &data_offset)) {
1730                 dac_info = (struct _COMPASSIONATE_DATA *)
1731                         (mode_info->atom_context->bios + data_offset);
1732
1733                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1734
1735                 if (!p_dac)
1736                         return NULL;
1737
1738                 bg = dac_info->ucDAC1_BG_Adjustment;
1739                 dac = dac_info->ucDAC1_DAC_Adjustment;
1740                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1741
1742         }
1743         return p_dac;
1744 }
1745
1746 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1747                                 struct drm_display_mode *mode)
1748 {
1749         struct radeon_mode_info *mode_info = &rdev->mode_info;
1750         ATOM_ANALOG_TV_INFO *tv_info;
1751         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1752         ATOM_DTD_FORMAT *dtd_timings;
1753         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1754         u8 frev, crev;
1755         u16 data_offset, misc;
1756
1757         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1758                                     &frev, &crev, &data_offset))
1759                 return false;
1760
1761         switch (crev) {
1762         case 1:
1763                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1764                 if (index >= MAX_SUPPORTED_TV_TIMING)
1765                         return false;
1766
1767                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1768                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1769                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1770                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1771                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1772
1773                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1774                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1775                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1776                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1777                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1778
1779                 mode->flags = 0;
1780                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1781                 if (misc & ATOM_VSYNC_POLARITY)
1782                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1783                 if (misc & ATOM_HSYNC_POLARITY)
1784                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1785                 if (misc & ATOM_COMPOSITESYNC)
1786                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1787                 if (misc & ATOM_INTERLACE)
1788                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1789                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1790                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1791
1792                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1793
1794                 if (index == 1) {
1795                         /* PAL timings appear to have wrong values for totals */
1796                         mode->crtc_htotal -= 1;
1797                         mode->crtc_vtotal -= 1;
1798                 }
1799                 break;
1800         case 2:
1801                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1802                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1803                         return false;
1804
1805                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1806                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1807                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1808                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1809                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1810                         le16_to_cpu(dtd_timings->usHSyncOffset);
1811                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1812                         le16_to_cpu(dtd_timings->usHSyncWidth);
1813
1814                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1815                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1816                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1817                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1818                         le16_to_cpu(dtd_timings->usVSyncOffset);
1819                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1820                         le16_to_cpu(dtd_timings->usVSyncWidth);
1821
1822                 mode->flags = 0;
1823                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1824                 if (misc & ATOM_VSYNC_POLARITY)
1825                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1826                 if (misc & ATOM_HSYNC_POLARITY)
1827                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1828                 if (misc & ATOM_COMPOSITESYNC)
1829                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1830                 if (misc & ATOM_INTERLACE)
1831                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1832                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1833                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1834
1835                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1836                 break;
1837         }
1838         return true;
1839 }
1840
1841 enum radeon_tv_std
1842 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1843 {
1844         struct radeon_mode_info *mode_info = &rdev->mode_info;
1845         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1846         uint16_t data_offset;
1847         uint8_t frev, crev;
1848         struct _ATOM_ANALOG_TV_INFO *tv_info;
1849         enum radeon_tv_std tv_std = TV_STD_NTSC;
1850
1851         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1852                                    &frev, &crev, &data_offset)) {
1853
1854                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1855                         (mode_info->atom_context->bios + data_offset);
1856
1857                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1858                 case ATOM_TV_NTSC:
1859                         tv_std = TV_STD_NTSC;
1860                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1861                         break;
1862                 case ATOM_TV_NTSCJ:
1863                         tv_std = TV_STD_NTSC_J;
1864                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1865                         break;
1866                 case ATOM_TV_PAL:
1867                         tv_std = TV_STD_PAL;
1868                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1869                         break;
1870                 case ATOM_TV_PALM:
1871                         tv_std = TV_STD_PAL_M;
1872                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1873                         break;
1874                 case ATOM_TV_PALN:
1875                         tv_std = TV_STD_PAL_N;
1876                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1877                         break;
1878                 case ATOM_TV_PALCN:
1879                         tv_std = TV_STD_PAL_CN;
1880                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1881                         break;
1882                 case ATOM_TV_PAL60:
1883                         tv_std = TV_STD_PAL_60;
1884                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1885                         break;
1886                 case ATOM_TV_SECAM:
1887                         tv_std = TV_STD_SECAM;
1888                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1889                         break;
1890                 default:
1891                         tv_std = TV_STD_NTSC;
1892                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1893                         break;
1894                 }
1895         }
1896         return tv_std;
1897 }
1898
1899 struct radeon_encoder_tv_dac *
1900 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1901 {
1902         struct drm_device *dev = encoder->base.dev;
1903         struct radeon_device *rdev = dev->dev_private;
1904         struct radeon_mode_info *mode_info = &rdev->mode_info;
1905         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1906         uint16_t data_offset;
1907         struct _COMPASSIONATE_DATA *dac_info;
1908         uint8_t frev, crev;
1909         uint8_t bg, dac;
1910         struct radeon_encoder_tv_dac *tv_dac = NULL;
1911
1912         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1913                                    &frev, &crev, &data_offset)) {
1914
1915                 dac_info = (struct _COMPASSIONATE_DATA *)
1916                         (mode_info->atom_context->bios + data_offset);
1917
1918                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1919
1920                 if (!tv_dac)
1921                         return NULL;
1922
1923                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1924                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1925                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1926
1927                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1928                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1929                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1930
1931                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1932                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1933                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1934
1935                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1936         }
1937         return tv_dac;
1938 }
1939
1940 static const char *thermal_controller_names[] = {
1941         "NONE",
1942         "lm63",
1943         "adm1032",
1944         "adm1030",
1945         "max6649",
1946         "lm64",
1947         "f75375",
1948         "asc7xxx",
1949 };
1950
1951 static const char *pp_lib_thermal_controller_names[] = {
1952         "NONE",
1953         "lm63",
1954         "adm1032",
1955         "adm1030",
1956         "max6649",
1957         "lm64",
1958         "f75375",
1959         "RV6xx",
1960         "RV770",
1961         "adt7473",
1962         "NONE",
1963         "External GPIO",
1964         "Evergreen",
1965         "emc2103",
1966         "Sumo",
1967         "Northern Islands",
1968         "Southern Islands",
1969         "lm96163",
1970         "Sea Islands",
1971 };
1972
1973 union power_info {
1974         struct _ATOM_POWERPLAY_INFO info;
1975         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1976         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1977         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1978         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1979         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1980 };
1981
1982 union pplib_clock_info {
1983         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1984         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1985         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1986         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1987         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1988         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
1989 };
1990
1991 union pplib_power_state {
1992         struct _ATOM_PPLIB_STATE v1;
1993         struct _ATOM_PPLIB_STATE_V2 v2;
1994 };
1995
1996 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1997                                                  int state_index,
1998                                                  u32 misc, u32 misc2)
1999 {
2000         rdev->pm.power_state[state_index].misc = misc;
2001         rdev->pm.power_state[state_index].misc2 = misc2;
2002         /* order matters! */
2003         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2004                 rdev->pm.power_state[state_index].type =
2005                         POWER_STATE_TYPE_POWERSAVE;
2006         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2007                 rdev->pm.power_state[state_index].type =
2008                         POWER_STATE_TYPE_BATTERY;
2009         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2010                 rdev->pm.power_state[state_index].type =
2011                         POWER_STATE_TYPE_BATTERY;
2012         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2013                 rdev->pm.power_state[state_index].type =
2014                         POWER_STATE_TYPE_BALANCED;
2015         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2016                 rdev->pm.power_state[state_index].type =
2017                         POWER_STATE_TYPE_PERFORMANCE;
2018                 rdev->pm.power_state[state_index].flags &=
2019                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2020         }
2021         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2022                 rdev->pm.power_state[state_index].type =
2023                         POWER_STATE_TYPE_BALANCED;
2024         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2025                 rdev->pm.power_state[state_index].type =
2026                         POWER_STATE_TYPE_DEFAULT;
2027                 rdev->pm.default_power_state_index = state_index;
2028                 rdev->pm.power_state[state_index].default_clock_mode =
2029                         &rdev->pm.power_state[state_index].clock_info[0];
2030         } else if (state_index == 0) {
2031                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2032                         RADEON_PM_MODE_NO_DISPLAY;
2033         }
2034 }
2035
2036 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2037 {
2038         struct radeon_mode_info *mode_info = &rdev->mode_info;
2039         u32 misc, misc2 = 0;
2040         int num_modes = 0, i;
2041         int state_index = 0;
2042         struct radeon_i2c_bus_rec i2c_bus;
2043         union power_info *power_info;
2044         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2045         u16 data_offset;
2046         u8 frev, crev;
2047
2048         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2049                                    &frev, &crev, &data_offset))
2050                 return state_index;
2051         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2052
2053         /* add the i2c bus for thermal/fan chip */
2054         if ((power_info->info.ucOverdriveThermalController > 0) &&
2055             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2056                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2057                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2058                          power_info->info.ucOverdriveControllerAddress >> 1);
2059                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2060                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2061                 if (rdev->pm.i2c_bus) {
2062                         struct i2c_board_info info = { };
2063                         const char *name = thermal_controller_names[power_info->info.
2064                                                                     ucOverdriveThermalController];
2065                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2066                         strlcpy(info.type, name, sizeof(info.type));
2067                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2068                 }
2069         }
2070         num_modes = power_info->info.ucNumOfPowerModeEntries;
2071         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2072                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2073         if (num_modes == 0)
2074                 return state_index;
2075         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2076         if (!rdev->pm.power_state)
2077                 return state_index;
2078         /* last mode is usually default, array is low to high */
2079         for (i = 0; i < num_modes; i++) {
2080                 rdev->pm.power_state[state_index].clock_info =
2081                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2082                 if (!rdev->pm.power_state[state_index].clock_info)
2083                         return state_index;
2084                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2085                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2086                 switch (frev) {
2087                 case 1:
2088                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2089                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2090                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2091                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2092                         /* skip invalid modes */
2093                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2094                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2095                                 continue;
2096                         rdev->pm.power_state[state_index].pcie_lanes =
2097                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2098                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2099                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2100                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2101                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2102                                         VOLTAGE_GPIO;
2103                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2104                                         radeon_lookup_gpio(rdev,
2105                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2106                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2107                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2108                                                 true;
2109                                 else
2110                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2111                                                 false;
2112                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2113                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2114                                         VOLTAGE_VDDC;
2115                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2116                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2117                         }
2118                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2119                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2120                         state_index++;
2121                         break;
2122                 case 2:
2123                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2124                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2125                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2126                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2127                         /* skip invalid modes */
2128                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2129                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2130                                 continue;
2131                         rdev->pm.power_state[state_index].pcie_lanes =
2132                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2133                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2134                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2135                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2136                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2137                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2138                                         VOLTAGE_GPIO;
2139                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2140                                         radeon_lookup_gpio(rdev,
2141                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2142                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2143                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2144                                                 true;
2145                                 else
2146                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2147                                                 false;
2148                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2149                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2150                                         VOLTAGE_VDDC;
2151                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2152                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2153                         }
2154                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2155                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2156                         state_index++;
2157                         break;
2158                 case 3:
2159                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2160                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2161                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2162                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2163                         /* skip invalid modes */
2164                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2165                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2166                                 continue;
2167                         rdev->pm.power_state[state_index].pcie_lanes =
2168                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2169                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2170                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2171                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2172                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2173                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2174                                         VOLTAGE_GPIO;
2175                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2176                                         radeon_lookup_gpio(rdev,
2177                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2178                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2179                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2180                                                 true;
2181                                 else
2182                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2183                                                 false;
2184                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2185                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2186                                         VOLTAGE_VDDC;
2187                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2188                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2189                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2190                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2191                                                 true;
2192                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2193                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2194                                 }
2195                         }
2196                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2197                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2198                         state_index++;
2199                         break;
2200                 }
2201         }
2202         /* last mode is usually default */
2203         if (rdev->pm.default_power_state_index == -1) {
2204                 rdev->pm.power_state[state_index - 1].type =
2205                         POWER_STATE_TYPE_DEFAULT;
2206                 rdev->pm.default_power_state_index = state_index - 1;
2207                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2208                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2209                 rdev->pm.power_state[state_index].flags &=
2210                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2211                 rdev->pm.power_state[state_index].misc = 0;
2212                 rdev->pm.power_state[state_index].misc2 = 0;
2213         }
2214         return state_index;
2215 }
2216
2217 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2218                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2219 {
2220         struct radeon_i2c_bus_rec i2c_bus;
2221
2222         /* add the i2c bus for thermal/fan chip */
2223         if (controller->ucType > 0) {
2224                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2225                         DRM_INFO("Internal thermal controller %s fan control\n",
2226                                  (controller->ucFanParameters &
2227                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2228                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2229                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2230                         DRM_INFO("Internal thermal controller %s fan control\n",
2231                                  (controller->ucFanParameters &
2232                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2233                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2234                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2235                         DRM_INFO("Internal thermal controller %s fan control\n",
2236                                  (controller->ucFanParameters &
2237                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2238                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2239                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2240                         DRM_INFO("Internal thermal controller %s fan control\n",
2241                                  (controller->ucFanParameters &
2242                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2243                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2244                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2245                         DRM_INFO("Internal thermal controller %s fan control\n",
2246                                  (controller->ucFanParameters &
2247                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2248                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2249                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2250                         DRM_INFO("Internal thermal controller %s fan control\n",
2251                                  (controller->ucFanParameters &
2252                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2253                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2254                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2255                         DRM_INFO("Internal thermal controller %s fan control\n",
2256                                  (controller->ucFanParameters &
2257                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2258                         rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2259                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2260                         DRM_INFO("Internal thermal controller %s fan control\n",
2261                                  (controller->ucFanParameters &
2262                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2263                         rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2264                 } else if ((controller->ucType ==
2265                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2266                            (controller->ucType ==
2267                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2268                            (controller->ucType ==
2269                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2270                         DRM_INFO("Special thermal controller config\n");
2271                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2272                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2273                                  pp_lib_thermal_controller_names[controller->ucType],
2274                                  controller->ucI2cAddress >> 1,
2275                                  (controller->ucFanParameters &
2276                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2277                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2278                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2279                         if (rdev->pm.i2c_bus) {
2280                                 struct i2c_board_info info = { };
2281                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2282                                 info.addr = controller->ucI2cAddress >> 1;
2283                                 strlcpy(info.type, name, sizeof(info.type));
2284                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2285                         }
2286                 } else {
2287                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2288                                  controller->ucType,
2289                                  controller->ucI2cAddress >> 1,
2290                                  (controller->ucFanParameters &
2291                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2292                 }
2293         }
2294 }
2295
2296 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2297                                           u16 *vddc, u16 *vddci, u16 *mvdd)
2298 {
2299         struct radeon_mode_info *mode_info = &rdev->mode_info;
2300         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2301         u8 frev, crev;
2302         u16 data_offset;
2303         union firmware_info *firmware_info;
2304
2305         *vddc = 0;
2306         *vddci = 0;
2307         *mvdd = 0;
2308
2309         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2310                                    &frev, &crev, &data_offset)) {
2311                 firmware_info =
2312                         (union firmware_info *)(mode_info->atom_context->bios +
2313                                                 data_offset);
2314                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2315                 if ((frev == 2) && (crev >= 2)) {
2316                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2317                         *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2318                 }
2319         }
2320 }
2321
2322 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2323                                                        int state_index, int mode_index,
2324                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2325 {
2326         int j;
2327         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2328         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2329         u16 vddc, vddci, mvdd;
2330
2331         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2332
2333         rdev->pm.power_state[state_index].misc = misc;
2334         rdev->pm.power_state[state_index].misc2 = misc2;
2335         rdev->pm.power_state[state_index].pcie_lanes =
2336                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2337                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2338         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2339         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2340                 rdev->pm.power_state[state_index].type =
2341                         POWER_STATE_TYPE_BATTERY;
2342                 break;
2343         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2344                 rdev->pm.power_state[state_index].type =
2345                         POWER_STATE_TYPE_BALANCED;
2346                 break;
2347         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2348                 rdev->pm.power_state[state_index].type =
2349                         POWER_STATE_TYPE_PERFORMANCE;
2350                 break;
2351         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2352                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2353                         rdev->pm.power_state[state_index].type =
2354                                 POWER_STATE_TYPE_PERFORMANCE;
2355                 break;
2356         }
2357         rdev->pm.power_state[state_index].flags = 0;
2358         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2359                 rdev->pm.power_state[state_index].flags |=
2360                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2361         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2362                 rdev->pm.power_state[state_index].type =
2363                         POWER_STATE_TYPE_DEFAULT;
2364                 rdev->pm.default_power_state_index = state_index;
2365                 rdev->pm.power_state[state_index].default_clock_mode =
2366                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2367                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2368                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2369                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2370                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2371                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2372                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2373                 } else {
2374                         u16 max_vddci = 0;
2375
2376                         if (ASIC_IS_DCE4(rdev))
2377                                 radeon_atom_get_max_voltage(rdev,
2378                                                             SET_VOLTAGE_TYPE_ASIC_VDDCI,
2379                                                             &max_vddci);
2380                         /* patch the table values with the default sclk/mclk from firmware info */
2381                         for (j = 0; j < mode_index; j++) {
2382                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2383                                         rdev->clock.default_mclk;
2384                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2385                                         rdev->clock.default_sclk;
2386                                 if (vddc)
2387                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2388                                                 vddc;
2389                                 if (max_vddci)
2390                                         rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2391                                                 max_vddci;
2392                         }
2393                 }
2394         }
2395 }
2396
2397 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2398                                                    int state_index, int mode_index,
2399                                                    union pplib_clock_info *clock_info)
2400 {
2401         u32 sclk, mclk;
2402         u16 vddc;
2403
2404         if (rdev->flags & RADEON_IS_IGP) {
2405                 if (rdev->family >= CHIP_PALM) {
2406                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2407                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2408                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2409                 } else {
2410                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2411                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2412                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2413                 }
2414         } else if (rdev->family >= CHIP_BONAIRE) {
2415                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2416                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2417                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2418                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2419                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2420                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2421                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2422                         VOLTAGE_NONE;
2423         } else if (rdev->family >= CHIP_TAHITI) {
2424                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2425                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2426                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2427                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2428                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2429                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2430                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2431                         VOLTAGE_SW;
2432                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2433                         le16_to_cpu(clock_info->si.usVDDC);
2434                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2435                         le16_to_cpu(clock_info->si.usVDDCI);
2436         } else if (rdev->family >= CHIP_CEDAR) {
2437                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2438                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2439                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2440                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2441                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2442                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2443                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2444                         VOLTAGE_SW;
2445                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2446                         le16_to_cpu(clock_info->evergreen.usVDDC);
2447                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2448                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2449         } else {
2450                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2451                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2452                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2453                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2454                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2455                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2456                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2457                         VOLTAGE_SW;
2458                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2459                         le16_to_cpu(clock_info->r600.usVDDC);
2460         }
2461
2462         /* patch up vddc if necessary */
2463         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2464         case ATOM_VIRTUAL_VOLTAGE_ID0:
2465         case ATOM_VIRTUAL_VOLTAGE_ID1:
2466         case ATOM_VIRTUAL_VOLTAGE_ID2:
2467         case ATOM_VIRTUAL_VOLTAGE_ID3:
2468         case ATOM_VIRTUAL_VOLTAGE_ID4:
2469         case ATOM_VIRTUAL_VOLTAGE_ID5:
2470         case ATOM_VIRTUAL_VOLTAGE_ID6:
2471         case ATOM_VIRTUAL_VOLTAGE_ID7:
2472                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2473                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2474                                              &vddc) == 0)
2475                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2476                 break;
2477         default:
2478                 break;
2479         }
2480
2481         if (rdev->flags & RADEON_IS_IGP) {
2482                 /* skip invalid modes */
2483                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2484                         return false;
2485         } else {
2486                 /* skip invalid modes */
2487                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2488                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2489                         return false;
2490         }
2491         return true;
2492 }
2493
2494 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2495 {
2496         struct radeon_mode_info *mode_info = &rdev->mode_info;
2497         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2498         union pplib_power_state *power_state;
2499         int i, j;
2500         int state_index = 0, mode_index = 0;
2501         union pplib_clock_info *clock_info;
2502         bool valid;
2503         union power_info *power_info;
2504         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2505         u16 data_offset;
2506         u8 frev, crev;
2507
2508         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2509                                    &frev, &crev, &data_offset))
2510                 return state_index;
2511         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2512
2513         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2514         if (power_info->pplib.ucNumStates == 0)
2515                 return state_index;
2516         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2517                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2518         if (!rdev->pm.power_state)
2519                 return state_index;
2520         /* first mode is usually default, followed by low to high */
2521         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2522                 mode_index = 0;
2523                 power_state = (union pplib_power_state *)
2524                         (mode_info->atom_context->bios + data_offset +
2525                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2526                          i * power_info->pplib.ucStateEntrySize);
2527                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2528                         (mode_info->atom_context->bios + data_offset +
2529                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2530                          (power_state->v1.ucNonClockStateIndex *
2531                           power_info->pplib.ucNonClockSize));
2532                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2533                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2534                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2535                                                              GFP_KERNEL);
2536                 if (!rdev->pm.power_state[i].clock_info)
2537                         return state_index;
2538                 if (power_info->pplib.ucStateEntrySize - 1) {
2539                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2540                                 clock_info = (union pplib_clock_info *)
2541                                         (mode_info->atom_context->bios + data_offset +
2542                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2543                                          (power_state->v1.ucClockStateIndices[j] *
2544                                           power_info->pplib.ucClockInfoSize));
2545                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2546                                                                                state_index, mode_index,
2547                                                                                clock_info);
2548                                 if (valid)
2549                                         mode_index++;
2550                         }
2551                 } else {
2552                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2553                                 rdev->clock.default_mclk;
2554                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2555                                 rdev->clock.default_sclk;
2556                         mode_index++;
2557                 }
2558                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2559                 if (mode_index) {
2560                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2561                                                                    non_clock_info);
2562                         state_index++;
2563                 }
2564         }
2565         /* if multiple clock modes, mark the lowest as no display */
2566         for (i = 0; i < state_index; i++) {
2567                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2568                         rdev->pm.power_state[i].clock_info[0].flags |=
2569                                 RADEON_PM_MODE_NO_DISPLAY;
2570         }
2571         /* first mode is usually default */
2572         if (rdev->pm.default_power_state_index == -1) {
2573                 rdev->pm.power_state[0].type =
2574                         POWER_STATE_TYPE_DEFAULT;
2575                 rdev->pm.default_power_state_index = 0;
2576                 rdev->pm.power_state[0].default_clock_mode =
2577                         &rdev->pm.power_state[0].clock_info[0];
2578         }
2579         return state_index;
2580 }
2581
2582 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2583 {
2584         struct radeon_mode_info *mode_info = &rdev->mode_info;
2585         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2586         union pplib_power_state *power_state;
2587         int i, j, non_clock_array_index, clock_array_index;
2588         int state_index = 0, mode_index = 0;
2589         union pplib_clock_info *clock_info;
2590         struct _StateArray *state_array;
2591         struct _ClockInfoArray *clock_info_array;
2592         struct _NonClockInfoArray *non_clock_info_array;
2593         bool valid;
2594         union power_info *power_info;
2595         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2596         u16 data_offset;
2597         u8 frev, crev;
2598         u8 *power_state_offset;
2599
2600         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2601                                    &frev, &crev, &data_offset))
2602                 return state_index;
2603         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2604
2605         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2606         state_array = (struct _StateArray *)
2607                 (mode_info->atom_context->bios + data_offset +
2608                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2609         clock_info_array = (struct _ClockInfoArray *)
2610                 (mode_info->atom_context->bios + data_offset +
2611                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2612         non_clock_info_array = (struct _NonClockInfoArray *)
2613                 (mode_info->atom_context->bios + data_offset +
2614                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2615         if (state_array->ucNumEntries == 0)
2616                 return state_index;
2617         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2618                                        state_array->ucNumEntries, GFP_KERNEL);
2619         if (!rdev->pm.power_state)
2620                 return state_index;
2621         power_state_offset = (u8 *)state_array->states;
2622         for (i = 0; i < state_array->ucNumEntries; i++) {
2623                 mode_index = 0;
2624                 power_state = (union pplib_power_state *)power_state_offset;
2625                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2626                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2627                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2628                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2629                                                              (power_state->v2.ucNumDPMLevels ?
2630                                                               power_state->v2.ucNumDPMLevels : 1),
2631                                                              GFP_KERNEL);
2632                 if (!rdev->pm.power_state[i].clock_info)
2633                         return state_index;
2634                 if (power_state->v2.ucNumDPMLevels) {
2635                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2636                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2637                                 clock_info = (union pplib_clock_info *)
2638                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2639                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2640                                                                                state_index, mode_index,
2641                                                                                clock_info);
2642                                 if (valid)
2643                                         mode_index++;
2644                         }
2645                 } else {
2646                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2647                                 rdev->clock.default_mclk;
2648                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2649                                 rdev->clock.default_sclk;
2650                         mode_index++;
2651                 }
2652                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2653                 if (mode_index) {
2654                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2655                                                                    non_clock_info);
2656                         state_index++;
2657                 }
2658                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2659         }
2660         /* if multiple clock modes, mark the lowest as no display */
2661         for (i = 0; i < state_index; i++) {
2662                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2663                         rdev->pm.power_state[i].clock_info[0].flags |=
2664                                 RADEON_PM_MODE_NO_DISPLAY;
2665         }
2666         /* first mode is usually default */
2667         if (rdev->pm.default_power_state_index == -1) {
2668                 rdev->pm.power_state[0].type =
2669                         POWER_STATE_TYPE_DEFAULT;
2670                 rdev->pm.default_power_state_index = 0;
2671                 rdev->pm.power_state[0].default_clock_mode =
2672                         &rdev->pm.power_state[0].clock_info[0];
2673         }
2674         return state_index;
2675 }
2676
2677 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2678 {
2679         struct radeon_mode_info *mode_info = &rdev->mode_info;
2680         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2681         u16 data_offset;
2682         u8 frev, crev;
2683         int state_index = 0;
2684
2685         rdev->pm.default_power_state_index = -1;
2686
2687         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2688                                    &frev, &crev, &data_offset)) {
2689                 switch (frev) {
2690                 case 1:
2691                 case 2:
2692                 case 3:
2693                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2694                         break;
2695                 case 4:
2696                 case 5:
2697                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2698                         break;
2699                 case 6:
2700                         state_index = radeon_atombios_parse_power_table_6(rdev);
2701                         break;
2702                 default:
2703                         break;
2704                 }
2705         }
2706
2707         if (state_index == 0) {
2708                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2709                 if (rdev->pm.power_state) {
2710                         rdev->pm.power_state[0].clock_info =
2711                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2712                         if (rdev->pm.power_state[0].clock_info) {
2713                                 /* add the default mode */
2714                                 rdev->pm.power_state[state_index].type =
2715                                         POWER_STATE_TYPE_DEFAULT;
2716                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2717                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2718                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2719                                 rdev->pm.power_state[state_index].default_clock_mode =
2720                                         &rdev->pm.power_state[state_index].clock_info[0];
2721                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2722                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2723                                 rdev->pm.default_power_state_index = state_index;
2724                                 rdev->pm.power_state[state_index].flags = 0;
2725                                 state_index++;
2726                         }
2727                 }
2728         }
2729
2730         rdev->pm.num_power_states = state_index;
2731
2732         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2733         rdev->pm.current_clock_mode_index = 0;
2734         if (rdev->pm.default_power_state_index >= 0)
2735                 rdev->pm.current_vddc =
2736                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2737         else
2738                 rdev->pm.current_vddc = 0;
2739 }
2740
2741 union get_clock_dividers {
2742         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2743         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2744         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2745         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2746         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2747         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2748         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2749 };
2750
2751 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2752                                    u8 clock_type,
2753                                    u32 clock,
2754                                    bool strobe_mode,
2755                                    struct atom_clock_dividers *dividers)
2756 {
2757         union get_clock_dividers args;
2758         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2759         u8 frev, crev;
2760
2761         memset(&args, 0, sizeof(args));
2762         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2763
2764         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2765                 return -EINVAL;
2766
2767         switch (crev) {
2768         case 1:
2769                 /* r4xx, r5xx */
2770                 args.v1.ucAction = clock_type;
2771                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2772
2773                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2774
2775                 dividers->post_div = args.v1.ucPostDiv;
2776                 dividers->fb_div = args.v1.ucFbDiv;
2777                 dividers->enable_post_div = true;
2778                 break;
2779         case 2:
2780         case 3:
2781         case 5:
2782                 /* r6xx, r7xx, evergreen, ni, si */
2783                 if (rdev->family <= CHIP_RV770) {
2784                         args.v2.ucAction = clock_type;
2785                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2786
2787                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2788
2789                         dividers->post_div = args.v2.ucPostDiv;
2790                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2791                         dividers->ref_div = args.v2.ucAction;
2792                         if (rdev->family == CHIP_RV770) {
2793                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2794                                         true : false;
2795                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2796                         } else
2797                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2798                 } else {
2799                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2800                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2801
2802                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2803
2804                                 dividers->post_div = args.v3.ucPostDiv;
2805                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2806                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2807                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2808                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2809                                 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2810                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2811                                 dividers->ref_div = args.v3.ucRefDiv;
2812                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2813                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2814                         } else {
2815                                 /* for SI we use ComputeMemoryClockParam for memory plls */
2816                                 if (rdev->family >= CHIP_TAHITI)
2817                                         return -EINVAL;
2818                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2819                                 if (strobe_mode)
2820                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2821
2822                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2823
2824                                 dividers->post_div = args.v5.ucPostDiv;
2825                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2826                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2827                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2828                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2829                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2830                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2831                                 dividers->ref_div = args.v5.ucRefDiv;
2832                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2833                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2834                         }
2835                 }
2836                 break;
2837         case 4:
2838                 /* fusion */
2839                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2840
2841                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2842
2843                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2844                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2845                 break;
2846         case 6:
2847                 /* CI */
2848                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2849                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2850                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
2851
2852                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2853
2854                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2855                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2856                 dividers->ref_div = args.v6_out.ucPllRefDiv;
2857                 dividers->post_div = args.v6_out.ucPllPostDiv;
2858                 dividers->flags = args.v6_out.ucPllCntlFlag;
2859                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2860                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2861                 break;
2862         default:
2863                 return -EINVAL;
2864         }
2865         return 0;
2866 }
2867
2868 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2869                                         u32 clock,
2870                                         bool strobe_mode,
2871                                         struct atom_mpll_param *mpll_param)
2872 {
2873         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2874         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2875         u8 frev, crev;
2876
2877         memset(&args, 0, sizeof(args));
2878         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2879
2880         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2881                 return -EINVAL;
2882
2883         switch (frev) {
2884         case 2:
2885                 switch (crev) {
2886                 case 1:
2887                         /* SI */
2888                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
2889                         args.ucInputFlag = 0;
2890                         if (strobe_mode)
2891                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2892
2893                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2894
2895                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2896                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2897                         mpll_param->post_div = args.ucPostDiv;
2898                         mpll_param->dll_speed = args.ucDllSpeed;
2899                         mpll_param->bwcntl = args.ucBWCntl;
2900                         mpll_param->vco_mode =
2901                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0;
2902                         mpll_param->yclk_sel =
2903                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2904                         mpll_param->qdr =
2905                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2906                         mpll_param->half_rate =
2907                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2908                         break;
2909                 default:
2910                         return -EINVAL;
2911                 }
2912                 break;
2913         default:
2914                 return -EINVAL;
2915         }
2916         return 0;
2917 }
2918
2919 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2920 {
2921         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2922         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2923
2924         args.ucEnable = enable;
2925
2926         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2927 }
2928
2929 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2930 {
2931         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2932         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2933
2934         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2935         return le32_to_cpu(args.ulReturnEngineClock);
2936 }
2937
2938 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2939 {
2940         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2941         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2942
2943         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2944         return le32_to_cpu(args.ulReturnMemoryClock);
2945 }
2946
2947 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2948                                   uint32_t eng_clock)
2949 {
2950         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2951         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2952
2953         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2954
2955         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2956 }
2957
2958 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2959                                   uint32_t mem_clock)
2960 {
2961         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2962         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2963
2964         if (rdev->flags & RADEON_IS_IGP)
2965                 return;
2966
2967         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2968
2969         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2970 }
2971
2972 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
2973                                          u32 eng_clock, u32 mem_clock)
2974 {
2975         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2976         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2977         u32 tmp;
2978
2979         memset(&args, 0, sizeof(args));
2980
2981         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
2982         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
2983
2984         args.ulTargetEngineClock = cpu_to_le32(tmp);
2985         if (mem_clock)
2986                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
2987
2988         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2989 }
2990
2991 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
2992                                    u32 mem_clock)
2993 {
2994         u32 args;
2995         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
2996
2997         args = cpu_to_le32(mem_clock);  /* 10 khz */
2998
2999         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3000 }
3001
3002 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3003                                u32 mem_clock)
3004 {
3005         SET_MEMORY_CLOCK_PS_ALLOCATION args;
3006         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3007         u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3008
3009         args.ulTargetMemoryClock = cpu_to_le32(tmp);    /* 10 khz */
3010
3011         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3012 }
3013
3014 union set_voltage {
3015         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3016         struct _SET_VOLTAGE_PARAMETERS v1;
3017         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3018         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3019 };
3020
3021 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3022 {
3023         union set_voltage args;
3024         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3025         u8 frev, crev, volt_index = voltage_level;
3026
3027         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3028                 return;
3029
3030         /* 0xff01 is a flag rather then an actual voltage */
3031         if (voltage_level == 0xff01)
3032                 return;
3033
3034         switch (crev) {
3035         case 1:
3036                 args.v1.ucVoltageType = voltage_type;
3037                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3038                 args.v1.ucVoltageIndex = volt_index;
3039                 break;
3040         case 2:
3041                 args.v2.ucVoltageType = voltage_type;
3042                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3043                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3044                 break;
3045         case 3:
3046                 args.v3.ucVoltageType = voltage_type;
3047                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3048                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3049                 break;
3050         default:
3051                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3052                 return;
3053         }
3054
3055         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3056 }
3057
3058 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3059                              u16 voltage_id, u16 *voltage)
3060 {
3061         union set_voltage args;
3062         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3063         u8 frev, crev;
3064
3065         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3066                 return -EINVAL;
3067
3068         switch (crev) {
3069         case 1:
3070                 return -EINVAL;
3071         case 2:
3072                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3073                 args.v2.ucVoltageMode = 0;
3074                 args.v2.usVoltageLevel = 0;
3075
3076                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3077
3078                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3079                 break;
3080         case 3:
3081                 args.v3.ucVoltageType = voltage_type;
3082                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3083                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3084
3085                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3086
3087                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3088                 break;
3089         default:
3090                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3091                 return -EINVAL;
3092         }
3093
3094         return 0;
3095 }
3096
3097 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3098                                                       u16 *voltage,
3099                                                       u16 leakage_idx)
3100 {
3101         return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3102 }
3103
3104 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3105                                           u16 *leakage_id)
3106 {
3107         union set_voltage args;
3108         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3109         u8 frev, crev;
3110
3111         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3112                 return -EINVAL;
3113
3114         switch (crev) {
3115         case 3:
3116         case 4:
3117                 args.v3.ucVoltageType = 0;
3118                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3119                 args.v3.usVoltageLevel = 0;
3120
3121                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3122
3123                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3124                 break;
3125         default:
3126                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3127                 return -EINVAL;
3128         }
3129
3130         return 0;
3131 }
3132
3133 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3134                                                          u16 *vddc, u16 *vddci,
3135                                                          u16 virtual_voltage_id,
3136                                                          u16 vbios_voltage_id)
3137 {
3138         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3139         u8 frev, crev;
3140         u16 data_offset, size;
3141         int i, j;
3142         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3143         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3144
3145         *vddc = 0;
3146         *vddci = 0;
3147
3148         if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3149                                     &frev, &crev, &data_offset))
3150                 return -EINVAL;
3151
3152         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3153                 (rdev->mode_info.atom_context->bios + data_offset);
3154
3155         switch (frev) {
3156         case 1:
3157                 return -EINVAL;
3158         case 2:
3159                 switch (crev) {
3160                 case 1:
3161                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3162                                 return -EINVAL;
3163                         leakage_bin = (u16 *)
3164                                 (rdev->mode_info.atom_context->bios + data_offset +
3165                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
3166                         vddc_id_buf = (u16 *)
3167                                 (rdev->mode_info.atom_context->bios + data_offset +
3168                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3169                         vddc_buf = (u16 *)
3170                                 (rdev->mode_info.atom_context->bios + data_offset +
3171                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3172                         vddci_id_buf = (u16 *)
3173                                 (rdev->mode_info.atom_context->bios + data_offset +
3174                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3175                         vddci_buf = (u16 *)
3176                                 (rdev->mode_info.atom_context->bios + data_offset +
3177                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3178
3179                         if (profile->ucElbVDDC_Num > 0) {
3180                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3181                                         if (vddc_id_buf[i] == virtual_voltage_id) {
3182                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3183                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3184                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3185                                                                 break;
3186                                                         }
3187                                                 }
3188                                                 break;
3189                                         }
3190                                 }
3191                         }
3192                         if (profile->ucElbVDDCI_Num > 0) {
3193                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3194                                         if (vddci_id_buf[i] == virtual_voltage_id) {
3195                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3196                                                         if (vbios_voltage_id <= leakage_bin[j]) {
3197                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3198                                                                 break;
3199                                                         }
3200                                                 }
3201                                                 break;
3202                                         }
3203                                 }
3204                         }
3205                         break;
3206                 default:
3207                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3208                         return -EINVAL;
3209                 }
3210                 break;
3211         default:
3212                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3213                 return -EINVAL;
3214         }
3215
3216         return 0;
3217 }
3218
3219 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3220                                           u16 voltage_level, u8 voltage_type,
3221                                           u32 *gpio_value, u32 *gpio_mask)
3222 {
3223         union set_voltage args;
3224         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3225         u8 frev, crev;
3226
3227         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3228                 return -EINVAL;
3229
3230         switch (crev) {
3231         case 1:
3232                 return -EINVAL;
3233         case 2:
3234                 args.v2.ucVoltageType = voltage_type;
3235                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3236                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3237
3238                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3239
3240                 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3241
3242                 args.v2.ucVoltageType = voltage_type;
3243                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3244                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3245
3246                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3247
3248                 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3249                 break;
3250         default:
3251                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3252                 return -EINVAL;
3253         }
3254
3255         return 0;
3256 }
3257
3258 union voltage_object_info {
3259         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3260         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3261         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3262 };
3263
3264 union voltage_object {
3265         struct _ATOM_VOLTAGE_OBJECT v1;
3266         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3267         union _ATOM_VOLTAGE_OBJECT_V3 v3;
3268 };
3269
3270 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3271                                                           u8 voltage_type)
3272 {
3273         u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3274         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3275         u8 *start = (u8 *)v1;
3276
3277         while (offset < size) {
3278                 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3279                 if (vo->ucVoltageType == voltage_type)
3280                         return vo;
3281                 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3282                         vo->asFormula.ucNumOfVoltageEntries;
3283         }
3284         return NULL;
3285 }
3286
3287 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3288                                                              u8 voltage_type)
3289 {
3290         u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3291         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3292         u8 *start = (u8*)v2;
3293
3294         while (offset < size) {
3295                 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3296                 if (vo->ucVoltageType == voltage_type)
3297                         return vo;
3298                 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3299                         (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3300         }
3301         return NULL;
3302 }
3303
3304 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3305                                                              u8 voltage_type, u8 voltage_mode)
3306 {
3307         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3308         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3309         u8 *start = (u8*)v3;
3310
3311         while (offset < size) {
3312                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3313                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3314                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3315                         return vo;
3316                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3317         }
3318         return NULL;
3319 }
3320
3321 bool
3322 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3323                             u8 voltage_type, u8 voltage_mode)
3324 {
3325         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3326         u8 frev, crev;
3327         u16 data_offset, size;
3328         union voltage_object_info *voltage_info;
3329         union voltage_object *voltage_object = NULL;
3330
3331         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3332                                    &frev, &crev, &data_offset)) {
3333                 voltage_info = (union voltage_object_info *)
3334                         (rdev->mode_info.atom_context->bios + data_offset);
3335
3336                 switch (frev) {
3337                 case 1:
3338                 case 2:
3339                         switch (crev) {
3340                         case 1:
3341                                 voltage_object = (union voltage_object *)
3342                                         atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3343                                 if (voltage_object &&
3344                                     (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3345                                         return true;
3346                                 break;
3347                         case 2:
3348                                 voltage_object = (union voltage_object *)
3349                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3350                                 if (voltage_object &&
3351                                     (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3352                                         return true;
3353                                 break;
3354                         default:
3355                                 DRM_ERROR("unknown voltage object table\n");
3356                                 return false;
3357                         }
3358                         break;
3359                 case 3:
3360                         switch (crev) {
3361                         case 1:
3362                                 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3363                                                                   voltage_type, voltage_mode))
3364                                         return true;
3365                                 break;
3366                         default:
3367                                 DRM_ERROR("unknown voltage object table\n");
3368                                 return false;
3369                         }
3370                         break;
3371                 default:
3372                         DRM_ERROR("unknown voltage object table\n");
3373                         return false;
3374                 }
3375
3376         }
3377         return false;
3378 }
3379
3380 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3381                                 u8 voltage_type, u16 *max_voltage)
3382 {
3383         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3384         u8 frev, crev;
3385         u16 data_offset, size;
3386         union voltage_object_info *voltage_info;
3387         union voltage_object *voltage_object = NULL;
3388
3389         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3390                                    &frev, &crev, &data_offset)) {
3391                 voltage_info = (union voltage_object_info *)
3392                         (rdev->mode_info.atom_context->bios + data_offset);
3393
3394                 switch (crev) {
3395                 case 1:
3396                         voltage_object = (union voltage_object *)
3397                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3398                         if (voltage_object) {
3399                                 ATOM_VOLTAGE_FORMULA *formula =
3400                                         &voltage_object->v1.asFormula;
3401                                 if (formula->ucFlag & 1)
3402                                         *max_voltage =
3403                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3404                                                 formula->ucNumOfVoltageEntries / 2 *
3405                                                 le16_to_cpu(formula->usVoltageStep);
3406                                 else
3407                                         *max_voltage =
3408                                                 le16_to_cpu(formula->usVoltageBaseLevel) +
3409                                                 (formula->ucNumOfVoltageEntries - 1) *
3410                                                 le16_to_cpu(formula->usVoltageStep);
3411                                 return 0;
3412                         }
3413                         break;
3414                 case 2:
3415                         voltage_object = (union voltage_object *)
3416                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3417                         if (voltage_object) {
3418                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3419                                         &voltage_object->v2.asFormula;
3420                                 if (formula->ucNumOfVoltageEntries) {
3421                                         VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3422                                                 ((u8 *)&formula->asVIDAdjustEntries[0] +
3423                                                  (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3424                                         *max_voltage =
3425                                                 le16_to_cpu(lut->usVoltageValue);
3426                                         return 0;
3427                                 }
3428                         }
3429                         break;
3430                 default:
3431                         DRM_ERROR("unknown voltage object table\n");
3432                         return -EINVAL;
3433                 }
3434
3435         }
3436         return -EINVAL;
3437 }
3438
3439 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3440                                 u8 voltage_type, u16 *min_voltage)
3441 {
3442         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3443         u8 frev, crev;
3444         u16 data_offset, size;
3445         union voltage_object_info *voltage_info;
3446         union voltage_object *voltage_object = NULL;
3447
3448         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3449                                    &frev, &crev, &data_offset)) {
3450                 voltage_info = (union voltage_object_info *)
3451                         (rdev->mode_info.atom_context->bios + data_offset);
3452
3453                 switch (crev) {
3454                 case 1:
3455                         voltage_object = (union voltage_object *)
3456                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3457                         if (voltage_object) {
3458                                 ATOM_VOLTAGE_FORMULA *formula =
3459                                         &voltage_object->v1.asFormula;
3460                                 *min_voltage =
3461                                         le16_to_cpu(formula->usVoltageBaseLevel);
3462                                 return 0;
3463                         }
3464                         break;
3465                 case 2:
3466                         voltage_object = (union voltage_object *)
3467                                 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3468                         if (voltage_object) {
3469                                 ATOM_VOLTAGE_FORMULA_V2 *formula =
3470                                         &voltage_object->v2.asFormula;
3471                                 if (formula->ucNumOfVoltageEntries) {
3472                                         *min_voltage =
3473                                                 le16_to_cpu(formula->asVIDAdjustEntries[
3474                                                                     0
3475                                                                     ].usVoltageValue);
3476                                         return 0;
3477                                 }
3478                         }
3479                         break;
3480                 default:
3481                         DRM_ERROR("unknown voltage object table\n");
3482                         return -EINVAL;
3483                 }
3484
3485         }
3486         return -EINVAL;
3487 }
3488
3489 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3490                                  u8 voltage_type, u16 *voltage_step)
3491 {
3492         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3493         u8 frev, crev;
3494         u16 data_offset, size;
3495         union voltage_object_info *voltage_info;
3496         union voltage_object *voltage_object = NULL;
3497
3498         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3499                                    &frev, &crev, &data_offset)) {
3500                 voltage_info = (union voltage_object_info *)
3501                         (rdev->mode_info.atom_context->bios + data_offset);
3502
3503                 switch (crev) {
3504                 case 1:
3505                         voltage_object = (union voltage_object *)
3506                                 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3507                         if (voltage_object) {
3508                                 ATOM_VOLTAGE_FORMULA *formula =
3509                                         &voltage_object->v1.asFormula;
3510                                 if (formula->ucFlag & 1)
3511                                         *voltage_step =
3512                                                 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3513                                 else
3514                                         *voltage_step =
3515                                                 le16_to_cpu(formula->usVoltageStep);
3516                                 return 0;
3517                         }
3518                         break;
3519                 case 2:
3520                         return -EINVAL;
3521                 default:
3522                         DRM_ERROR("unknown voltage object table\n");
3523                         return -EINVAL;
3524                 }
3525
3526         }
3527         return -EINVAL;
3528 }
3529
3530 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3531                                       u8 voltage_type,
3532                                       u16 nominal_voltage,
3533                                       u16 *true_voltage)
3534 {
3535         u16 min_voltage, max_voltage, voltage_step;
3536
3537         if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3538                 return -EINVAL;
3539         if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3540                 return -EINVAL;
3541         if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3542                 return -EINVAL;
3543
3544         if (nominal_voltage <= min_voltage)
3545                 *true_voltage = min_voltage;
3546         else if (nominal_voltage >= max_voltage)
3547                 *true_voltage = max_voltage;
3548         else
3549                 *true_voltage = min_voltage +
3550                         ((nominal_voltage - min_voltage) / voltage_step) *
3551                         voltage_step;
3552
3553         return 0;
3554 }
3555
3556 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3557                                   u8 voltage_type, u8 voltage_mode,
3558                                   struct atom_voltage_table *voltage_table)
3559 {
3560         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3561         u8 frev, crev;
3562         u16 data_offset, size;
3563         int i, ret;
3564         union voltage_object_info *voltage_info;
3565         union voltage_object *voltage_object = NULL;
3566
3567         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3568                                    &frev, &crev, &data_offset)) {
3569                 voltage_info = (union voltage_object_info *)
3570                         (rdev->mode_info.atom_context->bios + data_offset);
3571
3572                 switch (frev) {
3573                 case 1:
3574                 case 2:
3575                         switch (crev) {
3576                         case 1:
3577                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3578                                 return -EINVAL;
3579                         case 2:
3580                                 voltage_object = (union voltage_object *)
3581                                         atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3582                                 if (voltage_object) {
3583                                         ATOM_VOLTAGE_FORMULA_V2 *formula =
3584                                                 &voltage_object->v2.asFormula;
3585                                         VOLTAGE_LUT_ENTRY *lut;
3586                                         if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3587                                                 return -EINVAL;
3588                                         lut = &formula->asVIDAdjustEntries[0];
3589                                         for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3590                                                 voltage_table->entries[i].value =
3591                                                         le16_to_cpu(lut->usVoltageValue);
3592                                                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3593                                                                                             voltage_table->entries[i].value,
3594                                                                                             voltage_type,
3595                                                                                             &voltage_table->entries[i].smio_low,
3596                                                                                             &voltage_table->mask_low);
3597                                                 if (ret)
3598                                                         return ret;
3599                                                 lut = (VOLTAGE_LUT_ENTRY *)
3600                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3601                                         }
3602                                         voltage_table->count = formula->ucNumOfVoltageEntries;
3603                                         return 0;
3604                                 }
3605                                 break;
3606                         default:
3607                                 DRM_ERROR("unknown voltage object table\n");
3608                                 return -EINVAL;
3609                         }
3610                         break;
3611                 case 3:
3612                         switch (crev) {
3613                         case 1:
3614                                 voltage_object = (union voltage_object *)
3615                                         atom_lookup_voltage_object_v3(&voltage_info->v3,
3616                                                                       voltage_type, voltage_mode);
3617                                 if (voltage_object) {
3618                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3619                                                 &voltage_object->v3.asGpioVoltageObj;
3620                                         VOLTAGE_LUT_ENTRY_V2 *lut;
3621                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3622                                                 return -EINVAL;
3623                                         lut = &gpio->asVolGpioLut[0];
3624                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3625                                                 voltage_table->entries[i].value =
3626                                                         le16_to_cpu(lut->usVoltageValue);
3627                                                 voltage_table->entries[i].smio_low =
3628                                                         le32_to_cpu(lut->ulVoltageId);
3629                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3630                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3631                                         }
3632                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3633                                         voltage_table->count = gpio->ucGpioEntryNum;
3634                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
3635                                         return 0;
3636                                 }
3637                                 break;
3638                         default:
3639                                 DRM_ERROR("unknown voltage object table\n");
3640                                 return -EINVAL;
3641                         }
3642                         break;
3643                 default:
3644                         DRM_ERROR("unknown voltage object table\n");
3645                         return -EINVAL;
3646                 }
3647         }
3648         return -EINVAL;
3649 }
3650
3651 union vram_info {
3652         struct _ATOM_VRAM_INFO_V3 v1_3;
3653         struct _ATOM_VRAM_INFO_V4 v1_4;
3654         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3655 };
3656
3657 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3658                                 u8 module_index, struct atom_memory_info *mem_info)
3659 {
3660         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3661         u8 frev, crev, i;
3662         u16 data_offset, size;
3663         union vram_info *vram_info;
3664
3665         memset(mem_info, 0, sizeof(struct atom_memory_info));
3666
3667         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3668                                    &frev, &crev, &data_offset)) {
3669                 vram_info = (union vram_info *)
3670                         (rdev->mode_info.atom_context->bios + data_offset);
3671                 switch (frev) {
3672                 case 1:
3673                         switch (crev) {
3674                         case 3:
3675                                 /* r6xx */
3676                                 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3677                                         ATOM_VRAM_MODULE_V3 *vram_module =
3678                                                 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3679
3680                                         for (i = 0; i < module_index; i++) {
3681                                                 if (le16_to_cpu(vram_module->usSize) == 0)
3682                                                         return -EINVAL;
3683                                                 vram_module = (ATOM_VRAM_MODULE_V3 *)
3684                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3685                                         }
3686                                         mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3687                                         mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3688                                 } else
3689                                         return -EINVAL;
3690                                 break;
3691                         case 4:
3692                                 /* r7xx, evergreen */
3693                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3694                                         ATOM_VRAM_MODULE_V4 *vram_module =
3695                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3696
3697                                         for (i = 0; i < module_index; i++) {
3698                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3699                                                         return -EINVAL;
3700                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3701                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3702                                         }
3703                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3704                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3705                                 } else
3706                                         return -EINVAL;
3707                                 break;
3708                         default:
3709                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3710                                 return -EINVAL;
3711                         }
3712                         break;
3713                 case 2:
3714                         switch (crev) {
3715                         case 1:
3716                                 /* ni */
3717                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3718                                         ATOM_VRAM_MODULE_V7 *vram_module =
3719                                                 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3720
3721                                         for (i = 0; i < module_index; i++) {
3722                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3723                                                         return -EINVAL;
3724                                                 vram_module = (ATOM_VRAM_MODULE_V7 *)
3725                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3726                                         }
3727                                         mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3728                                         mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3729                                 } else
3730                                         return -EINVAL;
3731                                 break;
3732                         default:
3733                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3734                                 return -EINVAL;
3735                         }
3736                         break;
3737                 default:
3738                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3739                         return -EINVAL;
3740                 }
3741                 return 0;
3742         }
3743         return -EINVAL;
3744 }
3745
3746 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3747                                      bool gddr5, u8 module_index,
3748                                      struct atom_memory_clock_range_table *mclk_range_table)
3749 {
3750         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3751         u8 frev, crev, i;
3752         u16 data_offset, size;
3753         union vram_info *vram_info;
3754         u32 mem_timing_size = gddr5 ?
3755                 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3756
3757         memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3758
3759         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3760                                    &frev, &crev, &data_offset)) {
3761                 vram_info = (union vram_info *)
3762                         (rdev->mode_info.atom_context->bios + data_offset);
3763                 switch (frev) {
3764                 case 1:
3765                         switch (crev) {
3766                         case 3:
3767                                 DRM_ERROR("old table version %d, %d\n", frev, crev);
3768                                 return -EINVAL;
3769                         case 4:
3770                                 /* r7xx, evergreen */
3771                                 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3772                                         ATOM_VRAM_MODULE_V4 *vram_module =
3773                                                 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3774                                         ATOM_MEMORY_TIMING_FORMAT *format;
3775
3776                                         for (i = 0; i < module_index; i++) {
3777                                                 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3778                                                         return -EINVAL;
3779                                                 vram_module = (ATOM_VRAM_MODULE_V4 *)
3780                                                         ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3781                                         }
3782                                         mclk_range_table->num_entries = (u8)
3783                                                 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3784                                                  mem_timing_size);
3785                                         format = &vram_module->asMemTiming[0];
3786                                         for (i = 0; i < mclk_range_table->num_entries; i++) {
3787                                                 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3788                                                 format = (ATOM_MEMORY_TIMING_FORMAT *)
3789                                                         ((u8 *)format + mem_timing_size);
3790                                         }
3791                                 } else
3792                                         return -EINVAL;
3793                                 break;
3794                         default:
3795                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3796                                 return -EINVAL;
3797                         }
3798                         break;
3799                 case 2:
3800                         DRM_ERROR("new table version %d, %d\n", frev, crev);
3801                         return -EINVAL;
3802                 default:
3803                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3804                         return -EINVAL;
3805                 }
3806                 return 0;
3807         }
3808         return -EINVAL;
3809 }
3810
3811 #define MEM_ID_MASK           0xff000000
3812 #define MEM_ID_SHIFT          24
3813 #define CLOCK_RANGE_MASK      0x00ffffff
3814 #define CLOCK_RANGE_SHIFT     0
3815 #define LOW_NIBBLE_MASK       0xf
3816 #define DATA_EQU_PREV         0
3817 #define DATA_FROM_TABLE       4
3818
3819 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3820                                   u8 module_index,
3821                                   struct atom_mc_reg_table *reg_table)
3822 {
3823         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3824         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3825         u32 i = 0, j;
3826         u16 data_offset, size;
3827         union vram_info *vram_info;
3828
3829         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3830
3831         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3832                                    &frev, &crev, &data_offset)) {
3833                 vram_info = (union vram_info *)
3834                         (rdev->mode_info.atom_context->bios + data_offset);
3835                 switch (frev) {
3836                 case 1:
3837                         DRM_ERROR("old table version %d, %d\n", frev, crev);
3838                         return -EINVAL;
3839                 case 2:
3840                         switch (crev) {
3841                         case 1:
3842                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3843                                         ATOM_INIT_REG_BLOCK *reg_block =
3844                                                 (ATOM_INIT_REG_BLOCK *)
3845                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3846                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3847                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3848                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
3849                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
3850                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
3851                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3852                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3853                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3854                                                 return -EINVAL;
3855                                         while (i < num_entries) {
3856                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3857                                                         break;
3858                                                 reg_table->mc_reg_address[i].s1 =
3859                                                         (u16)(le16_to_cpu(format->usRegIndex));
3860                                                 reg_table->mc_reg_address[i].pre_reg_data =
3861                                                         (u8)(format->ucPreRegDataLength);
3862                                                 i++;
3863                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
3864                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3865                                         }
3866                                         reg_table->last = i;
3867                                         while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
3868                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3869                                                 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
3870                                                 if (module_index == t_mem_id) {
3871                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
3872                                                                 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
3873                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
3874                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
3875                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3876                                                                                 (u32)*((u32 *)reg_data + j);
3877                                                                         j++;
3878                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
3879                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
3880                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
3881                                                                 }
3882                                                         }
3883                                                         num_ranges++;
3884                                                 }
3885                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3886                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
3887                                         }
3888                                         if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
3889                                                 return -EINVAL;
3890                                         reg_table->num_entries = num_ranges;
3891                                 } else
3892                                         return -EINVAL;
3893                                 break;
3894                         default:
3895                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3896                                 return -EINVAL;
3897                         }
3898                         break;
3899                 default:
3900                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3901                         return -EINVAL;
3902                 }
3903                 return 0;
3904         }
3905         return -EINVAL;
3906 }
3907
3908 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
3909 {
3910         struct radeon_device *rdev = dev->dev_private;
3911         uint32_t bios_2_scratch, bios_6_scratch;
3912
3913         if (rdev->family >= CHIP_R600) {
3914                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3915                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3916         } else {
3917                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3918                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3919         }
3920
3921         /* let the bios control the backlight */
3922         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
3923
3924         /* tell the bios not to handle mode switching */
3925         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
3926
3927         if (rdev->family >= CHIP_R600) {
3928                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3929                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3930         } else {
3931                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3932                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3933         }
3934
3935 }
3936
3937 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
3938 {
3939         uint32_t scratch_reg;
3940         int i;
3941
3942         if (rdev->family >= CHIP_R600)
3943                 scratch_reg = R600_BIOS_0_SCRATCH;
3944         else
3945                 scratch_reg = RADEON_BIOS_0_SCRATCH;
3946
3947         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3948                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
3949 }
3950
3951 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
3952 {
3953         uint32_t scratch_reg;
3954         int i;
3955
3956         if (rdev->family >= CHIP_R600)
3957                 scratch_reg = R600_BIOS_0_SCRATCH;
3958         else
3959                 scratch_reg = RADEON_BIOS_0_SCRATCH;
3960
3961         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
3962                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
3963 }
3964
3965 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
3966 {
3967         struct drm_device *dev = encoder->dev;
3968         struct radeon_device *rdev = dev->dev_private;
3969         uint32_t bios_6_scratch;
3970
3971         if (rdev->family >= CHIP_R600)
3972                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
3973         else
3974                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3975
3976         if (lock) {
3977                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
3978                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
3979         } else {
3980                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
3981                 bios_6_scratch |= ATOM_S6_ACC_MODE;
3982         }
3983
3984         if (rdev->family >= CHIP_R600)
3985                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3986         else
3987                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3988 }
3989
3990 /* at some point we may want to break this out into individual functions */
3991 void
3992 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
3993                                        struct drm_encoder *encoder,
3994                                        bool connected)
3995 {
3996         struct drm_device *dev = connector->dev;
3997         struct radeon_device *rdev = dev->dev_private;
3998         struct radeon_connector *radeon_connector =
3999             to_radeon_connector(connector);
4000         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4001         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4002
4003         if (rdev->family >= CHIP_R600) {
4004                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4005                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4006                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4007         } else {
4008                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4009                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4010                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4011         }
4012
4013         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4014             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4015                 if (connected) {
4016                         DRM_DEBUG_KMS("TV1 connected\n");
4017                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4018                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4019                 } else {
4020                         DRM_DEBUG_KMS("TV1 disconnected\n");
4021                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4022                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4023                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4024                 }
4025         }
4026         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4027             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4028                 if (connected) {
4029                         DRM_DEBUG_KMS("CV connected\n");
4030                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4031                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4032                 } else {
4033                         DRM_DEBUG_KMS("CV disconnected\n");
4034                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
4035                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4036                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4037                 }
4038         }
4039         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4040             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4041                 if (connected) {
4042                         DRM_DEBUG_KMS("LCD1 connected\n");
4043                         bios_0_scratch |= ATOM_S0_LCD1;
4044                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4045                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4046                 } else {
4047                         DRM_DEBUG_KMS("LCD1 disconnected\n");
4048                         bios_0_scratch &= ~ATOM_S0_LCD1;
4049                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4050                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4051                 }
4052         }
4053         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4054             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4055                 if (connected) {
4056                         DRM_DEBUG_KMS("CRT1 connected\n");
4057                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4058                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4059                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4060                 } else {
4061                         DRM_DEBUG_KMS("CRT1 disconnected\n");
4062                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4063                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4064                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4065                 }
4066         }
4067         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4068             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4069                 if (connected) {
4070                         DRM_DEBUG_KMS("CRT2 connected\n");
4071                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4072                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4073                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4074                 } else {
4075                         DRM_DEBUG_KMS("CRT2 disconnected\n");
4076                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4077                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4078                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4079                 }
4080         }
4081         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4082             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4083                 if (connected) {
4084                         DRM_DEBUG_KMS("DFP1 connected\n");
4085                         bios_0_scratch |= ATOM_S0_DFP1;
4086                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4087                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4088                 } else {
4089                         DRM_DEBUG_KMS("DFP1 disconnected\n");
4090                         bios_0_scratch &= ~ATOM_S0_DFP1;
4091                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4092                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4093                 }
4094         }
4095         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4096             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4097                 if (connected) {
4098                         DRM_DEBUG_KMS("DFP2 connected\n");
4099                         bios_0_scratch |= ATOM_S0_DFP2;
4100                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4101                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4102                 } else {
4103                         DRM_DEBUG_KMS("DFP2 disconnected\n");
4104                         bios_0_scratch &= ~ATOM_S0_DFP2;
4105                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4106                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4107                 }
4108         }
4109         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4110             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4111                 if (connected) {
4112                         DRM_DEBUG_KMS("DFP3 connected\n");
4113                         bios_0_scratch |= ATOM_S0_DFP3;
4114                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4115                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4116                 } else {
4117                         DRM_DEBUG_KMS("DFP3 disconnected\n");
4118                         bios_0_scratch &= ~ATOM_S0_DFP3;
4119                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4120                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4121                 }
4122         }
4123         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4124             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4125                 if (connected) {
4126                         DRM_DEBUG_KMS("DFP4 connected\n");
4127                         bios_0_scratch |= ATOM_S0_DFP4;
4128                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4129                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4130                 } else {
4131                         DRM_DEBUG_KMS("DFP4 disconnected\n");
4132                         bios_0_scratch &= ~ATOM_S0_DFP4;
4133                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4134                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4135                 }
4136         }
4137         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4138             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4139                 if (connected) {
4140                         DRM_DEBUG_KMS("DFP5 connected\n");
4141                         bios_0_scratch |= ATOM_S0_DFP5;
4142                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4143                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4144                 } else {
4145                         DRM_DEBUG_KMS("DFP5 disconnected\n");
4146                         bios_0_scratch &= ~ATOM_S0_DFP5;
4147                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4148                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4149                 }
4150         }
4151         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4152             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4153                 if (connected) {
4154                         DRM_DEBUG_KMS("DFP6 connected\n");
4155                         bios_0_scratch |= ATOM_S0_DFP6;
4156                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4157                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4158                 } else {
4159                         DRM_DEBUG_KMS("DFP6 disconnected\n");
4160                         bios_0_scratch &= ~ATOM_S0_DFP6;
4161                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4162                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4163                 }
4164         }
4165
4166         if (rdev->family >= CHIP_R600) {
4167                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4168                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4169                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4170         } else {
4171                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4172                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4173                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4174         }
4175 }
4176
4177 void
4178 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4179 {
4180         struct drm_device *dev = encoder->dev;
4181         struct radeon_device *rdev = dev->dev_private;
4182         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4183         uint32_t bios_3_scratch;
4184
4185         if (ASIC_IS_DCE4(rdev))
4186                 return;
4187
4188         if (rdev->family >= CHIP_R600)
4189                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4190         else
4191                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4192
4193         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4194                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4195                 bios_3_scratch |= (crtc << 18);
4196         }
4197         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4198                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4199                 bios_3_scratch |= (crtc << 24);
4200         }
4201         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4202                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4203                 bios_3_scratch |= (crtc << 16);
4204         }
4205         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4206                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4207                 bios_3_scratch |= (crtc << 20);
4208         }
4209         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4210                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4211                 bios_3_scratch |= (crtc << 17);
4212         }
4213         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4214                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4215                 bios_3_scratch |= (crtc << 19);
4216         }
4217         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4218                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4219                 bios_3_scratch |= (crtc << 23);
4220         }
4221         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4222                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4223                 bios_3_scratch |= (crtc << 25);
4224         }
4225
4226         if (rdev->family >= CHIP_R600)
4227                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4228         else
4229                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4230 }
4231
4232 void
4233 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4234 {
4235         struct drm_device *dev = encoder->dev;
4236         struct radeon_device *rdev = dev->dev_private;
4237         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4238         uint32_t bios_2_scratch;
4239
4240         if (ASIC_IS_DCE4(rdev))
4241                 return;
4242
4243         if (rdev->family >= CHIP_R600)
4244                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4245         else
4246                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4247
4248         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4249                 if (on)
4250                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4251                 else
4252                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4253         }
4254         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4255                 if (on)
4256                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4257                 else
4258                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4259         }
4260         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4261                 if (on)
4262                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4263                 else
4264                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4265         }
4266         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4267                 if (on)
4268                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4269                 else
4270                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4271         }
4272         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4273                 if (on)
4274                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4275                 else
4276                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4277         }
4278         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4279                 if (on)
4280                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4281                 else
4282                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4283         }
4284         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4285                 if (on)
4286                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4287                 else
4288                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4289         }
4290         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4291                 if (on)
4292                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4293                 else
4294                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4295         }
4296         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4297                 if (on)
4298                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4299                 else
4300                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4301         }
4302         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4303                 if (on)
4304                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4305                 else
4306                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4307         }
4308
4309         if (rdev->family >= CHIP_R600)
4310                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4311         else
4312                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4313 }