2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
51 /* from radeon_legacy_encoder.c */
53 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
56 union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80 gpio = i2c_info->asGPIO_Info[id];
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
103 static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
106 struct radeon_i2c_bus_rec *i2c_bus,
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev->pdev->device == 0x791e) &&
112 (dev->pdev->subsystem_vendor == 0x1043) &&
113 (dev->pdev->subsystem_device == 0x826d)) {
114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
116 *connector_type = DRM_MODE_CONNECTOR_DVID;
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev->pdev->device == 0x7941) &&
121 (dev->pdev->subsystem_vendor == 0x147b) &&
122 (dev->pdev->subsystem_device == 0x2412)) {
123 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev->pdev->device == 0x5653) &&
129 (dev->pdev->subsystem_vendor == 0x1462) &&
130 (dev->pdev->subsystem_device == 0x0291)) {
131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
132 i2c_bus->valid = false;
137 /* HIS X1300 is DVI+VGA, not DVI+DVI */
138 if ((dev->pdev->device == 0x7146) &&
139 (dev->pdev->subsystem_vendor == 0x17af) &&
140 (dev->pdev->subsystem_device == 0x2058)) {
141 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
146 if ((dev->pdev->device == 0x71C5) &&
147 (dev->pdev->subsystem_vendor == 0x106b) &&
148 (dev->pdev->subsystem_device == 0x0080)) {
149 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
150 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
154 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
155 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
156 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
157 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
162 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
163 if ((dev->pdev->device == 0x9598) &&
164 (dev->pdev->subsystem_vendor == 0x1043) &&
165 (dev->pdev->subsystem_device == 0x01da)) {
166 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
167 *connector_type = DRM_MODE_CONNECTOR_DVID;
174 const int supported_devices_connector_convert[] = {
175 DRM_MODE_CONNECTOR_Unknown,
176 DRM_MODE_CONNECTOR_VGA,
177 DRM_MODE_CONNECTOR_DVII,
178 DRM_MODE_CONNECTOR_DVID,
179 DRM_MODE_CONNECTOR_DVIA,
180 DRM_MODE_CONNECTOR_SVIDEO,
181 DRM_MODE_CONNECTOR_Composite,
182 DRM_MODE_CONNECTOR_LVDS,
183 DRM_MODE_CONNECTOR_Unknown,
184 DRM_MODE_CONNECTOR_Unknown,
185 DRM_MODE_CONNECTOR_HDMIA,
186 DRM_MODE_CONNECTOR_HDMIB,
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_Unknown,
189 DRM_MODE_CONNECTOR_9PinDIN,
190 DRM_MODE_CONNECTOR_DisplayPort
193 const int object_connector_convert[] = {
194 DRM_MODE_CONNECTOR_Unknown,
195 DRM_MODE_CONNECTOR_DVII,
196 DRM_MODE_CONNECTOR_DVII,
197 DRM_MODE_CONNECTOR_DVID,
198 DRM_MODE_CONNECTOR_DVID,
199 DRM_MODE_CONNECTOR_VGA,
200 DRM_MODE_CONNECTOR_Composite,
201 DRM_MODE_CONNECTOR_SVIDEO,
202 DRM_MODE_CONNECTOR_Unknown,
203 DRM_MODE_CONNECTOR_9PinDIN,
204 DRM_MODE_CONNECTOR_Unknown,
205 DRM_MODE_CONNECTOR_HDMIA,
206 DRM_MODE_CONNECTOR_HDMIB,
207 DRM_MODE_CONNECTOR_HDMIB,
208 DRM_MODE_CONNECTOR_LVDS,
209 DRM_MODE_CONNECTOR_9PinDIN,
210 DRM_MODE_CONNECTOR_Unknown,
211 DRM_MODE_CONNECTOR_Unknown,
212 DRM_MODE_CONNECTOR_Unknown,
213 DRM_MODE_CONNECTOR_DisplayPort
216 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
218 struct radeon_device *rdev = dev->dev_private;
219 struct radeon_mode_info *mode_info = &rdev->mode_info;
220 struct atom_context *ctx = mode_info->atom_context;
221 int index = GetIndexIntoMasterTable(DATA, Object_Header);
222 uint16_t size, data_offset;
223 uint8_t frev, crev, line_mux = 0;
224 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
225 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
226 ATOM_OBJECT_HEADER *obj_header;
227 int i, j, path_size, device_support;
229 uint16_t igp_lane_info;
231 struct radeon_i2c_bus_rec ddc_bus;
233 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
235 if (data_offset == 0)
241 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
242 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
243 (ctx->bios + data_offset +
244 le16_to_cpu(obj_header->usDisplayPathTableOffset));
245 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
246 (ctx->bios + data_offset +
247 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
248 device_support = le16_to_cpu(obj_header->usDeviceSupport);
251 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
252 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
253 ATOM_DISPLAY_OBJECT_PATH *path;
255 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
256 path_size += le16_to_cpu(path->usSize);
259 if (device_support & le16_to_cpu(path->usDeviceTag)) {
260 uint8_t con_obj_id, con_obj_num, con_obj_type;
263 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
266 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
269 (le16_to_cpu(path->usConnObjectId) &
270 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
272 if ((le16_to_cpu(path->usDeviceTag) ==
273 ATOM_DEVICE_TV1_SUPPORT)
274 || (le16_to_cpu(path->usDeviceTag) ==
275 ATOM_DEVICE_TV2_SUPPORT)
276 || (le16_to_cpu(path->usDeviceTag) ==
277 ATOM_DEVICE_CV_SUPPORT))
280 if ((rdev->family == CHIP_RS780) &&
282 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
283 uint16_t igp_offset = 0;
284 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
287 GetIndexIntoMasterTable(DATA,
288 IntegratedSystemInfo);
290 atom_parse_data_header(ctx, index, &size, &frev,
295 (ATOM_INTEGRATED_SYSTEM_INFO_V2
296 *) (ctx->bios + igp_offset);
299 uint32_t slot_config, ct;
301 if (con_obj_num == 1)
310 ct = (slot_config >> 16) & 0xff;
312 object_connector_convert
315 slot_config & 0xffff;
323 object_connector_convert[con_obj_id];
326 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
329 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
331 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
334 (le16_to_cpu(path->usGraphicObjIds[j]) &
335 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
337 (le16_to_cpu(path->usGraphicObjIds[j]) &
338 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
340 (le16_to_cpu(path->usGraphicObjIds[j]) &
341 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
343 /* FIXME: add support for router objects */
344 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
345 if (enc_obj_num == 2)
350 radeon_add_atom_encoder(dev,
359 /* look up gpio for ddc */
360 if ((le16_to_cpu(path->usDeviceTag) &
361 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
363 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
364 if (le16_to_cpu(path->usConnObjectId) ==
365 le16_to_cpu(con_obj->asObjects[j].
367 ATOM_COMMON_RECORD_HEADER
369 (ATOM_COMMON_RECORD_HEADER
371 (ctx->bios + data_offset +
372 le16_to_cpu(con_obj->
375 ATOM_I2C_RECORD *i2c_record;
377 while (record->ucRecordType > 0
380 ATOM_MAX_OBJECT_RECORD_NUMBER) {
387 case ATOM_I2C_RECORD_TYPE:
398 (ATOM_COMMON_RECORD_HEADER
410 if ((le16_to_cpu(path->usDeviceTag) ==
411 ATOM_DEVICE_TV1_SUPPORT)
412 || (le16_to_cpu(path->usDeviceTag) ==
413 ATOM_DEVICE_TV2_SUPPORT)
414 || (le16_to_cpu(path->usDeviceTag) ==
415 ATOM_DEVICE_CV_SUPPORT))
416 ddc_bus.valid = false;
418 ddc_bus = radeon_lookup_gpio(dev, line_mux);
420 radeon_add_atom_connector(dev,
425 connector_type, &ddc_bus,
426 linkb, igp_lane_info);
431 radeon_link_encoder_connector(dev);
436 struct bios_connector {
441 struct radeon_i2c_bus_rec ddc_bus;
444 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
448 struct radeon_device *rdev = dev->dev_private;
449 struct radeon_mode_info *mode_info = &rdev->mode_info;
450 struct atom_context *ctx = mode_info->atom_context;
451 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
452 uint16_t size, data_offset;
454 uint16_t device_support;
456 union atom_supported_devices *supported_devices;
458 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
460 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
463 (union atom_supported_devices *)(ctx->bios + data_offset);
465 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
467 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
468 ATOM_CONNECTOR_INFO_I2C ci =
469 supported_devices->info.asConnInfo[i];
471 bios_connectors[i].valid = false;
473 if (!(device_support & (1 << i))) {
477 if (i == ATOM_DEVICE_CV_INDEX) {
478 DRM_DEBUG("Skipping Component Video\n");
482 if (i == ATOM_DEVICE_TV1_INDEX) {
483 DRM_DEBUG("Skipping TV Out\n");
487 bios_connectors[i].connector_type =
488 supported_devices_connector_convert[ci.sucConnectorInfo.
492 if (bios_connectors[i].connector_type ==
493 DRM_MODE_CONNECTOR_Unknown)
496 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
498 if ((rdev->family == CHIP_RS690) ||
499 (rdev->family == CHIP_RS740)) {
500 if ((i == ATOM_DEVICE_DFP2_INDEX)
501 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
502 bios_connectors[i].line_mux =
503 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
504 else if ((i == ATOM_DEVICE_DFP3_INDEX)
505 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
506 bios_connectors[i].line_mux =
507 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
509 bios_connectors[i].line_mux =
510 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
512 bios_connectors[i].line_mux =
513 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
515 /* give tv unique connector ids */
516 if (i == ATOM_DEVICE_TV1_INDEX) {
517 bios_connectors[i].ddc_bus.valid = false;
518 bios_connectors[i].line_mux = 50;
519 } else if (i == ATOM_DEVICE_TV2_INDEX) {
520 bios_connectors[i].ddc_bus.valid = false;
521 bios_connectors[i].line_mux = 51;
522 } else if (i == ATOM_DEVICE_CV_INDEX) {
523 bios_connectors[i].ddc_bus.valid = false;
524 bios_connectors[i].line_mux = 52;
526 bios_connectors[i].ddc_bus =
527 radeon_lookup_gpio(dev,
528 bios_connectors[i].line_mux);
530 /* Always set the connector type to VGA for CRT1/CRT2. if they are
531 * shared with a DVI port, we'll pick up the DVI connector when we
532 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
534 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
535 bios_connectors[i].connector_type =
536 DRM_MODE_CONNECTOR_VGA;
538 if (!radeon_atom_apply_quirks
539 (dev, (1 << i), &bios_connectors[i].connector_type,
540 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
543 bios_connectors[i].valid = true;
544 bios_connectors[i].devices = (1 << i);
546 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
547 radeon_add_atom_encoder(dev,
548 radeon_get_encoder_id(dev,
553 radeon_add_legacy_encoder(dev,
554 radeon_get_encoder_id(dev,
561 /* combine shared connectors */
562 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
563 if (bios_connectors[i].valid) {
564 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
565 if (bios_connectors[j].valid && (i != j)) {
566 if (bios_connectors[i].line_mux ==
567 bios_connectors[j].line_mux) {
568 if (((bios_connectors[i].
570 (ATOM_DEVICE_DFP_SUPPORT))
571 && (bios_connectors[j].
573 (ATOM_DEVICE_CRT_SUPPORT)))
575 ((bios_connectors[j].
577 (ATOM_DEVICE_DFP_SUPPORT))
578 && (bios_connectors[i].
580 (ATOM_DEVICE_CRT_SUPPORT)))) {
587 DRM_MODE_CONNECTOR_DVII;
597 /* add the connectors */
598 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
599 if (bios_connectors[i].valid)
600 radeon_add_atom_connector(dev,
601 bios_connectors[i].line_mux,
602 bios_connectors[i].devices,
605 &bios_connectors[i].ddc_bus,
609 radeon_link_encoder_connector(dev);
614 union firmware_info {
615 ATOM_FIRMWARE_INFO info;
616 ATOM_FIRMWARE_INFO_V1_2 info_12;
617 ATOM_FIRMWARE_INFO_V1_3 info_13;
618 ATOM_FIRMWARE_INFO_V1_4 info_14;
621 bool radeon_atom_get_clock_info(struct drm_device *dev)
623 struct radeon_device *rdev = dev->dev_private;
624 struct radeon_mode_info *mode_info = &rdev->mode_info;
625 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
626 union firmware_info *firmware_info;
628 struct radeon_pll *p1pll = &rdev->clock.p1pll;
629 struct radeon_pll *p2pll = &rdev->clock.p2pll;
630 struct radeon_pll *spll = &rdev->clock.spll;
631 struct radeon_pll *mpll = &rdev->clock.mpll;
632 uint16_t data_offset;
634 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
635 &crev, &data_offset);
638 (union firmware_info *)(mode_info->atom_context->bios +
643 p1pll->reference_freq =
644 le16_to_cpu(firmware_info->info.usReferenceClock);
645 p1pll->reference_div = 0;
648 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
650 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
652 if (p1pll->pll_out_min == 0) {
653 if (ASIC_IS_AVIVO(rdev))
654 p1pll->pll_out_min = 64800;
656 p1pll->pll_out_min = 20000;
660 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
662 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
667 spll->reference_freq =
668 le16_to_cpu(firmware_info->info.usReferenceClock);
669 spll->reference_div = 0;
672 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
674 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
677 if (spll->pll_out_min == 0) {
678 if (ASIC_IS_AVIVO(rdev))
679 spll->pll_out_min = 64800;
681 spll->pll_out_min = 20000;
685 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
687 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
690 mpll->reference_freq =
691 le16_to_cpu(firmware_info->info.usReferenceClock);
692 mpll->reference_div = 0;
695 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
697 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
700 if (mpll->pll_out_min == 0) {
701 if (ASIC_IS_AVIVO(rdev))
702 mpll->pll_out_min = 64800;
704 mpll->pll_out_min = 20000;
708 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
710 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
712 rdev->clock.default_sclk =
713 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
714 rdev->clock.default_mclk =
715 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
722 struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
726 struct drm_device *dev = encoder->base.dev;
727 struct radeon_device *rdev = dev->dev_private;
728 struct radeon_mode_info *mode_info = &rdev->mode_info;
729 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
730 uint16_t data_offset;
731 struct _ATOM_TMDS_INFO *tmds_info;
735 struct radeon_encoder_int_tmds *tmds = NULL;
737 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
738 &crev, &data_offset);
741 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
746 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
751 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
752 for (i = 0; i < 4; i++) {
753 tmds->tmds_pll[i].freq =
754 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
755 tmds->tmds_pll[i].value =
756 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
757 tmds->tmds_pll[i].value |=
758 (tmds_info->asMiscInfo[i].
759 ucPLL_VCO_Gain & 0x3f) << 6;
760 tmds->tmds_pll[i].value |=
761 (tmds_info->asMiscInfo[i].
762 ucPLL_DutyCycle & 0xf) << 12;
763 tmds->tmds_pll[i].value |=
764 (tmds_info->asMiscInfo[i].
765 ucPLL_VoltageSwing & 0xf) << 16;
767 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
768 tmds->tmds_pll[i].freq,
769 tmds->tmds_pll[i].value);
771 if (maxfreq == tmds->tmds_pll[i].freq) {
772 tmds->tmds_pll[i].freq = 0xffffffff;
781 struct _ATOM_LVDS_INFO info;
782 struct _ATOM_LVDS_INFO_V12 info_12;
785 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
789 struct drm_device *dev = encoder->base.dev;
790 struct radeon_device *rdev = dev->dev_private;
791 struct radeon_mode_info *mode_info = &rdev->mode_info;
792 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
793 uint16_t data_offset;
794 union lvds_info *lvds_info;
796 struct radeon_encoder_atom_dig *lvds = NULL;
798 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
799 &crev, &data_offset);
802 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
806 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
811 lvds->native_mode.dotclock =
812 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
813 lvds->native_mode.panel_xres =
814 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
815 lvds->native_mode.panel_yres =
816 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
817 lvds->native_mode.hblank =
818 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
819 lvds->native_mode.hoverplus =
820 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
821 lvds->native_mode.hsync_width =
822 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
823 lvds->native_mode.vblank =
824 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
825 lvds->native_mode.voverplus =
826 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
827 lvds->native_mode.vsync_width =
828 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
829 lvds->panel_pwr_delay =
830 le16_to_cpu(lvds_info->info.usOffDelayInMs);
831 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
833 encoder->native_mode = lvds->native_mode;
838 struct radeon_encoder_primary_dac *
839 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
841 struct drm_device *dev = encoder->base.dev;
842 struct radeon_device *rdev = dev->dev_private;
843 struct radeon_mode_info *mode_info = &rdev->mode_info;
844 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
845 uint16_t data_offset;
846 struct _COMPASSIONATE_DATA *dac_info;
849 struct radeon_encoder_primary_dac *p_dac = NULL;
851 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
853 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
856 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
861 bg = dac_info->ucDAC1_BG_Adjustment;
862 dac = dac_info->ucDAC1_DAC_Adjustment;
863 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
869 struct radeon_encoder_tv_dac *
870 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
872 struct drm_device *dev = encoder->base.dev;
873 struct radeon_device *rdev = dev->dev_private;
874 struct radeon_mode_info *mode_info = &rdev->mode_info;
875 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
876 uint16_t data_offset;
877 struct _COMPASSIONATE_DATA *dac_info;
880 struct radeon_encoder_tv_dac *tv_dac = NULL;
882 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
884 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
887 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
892 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
893 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
894 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
896 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
897 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
898 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
900 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
901 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
902 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
908 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
910 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
911 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
913 args.ucEnable = enable;
915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
918 void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
920 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
921 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
923 args.ucEnable = enable;
925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
928 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
931 SET_ENGINE_CLOCK_PS_ALLOCATION args;
932 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
934 args.ulTargetEngineClock = eng_clock; /* 10 khz */
936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
939 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
942 SET_MEMORY_CLOCK_PS_ALLOCATION args;
943 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
945 if (rdev->flags & RADEON_IS_IGP)
948 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
950 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
953 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
955 struct radeon_device *rdev = dev->dev_private;
956 uint32_t bios_2_scratch, bios_6_scratch;
958 if (rdev->family >= CHIP_R600) {
959 bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
960 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
962 bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
963 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
966 /* let the bios control the backlight */
967 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
969 /* tell the bios not to handle mode switching */
970 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
972 if (rdev->family >= CHIP_R600) {
973 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
974 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
976 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
977 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
982 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
984 struct drm_device *dev = encoder->dev;
985 struct radeon_device *rdev = dev->dev_private;
986 uint32_t bios_6_scratch;
988 if (rdev->family >= CHIP_R600)
989 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
991 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
994 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
996 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
998 if (rdev->family >= CHIP_R600)
999 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1001 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1004 /* at some point we may want to break this out into individual functions */
1006 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1007 struct drm_encoder *encoder,
1010 struct drm_device *dev = connector->dev;
1011 struct radeon_device *rdev = dev->dev_private;
1012 struct radeon_connector *radeon_connector =
1013 to_radeon_connector(connector);
1014 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1015 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1017 if (rdev->family >= CHIP_R600) {
1018 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1019 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1020 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1022 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1023 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1024 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1027 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1028 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1030 DRM_DEBUG("TV1 connected\n");
1031 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1032 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1034 DRM_DEBUG("TV1 disconnected\n");
1035 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1036 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1037 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1040 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1041 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1043 DRM_DEBUG("CV connected\n");
1044 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1045 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1047 DRM_DEBUG("CV disconnected\n");
1048 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1049 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1050 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1053 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1054 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1056 DRM_DEBUG("LCD1 connected\n");
1057 bios_0_scratch |= ATOM_S0_LCD1;
1058 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1059 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1061 DRM_DEBUG("LCD1 disconnected\n");
1062 bios_0_scratch &= ~ATOM_S0_LCD1;
1063 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1064 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1067 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1068 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1070 DRM_DEBUG("CRT1 connected\n");
1071 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1072 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1073 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1075 DRM_DEBUG("CRT1 disconnected\n");
1076 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1077 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1078 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1081 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1082 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1084 DRM_DEBUG("CRT2 connected\n");
1085 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1086 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1087 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1089 DRM_DEBUG("CRT2 disconnected\n");
1090 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1091 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1092 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1095 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1096 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1098 DRM_DEBUG("DFP1 connected\n");
1099 bios_0_scratch |= ATOM_S0_DFP1;
1100 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1101 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1103 DRM_DEBUG("DFP1 disconnected\n");
1104 bios_0_scratch &= ~ATOM_S0_DFP1;
1105 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1106 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1109 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1110 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1112 DRM_DEBUG("DFP2 connected\n");
1113 bios_0_scratch |= ATOM_S0_DFP2;
1114 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1115 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1117 DRM_DEBUG("DFP2 disconnected\n");
1118 bios_0_scratch &= ~ATOM_S0_DFP2;
1119 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1120 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1123 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1124 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1126 DRM_DEBUG("DFP3 connected\n");
1127 bios_0_scratch |= ATOM_S0_DFP3;
1128 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1129 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1131 DRM_DEBUG("DFP3 disconnected\n");
1132 bios_0_scratch &= ~ATOM_S0_DFP3;
1133 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1134 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1137 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1138 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1140 DRM_DEBUG("DFP4 connected\n");
1141 bios_0_scratch |= ATOM_S0_DFP4;
1142 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1143 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1145 DRM_DEBUG("DFP4 disconnected\n");
1146 bios_0_scratch &= ~ATOM_S0_DFP4;
1147 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1148 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1151 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1152 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1154 DRM_DEBUG("DFP5 connected\n");
1155 bios_0_scratch |= ATOM_S0_DFP5;
1156 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1157 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1159 DRM_DEBUG("DFP5 disconnected\n");
1160 bios_0_scratch &= ~ATOM_S0_DFP5;
1161 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1162 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1166 if (rdev->family >= CHIP_R600) {
1167 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1168 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1169 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1171 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1172 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1173 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1178 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1180 struct drm_device *dev = encoder->dev;
1181 struct radeon_device *rdev = dev->dev_private;
1182 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1183 uint32_t bios_3_scratch;
1185 if (rdev->family >= CHIP_R600)
1186 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1188 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1190 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1191 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1192 bios_3_scratch |= (crtc << 18);
1194 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1195 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1196 bios_3_scratch |= (crtc << 24);
1198 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1199 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1200 bios_3_scratch |= (crtc << 16);
1202 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1203 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1204 bios_3_scratch |= (crtc << 20);
1206 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1207 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1208 bios_3_scratch |= (crtc << 17);
1210 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1211 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1212 bios_3_scratch |= (crtc << 19);
1214 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1215 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1216 bios_3_scratch |= (crtc << 23);
1218 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1219 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1220 bios_3_scratch |= (crtc << 25);
1223 if (rdev->family >= CHIP_R600)
1224 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1226 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1230 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1232 struct drm_device *dev = encoder->dev;
1233 struct radeon_device *rdev = dev->dev_private;
1234 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1235 uint32_t bios_2_scratch;
1237 if (rdev->family >= CHIP_R600)
1238 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1240 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1242 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1244 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1246 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1248 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1250 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1252 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1254 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1256 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1258 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1260 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1262 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1264 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1266 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1268 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1270 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1272 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1274 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1276 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1278 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1280 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1282 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1284 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1286 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1288 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1290 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1292 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1294 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1296 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1298 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1300 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1303 if (rdev->family >= CHIP_R600)
1304 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1306 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);