2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
57 uint32_t supported_device);
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
88 if (gpio->sucI2cId.ucAccess == id) {
89 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
90 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
91 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
92 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
93 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
94 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
95 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
96 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
97 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
98 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
99 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
100 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
101 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
102 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
103 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
104 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
106 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
107 i2c.hw_capable = true;
109 i2c.hw_capable = false;
111 if (gpio->sucI2cId.ucAccess == 0xa0)
116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
118 if (i2c.mask_clk_reg)
128 void radeon_atombios_i2c_init(struct radeon_device *rdev)
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
170 i2c.hw_capable = false;
172 if (gpio->sucI2cId.ucAccess == 0xa0)
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
179 if (i2c.mask_clk_reg) {
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
188 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
191 struct atom_context *ctx = rdev->mode_info.atom_context;
192 struct radeon_gpio_rec gpio;
193 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
194 struct _ATOM_GPIO_PIN_LUT *gpio_info;
195 ATOM_GPIO_PIN_ASSIGNMENT *pin;
196 u16 data_offset, size;
199 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
202 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
203 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
205 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
206 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
208 for (i = 0; i < num_indices; i++) {
209 pin = &gpio_info->asGPIO_Pin[i];
210 if (id == pin->ucGPIO_ID) {
211 gpio.id = pin->ucGPIO_ID;
212 gpio.reg = pin->usGpioPin_AIndex * 4;
213 gpio.mask = (1 << pin->ucGpioPinBitShift);
223 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
224 struct radeon_gpio_rec *gpio)
226 struct radeon_hpd hpd;
229 if (ASIC_IS_DCE4(rdev))
230 reg = EVERGREEN_DC_GPIO_HPD_A;
232 reg = AVIVO_DC_GPIO_HPD_A;
235 if (gpio->reg == reg) {
238 hpd.hpd = RADEON_HPD_1;
241 hpd.hpd = RADEON_HPD_2;
244 hpd.hpd = RADEON_HPD_3;
247 hpd.hpd = RADEON_HPD_4;
250 hpd.hpd = RADEON_HPD_5;
253 hpd.hpd = RADEON_HPD_6;
256 hpd.hpd = RADEON_HPD_NONE;
260 hpd.hpd = RADEON_HPD_NONE;
264 static bool radeon_atom_apply_quirks(struct drm_device *dev,
265 uint32_t supported_device,
267 struct radeon_i2c_bus_rec *i2c_bus,
269 struct radeon_hpd *hpd)
272 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
273 if ((dev->pdev->device == 0x791e) &&
274 (dev->pdev->subsystem_vendor == 0x1043) &&
275 (dev->pdev->subsystem_device == 0x826d)) {
276 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
277 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
278 *connector_type = DRM_MODE_CONNECTOR_DVID;
281 /* Asrock RS600 board lists the DVI port as HDMI */
282 if ((dev->pdev->device == 0x7941) &&
283 (dev->pdev->subsystem_vendor == 0x1849) &&
284 (dev->pdev->subsystem_device == 0x7941)) {
285 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
286 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
287 *connector_type = DRM_MODE_CONNECTOR_DVID;
290 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
291 if ((dev->pdev->device == 0x7941) &&
292 (dev->pdev->subsystem_vendor == 0x147b) &&
293 (dev->pdev->subsystem_device == 0x2412)) {
294 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
298 /* Falcon NW laptop lists vga ddc line for LVDS */
299 if ((dev->pdev->device == 0x5653) &&
300 (dev->pdev->subsystem_vendor == 0x1462) &&
301 (dev->pdev->subsystem_device == 0x0291)) {
302 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
303 i2c_bus->valid = false;
308 /* HIS X1300 is DVI+VGA, not DVI+DVI */
309 if ((dev->pdev->device == 0x7146) &&
310 (dev->pdev->subsystem_vendor == 0x17af) &&
311 (dev->pdev->subsystem_device == 0x2058)) {
312 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
316 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
317 if ((dev->pdev->device == 0x7142) &&
318 (dev->pdev->subsystem_vendor == 0x1458) &&
319 (dev->pdev->subsystem_device == 0x2134)) {
320 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
326 if ((dev->pdev->device == 0x71C5) &&
327 (dev->pdev->subsystem_vendor == 0x106b) &&
328 (dev->pdev->subsystem_device == 0x0080)) {
329 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
330 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
332 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
336 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
337 if ((dev->pdev->device == 0x9598) &&
338 (dev->pdev->subsystem_vendor == 0x1043) &&
339 (dev->pdev->subsystem_device == 0x01da)) {
340 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
341 *connector_type = DRM_MODE_CONNECTOR_DVII;
345 /* ASUS HD 3600 board lists the DVI port as HDMI */
346 if ((dev->pdev->device == 0x9598) &&
347 (dev->pdev->subsystem_vendor == 0x1043) &&
348 (dev->pdev->subsystem_device == 0x01e4)) {
349 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
350 *connector_type = DRM_MODE_CONNECTOR_DVII;
354 /* ASUS HD 3450 board lists the DVI port as HDMI */
355 if ((dev->pdev->device == 0x95C5) &&
356 (dev->pdev->subsystem_vendor == 0x1043) &&
357 (dev->pdev->subsystem_device == 0x01e2)) {
358 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
359 *connector_type = DRM_MODE_CONNECTOR_DVII;
363 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
364 * HDMI + VGA reporting as HDMI
366 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
367 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
368 *connector_type = DRM_MODE_CONNECTOR_VGA;
373 /* Acer laptop reports DVI-D as DVI-I */
374 if ((dev->pdev->device == 0x95c4) &&
375 (dev->pdev->subsystem_vendor == 0x1025) &&
376 (dev->pdev->subsystem_device == 0x013c)) {
377 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
378 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
379 *connector_type = DRM_MODE_CONNECTOR_DVID;
382 /* XFX Pine Group device rv730 reports no VGA DDC lines
383 * even though they are wired up to record 0x93
385 if ((dev->pdev->device == 0x9498) &&
386 (dev->pdev->subsystem_vendor == 0x1682) &&
387 (dev->pdev->subsystem_device == 0x2452)) {
388 struct radeon_device *rdev = dev->dev_private;
389 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
394 const int supported_devices_connector_convert[] = {
395 DRM_MODE_CONNECTOR_Unknown,
396 DRM_MODE_CONNECTOR_VGA,
397 DRM_MODE_CONNECTOR_DVII,
398 DRM_MODE_CONNECTOR_DVID,
399 DRM_MODE_CONNECTOR_DVIA,
400 DRM_MODE_CONNECTOR_SVIDEO,
401 DRM_MODE_CONNECTOR_Composite,
402 DRM_MODE_CONNECTOR_LVDS,
403 DRM_MODE_CONNECTOR_Unknown,
404 DRM_MODE_CONNECTOR_Unknown,
405 DRM_MODE_CONNECTOR_HDMIA,
406 DRM_MODE_CONNECTOR_HDMIB,
407 DRM_MODE_CONNECTOR_Unknown,
408 DRM_MODE_CONNECTOR_Unknown,
409 DRM_MODE_CONNECTOR_9PinDIN,
410 DRM_MODE_CONNECTOR_DisplayPort
413 const uint16_t supported_devices_connector_object_id_convert[] = {
414 CONNECTOR_OBJECT_ID_NONE,
415 CONNECTOR_OBJECT_ID_VGA,
416 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
417 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
418 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
419 CONNECTOR_OBJECT_ID_COMPOSITE,
420 CONNECTOR_OBJECT_ID_SVIDEO,
421 CONNECTOR_OBJECT_ID_LVDS,
422 CONNECTOR_OBJECT_ID_9PIN_DIN,
423 CONNECTOR_OBJECT_ID_9PIN_DIN,
424 CONNECTOR_OBJECT_ID_DISPLAYPORT,
425 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
426 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
427 CONNECTOR_OBJECT_ID_SVIDEO
430 const int object_connector_convert[] = {
431 DRM_MODE_CONNECTOR_Unknown,
432 DRM_MODE_CONNECTOR_DVII,
433 DRM_MODE_CONNECTOR_DVII,
434 DRM_MODE_CONNECTOR_DVID,
435 DRM_MODE_CONNECTOR_DVID,
436 DRM_MODE_CONNECTOR_VGA,
437 DRM_MODE_CONNECTOR_Composite,
438 DRM_MODE_CONNECTOR_SVIDEO,
439 DRM_MODE_CONNECTOR_Unknown,
440 DRM_MODE_CONNECTOR_Unknown,
441 DRM_MODE_CONNECTOR_9PinDIN,
442 DRM_MODE_CONNECTOR_Unknown,
443 DRM_MODE_CONNECTOR_HDMIA,
444 DRM_MODE_CONNECTOR_HDMIB,
445 DRM_MODE_CONNECTOR_LVDS,
446 DRM_MODE_CONNECTOR_9PinDIN,
447 DRM_MODE_CONNECTOR_Unknown,
448 DRM_MODE_CONNECTOR_Unknown,
449 DRM_MODE_CONNECTOR_Unknown,
450 DRM_MODE_CONNECTOR_DisplayPort,
451 DRM_MODE_CONNECTOR_eDP,
452 DRM_MODE_CONNECTOR_Unknown
455 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
457 struct radeon_device *rdev = dev->dev_private;
458 struct radeon_mode_info *mode_info = &rdev->mode_info;
459 struct atom_context *ctx = mode_info->atom_context;
460 int index = GetIndexIntoMasterTable(DATA, Object_Header);
461 u16 size, data_offset;
463 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
464 ATOM_OBJECT_TABLE *router_obj;
465 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
466 ATOM_OBJECT_HEADER *obj_header;
467 int i, j, k, path_size, device_support;
469 u16 igp_lane_info, conn_id, connector_object_id;
471 struct radeon_i2c_bus_rec ddc_bus;
472 struct radeon_router router;
473 struct radeon_gpio_rec gpio;
474 struct radeon_hpd hpd;
476 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
482 router.valid = false;
484 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
485 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
486 (ctx->bios + data_offset +
487 le16_to_cpu(obj_header->usDisplayPathTableOffset));
488 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
489 (ctx->bios + data_offset +
490 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
491 router_obj = (ATOM_OBJECT_TABLE *)
492 (ctx->bios + data_offset +
493 le16_to_cpu(obj_header->usRouterObjectTableOffset));
494 device_support = le16_to_cpu(obj_header->usDeviceSupport);
497 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
498 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
499 ATOM_DISPLAY_OBJECT_PATH *path;
501 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
502 path_size += le16_to_cpu(path->usSize);
504 if (device_support & le16_to_cpu(path->usDeviceTag)) {
505 uint8_t con_obj_id, con_obj_num, con_obj_type;
508 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
511 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
514 (le16_to_cpu(path->usConnObjectId) &
515 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
517 /* TODO CV support */
518 if (le16_to_cpu(path->usDeviceTag) ==
519 ATOM_DEVICE_CV_SUPPORT)
523 if ((rdev->flags & RADEON_IS_IGP) &&
525 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
526 uint16_t igp_offset = 0;
527 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
530 GetIndexIntoMasterTable(DATA,
531 IntegratedSystemInfo);
533 if (atom_parse_data_header(ctx, index, &size, &frev,
534 &crev, &igp_offset)) {
538 (ATOM_INTEGRATED_SYSTEM_INFO_V2
539 *) (ctx->bios + igp_offset);
542 uint32_t slot_config, ct;
544 if (con_obj_num == 1)
553 ct = (slot_config >> 16) & 0xff;
555 object_connector_convert
557 connector_object_id = ct;
559 slot_config & 0xffff;
567 object_connector_convert[con_obj_id];
568 connector_object_id = con_obj_id;
573 object_connector_convert[con_obj_id];
574 connector_object_id = con_obj_id;
577 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
580 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
581 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
584 (le16_to_cpu(path->usGraphicObjIds[j]) &
585 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
587 (le16_to_cpu(path->usGraphicObjIds[j]) &
588 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
590 (le16_to_cpu(path->usGraphicObjIds[j]) &
591 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
593 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
594 if (grph_obj_num == 2)
599 radeon_add_atom_encoder(dev,
605 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
606 router.valid = false;
607 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
608 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
609 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
610 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
611 (ctx->bios + data_offset +
612 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
613 ATOM_I2C_RECORD *i2c_record;
614 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
615 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
616 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
617 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
618 (ctx->bios + data_offset +
619 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
622 router.router_id = router_obj_id;
623 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
625 if (le16_to_cpu(path->usConnObjectId) ==
626 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
630 while (record->ucRecordType > 0 &&
631 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
632 switch (record->ucRecordType) {
633 case ATOM_I2C_RECORD_TYPE:
638 (ATOM_I2C_ID_CONFIG_ACCESS *)
639 &i2c_record->sucI2cId;
641 radeon_lookup_i2c_gpio(rdev,
644 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
646 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
647 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
650 router.mux_type = ddc_path->ucMuxType;
651 router.mux_control_pin = ddc_path->ucMuxControlPin;
652 router.mux_state = ddc_path->ucMuxState[enum_id];
655 record = (ATOM_COMMON_RECORD_HEADER *)
656 ((char *)record + record->ucRecordSize);
663 /* look up gpio for ddc, hpd */
664 ddc_bus.valid = false;
665 hpd.hpd = RADEON_HPD_NONE;
666 if ((le16_to_cpu(path->usDeviceTag) &
667 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
668 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
669 if (le16_to_cpu(path->usConnObjectId) ==
670 le16_to_cpu(con_obj->asObjects[j].
672 ATOM_COMMON_RECORD_HEADER
674 (ATOM_COMMON_RECORD_HEADER
676 (ctx->bios + data_offset +
677 le16_to_cpu(con_obj->
680 ATOM_I2C_RECORD *i2c_record;
681 ATOM_HPD_INT_RECORD *hpd_record;
682 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
684 while (record->ucRecordType > 0
687 ATOM_MAX_OBJECT_RECORD_NUMBER) {
688 switch (record->ucRecordType) {
689 case ATOM_I2C_RECORD_TYPE:
694 (ATOM_I2C_ID_CONFIG_ACCESS *)
695 &i2c_record->sucI2cId;
696 ddc_bus = radeon_lookup_i2c_gpio(rdev,
700 case ATOM_HPD_INT_RECORD_TYPE:
702 (ATOM_HPD_INT_RECORD *)
704 gpio = radeon_lookup_gpio(rdev,
705 hpd_record->ucHPDIntGPIOID);
706 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
707 hpd.plugged_state = hpd_record->ucPlugged_PinState;
711 (ATOM_COMMON_RECORD_HEADER
722 /* needed for aux chan transactions */
723 ddc_bus.hpd = hpd.hpd;
725 conn_id = le16_to_cpu(path->usConnObjectId);
727 if (!radeon_atom_apply_quirks
728 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
729 &ddc_bus, &conn_id, &hpd))
732 radeon_add_atom_connector(dev,
736 connector_type, &ddc_bus,
737 linkb, igp_lane_info,
745 radeon_link_encoder_connector(dev);
750 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
754 struct radeon_device *rdev = dev->dev_private;
756 if (rdev->flags & RADEON_IS_IGP) {
757 return supported_devices_connector_object_id_convert
759 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
760 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
761 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
762 struct radeon_mode_info *mode_info = &rdev->mode_info;
763 struct atom_context *ctx = mode_info->atom_context;
764 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
765 uint16_t size, data_offset;
767 ATOM_XTMDS_INFO *xtmds;
769 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
770 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
772 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
773 if (connector_type == DRM_MODE_CONNECTOR_DVII)
774 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
776 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
778 if (connector_type == DRM_MODE_CONNECTOR_DVII)
779 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
781 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
784 return supported_devices_connector_object_id_convert
787 return supported_devices_connector_object_id_convert
792 struct bios_connector {
797 struct radeon_i2c_bus_rec ddc_bus;
798 struct radeon_hpd hpd;
801 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
805 struct radeon_device *rdev = dev->dev_private;
806 struct radeon_mode_info *mode_info = &rdev->mode_info;
807 struct atom_context *ctx = mode_info->atom_context;
808 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
809 uint16_t size, data_offset;
811 uint16_t device_support;
813 union atom_supported_devices *supported_devices;
814 int i, j, max_device;
815 struct bios_connector *bios_connectors;
816 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
817 struct radeon_router router;
819 router.valid = false;
821 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
822 if (!bios_connectors)
825 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
827 kfree(bios_connectors);
832 (union atom_supported_devices *)(ctx->bios + data_offset);
834 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
837 max_device = ATOM_MAX_SUPPORTED_DEVICE;
839 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
841 for (i = 0; i < max_device; i++) {
842 ATOM_CONNECTOR_INFO_I2C ci =
843 supported_devices->info.asConnInfo[i];
845 bios_connectors[i].valid = false;
847 if (!(device_support & (1 << i))) {
851 if (i == ATOM_DEVICE_CV_INDEX) {
852 DRM_DEBUG_KMS("Skipping Component Video\n");
856 bios_connectors[i].connector_type =
857 supported_devices_connector_convert[ci.sucConnectorInfo.
861 if (bios_connectors[i].connector_type ==
862 DRM_MODE_CONNECTOR_Unknown)
865 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
867 bios_connectors[i].line_mux =
868 ci.sucI2cId.ucAccess;
870 /* give tv unique connector ids */
871 if (i == ATOM_DEVICE_TV1_INDEX) {
872 bios_connectors[i].ddc_bus.valid = false;
873 bios_connectors[i].line_mux = 50;
874 } else if (i == ATOM_DEVICE_TV2_INDEX) {
875 bios_connectors[i].ddc_bus.valid = false;
876 bios_connectors[i].line_mux = 51;
877 } else if (i == ATOM_DEVICE_CV_INDEX) {
878 bios_connectors[i].ddc_bus.valid = false;
879 bios_connectors[i].line_mux = 52;
881 bios_connectors[i].ddc_bus =
882 radeon_lookup_i2c_gpio(rdev,
883 bios_connectors[i].line_mux);
885 if ((crev > 1) && (frev > 1)) {
886 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
889 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
892 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
895 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
899 if (i == ATOM_DEVICE_DFP1_INDEX)
900 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
901 else if (i == ATOM_DEVICE_DFP2_INDEX)
902 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
904 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
907 /* Always set the connector type to VGA for CRT1/CRT2. if they are
908 * shared with a DVI port, we'll pick up the DVI connector when we
909 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
911 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
912 bios_connectors[i].connector_type =
913 DRM_MODE_CONNECTOR_VGA;
915 if (!radeon_atom_apply_quirks
916 (dev, (1 << i), &bios_connectors[i].connector_type,
917 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
918 &bios_connectors[i].hpd))
921 bios_connectors[i].valid = true;
922 bios_connectors[i].devices = (1 << i);
924 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
925 radeon_add_atom_encoder(dev,
926 radeon_get_encoder_id(dev,
931 radeon_add_legacy_encoder(dev,
932 radeon_get_encoder_id(dev,
938 /* combine shared connectors */
939 for (i = 0; i < max_device; i++) {
940 if (bios_connectors[i].valid) {
941 for (j = 0; j < max_device; j++) {
942 if (bios_connectors[j].valid && (i != j)) {
943 if (bios_connectors[i].line_mux ==
944 bios_connectors[j].line_mux) {
945 /* make sure not to combine LVDS */
946 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
947 bios_connectors[i].line_mux = 53;
948 bios_connectors[i].ddc_bus.valid = false;
951 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
952 bios_connectors[j].line_mux = 53;
953 bios_connectors[j].ddc_bus.valid = false;
956 /* combine analog and digital for DVI-I */
957 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
958 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
959 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
960 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
961 bios_connectors[i].devices |=
962 bios_connectors[j].devices;
963 bios_connectors[i].connector_type =
964 DRM_MODE_CONNECTOR_DVII;
965 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
966 bios_connectors[i].hpd =
967 bios_connectors[j].hpd;
968 bios_connectors[j].valid = false;
976 /* add the connectors */
977 for (i = 0; i < max_device; i++) {
978 if (bios_connectors[i].valid) {
979 uint16_t connector_object_id =
980 atombios_get_connector_object_id(dev,
981 bios_connectors[i].connector_type,
982 bios_connectors[i].devices);
983 radeon_add_atom_connector(dev,
984 bios_connectors[i].line_mux,
985 bios_connectors[i].devices,
988 &bios_connectors[i].ddc_bus,
991 &bios_connectors[i].hpd,
996 radeon_link_encoder_connector(dev);
998 kfree(bios_connectors);
1002 union firmware_info {
1003 ATOM_FIRMWARE_INFO info;
1004 ATOM_FIRMWARE_INFO_V1_2 info_12;
1005 ATOM_FIRMWARE_INFO_V1_3 info_13;
1006 ATOM_FIRMWARE_INFO_V1_4 info_14;
1007 ATOM_FIRMWARE_INFO_V2_1 info_21;
1010 bool radeon_atom_get_clock_info(struct drm_device *dev)
1012 struct radeon_device *rdev = dev->dev_private;
1013 struct radeon_mode_info *mode_info = &rdev->mode_info;
1014 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1015 union firmware_info *firmware_info;
1017 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1018 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1019 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1020 struct radeon_pll *spll = &rdev->clock.spll;
1021 struct radeon_pll *mpll = &rdev->clock.mpll;
1022 uint16_t data_offset;
1024 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1025 &frev, &crev, &data_offset)) {
1027 (union firmware_info *)(mode_info->atom_context->bios +
1030 p1pll->reference_freq =
1031 le16_to_cpu(firmware_info->info.usReferenceClock);
1032 p1pll->reference_div = 0;
1035 p1pll->pll_out_min =
1036 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1038 p1pll->pll_out_min =
1039 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1040 p1pll->pll_out_max =
1041 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1044 p1pll->lcd_pll_out_min =
1045 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1046 if (p1pll->lcd_pll_out_min == 0)
1047 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1048 p1pll->lcd_pll_out_max =
1049 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1050 if (p1pll->lcd_pll_out_max == 0)
1051 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1053 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1054 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1057 if (p1pll->pll_out_min == 0) {
1058 if (ASIC_IS_AVIVO(rdev))
1059 p1pll->pll_out_min = 64800;
1061 p1pll->pll_out_min = 20000;
1062 } else if (p1pll->pll_out_min > 64800) {
1063 /* Limiting the pll output range is a good thing generally as
1064 * it limits the number of possible pll combinations for a given
1065 * frequency presumably to the ones that work best on each card.
1066 * However, certain duallink DVI monitors seem to like
1067 * pll combinations that would be limited by this at least on
1068 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1071 if (!radeon_new_pll)
1072 p1pll->pll_out_min = 64800;
1076 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1078 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1083 spll->reference_freq =
1084 le16_to_cpu(firmware_info->info.usReferenceClock);
1085 spll->reference_div = 0;
1088 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1090 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1093 if (spll->pll_out_min == 0) {
1094 if (ASIC_IS_AVIVO(rdev))
1095 spll->pll_out_min = 64800;
1097 spll->pll_out_min = 20000;
1101 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1103 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1106 mpll->reference_freq =
1107 le16_to_cpu(firmware_info->info.usReferenceClock);
1108 mpll->reference_div = 0;
1111 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1113 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1116 if (mpll->pll_out_min == 0) {
1117 if (ASIC_IS_AVIVO(rdev))
1118 mpll->pll_out_min = 64800;
1120 mpll->pll_out_min = 20000;
1124 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1126 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1128 rdev->clock.default_sclk =
1129 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1130 rdev->clock.default_mclk =
1131 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1133 if (ASIC_IS_DCE4(rdev)) {
1134 rdev->clock.default_dispclk =
1135 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1136 if (rdev->clock.default_dispclk == 0)
1137 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1138 rdev->clock.dp_extclk =
1139 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1150 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1151 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1154 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1156 struct radeon_mode_info *mode_info = &rdev->mode_info;
1157 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1158 union igp_info *igp_info;
1162 /* sideport is AMD only */
1163 if (rdev->family == CHIP_RS600)
1166 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1167 &frev, &crev, &data_offset)) {
1168 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1172 if (igp_info->info.ulBootUpMemoryClock)
1176 if (igp_info->info_2.ucMemoryType & 0x0f)
1180 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1187 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1188 struct radeon_encoder_int_tmds *tmds)
1190 struct drm_device *dev = encoder->base.dev;
1191 struct radeon_device *rdev = dev->dev_private;
1192 struct radeon_mode_info *mode_info = &rdev->mode_info;
1193 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1194 uint16_t data_offset;
1195 struct _ATOM_TMDS_INFO *tmds_info;
1200 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1201 &frev, &crev, &data_offset)) {
1203 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1206 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1207 for (i = 0; i < 4; i++) {
1208 tmds->tmds_pll[i].freq =
1209 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1210 tmds->tmds_pll[i].value =
1211 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1212 tmds->tmds_pll[i].value |=
1213 (tmds_info->asMiscInfo[i].
1214 ucPLL_VCO_Gain & 0x3f) << 6;
1215 tmds->tmds_pll[i].value |=
1216 (tmds_info->asMiscInfo[i].
1217 ucPLL_DutyCycle & 0xf) << 12;
1218 tmds->tmds_pll[i].value |=
1219 (tmds_info->asMiscInfo[i].
1220 ucPLL_VoltageSwing & 0xf) << 16;
1222 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1223 tmds->tmds_pll[i].freq,
1224 tmds->tmds_pll[i].value);
1226 if (maxfreq == tmds->tmds_pll[i].freq) {
1227 tmds->tmds_pll[i].freq = 0xffffffff;
1236 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1241 struct drm_device *dev = encoder->base.dev;
1242 struct radeon_device *rdev = dev->dev_private;
1243 struct radeon_mode_info *mode_info = &rdev->mode_info;
1244 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1245 uint16_t data_offset;
1246 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1248 struct radeon_atom_ss *ss = NULL;
1251 if (id > ATOM_MAX_SS_ENTRY)
1254 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1255 &frev, &crev, &data_offset)) {
1257 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1260 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1265 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1266 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1268 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1269 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1270 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1271 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1272 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1273 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1282 struct _ATOM_LVDS_INFO info;
1283 struct _ATOM_LVDS_INFO_V12 info_12;
1286 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1290 struct drm_device *dev = encoder->base.dev;
1291 struct radeon_device *rdev = dev->dev_private;
1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1294 uint16_t data_offset, misc;
1295 union lvds_info *lvds_info;
1297 struct radeon_encoder_atom_dig *lvds = NULL;
1299 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1300 &frev, &crev, &data_offset)) {
1302 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1304 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1309 lvds->native_mode.clock =
1310 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1311 lvds->native_mode.hdisplay =
1312 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1313 lvds->native_mode.vdisplay =
1314 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1315 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1316 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1317 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1318 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1319 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1320 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1321 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1322 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1323 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1324 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1325 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1326 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1327 lvds->panel_pwr_delay =
1328 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1329 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1331 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1332 if (misc & ATOM_VSYNC_POLARITY)
1333 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1334 if (misc & ATOM_HSYNC_POLARITY)
1335 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1336 if (misc & ATOM_COMPOSITESYNC)
1337 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1338 if (misc & ATOM_INTERLACE)
1339 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1340 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1341 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1343 /* set crtc values */
1344 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1346 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1348 if (ASIC_IS_AVIVO(rdev)) {
1349 if (radeon_new_pll == 0)
1350 lvds->pll_algo = PLL_ALGO_LEGACY;
1352 lvds->pll_algo = PLL_ALGO_NEW;
1354 if (radeon_new_pll == 1)
1355 lvds->pll_algo = PLL_ALGO_NEW;
1357 lvds->pll_algo = PLL_ALGO_LEGACY;
1360 encoder->native_mode = lvds->native_mode;
1365 struct radeon_encoder_primary_dac *
1366 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1368 struct drm_device *dev = encoder->base.dev;
1369 struct radeon_device *rdev = dev->dev_private;
1370 struct radeon_mode_info *mode_info = &rdev->mode_info;
1371 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1372 uint16_t data_offset;
1373 struct _COMPASSIONATE_DATA *dac_info;
1376 struct radeon_encoder_primary_dac *p_dac = NULL;
1378 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1379 &frev, &crev, &data_offset)) {
1380 dac_info = (struct _COMPASSIONATE_DATA *)
1381 (mode_info->atom_context->bios + data_offset);
1383 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1388 bg = dac_info->ucDAC1_BG_Adjustment;
1389 dac = dac_info->ucDAC1_DAC_Adjustment;
1390 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1396 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1397 struct drm_display_mode *mode)
1399 struct radeon_mode_info *mode_info = &rdev->mode_info;
1400 ATOM_ANALOG_TV_INFO *tv_info;
1401 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1402 ATOM_DTD_FORMAT *dtd_timings;
1403 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1405 u16 data_offset, misc;
1407 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1408 &frev, &crev, &data_offset))
1413 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1414 if (index >= MAX_SUPPORTED_TV_TIMING)
1417 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1418 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1419 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1420 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1421 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1423 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1424 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1425 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1426 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1427 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1430 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1431 if (misc & ATOM_VSYNC_POLARITY)
1432 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1433 if (misc & ATOM_HSYNC_POLARITY)
1434 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1435 if (misc & ATOM_COMPOSITESYNC)
1436 mode->flags |= DRM_MODE_FLAG_CSYNC;
1437 if (misc & ATOM_INTERLACE)
1438 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1439 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1440 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1442 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1445 /* PAL timings appear to have wrong values for totals */
1446 mode->crtc_htotal -= 1;
1447 mode->crtc_vtotal -= 1;
1451 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1452 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1455 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1456 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1457 le16_to_cpu(dtd_timings->usHBlanking_Time);
1458 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1459 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1460 le16_to_cpu(dtd_timings->usHSyncOffset);
1461 mode->crtc_hsync_end = mode->crtc_hsync_start +
1462 le16_to_cpu(dtd_timings->usHSyncWidth);
1464 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1465 le16_to_cpu(dtd_timings->usVBlanking_Time);
1466 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1467 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1468 le16_to_cpu(dtd_timings->usVSyncOffset);
1469 mode->crtc_vsync_end = mode->crtc_vsync_start +
1470 le16_to_cpu(dtd_timings->usVSyncWidth);
1473 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1474 if (misc & ATOM_VSYNC_POLARITY)
1475 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1476 if (misc & ATOM_HSYNC_POLARITY)
1477 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1478 if (misc & ATOM_COMPOSITESYNC)
1479 mode->flags |= DRM_MODE_FLAG_CSYNC;
1480 if (misc & ATOM_INTERLACE)
1481 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1482 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1483 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1485 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1492 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1494 struct radeon_mode_info *mode_info = &rdev->mode_info;
1495 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1496 uint16_t data_offset;
1498 struct _ATOM_ANALOG_TV_INFO *tv_info;
1499 enum radeon_tv_std tv_std = TV_STD_NTSC;
1501 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1502 &frev, &crev, &data_offset)) {
1504 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1505 (mode_info->atom_context->bios + data_offset);
1507 switch (tv_info->ucTV_BootUpDefaultStandard) {
1509 tv_std = TV_STD_NTSC;
1510 DRM_INFO("Default TV standard: NTSC\n");
1513 tv_std = TV_STD_NTSC_J;
1514 DRM_INFO("Default TV standard: NTSC-J\n");
1517 tv_std = TV_STD_PAL;
1518 DRM_INFO("Default TV standard: PAL\n");
1521 tv_std = TV_STD_PAL_M;
1522 DRM_INFO("Default TV standard: PAL-M\n");
1525 tv_std = TV_STD_PAL_N;
1526 DRM_INFO("Default TV standard: PAL-N\n");
1529 tv_std = TV_STD_PAL_CN;
1530 DRM_INFO("Default TV standard: PAL-CN\n");
1533 tv_std = TV_STD_PAL_60;
1534 DRM_INFO("Default TV standard: PAL-60\n");
1537 tv_std = TV_STD_SECAM;
1538 DRM_INFO("Default TV standard: SECAM\n");
1541 tv_std = TV_STD_NTSC;
1542 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1549 struct radeon_encoder_tv_dac *
1550 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1552 struct drm_device *dev = encoder->base.dev;
1553 struct radeon_device *rdev = dev->dev_private;
1554 struct radeon_mode_info *mode_info = &rdev->mode_info;
1555 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1556 uint16_t data_offset;
1557 struct _COMPASSIONATE_DATA *dac_info;
1560 struct radeon_encoder_tv_dac *tv_dac = NULL;
1562 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1563 &frev, &crev, &data_offset)) {
1565 dac_info = (struct _COMPASSIONATE_DATA *)
1566 (mode_info->atom_context->bios + data_offset);
1568 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1573 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1574 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1575 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1577 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1578 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1579 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1581 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1582 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1583 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1585 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1590 static const char *thermal_controller_names[] = {
1601 static const char *pp_lib_thermal_controller_names[] = {
1614 "adt7473 with internal",
1619 struct _ATOM_POWERPLAY_INFO info;
1620 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1621 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1622 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1625 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1627 struct radeon_mode_info *mode_info = &rdev->mode_info;
1628 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1631 u32 misc, misc2 = 0, sclk, mclk;
1632 union power_info *power_info;
1633 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1634 struct _ATOM_PPLIB_STATE *power_state;
1635 int num_modes = 0, i, j;
1636 int state_index = 0, mode_index = 0;
1637 struct radeon_i2c_bus_rec i2c_bus;
1639 rdev->pm.default_power_state_index = -1;
1641 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1642 &frev, &crev, &data_offset)) {
1643 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1645 /* add the i2c bus for thermal/fan chip */
1646 if (power_info->info.ucOverdriveThermalController > 0) {
1647 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1648 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1649 power_info->info.ucOverdriveControllerAddress >> 1);
1650 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1651 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1652 if (rdev->pm.i2c_bus) {
1653 struct i2c_board_info info = { };
1654 const char *name = thermal_controller_names[power_info->info.
1655 ucOverdriveThermalController];
1656 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1657 strlcpy(info.type, name, sizeof(info.type));
1658 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1661 num_modes = power_info->info.ucNumOfPowerModeEntries;
1662 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1663 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1664 /* last mode is usually default, array is low to high */
1665 for (i = 0; i < num_modes; i++) {
1666 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1669 rdev->pm.power_state[state_index].num_clock_modes = 1;
1670 rdev->pm.power_state[state_index].clock_info[0].mclk =
1671 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1672 rdev->pm.power_state[state_index].clock_info[0].sclk =
1673 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1674 /* skip invalid modes */
1675 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1676 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1678 rdev->pm.power_state[state_index].pcie_lanes =
1679 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1680 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1681 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1682 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1683 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1685 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1686 radeon_lookup_gpio(rdev,
1687 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1688 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1689 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1692 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1694 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1695 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1697 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1698 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1700 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1701 rdev->pm.power_state[state_index].misc = misc;
1702 /* order matters! */
1703 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1704 rdev->pm.power_state[state_index].type =
1705 POWER_STATE_TYPE_POWERSAVE;
1706 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1707 rdev->pm.power_state[state_index].type =
1708 POWER_STATE_TYPE_BATTERY;
1709 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1710 rdev->pm.power_state[state_index].type =
1711 POWER_STATE_TYPE_BATTERY;
1712 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1713 rdev->pm.power_state[state_index].type =
1714 POWER_STATE_TYPE_BALANCED;
1715 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1716 rdev->pm.power_state[state_index].type =
1717 POWER_STATE_TYPE_PERFORMANCE;
1718 rdev->pm.power_state[state_index].flags &=
1719 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1721 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1722 rdev->pm.power_state[state_index].type =
1723 POWER_STATE_TYPE_DEFAULT;
1724 rdev->pm.default_power_state_index = state_index;
1725 rdev->pm.power_state[state_index].default_clock_mode =
1726 &rdev->pm.power_state[state_index].clock_info[0];
1727 rdev->pm.power_state[state_index].flags &=
1728 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1729 } else if (state_index == 0) {
1730 rdev->pm.power_state[state_index].clock_info[0].flags |=
1731 RADEON_PM_MODE_NO_DISPLAY;
1736 rdev->pm.power_state[state_index].num_clock_modes = 1;
1737 rdev->pm.power_state[state_index].clock_info[0].mclk =
1738 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1739 rdev->pm.power_state[state_index].clock_info[0].sclk =
1740 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1741 /* skip invalid modes */
1742 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1743 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1745 rdev->pm.power_state[state_index].pcie_lanes =
1746 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1747 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1748 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1749 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1750 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1751 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1753 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1754 radeon_lookup_gpio(rdev,
1755 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1756 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1757 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1760 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1762 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1763 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1765 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1766 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1768 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1769 rdev->pm.power_state[state_index].misc = misc;
1770 rdev->pm.power_state[state_index].misc2 = misc2;
1771 /* order matters! */
1772 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1773 rdev->pm.power_state[state_index].type =
1774 POWER_STATE_TYPE_POWERSAVE;
1775 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1776 rdev->pm.power_state[state_index].type =
1777 POWER_STATE_TYPE_BATTERY;
1778 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1779 rdev->pm.power_state[state_index].type =
1780 POWER_STATE_TYPE_BATTERY;
1781 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1782 rdev->pm.power_state[state_index].type =
1783 POWER_STATE_TYPE_BALANCED;
1784 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1785 rdev->pm.power_state[state_index].type =
1786 POWER_STATE_TYPE_PERFORMANCE;
1787 rdev->pm.power_state[state_index].flags &=
1788 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1790 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1791 rdev->pm.power_state[state_index].type =
1792 POWER_STATE_TYPE_BALANCED;
1793 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1794 rdev->pm.power_state[state_index].flags &=
1795 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1796 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1797 rdev->pm.power_state[state_index].type =
1798 POWER_STATE_TYPE_DEFAULT;
1799 rdev->pm.default_power_state_index = state_index;
1800 rdev->pm.power_state[state_index].default_clock_mode =
1801 &rdev->pm.power_state[state_index].clock_info[0];
1802 rdev->pm.power_state[state_index].flags &=
1803 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1804 } else if (state_index == 0) {
1805 rdev->pm.power_state[state_index].clock_info[0].flags |=
1806 RADEON_PM_MODE_NO_DISPLAY;
1811 rdev->pm.power_state[state_index].num_clock_modes = 1;
1812 rdev->pm.power_state[state_index].clock_info[0].mclk =
1813 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1814 rdev->pm.power_state[state_index].clock_info[0].sclk =
1815 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1816 /* skip invalid modes */
1817 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1818 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1820 rdev->pm.power_state[state_index].pcie_lanes =
1821 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1822 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1823 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1824 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1825 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1826 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1828 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1829 radeon_lookup_gpio(rdev,
1830 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1831 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1832 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1835 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1837 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1838 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1840 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1841 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1842 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1843 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1845 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1846 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1849 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1850 rdev->pm.power_state[state_index].misc = misc;
1851 rdev->pm.power_state[state_index].misc2 = misc2;
1852 /* order matters! */
1853 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1854 rdev->pm.power_state[state_index].type =
1855 POWER_STATE_TYPE_POWERSAVE;
1856 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1857 rdev->pm.power_state[state_index].type =
1858 POWER_STATE_TYPE_BATTERY;
1859 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1860 rdev->pm.power_state[state_index].type =
1861 POWER_STATE_TYPE_BATTERY;
1862 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1863 rdev->pm.power_state[state_index].type =
1864 POWER_STATE_TYPE_BALANCED;
1865 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1866 rdev->pm.power_state[state_index].type =
1867 POWER_STATE_TYPE_PERFORMANCE;
1868 rdev->pm.power_state[state_index].flags &=
1869 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1871 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1872 rdev->pm.power_state[state_index].type =
1873 POWER_STATE_TYPE_BALANCED;
1874 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1875 rdev->pm.power_state[state_index].type =
1876 POWER_STATE_TYPE_DEFAULT;
1877 rdev->pm.default_power_state_index = state_index;
1878 rdev->pm.power_state[state_index].default_clock_mode =
1879 &rdev->pm.power_state[state_index].clock_info[0];
1880 } else if (state_index == 0) {
1881 rdev->pm.power_state[state_index].clock_info[0].flags |=
1882 RADEON_PM_MODE_NO_DISPLAY;
1888 /* last mode is usually default */
1889 if (rdev->pm.default_power_state_index == -1) {
1890 rdev->pm.power_state[state_index - 1].type =
1891 POWER_STATE_TYPE_DEFAULT;
1892 rdev->pm.default_power_state_index = state_index - 1;
1893 rdev->pm.power_state[state_index - 1].default_clock_mode =
1894 &rdev->pm.power_state[state_index - 1].clock_info[0];
1895 rdev->pm.power_state[state_index].flags &=
1896 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1897 rdev->pm.power_state[state_index].misc = 0;
1898 rdev->pm.power_state[state_index].misc2 = 0;
1901 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1902 uint8_t fw_frev, fw_crev;
1903 uint16_t fw_data_offset, vddc = 0;
1904 union firmware_info *firmware_info;
1905 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1907 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1908 &fw_frev, &fw_crev, &fw_data_offset)) {
1910 (union firmware_info *)(mode_info->atom_context->bios +
1912 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1915 /* add the i2c bus for thermal/fan chip */
1916 if (controller->ucType > 0) {
1917 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
1918 DRM_INFO("Internal thermal controller %s fan control\n",
1919 (controller->ucFanParameters &
1920 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1921 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
1922 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
1923 DRM_INFO("Internal thermal controller %s fan control\n",
1924 (controller->ucFanParameters &
1925 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1926 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
1927 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
1928 DRM_INFO("Internal thermal controller %s fan control\n",
1929 (controller->ucFanParameters &
1930 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1931 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
1932 } else if ((controller->ucType ==
1933 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1934 (controller->ucType ==
1935 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1936 DRM_INFO("Special thermal controller config\n");
1938 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1939 pp_lib_thermal_controller_names[controller->ucType],
1940 controller->ucI2cAddress >> 1,
1941 (controller->ucFanParameters &
1942 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1943 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1944 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1945 if (rdev->pm.i2c_bus) {
1946 struct i2c_board_info info = { };
1947 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1948 info.addr = controller->ucI2cAddress >> 1;
1949 strlcpy(info.type, name, sizeof(info.type));
1950 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1955 /* first mode is usually default, followed by low to high */
1956 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1958 power_state = (struct _ATOM_PPLIB_STATE *)
1959 (mode_info->atom_context->bios +
1961 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1962 i * power_info->info_4.ucStateEntrySize);
1963 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1964 (mode_info->atom_context->bios +
1966 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1967 (power_state->ucNonClockStateIndex *
1968 power_info->info_4.ucNonClockSize));
1969 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1970 if (rdev->flags & RADEON_IS_IGP) {
1971 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1972 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1973 (mode_info->atom_context->bios +
1975 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1976 (power_state->ucClockStateIndices[j] *
1977 power_info->info_4.ucClockInfoSize));
1978 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1979 sclk |= clock_info->ucLowEngineClockHigh << 16;
1980 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1981 /* skip invalid modes */
1982 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1984 /* voltage works differently on IGPs */
1986 } else if (ASIC_IS_DCE4(rdev)) {
1987 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1988 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1989 (mode_info->atom_context->bios +
1991 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1992 (power_state->ucClockStateIndices[j] *
1993 power_info->info_4.ucClockInfoSize));
1994 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1995 sclk |= clock_info->ucEngineClockHigh << 16;
1996 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1997 mclk |= clock_info->ucMemoryClockHigh << 16;
1998 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1999 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2000 /* skip invalid modes */
2001 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2002 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2004 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2006 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2011 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2012 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2013 (mode_info->atom_context->bios +
2015 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2016 (power_state->ucClockStateIndices[j] *
2017 power_info->info_4.ucClockInfoSize));
2018 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2019 sclk |= clock_info->ucEngineClockHigh << 16;
2020 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2021 mclk |= clock_info->ucMemoryClockHigh << 16;
2022 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2023 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2024 /* skip invalid modes */
2025 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2026 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2028 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2030 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2035 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2037 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2038 misc2 = le16_to_cpu(non_clock_info->usClassification);
2039 rdev->pm.power_state[state_index].misc = misc;
2040 rdev->pm.power_state[state_index].misc2 = misc2;
2041 rdev->pm.power_state[state_index].pcie_lanes =
2042 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2043 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2044 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2045 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2046 rdev->pm.power_state[state_index].type =
2047 POWER_STATE_TYPE_BATTERY;
2049 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2050 rdev->pm.power_state[state_index].type =
2051 POWER_STATE_TYPE_BALANCED;
2053 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2054 rdev->pm.power_state[state_index].type =
2055 POWER_STATE_TYPE_PERFORMANCE;
2058 rdev->pm.power_state[state_index].flags = 0;
2059 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2060 rdev->pm.power_state[state_index].flags |=
2061 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2062 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2063 rdev->pm.power_state[state_index].type =
2064 POWER_STATE_TYPE_DEFAULT;
2065 rdev->pm.default_power_state_index = state_index;
2066 rdev->pm.power_state[state_index].default_clock_mode =
2067 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2068 /* patch the table values with the default slck/mclk from firmware info */
2069 for (j = 0; j < mode_index; j++) {
2070 rdev->pm.power_state[state_index].clock_info[j].mclk =
2071 rdev->clock.default_mclk;
2072 rdev->pm.power_state[state_index].clock_info[j].sclk =
2073 rdev->clock.default_sclk;
2075 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2082 /* if multiple clock modes, mark the lowest as no display */
2083 for (i = 0; i < state_index; i++) {
2084 if (rdev->pm.power_state[i].num_clock_modes > 1)
2085 rdev->pm.power_state[i].clock_info[0].flags |=
2086 RADEON_PM_MODE_NO_DISPLAY;
2088 /* first mode is usually default */
2089 if (rdev->pm.default_power_state_index == -1) {
2090 rdev->pm.power_state[0].type =
2091 POWER_STATE_TYPE_DEFAULT;
2092 rdev->pm.default_power_state_index = 0;
2093 rdev->pm.power_state[0].default_clock_mode =
2094 &rdev->pm.power_state[0].clock_info[0];
2098 /* add the default mode */
2099 rdev->pm.power_state[state_index].type =
2100 POWER_STATE_TYPE_DEFAULT;
2101 rdev->pm.power_state[state_index].num_clock_modes = 1;
2102 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2103 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2104 rdev->pm.power_state[state_index].default_clock_mode =
2105 &rdev->pm.power_state[state_index].clock_info[0];
2106 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2107 rdev->pm.power_state[state_index].pcie_lanes = 16;
2108 rdev->pm.default_power_state_index = state_index;
2109 rdev->pm.power_state[state_index].flags = 0;
2113 rdev->pm.num_power_states = state_index;
2115 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2116 rdev->pm.current_clock_mode_index = 0;
2117 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2120 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2122 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2123 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2125 args.ucEnable = enable;
2127 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2130 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2132 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2133 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2135 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2136 return args.ulReturnEngineClock;
2139 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2141 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2142 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2144 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2145 return args.ulReturnMemoryClock;
2148 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2151 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2152 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2154 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2159 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2162 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2163 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2165 if (rdev->flags & RADEON_IS_IGP)
2168 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2170 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2174 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2175 struct _SET_VOLTAGE_PARAMETERS v1;
2176 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2181 union set_voltage args;
2182 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2183 u8 frev, crev, volt_index = level;
2185 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2190 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2191 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2192 args.v1.ucVoltageIndex = volt_index;
2195 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2196 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2197 args.v2.usVoltageLevel = cpu_to_le16(level);
2200 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2204 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2209 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2211 struct radeon_device *rdev = dev->dev_private;
2212 uint32_t bios_2_scratch, bios_6_scratch;
2214 if (rdev->family >= CHIP_R600) {
2215 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2216 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2218 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2219 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2222 /* let the bios control the backlight */
2223 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2225 /* tell the bios not to handle mode switching */
2226 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2228 if (rdev->family >= CHIP_R600) {
2229 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2230 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2232 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2233 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2238 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2240 uint32_t scratch_reg;
2243 if (rdev->family >= CHIP_R600)
2244 scratch_reg = R600_BIOS_0_SCRATCH;
2246 scratch_reg = RADEON_BIOS_0_SCRATCH;
2248 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2249 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2252 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2254 uint32_t scratch_reg;
2257 if (rdev->family >= CHIP_R600)
2258 scratch_reg = R600_BIOS_0_SCRATCH;
2260 scratch_reg = RADEON_BIOS_0_SCRATCH;
2262 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2263 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2266 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2268 struct drm_device *dev = encoder->dev;
2269 struct radeon_device *rdev = dev->dev_private;
2270 uint32_t bios_6_scratch;
2272 if (rdev->family >= CHIP_R600)
2273 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2275 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2278 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2280 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2282 if (rdev->family >= CHIP_R600)
2283 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2285 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2288 /* at some point we may want to break this out into individual functions */
2290 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2291 struct drm_encoder *encoder,
2294 struct drm_device *dev = connector->dev;
2295 struct radeon_device *rdev = dev->dev_private;
2296 struct radeon_connector *radeon_connector =
2297 to_radeon_connector(connector);
2298 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2299 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2301 if (rdev->family >= CHIP_R600) {
2302 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2303 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2304 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2306 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2307 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2308 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2311 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2312 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2314 DRM_DEBUG_KMS("TV1 connected\n");
2315 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2316 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2318 DRM_DEBUG_KMS("TV1 disconnected\n");
2319 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2320 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2321 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2324 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2325 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2327 DRM_DEBUG_KMS("CV connected\n");
2328 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2329 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2331 DRM_DEBUG_KMS("CV disconnected\n");
2332 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2333 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2334 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2337 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2338 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2340 DRM_DEBUG_KMS("LCD1 connected\n");
2341 bios_0_scratch |= ATOM_S0_LCD1;
2342 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2343 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2345 DRM_DEBUG_KMS("LCD1 disconnected\n");
2346 bios_0_scratch &= ~ATOM_S0_LCD1;
2347 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2348 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2351 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2352 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2354 DRM_DEBUG_KMS("CRT1 connected\n");
2355 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2356 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2357 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2359 DRM_DEBUG_KMS("CRT1 disconnected\n");
2360 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2361 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2362 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2365 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2366 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2368 DRM_DEBUG_KMS("CRT2 connected\n");
2369 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2370 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2371 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2373 DRM_DEBUG_KMS("CRT2 disconnected\n");
2374 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2375 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2376 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2379 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2380 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2382 DRM_DEBUG_KMS("DFP1 connected\n");
2383 bios_0_scratch |= ATOM_S0_DFP1;
2384 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2385 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2387 DRM_DEBUG_KMS("DFP1 disconnected\n");
2388 bios_0_scratch &= ~ATOM_S0_DFP1;
2389 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2390 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2393 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2394 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2396 DRM_DEBUG_KMS("DFP2 connected\n");
2397 bios_0_scratch |= ATOM_S0_DFP2;
2398 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2399 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2401 DRM_DEBUG_KMS("DFP2 disconnected\n");
2402 bios_0_scratch &= ~ATOM_S0_DFP2;
2403 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2404 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2407 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2408 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2410 DRM_DEBUG_KMS("DFP3 connected\n");
2411 bios_0_scratch |= ATOM_S0_DFP3;
2412 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2413 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2415 DRM_DEBUG_KMS("DFP3 disconnected\n");
2416 bios_0_scratch &= ~ATOM_S0_DFP3;
2417 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2418 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2421 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2422 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2424 DRM_DEBUG_KMS("DFP4 connected\n");
2425 bios_0_scratch |= ATOM_S0_DFP4;
2426 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2427 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2429 DRM_DEBUG_KMS("DFP4 disconnected\n");
2430 bios_0_scratch &= ~ATOM_S0_DFP4;
2431 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2432 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2435 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2436 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2438 DRM_DEBUG_KMS("DFP5 connected\n");
2439 bios_0_scratch |= ATOM_S0_DFP5;
2440 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2441 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2443 DRM_DEBUG_KMS("DFP5 disconnected\n");
2444 bios_0_scratch &= ~ATOM_S0_DFP5;
2445 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2446 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2450 if (rdev->family >= CHIP_R600) {
2451 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2452 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2453 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2455 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2456 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2457 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2462 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2464 struct drm_device *dev = encoder->dev;
2465 struct radeon_device *rdev = dev->dev_private;
2466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2467 uint32_t bios_3_scratch;
2469 if (rdev->family >= CHIP_R600)
2470 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2472 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2474 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2475 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2476 bios_3_scratch |= (crtc << 18);
2478 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2479 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2480 bios_3_scratch |= (crtc << 24);
2482 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2483 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2484 bios_3_scratch |= (crtc << 16);
2486 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2487 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2488 bios_3_scratch |= (crtc << 20);
2490 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2491 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2492 bios_3_scratch |= (crtc << 17);
2494 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2495 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2496 bios_3_scratch |= (crtc << 19);
2498 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2499 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2500 bios_3_scratch |= (crtc << 23);
2502 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2503 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2504 bios_3_scratch |= (crtc << 25);
2507 if (rdev->family >= CHIP_R600)
2508 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2510 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2514 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2516 struct drm_device *dev = encoder->dev;
2517 struct radeon_device *rdev = dev->dev_private;
2518 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2519 uint32_t bios_2_scratch;
2521 if (rdev->family >= CHIP_R600)
2522 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2524 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2526 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2528 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2530 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2532 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2534 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2536 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2538 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2540 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2542 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2544 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2546 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2548 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2550 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2552 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2554 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2556 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2558 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2560 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2562 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2564 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2566 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2568 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2570 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2572 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2574 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2576 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2578 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2580 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2582 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2584 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2587 if (rdev->family >= CHIP_R600)
2588 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2590 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);