2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
104 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
130 i2c.hw_capable = false;
132 if (gpio->sucI2cId.ucAccess == 0xa0)
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
139 if (i2c.mask_clk_reg)
149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
175 (gpio->usClkMaskRegisterIndex == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
188 (gpio->usClkMaskRegisterIndex == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
213 i2c.hw_capable = false;
215 if (gpio->sucI2cId.ucAccess == 0xa0)
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
222 if (i2c.mask_clk_reg) {
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = pin->usGpioPin_AIndex * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
269 struct radeon_hpd hpd;
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
277 reg = AVIVO_DC_GPIO_HPD_A;
280 if (gpio->reg == reg) {
283 hpd.hpd = RADEON_HPD_1;
286 hpd.hpd = RADEON_HPD_2;
289 hpd.hpd = RADEON_HPD_3;
292 hpd.hpd = RADEON_HPD_4;
295 hpd.hpd = RADEON_HPD_5;
298 hpd.hpd = RADEON_HPD_6;
301 hpd.hpd = RADEON_HPD_NONE;
305 hpd.hpd = RADEON_HPD_NONE;
309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
312 struct radeon_i2c_bus_rec *i2c_bus,
314 struct radeon_hpd *hpd)
316 struct radeon_device *rdev = dev->dev_private;
318 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
319 if ((dev->pdev->device == 0x791e) &&
320 (dev->pdev->subsystem_vendor == 0x1043) &&
321 (dev->pdev->subsystem_device == 0x826d)) {
322 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
323 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
324 *connector_type = DRM_MODE_CONNECTOR_DVID;
327 /* Asrock RS600 board lists the DVI port as HDMI */
328 if ((dev->pdev->device == 0x7941) &&
329 (dev->pdev->subsystem_vendor == 0x1849) &&
330 (dev->pdev->subsystem_device == 0x7941)) {
331 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
332 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
333 *connector_type = DRM_MODE_CONNECTOR_DVID;
336 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
337 if ((dev->pdev->device == 0x796e) &&
338 (dev->pdev->subsystem_vendor == 0x1462) &&
339 (dev->pdev->subsystem_device == 0x7302)) {
340 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
341 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
345 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
346 if ((dev->pdev->device == 0x7941) &&
347 (dev->pdev->subsystem_vendor == 0x147b) &&
348 (dev->pdev->subsystem_device == 0x2412)) {
349 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
353 /* Falcon NW laptop lists vga ddc line for LVDS */
354 if ((dev->pdev->device == 0x5653) &&
355 (dev->pdev->subsystem_vendor == 0x1462) &&
356 (dev->pdev->subsystem_device == 0x0291)) {
357 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
358 i2c_bus->valid = false;
363 /* HIS X1300 is DVI+VGA, not DVI+DVI */
364 if ((dev->pdev->device == 0x7146) &&
365 (dev->pdev->subsystem_vendor == 0x17af) &&
366 (dev->pdev->subsystem_device == 0x2058)) {
367 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
371 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
372 if ((dev->pdev->device == 0x7142) &&
373 (dev->pdev->subsystem_vendor == 0x1458) &&
374 (dev->pdev->subsystem_device == 0x2134)) {
375 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
381 if ((dev->pdev->device == 0x71C5) &&
382 (dev->pdev->subsystem_vendor == 0x106b) &&
383 (dev->pdev->subsystem_device == 0x0080)) {
384 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
385 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
387 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
391 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
392 if ((dev->pdev->device == 0x9598) &&
393 (dev->pdev->subsystem_vendor == 0x1043) &&
394 (dev->pdev->subsystem_device == 0x01da)) {
395 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
396 *connector_type = DRM_MODE_CONNECTOR_DVII;
400 /* ASUS HD 3600 board lists the DVI port as HDMI */
401 if ((dev->pdev->device == 0x9598) &&
402 (dev->pdev->subsystem_vendor == 0x1043) &&
403 (dev->pdev->subsystem_device == 0x01e4)) {
404 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
405 *connector_type = DRM_MODE_CONNECTOR_DVII;
409 /* ASUS HD 3450 board lists the DVI port as HDMI */
410 if ((dev->pdev->device == 0x95C5) &&
411 (dev->pdev->subsystem_vendor == 0x1043) &&
412 (dev->pdev->subsystem_device == 0x01e2)) {
413 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
414 *connector_type = DRM_MODE_CONNECTOR_DVII;
418 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
419 * HDMI + VGA reporting as HDMI
421 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
422 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
423 *connector_type = DRM_MODE_CONNECTOR_VGA;
428 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
429 if ((dev->pdev->device == 0x95c4) &&
430 (dev->pdev->subsystem_vendor == 0x1025) &&
431 (dev->pdev->subsystem_device == 0x013c)) {
432 struct radeon_gpio_rec gpio;
434 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
435 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
436 gpio = radeon_lookup_gpio(rdev, 6);
437 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
438 *connector_type = DRM_MODE_CONNECTOR_DVID;
439 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
440 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
441 gpio = radeon_lookup_gpio(rdev, 7);
442 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
446 /* XFX Pine Group device rv730 reports no VGA DDC lines
447 * even though they are wired up to record 0x93
449 if ((dev->pdev->device == 0x9498) &&
450 (dev->pdev->subsystem_vendor == 0x1682) &&
451 (dev->pdev->subsystem_device == 0x2452)) {
452 struct radeon_device *rdev = dev->dev_private;
453 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
458 const int supported_devices_connector_convert[] = {
459 DRM_MODE_CONNECTOR_Unknown,
460 DRM_MODE_CONNECTOR_VGA,
461 DRM_MODE_CONNECTOR_DVII,
462 DRM_MODE_CONNECTOR_DVID,
463 DRM_MODE_CONNECTOR_DVIA,
464 DRM_MODE_CONNECTOR_SVIDEO,
465 DRM_MODE_CONNECTOR_Composite,
466 DRM_MODE_CONNECTOR_LVDS,
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_HDMIA,
470 DRM_MODE_CONNECTOR_HDMIB,
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_Unknown,
473 DRM_MODE_CONNECTOR_9PinDIN,
474 DRM_MODE_CONNECTOR_DisplayPort
477 const uint16_t supported_devices_connector_object_id_convert[] = {
478 CONNECTOR_OBJECT_ID_NONE,
479 CONNECTOR_OBJECT_ID_VGA,
480 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
481 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
482 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
483 CONNECTOR_OBJECT_ID_COMPOSITE,
484 CONNECTOR_OBJECT_ID_SVIDEO,
485 CONNECTOR_OBJECT_ID_LVDS,
486 CONNECTOR_OBJECT_ID_9PIN_DIN,
487 CONNECTOR_OBJECT_ID_9PIN_DIN,
488 CONNECTOR_OBJECT_ID_DISPLAYPORT,
489 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
490 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
491 CONNECTOR_OBJECT_ID_SVIDEO
494 const int object_connector_convert[] = {
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_DVII,
497 DRM_MODE_CONNECTOR_DVII,
498 DRM_MODE_CONNECTOR_DVID,
499 DRM_MODE_CONNECTOR_DVID,
500 DRM_MODE_CONNECTOR_VGA,
501 DRM_MODE_CONNECTOR_Composite,
502 DRM_MODE_CONNECTOR_SVIDEO,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_9PinDIN,
506 DRM_MODE_CONNECTOR_Unknown,
507 DRM_MODE_CONNECTOR_HDMIA,
508 DRM_MODE_CONNECTOR_HDMIB,
509 DRM_MODE_CONNECTOR_LVDS,
510 DRM_MODE_CONNECTOR_9PinDIN,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_Unknown,
514 DRM_MODE_CONNECTOR_DisplayPort,
515 DRM_MODE_CONNECTOR_eDP,
516 DRM_MODE_CONNECTOR_Unknown
519 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
521 struct radeon_device *rdev = dev->dev_private;
522 struct radeon_mode_info *mode_info = &rdev->mode_info;
523 struct atom_context *ctx = mode_info->atom_context;
524 int index = GetIndexIntoMasterTable(DATA, Object_Header);
525 u16 size, data_offset;
527 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
528 ATOM_OBJECT_TABLE *router_obj;
529 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
530 ATOM_OBJECT_HEADER *obj_header;
531 int i, j, k, path_size, device_support;
533 u16 igp_lane_info, conn_id, connector_object_id;
534 struct radeon_i2c_bus_rec ddc_bus;
535 struct radeon_router router;
536 struct radeon_gpio_rec gpio;
537 struct radeon_hpd hpd;
539 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
545 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
546 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usDisplayPathTableOffset));
549 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
552 router_obj = (ATOM_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usRouterObjectTableOffset));
555 device_support = le16_to_cpu(obj_header->usDeviceSupport);
558 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
559 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
560 ATOM_DISPLAY_OBJECT_PATH *path;
562 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
563 path_size += le16_to_cpu(path->usSize);
565 if (device_support & le16_to_cpu(path->usDeviceTag)) {
566 uint8_t con_obj_id, con_obj_num, con_obj_type;
569 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
572 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
575 (le16_to_cpu(path->usConnObjectId) &
576 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
578 /* TODO CV support */
579 if (le16_to_cpu(path->usDeviceTag) ==
580 ATOM_DEVICE_CV_SUPPORT)
584 if ((rdev->flags & RADEON_IS_IGP) &&
586 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
587 uint16_t igp_offset = 0;
588 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
591 GetIndexIntoMasterTable(DATA,
592 IntegratedSystemInfo);
594 if (atom_parse_data_header(ctx, index, &size, &frev,
595 &crev, &igp_offset)) {
599 (ATOM_INTEGRATED_SYSTEM_INFO_V2
600 *) (ctx->bios + igp_offset);
603 uint32_t slot_config, ct;
605 if (con_obj_num == 1)
614 ct = (slot_config >> 16) & 0xff;
616 object_connector_convert
618 connector_object_id = ct;
620 slot_config & 0xffff;
628 object_connector_convert[con_obj_id];
629 connector_object_id = con_obj_id;
634 object_connector_convert[con_obj_id];
635 connector_object_id = con_obj_id;
638 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
641 router.ddc_valid = false;
642 router.cd_valid = false;
643 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
644 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
647 (le16_to_cpu(path->usGraphicObjIds[j]) &
648 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
650 (le16_to_cpu(path->usGraphicObjIds[j]) &
651 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
653 (le16_to_cpu(path->usGraphicObjIds[j]) &
654 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
656 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
657 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
659 radeon_add_atom_encoder(dev,
665 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
666 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
667 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
668 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
669 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
670 (ctx->bios + data_offset +
671 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
672 ATOM_I2C_RECORD *i2c_record;
673 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
674 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
675 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
676 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
677 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
678 (ctx->bios + data_offset +
679 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
682 router.router_id = router_obj_id;
683 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
685 if (le16_to_cpu(path->usConnObjectId) ==
686 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
690 while (record->ucRecordType > 0 &&
691 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
692 switch (record->ucRecordType) {
693 case ATOM_I2C_RECORD_TYPE:
698 (ATOM_I2C_ID_CONFIG_ACCESS *)
699 &i2c_record->sucI2cId;
701 radeon_lookup_i2c_gpio(rdev,
704 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
706 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
707 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
709 router.ddc_valid = true;
710 router.ddc_mux_type = ddc_path->ucMuxType;
711 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
712 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
714 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
715 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
717 router.cd_valid = true;
718 router.cd_mux_type = cd_path->ucMuxType;
719 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
720 router.cd_mux_state = cd_path->ucMuxState[enum_id];
723 record = (ATOM_COMMON_RECORD_HEADER *)
724 ((char *)record + record->ucRecordSize);
731 /* look up gpio for ddc, hpd */
732 ddc_bus.valid = false;
733 hpd.hpd = RADEON_HPD_NONE;
734 if ((le16_to_cpu(path->usDeviceTag) &
735 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
736 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
737 if (le16_to_cpu(path->usConnObjectId) ==
738 le16_to_cpu(con_obj->asObjects[j].
740 ATOM_COMMON_RECORD_HEADER
742 (ATOM_COMMON_RECORD_HEADER
744 (ctx->bios + data_offset +
745 le16_to_cpu(con_obj->
748 ATOM_I2C_RECORD *i2c_record;
749 ATOM_HPD_INT_RECORD *hpd_record;
750 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
752 while (record->ucRecordType > 0
755 ATOM_MAX_OBJECT_RECORD_NUMBER) {
756 switch (record->ucRecordType) {
757 case ATOM_I2C_RECORD_TYPE:
762 (ATOM_I2C_ID_CONFIG_ACCESS *)
763 &i2c_record->sucI2cId;
764 ddc_bus = radeon_lookup_i2c_gpio(rdev,
768 case ATOM_HPD_INT_RECORD_TYPE:
770 (ATOM_HPD_INT_RECORD *)
772 gpio = radeon_lookup_gpio(rdev,
773 hpd_record->ucHPDIntGPIOID);
774 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
775 hpd.plugged_state = hpd_record->ucPlugged_PinState;
779 (ATOM_COMMON_RECORD_HEADER
790 /* needed for aux chan transactions */
791 ddc_bus.hpd = hpd.hpd;
793 conn_id = le16_to_cpu(path->usConnObjectId);
795 if (!radeon_atom_apply_quirks
796 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
797 &ddc_bus, &conn_id, &hpd))
800 radeon_add_atom_connector(dev,
804 connector_type, &ddc_bus,
813 radeon_link_encoder_connector(dev);
818 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
822 struct radeon_device *rdev = dev->dev_private;
824 if (rdev->flags & RADEON_IS_IGP) {
825 return supported_devices_connector_object_id_convert
827 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
828 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
829 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
830 struct radeon_mode_info *mode_info = &rdev->mode_info;
831 struct atom_context *ctx = mode_info->atom_context;
832 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
833 uint16_t size, data_offset;
835 ATOM_XTMDS_INFO *xtmds;
837 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
838 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
840 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
841 if (connector_type == DRM_MODE_CONNECTOR_DVII)
842 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
844 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
846 if (connector_type == DRM_MODE_CONNECTOR_DVII)
847 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
849 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
852 return supported_devices_connector_object_id_convert
855 return supported_devices_connector_object_id_convert
860 struct bios_connector {
865 struct radeon_i2c_bus_rec ddc_bus;
866 struct radeon_hpd hpd;
869 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
873 struct radeon_device *rdev = dev->dev_private;
874 struct radeon_mode_info *mode_info = &rdev->mode_info;
875 struct atom_context *ctx = mode_info->atom_context;
876 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
877 uint16_t size, data_offset;
879 uint16_t device_support;
881 union atom_supported_devices *supported_devices;
882 int i, j, max_device;
883 struct bios_connector *bios_connectors;
884 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
885 struct radeon_router router;
887 router.ddc_valid = false;
888 router.cd_valid = false;
890 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
891 if (!bios_connectors)
894 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
896 kfree(bios_connectors);
901 (union atom_supported_devices *)(ctx->bios + data_offset);
903 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
906 max_device = ATOM_MAX_SUPPORTED_DEVICE;
908 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
910 for (i = 0; i < max_device; i++) {
911 ATOM_CONNECTOR_INFO_I2C ci =
912 supported_devices->info.asConnInfo[i];
914 bios_connectors[i].valid = false;
916 if (!(device_support & (1 << i))) {
920 if (i == ATOM_DEVICE_CV_INDEX) {
921 DRM_DEBUG_KMS("Skipping Component Video\n");
925 bios_connectors[i].connector_type =
926 supported_devices_connector_convert[ci.sucConnectorInfo.
930 if (bios_connectors[i].connector_type ==
931 DRM_MODE_CONNECTOR_Unknown)
934 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
936 bios_connectors[i].line_mux =
937 ci.sucI2cId.ucAccess;
939 /* give tv unique connector ids */
940 if (i == ATOM_DEVICE_TV1_INDEX) {
941 bios_connectors[i].ddc_bus.valid = false;
942 bios_connectors[i].line_mux = 50;
943 } else if (i == ATOM_DEVICE_TV2_INDEX) {
944 bios_connectors[i].ddc_bus.valid = false;
945 bios_connectors[i].line_mux = 51;
946 } else if (i == ATOM_DEVICE_CV_INDEX) {
947 bios_connectors[i].ddc_bus.valid = false;
948 bios_connectors[i].line_mux = 52;
950 bios_connectors[i].ddc_bus =
951 radeon_lookup_i2c_gpio(rdev,
952 bios_connectors[i].line_mux);
954 if ((crev > 1) && (frev > 1)) {
955 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
958 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
961 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
964 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
968 if (i == ATOM_DEVICE_DFP1_INDEX)
969 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
970 else if (i == ATOM_DEVICE_DFP2_INDEX)
971 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
973 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
976 /* Always set the connector type to VGA for CRT1/CRT2. if they are
977 * shared with a DVI port, we'll pick up the DVI connector when we
978 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
980 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
981 bios_connectors[i].connector_type =
982 DRM_MODE_CONNECTOR_VGA;
984 if (!radeon_atom_apply_quirks
985 (dev, (1 << i), &bios_connectors[i].connector_type,
986 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
987 &bios_connectors[i].hpd))
990 bios_connectors[i].valid = true;
991 bios_connectors[i].devices = (1 << i);
993 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
994 radeon_add_atom_encoder(dev,
995 radeon_get_encoder_enum(dev,
1000 radeon_add_legacy_encoder(dev,
1001 radeon_get_encoder_enum(dev,
1007 /* combine shared connectors */
1008 for (i = 0; i < max_device; i++) {
1009 if (bios_connectors[i].valid) {
1010 for (j = 0; j < max_device; j++) {
1011 if (bios_connectors[j].valid && (i != j)) {
1012 if (bios_connectors[i].line_mux ==
1013 bios_connectors[j].line_mux) {
1014 /* make sure not to combine LVDS */
1015 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1016 bios_connectors[i].line_mux = 53;
1017 bios_connectors[i].ddc_bus.valid = false;
1020 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1021 bios_connectors[j].line_mux = 53;
1022 bios_connectors[j].ddc_bus.valid = false;
1025 /* combine analog and digital for DVI-I */
1026 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1027 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1028 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1029 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1030 bios_connectors[i].devices |=
1031 bios_connectors[j].devices;
1032 bios_connectors[i].connector_type =
1033 DRM_MODE_CONNECTOR_DVII;
1034 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1035 bios_connectors[i].hpd =
1036 bios_connectors[j].hpd;
1037 bios_connectors[j].valid = false;
1045 /* add the connectors */
1046 for (i = 0; i < max_device; i++) {
1047 if (bios_connectors[i].valid) {
1048 uint16_t connector_object_id =
1049 atombios_get_connector_object_id(dev,
1050 bios_connectors[i].connector_type,
1051 bios_connectors[i].devices);
1052 radeon_add_atom_connector(dev,
1053 bios_connectors[i].line_mux,
1054 bios_connectors[i].devices,
1057 &bios_connectors[i].ddc_bus,
1059 connector_object_id,
1060 &bios_connectors[i].hpd,
1065 radeon_link_encoder_connector(dev);
1067 kfree(bios_connectors);
1071 union firmware_info {
1072 ATOM_FIRMWARE_INFO info;
1073 ATOM_FIRMWARE_INFO_V1_2 info_12;
1074 ATOM_FIRMWARE_INFO_V1_3 info_13;
1075 ATOM_FIRMWARE_INFO_V1_4 info_14;
1076 ATOM_FIRMWARE_INFO_V2_1 info_21;
1079 bool radeon_atom_get_clock_info(struct drm_device *dev)
1081 struct radeon_device *rdev = dev->dev_private;
1082 struct radeon_mode_info *mode_info = &rdev->mode_info;
1083 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1084 union firmware_info *firmware_info;
1086 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1087 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1088 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1089 struct radeon_pll *spll = &rdev->clock.spll;
1090 struct radeon_pll *mpll = &rdev->clock.mpll;
1091 uint16_t data_offset;
1093 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1094 &frev, &crev, &data_offset)) {
1096 (union firmware_info *)(mode_info->atom_context->bios +
1099 p1pll->reference_freq =
1100 le16_to_cpu(firmware_info->info.usReferenceClock);
1101 p1pll->reference_div = 0;
1104 p1pll->pll_out_min =
1105 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1107 p1pll->pll_out_min =
1108 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1109 p1pll->pll_out_max =
1110 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1113 p1pll->lcd_pll_out_min =
1114 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1115 if (p1pll->lcd_pll_out_min == 0)
1116 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1117 p1pll->lcd_pll_out_max =
1118 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1119 if (p1pll->lcd_pll_out_max == 0)
1120 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1122 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1123 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1126 if (p1pll->pll_out_min == 0) {
1127 if (ASIC_IS_AVIVO(rdev))
1128 p1pll->pll_out_min = 64800;
1130 p1pll->pll_out_min = 20000;
1131 } else if (p1pll->pll_out_min > 64800) {
1132 /* Limiting the pll output range is a good thing generally as
1133 * it limits the number of possible pll combinations for a given
1134 * frequency presumably to the ones that work best on each card.
1135 * However, certain duallink DVI monitors seem to like
1136 * pll combinations that would be limited by this at least on
1137 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1140 p1pll->pll_out_min = 64800;
1144 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1146 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1151 spll->reference_freq =
1152 le16_to_cpu(firmware_info->info.usReferenceClock);
1153 spll->reference_div = 0;
1156 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1158 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1161 if (spll->pll_out_min == 0) {
1162 if (ASIC_IS_AVIVO(rdev))
1163 spll->pll_out_min = 64800;
1165 spll->pll_out_min = 20000;
1169 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1171 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1174 mpll->reference_freq =
1175 le16_to_cpu(firmware_info->info.usReferenceClock);
1176 mpll->reference_div = 0;
1179 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1181 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1184 if (mpll->pll_out_min == 0) {
1185 if (ASIC_IS_AVIVO(rdev))
1186 mpll->pll_out_min = 64800;
1188 mpll->pll_out_min = 20000;
1192 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1194 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1196 rdev->clock.default_sclk =
1197 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1198 rdev->clock.default_mclk =
1199 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1201 if (ASIC_IS_DCE4(rdev)) {
1202 rdev->clock.default_dispclk =
1203 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1204 if (rdev->clock.default_dispclk == 0)
1205 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1206 rdev->clock.dp_extclk =
1207 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1218 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1219 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1222 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1224 struct radeon_mode_info *mode_info = &rdev->mode_info;
1225 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1226 union igp_info *igp_info;
1230 /* sideport is AMD only */
1231 if (rdev->family == CHIP_RS600)
1234 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1235 &frev, &crev, &data_offset)) {
1236 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1240 if (igp_info->info.ulBootUpMemoryClock)
1244 if (igp_info->info_2.ulBootUpSidePortClock)
1248 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1255 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1256 struct radeon_encoder_int_tmds *tmds)
1258 struct drm_device *dev = encoder->base.dev;
1259 struct radeon_device *rdev = dev->dev_private;
1260 struct radeon_mode_info *mode_info = &rdev->mode_info;
1261 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1262 uint16_t data_offset;
1263 struct _ATOM_TMDS_INFO *tmds_info;
1268 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1269 &frev, &crev, &data_offset)) {
1271 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1274 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1275 for (i = 0; i < 4; i++) {
1276 tmds->tmds_pll[i].freq =
1277 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1278 tmds->tmds_pll[i].value =
1279 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1280 tmds->tmds_pll[i].value |=
1281 (tmds_info->asMiscInfo[i].
1282 ucPLL_VCO_Gain & 0x3f) << 6;
1283 tmds->tmds_pll[i].value |=
1284 (tmds_info->asMiscInfo[i].
1285 ucPLL_DutyCycle & 0xf) << 12;
1286 tmds->tmds_pll[i].value |=
1287 (tmds_info->asMiscInfo[i].
1288 ucPLL_VoltageSwing & 0xf) << 16;
1290 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1291 tmds->tmds_pll[i].freq,
1292 tmds->tmds_pll[i].value);
1294 if (maxfreq == tmds->tmds_pll[i].freq) {
1295 tmds->tmds_pll[i].freq = 0xffffffff;
1304 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1305 struct radeon_atom_ss *ss,
1308 struct radeon_mode_info *mode_info = &rdev->mode_info;
1309 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1310 uint16_t data_offset, size;
1311 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1315 memset(ss, 0, sizeof(struct radeon_atom_ss));
1316 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1317 &frev, &crev, &data_offset)) {
1319 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1321 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1322 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1324 for (i = 0; i < num_indices; i++) {
1325 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1327 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1328 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1329 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1330 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1331 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1332 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1340 union asic_ss_info {
1341 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1342 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1343 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1346 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1347 struct radeon_atom_ss *ss,
1350 struct radeon_mode_info *mode_info = &rdev->mode_info;
1351 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1352 uint16_t data_offset, size;
1353 union asic_ss_info *ss_info;
1357 memset(ss, 0, sizeof(struct radeon_atom_ss));
1358 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1359 &frev, &crev, &data_offset)) {
1362 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1366 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1367 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1369 for (i = 0; i < num_indices; i++) {
1370 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1371 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1373 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1374 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1375 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1381 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1382 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1383 for (i = 0; i < num_indices; i++) {
1384 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1385 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1387 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1388 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1389 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1395 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1396 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1397 for (i = 0; i < num_indices; i++) {
1398 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1399 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1401 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1402 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1403 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1409 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1418 struct _ATOM_LVDS_INFO info;
1419 struct _ATOM_LVDS_INFO_V12 info_12;
1422 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1426 struct drm_device *dev = encoder->base.dev;
1427 struct radeon_device *rdev = dev->dev_private;
1428 struct radeon_mode_info *mode_info = &rdev->mode_info;
1429 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1430 uint16_t data_offset, misc;
1431 union lvds_info *lvds_info;
1433 struct radeon_encoder_atom_dig *lvds = NULL;
1434 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1436 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1437 &frev, &crev, &data_offset)) {
1439 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1441 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1446 lvds->native_mode.clock =
1447 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1448 lvds->native_mode.hdisplay =
1449 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1450 lvds->native_mode.vdisplay =
1451 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1452 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1453 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1454 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1455 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1456 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1457 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1458 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1459 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1460 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1461 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1462 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1463 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1464 lvds->panel_pwr_delay =
1465 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1466 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1468 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1469 if (misc & ATOM_VSYNC_POLARITY)
1470 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1471 if (misc & ATOM_HSYNC_POLARITY)
1472 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1473 if (misc & ATOM_COMPOSITESYNC)
1474 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1475 if (misc & ATOM_INTERLACE)
1476 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1477 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1478 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1480 /* set crtc values */
1481 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1483 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1485 encoder->native_mode = lvds->native_mode;
1487 if (encoder_enum == 2)
1490 lvds->linkb = false;
1496 struct radeon_encoder_primary_dac *
1497 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1499 struct drm_device *dev = encoder->base.dev;
1500 struct radeon_device *rdev = dev->dev_private;
1501 struct radeon_mode_info *mode_info = &rdev->mode_info;
1502 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1503 uint16_t data_offset;
1504 struct _COMPASSIONATE_DATA *dac_info;
1507 struct radeon_encoder_primary_dac *p_dac = NULL;
1509 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1510 &frev, &crev, &data_offset)) {
1511 dac_info = (struct _COMPASSIONATE_DATA *)
1512 (mode_info->atom_context->bios + data_offset);
1514 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1519 bg = dac_info->ucDAC1_BG_Adjustment;
1520 dac = dac_info->ucDAC1_DAC_Adjustment;
1521 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1527 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1528 struct drm_display_mode *mode)
1530 struct radeon_mode_info *mode_info = &rdev->mode_info;
1531 ATOM_ANALOG_TV_INFO *tv_info;
1532 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1533 ATOM_DTD_FORMAT *dtd_timings;
1534 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1536 u16 data_offset, misc;
1538 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1539 &frev, &crev, &data_offset))
1544 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1545 if (index >= MAX_SUPPORTED_TV_TIMING)
1548 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1549 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1550 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1551 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1552 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1554 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1555 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1556 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1557 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1558 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1561 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1562 if (misc & ATOM_VSYNC_POLARITY)
1563 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1564 if (misc & ATOM_HSYNC_POLARITY)
1565 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1566 if (misc & ATOM_COMPOSITESYNC)
1567 mode->flags |= DRM_MODE_FLAG_CSYNC;
1568 if (misc & ATOM_INTERLACE)
1569 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1570 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1571 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1573 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1576 /* PAL timings appear to have wrong values for totals */
1577 mode->crtc_htotal -= 1;
1578 mode->crtc_vtotal -= 1;
1582 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1583 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1586 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1587 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1588 le16_to_cpu(dtd_timings->usHBlanking_Time);
1589 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1590 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1591 le16_to_cpu(dtd_timings->usHSyncOffset);
1592 mode->crtc_hsync_end = mode->crtc_hsync_start +
1593 le16_to_cpu(dtd_timings->usHSyncWidth);
1595 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1596 le16_to_cpu(dtd_timings->usVBlanking_Time);
1597 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1598 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1599 le16_to_cpu(dtd_timings->usVSyncOffset);
1600 mode->crtc_vsync_end = mode->crtc_vsync_start +
1601 le16_to_cpu(dtd_timings->usVSyncWidth);
1604 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1605 if (misc & ATOM_VSYNC_POLARITY)
1606 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1607 if (misc & ATOM_HSYNC_POLARITY)
1608 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1609 if (misc & ATOM_COMPOSITESYNC)
1610 mode->flags |= DRM_MODE_FLAG_CSYNC;
1611 if (misc & ATOM_INTERLACE)
1612 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1613 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1614 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1616 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1623 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1625 struct radeon_mode_info *mode_info = &rdev->mode_info;
1626 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1627 uint16_t data_offset;
1629 struct _ATOM_ANALOG_TV_INFO *tv_info;
1630 enum radeon_tv_std tv_std = TV_STD_NTSC;
1632 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1633 &frev, &crev, &data_offset)) {
1635 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1636 (mode_info->atom_context->bios + data_offset);
1638 switch (tv_info->ucTV_BootUpDefaultStandard) {
1640 tv_std = TV_STD_NTSC;
1641 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1644 tv_std = TV_STD_NTSC_J;
1645 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1648 tv_std = TV_STD_PAL;
1649 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1652 tv_std = TV_STD_PAL_M;
1653 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1656 tv_std = TV_STD_PAL_N;
1657 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1660 tv_std = TV_STD_PAL_CN;
1661 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1664 tv_std = TV_STD_PAL_60;
1665 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1668 tv_std = TV_STD_SECAM;
1669 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1672 tv_std = TV_STD_NTSC;
1673 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1680 struct radeon_encoder_tv_dac *
1681 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1683 struct drm_device *dev = encoder->base.dev;
1684 struct radeon_device *rdev = dev->dev_private;
1685 struct radeon_mode_info *mode_info = &rdev->mode_info;
1686 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1687 uint16_t data_offset;
1688 struct _COMPASSIONATE_DATA *dac_info;
1691 struct radeon_encoder_tv_dac *tv_dac = NULL;
1693 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1694 &frev, &crev, &data_offset)) {
1696 dac_info = (struct _COMPASSIONATE_DATA *)
1697 (mode_info->atom_context->bios + data_offset);
1699 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1704 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1705 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1706 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1708 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1709 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1710 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1712 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1713 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1714 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1716 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1721 static const char *thermal_controller_names[] = {
1732 static const char *pp_lib_thermal_controller_names[] = {
1745 "adt7473 with internal",
1750 struct _ATOM_POWERPLAY_INFO info;
1751 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1752 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1753 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1756 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1758 struct radeon_mode_info *mode_info = &rdev->mode_info;
1759 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1762 u32 misc, misc2 = 0, sclk, mclk;
1763 union power_info *power_info;
1764 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1765 struct _ATOM_PPLIB_STATE *power_state;
1766 int num_modes = 0, i, j;
1767 int state_index = 0, mode_index = 0;
1768 struct radeon_i2c_bus_rec i2c_bus;
1770 rdev->pm.default_power_state_index = -1;
1772 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1773 &frev, &crev, &data_offset)) {
1774 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1776 /* add the i2c bus for thermal/fan chip */
1777 if (power_info->info.ucOverdriveThermalController > 0) {
1778 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1779 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1780 power_info->info.ucOverdriveControllerAddress >> 1);
1781 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1782 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1783 if (rdev->pm.i2c_bus) {
1784 struct i2c_board_info info = { };
1785 const char *name = thermal_controller_names[power_info->info.
1786 ucOverdriveThermalController];
1787 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1788 strlcpy(info.type, name, sizeof(info.type));
1789 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1792 num_modes = power_info->info.ucNumOfPowerModeEntries;
1793 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1794 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1795 /* last mode is usually default, array is low to high */
1796 for (i = 0; i < num_modes; i++) {
1797 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1800 rdev->pm.power_state[state_index].num_clock_modes = 1;
1801 rdev->pm.power_state[state_index].clock_info[0].mclk =
1802 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1803 rdev->pm.power_state[state_index].clock_info[0].sclk =
1804 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1805 /* skip invalid modes */
1806 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1807 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1809 rdev->pm.power_state[state_index].pcie_lanes =
1810 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1811 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1812 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1813 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1814 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1816 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1817 radeon_lookup_gpio(rdev,
1818 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1819 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1820 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1823 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1825 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1826 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1828 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1829 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1831 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1832 rdev->pm.power_state[state_index].misc = misc;
1833 /* order matters! */
1834 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1835 rdev->pm.power_state[state_index].type =
1836 POWER_STATE_TYPE_POWERSAVE;
1837 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1838 rdev->pm.power_state[state_index].type =
1839 POWER_STATE_TYPE_BATTERY;
1840 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1841 rdev->pm.power_state[state_index].type =
1842 POWER_STATE_TYPE_BATTERY;
1843 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1844 rdev->pm.power_state[state_index].type =
1845 POWER_STATE_TYPE_BALANCED;
1846 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1847 rdev->pm.power_state[state_index].type =
1848 POWER_STATE_TYPE_PERFORMANCE;
1849 rdev->pm.power_state[state_index].flags &=
1850 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1852 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1853 rdev->pm.power_state[state_index].type =
1854 POWER_STATE_TYPE_DEFAULT;
1855 rdev->pm.default_power_state_index = state_index;
1856 rdev->pm.power_state[state_index].default_clock_mode =
1857 &rdev->pm.power_state[state_index].clock_info[0];
1858 rdev->pm.power_state[state_index].flags &=
1859 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1860 } else if (state_index == 0) {
1861 rdev->pm.power_state[state_index].clock_info[0].flags |=
1862 RADEON_PM_MODE_NO_DISPLAY;
1867 rdev->pm.power_state[state_index].num_clock_modes = 1;
1868 rdev->pm.power_state[state_index].clock_info[0].mclk =
1869 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1870 rdev->pm.power_state[state_index].clock_info[0].sclk =
1871 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1872 /* skip invalid modes */
1873 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1874 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1876 rdev->pm.power_state[state_index].pcie_lanes =
1877 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1878 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1879 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1880 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1881 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1882 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1884 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1885 radeon_lookup_gpio(rdev,
1886 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1887 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1888 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1891 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1893 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1894 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1896 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1897 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1899 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1900 rdev->pm.power_state[state_index].misc = misc;
1901 rdev->pm.power_state[state_index].misc2 = misc2;
1902 /* order matters! */
1903 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1904 rdev->pm.power_state[state_index].type =
1905 POWER_STATE_TYPE_POWERSAVE;
1906 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1907 rdev->pm.power_state[state_index].type =
1908 POWER_STATE_TYPE_BATTERY;
1909 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1910 rdev->pm.power_state[state_index].type =
1911 POWER_STATE_TYPE_BATTERY;
1912 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1913 rdev->pm.power_state[state_index].type =
1914 POWER_STATE_TYPE_BALANCED;
1915 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1916 rdev->pm.power_state[state_index].type =
1917 POWER_STATE_TYPE_PERFORMANCE;
1918 rdev->pm.power_state[state_index].flags &=
1919 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1921 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1922 rdev->pm.power_state[state_index].type =
1923 POWER_STATE_TYPE_BALANCED;
1924 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1925 rdev->pm.power_state[state_index].flags &=
1926 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1927 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1928 rdev->pm.power_state[state_index].type =
1929 POWER_STATE_TYPE_DEFAULT;
1930 rdev->pm.default_power_state_index = state_index;
1931 rdev->pm.power_state[state_index].default_clock_mode =
1932 &rdev->pm.power_state[state_index].clock_info[0];
1933 rdev->pm.power_state[state_index].flags &=
1934 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1935 } else if (state_index == 0) {
1936 rdev->pm.power_state[state_index].clock_info[0].flags |=
1937 RADEON_PM_MODE_NO_DISPLAY;
1942 rdev->pm.power_state[state_index].num_clock_modes = 1;
1943 rdev->pm.power_state[state_index].clock_info[0].mclk =
1944 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1945 rdev->pm.power_state[state_index].clock_info[0].sclk =
1946 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1947 /* skip invalid modes */
1948 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1949 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1951 rdev->pm.power_state[state_index].pcie_lanes =
1952 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1953 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1954 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1955 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1956 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1957 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1959 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1960 radeon_lookup_gpio(rdev,
1961 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1962 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1963 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1966 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1968 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1969 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1971 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1972 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1973 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1974 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1976 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1977 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1980 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1981 rdev->pm.power_state[state_index].misc = misc;
1982 rdev->pm.power_state[state_index].misc2 = misc2;
1983 /* order matters! */
1984 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1985 rdev->pm.power_state[state_index].type =
1986 POWER_STATE_TYPE_POWERSAVE;
1987 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1988 rdev->pm.power_state[state_index].type =
1989 POWER_STATE_TYPE_BATTERY;
1990 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1991 rdev->pm.power_state[state_index].type =
1992 POWER_STATE_TYPE_BATTERY;
1993 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1994 rdev->pm.power_state[state_index].type =
1995 POWER_STATE_TYPE_BALANCED;
1996 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1997 rdev->pm.power_state[state_index].type =
1998 POWER_STATE_TYPE_PERFORMANCE;
1999 rdev->pm.power_state[state_index].flags &=
2000 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2002 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2003 rdev->pm.power_state[state_index].type =
2004 POWER_STATE_TYPE_BALANCED;
2005 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2006 rdev->pm.power_state[state_index].type =
2007 POWER_STATE_TYPE_DEFAULT;
2008 rdev->pm.default_power_state_index = state_index;
2009 rdev->pm.power_state[state_index].default_clock_mode =
2010 &rdev->pm.power_state[state_index].clock_info[0];
2011 } else if (state_index == 0) {
2012 rdev->pm.power_state[state_index].clock_info[0].flags |=
2013 RADEON_PM_MODE_NO_DISPLAY;
2019 /* last mode is usually default */
2020 if (rdev->pm.default_power_state_index == -1) {
2021 rdev->pm.power_state[state_index - 1].type =
2022 POWER_STATE_TYPE_DEFAULT;
2023 rdev->pm.default_power_state_index = state_index - 1;
2024 rdev->pm.power_state[state_index - 1].default_clock_mode =
2025 &rdev->pm.power_state[state_index - 1].clock_info[0];
2026 rdev->pm.power_state[state_index].flags &=
2027 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2028 rdev->pm.power_state[state_index].misc = 0;
2029 rdev->pm.power_state[state_index].misc2 = 0;
2032 int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2033 uint8_t fw_frev, fw_crev;
2034 uint16_t fw_data_offset, vddc = 0;
2035 union firmware_info *firmware_info;
2036 ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
2038 if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
2039 &fw_frev, &fw_crev, &fw_data_offset)) {
2041 (union firmware_info *)(mode_info->atom_context->bios +
2043 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2046 /* add the i2c bus for thermal/fan chip */
2047 if (controller->ucType > 0) {
2048 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2049 DRM_INFO("Internal thermal controller %s fan control\n",
2050 (controller->ucFanParameters &
2051 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2052 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2053 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2054 DRM_INFO("Internal thermal controller %s fan control\n",
2055 (controller->ucFanParameters &
2056 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2057 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2058 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2059 DRM_INFO("Internal thermal controller %s fan control\n",
2060 (controller->ucFanParameters &
2061 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2062 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2063 } else if ((controller->ucType ==
2064 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2065 (controller->ucType ==
2066 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
2067 DRM_INFO("Special thermal controller config\n");
2069 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2070 pp_lib_thermal_controller_names[controller->ucType],
2071 controller->ucI2cAddress >> 1,
2072 (controller->ucFanParameters &
2073 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2074 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2075 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2076 if (rdev->pm.i2c_bus) {
2077 struct i2c_board_info info = { };
2078 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2079 info.addr = controller->ucI2cAddress >> 1;
2080 strlcpy(info.type, name, sizeof(info.type));
2081 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2086 /* first mode is usually default, followed by low to high */
2087 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
2089 power_state = (struct _ATOM_PPLIB_STATE *)
2090 (mode_info->atom_context->bios +
2092 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
2093 i * power_info->info_4.ucStateEntrySize);
2094 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2095 (mode_info->atom_context->bios +
2097 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
2098 (power_state->ucNonClockStateIndex *
2099 power_info->info_4.ucNonClockSize));
2100 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
2101 if (rdev->flags & RADEON_IS_IGP) {
2102 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
2103 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
2104 (mode_info->atom_context->bios +
2106 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2107 (power_state->ucClockStateIndices[j] *
2108 power_info->info_4.ucClockInfoSize));
2109 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
2110 sclk |= clock_info->ucLowEngineClockHigh << 16;
2111 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2112 /* skip invalid modes */
2113 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2115 /* voltage works differently on IGPs */
2117 } else if (ASIC_IS_DCE4(rdev)) {
2118 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
2119 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
2120 (mode_info->atom_context->bios +
2122 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2123 (power_state->ucClockStateIndices[j] *
2124 power_info->info_4.ucClockInfoSize));
2125 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2126 sclk |= clock_info->ucEngineClockHigh << 16;
2127 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2128 mclk |= clock_info->ucMemoryClockHigh << 16;
2129 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2130 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2131 /* skip invalid modes */
2132 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2133 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2135 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2137 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2142 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
2143 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
2144 (mode_info->atom_context->bios +
2146 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
2147 (power_state->ucClockStateIndices[j] *
2148 power_info->info_4.ucClockInfoSize));
2149 sclk = le16_to_cpu(clock_info->usEngineClockLow);
2150 sclk |= clock_info->ucEngineClockHigh << 16;
2151 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
2152 mclk |= clock_info->ucMemoryClockHigh << 16;
2153 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2154 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2155 /* skip invalid modes */
2156 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2157 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2159 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2161 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2166 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2168 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2169 misc2 = le16_to_cpu(non_clock_info->usClassification);
2170 rdev->pm.power_state[state_index].misc = misc;
2171 rdev->pm.power_state[state_index].misc2 = misc2;
2172 rdev->pm.power_state[state_index].pcie_lanes =
2173 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2174 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2175 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2176 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2177 rdev->pm.power_state[state_index].type =
2178 POWER_STATE_TYPE_BATTERY;
2180 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2181 rdev->pm.power_state[state_index].type =
2182 POWER_STATE_TYPE_BALANCED;
2184 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2185 rdev->pm.power_state[state_index].type =
2186 POWER_STATE_TYPE_PERFORMANCE;
2188 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2189 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2190 rdev->pm.power_state[state_index].type =
2191 POWER_STATE_TYPE_PERFORMANCE;
2194 rdev->pm.power_state[state_index].flags = 0;
2195 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2196 rdev->pm.power_state[state_index].flags |=
2197 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2198 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2199 rdev->pm.power_state[state_index].type =
2200 POWER_STATE_TYPE_DEFAULT;
2201 rdev->pm.default_power_state_index = state_index;
2202 rdev->pm.power_state[state_index].default_clock_mode =
2203 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2204 /* patch the table values with the default slck/mclk from firmware info */
2205 for (j = 0; j < mode_index; j++) {
2206 rdev->pm.power_state[state_index].clock_info[j].mclk =
2207 rdev->clock.default_mclk;
2208 rdev->pm.power_state[state_index].clock_info[j].sclk =
2209 rdev->clock.default_sclk;
2211 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2218 /* if multiple clock modes, mark the lowest as no display */
2219 for (i = 0; i < state_index; i++) {
2220 if (rdev->pm.power_state[i].num_clock_modes > 1)
2221 rdev->pm.power_state[i].clock_info[0].flags |=
2222 RADEON_PM_MODE_NO_DISPLAY;
2224 /* first mode is usually default */
2225 if (rdev->pm.default_power_state_index == -1) {
2226 rdev->pm.power_state[0].type =
2227 POWER_STATE_TYPE_DEFAULT;
2228 rdev->pm.default_power_state_index = 0;
2229 rdev->pm.power_state[0].default_clock_mode =
2230 &rdev->pm.power_state[0].clock_info[0];
2234 /* add the default mode */
2235 rdev->pm.power_state[state_index].type =
2236 POWER_STATE_TYPE_DEFAULT;
2237 rdev->pm.power_state[state_index].num_clock_modes = 1;
2238 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2239 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2240 rdev->pm.power_state[state_index].default_clock_mode =
2241 &rdev->pm.power_state[state_index].clock_info[0];
2242 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2243 rdev->pm.power_state[state_index].pcie_lanes = 16;
2244 rdev->pm.default_power_state_index = state_index;
2245 rdev->pm.power_state[state_index].flags = 0;
2249 rdev->pm.num_power_states = state_index;
2251 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2252 rdev->pm.current_clock_mode_index = 0;
2253 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2256 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2258 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2259 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2261 args.ucEnable = enable;
2263 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2266 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2268 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2269 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2271 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2272 return args.ulReturnEngineClock;
2275 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2277 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2278 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2280 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2281 return args.ulReturnMemoryClock;
2284 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2287 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2288 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2290 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2292 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2295 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2298 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2299 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2301 if (rdev->flags & RADEON_IS_IGP)
2304 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2306 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2310 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2311 struct _SET_VOLTAGE_PARAMETERS v1;
2312 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2315 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2317 union set_voltage args;
2318 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2319 u8 frev, crev, volt_index = level;
2321 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2326 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2327 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2328 args.v1.ucVoltageIndex = volt_index;
2331 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2332 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2333 args.v2.usVoltageLevel = cpu_to_le16(level);
2336 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2345 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2347 struct radeon_device *rdev = dev->dev_private;
2348 uint32_t bios_2_scratch, bios_6_scratch;
2350 if (rdev->family >= CHIP_R600) {
2351 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2352 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2354 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2355 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2358 /* let the bios control the backlight */
2359 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2361 /* tell the bios not to handle mode switching */
2362 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2364 if (rdev->family >= CHIP_R600) {
2365 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2366 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2368 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2369 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2374 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2376 uint32_t scratch_reg;
2379 if (rdev->family >= CHIP_R600)
2380 scratch_reg = R600_BIOS_0_SCRATCH;
2382 scratch_reg = RADEON_BIOS_0_SCRATCH;
2384 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2385 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2388 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2390 uint32_t scratch_reg;
2393 if (rdev->family >= CHIP_R600)
2394 scratch_reg = R600_BIOS_0_SCRATCH;
2396 scratch_reg = RADEON_BIOS_0_SCRATCH;
2398 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2399 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2402 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2404 struct drm_device *dev = encoder->dev;
2405 struct radeon_device *rdev = dev->dev_private;
2406 uint32_t bios_6_scratch;
2408 if (rdev->family >= CHIP_R600)
2409 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2411 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2414 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2416 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2418 if (rdev->family >= CHIP_R600)
2419 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2421 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2424 /* at some point we may want to break this out into individual functions */
2426 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2427 struct drm_encoder *encoder,
2430 struct drm_device *dev = connector->dev;
2431 struct radeon_device *rdev = dev->dev_private;
2432 struct radeon_connector *radeon_connector =
2433 to_radeon_connector(connector);
2434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2435 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2437 if (rdev->family >= CHIP_R600) {
2438 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2439 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2440 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2442 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2443 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2444 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2447 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2448 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2450 DRM_DEBUG_KMS("TV1 connected\n");
2451 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2452 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2454 DRM_DEBUG_KMS("TV1 disconnected\n");
2455 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2456 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2457 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2460 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2461 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2463 DRM_DEBUG_KMS("CV connected\n");
2464 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2465 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2467 DRM_DEBUG_KMS("CV disconnected\n");
2468 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2469 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2470 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2473 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2474 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2476 DRM_DEBUG_KMS("LCD1 connected\n");
2477 bios_0_scratch |= ATOM_S0_LCD1;
2478 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2479 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2481 DRM_DEBUG_KMS("LCD1 disconnected\n");
2482 bios_0_scratch &= ~ATOM_S0_LCD1;
2483 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2484 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2487 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2488 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2490 DRM_DEBUG_KMS("CRT1 connected\n");
2491 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2492 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2493 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2495 DRM_DEBUG_KMS("CRT1 disconnected\n");
2496 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2497 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2498 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2501 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2502 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2504 DRM_DEBUG_KMS("CRT2 connected\n");
2505 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2506 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2507 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2509 DRM_DEBUG_KMS("CRT2 disconnected\n");
2510 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2511 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2512 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2515 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2516 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2518 DRM_DEBUG_KMS("DFP1 connected\n");
2519 bios_0_scratch |= ATOM_S0_DFP1;
2520 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2521 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2523 DRM_DEBUG_KMS("DFP1 disconnected\n");
2524 bios_0_scratch &= ~ATOM_S0_DFP1;
2525 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2526 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2529 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2530 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2532 DRM_DEBUG_KMS("DFP2 connected\n");
2533 bios_0_scratch |= ATOM_S0_DFP2;
2534 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2535 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2537 DRM_DEBUG_KMS("DFP2 disconnected\n");
2538 bios_0_scratch &= ~ATOM_S0_DFP2;
2539 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2540 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2543 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2544 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2546 DRM_DEBUG_KMS("DFP3 connected\n");
2547 bios_0_scratch |= ATOM_S0_DFP3;
2548 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2549 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2551 DRM_DEBUG_KMS("DFP3 disconnected\n");
2552 bios_0_scratch &= ~ATOM_S0_DFP3;
2553 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2554 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2557 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2558 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2560 DRM_DEBUG_KMS("DFP4 connected\n");
2561 bios_0_scratch |= ATOM_S0_DFP4;
2562 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2563 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2565 DRM_DEBUG_KMS("DFP4 disconnected\n");
2566 bios_0_scratch &= ~ATOM_S0_DFP4;
2567 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2568 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2571 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2572 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2574 DRM_DEBUG_KMS("DFP5 connected\n");
2575 bios_0_scratch |= ATOM_S0_DFP5;
2576 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2577 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2579 DRM_DEBUG_KMS("DFP5 disconnected\n");
2580 bios_0_scratch &= ~ATOM_S0_DFP5;
2581 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2582 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2586 if (rdev->family >= CHIP_R600) {
2587 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2588 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2589 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2591 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2592 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2593 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2598 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2600 struct drm_device *dev = encoder->dev;
2601 struct radeon_device *rdev = dev->dev_private;
2602 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2603 uint32_t bios_3_scratch;
2605 if (rdev->family >= CHIP_R600)
2606 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2608 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2610 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2611 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2612 bios_3_scratch |= (crtc << 18);
2614 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2615 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2616 bios_3_scratch |= (crtc << 24);
2618 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2619 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2620 bios_3_scratch |= (crtc << 16);
2622 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2623 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2624 bios_3_scratch |= (crtc << 20);
2626 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2627 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2628 bios_3_scratch |= (crtc << 17);
2630 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2631 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2632 bios_3_scratch |= (crtc << 19);
2634 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2635 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2636 bios_3_scratch |= (crtc << 23);
2638 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2639 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2640 bios_3_scratch |= (crtc << 25);
2643 if (rdev->family >= CHIP_R600)
2644 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2646 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2650 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2652 struct drm_device *dev = encoder->dev;
2653 struct radeon_device *rdev = dev->dev_private;
2654 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2655 uint32_t bios_2_scratch;
2657 if (rdev->family >= CHIP_R600)
2658 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2660 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2662 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2664 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2666 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2668 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2670 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2672 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2674 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2676 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2678 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2680 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2682 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2684 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2686 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2688 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2690 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2692 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2694 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2696 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2698 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2700 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2702 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2704 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2706 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2708 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2710 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2712 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2714 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2716 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2718 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2720 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2723 if (rdev->family >= CHIP_R600)
2724 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2726 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);