2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
39 /* If you boot an IGP board with a discrete card as the primary,
40 * the IGP rom is not accessible via the rom bar as the IGP rom is
41 * part of the system bios. On boot, the system bios puts a
42 * copy of the igp rom at the start of vram if a discrete card is
45 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
47 uint8_t __iomem *bios;
48 resource_size_t vram_base;
49 resource_size_t size = 256 * 1024; /* ??? */
51 if (!(rdev->flags & RADEON_IS_IGP))
52 if (!radeon_card_posted(rdev))
56 vram_base = pci_resource_start(rdev->pdev, 0);
57 bios = ioremap(vram_base, size);
62 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
66 rdev->bios = kmalloc(size, GFP_KERNEL);
67 if (rdev->bios == NULL) {
71 memcpy_fromio(rdev->bios, bios, size);
76 static bool radeon_read_bios(struct radeon_device *rdev)
78 uint8_t __iomem *bios;
82 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
83 bios = pci_map_rom(rdev->pdev, &size);
88 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
89 pci_unmap_rom(rdev->pdev, bios);
92 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
93 if (rdev->bios == NULL) {
94 pci_unmap_rom(rdev->pdev, bios);
97 pci_unmap_rom(rdev->pdev, bios);
101 /* ATRM is used to get the BIOS on the discrete cards in
104 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
107 int size = 64 * 1024;
110 if (!radeon_atrm_supported(rdev->pdev))
113 rdev->bios = kmalloc(size, GFP_KERNEL);
115 DRM_ERROR("Unable to allocate bios\n");
119 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
120 ret = radeon_atrm_get_bios_chunk(rdev->bios,
121 (i * ATRM_BIOS_PAGE),
127 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
133 static bool r700_read_disabled_bios(struct radeon_device *rdev)
135 uint32_t viph_control;
137 uint32_t d1vga_control;
138 uint32_t d2vga_control;
139 uint32_t vga_render_control;
141 uint32_t cg_spll_func_cntl = 0;
142 uint32_t cg_spll_status;
145 viph_control = RREG32(RADEON_VIPH_CONTROL);
146 bus_cntl = RREG32(RADEON_BUS_CNTL);
147 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
148 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
149 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
150 rom_cntl = RREG32(R600_ROM_CNTL);
153 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
155 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
156 /* Disable VGA mode */
157 WREG32(AVIVO_D1VGA_CONTROL,
158 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
159 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
160 WREG32(AVIVO_D2VGA_CONTROL,
161 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
162 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
163 WREG32(AVIVO_VGA_RENDER_CONTROL,
164 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
166 if (rdev->family == CHIP_RV730) {
167 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
169 /* enable bypass mode */
170 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
171 R600_SPLL_BYPASS_EN));
173 /* wait for SPLL_CHG_STATUS to change to 1 */
175 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
176 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
178 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
180 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
182 r = radeon_read_bios(rdev);
185 if (rdev->family == CHIP_RV730) {
186 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
188 /* wait for SPLL_CHG_STATUS to change to 1 */
190 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
191 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
193 WREG32(RADEON_VIPH_CONTROL, viph_control);
194 WREG32(RADEON_BUS_CNTL, bus_cntl);
195 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
196 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
197 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
198 WREG32(R600_ROM_CNTL, rom_cntl);
202 static bool r600_read_disabled_bios(struct radeon_device *rdev)
204 uint32_t viph_control;
206 uint32_t d1vga_control;
207 uint32_t d2vga_control;
208 uint32_t vga_render_control;
210 uint32_t general_pwrmgt;
211 uint32_t low_vid_lower_gpio_cntl;
212 uint32_t medium_vid_lower_gpio_cntl;
213 uint32_t high_vid_lower_gpio_cntl;
214 uint32_t ctxsw_vid_lower_gpio_cntl;
215 uint32_t lower_gpio_enable;
218 viph_control = RREG32(RADEON_VIPH_CONTROL);
219 bus_cntl = RREG32(RADEON_BUS_CNTL);
220 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
221 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
222 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
223 rom_cntl = RREG32(R600_ROM_CNTL);
224 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
225 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
226 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
227 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
228 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
229 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
232 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
234 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
235 /* Disable VGA mode */
236 WREG32(AVIVO_D1VGA_CONTROL,
237 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
238 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
239 WREG32(AVIVO_D2VGA_CONTROL,
240 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
241 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
242 WREG32(AVIVO_VGA_RENDER_CONTROL,
243 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
245 WREG32(R600_ROM_CNTL,
246 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
247 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
248 R600_SCK_OVERWRITE));
250 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
251 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
252 (low_vid_lower_gpio_cntl & ~0x400));
253 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
254 (medium_vid_lower_gpio_cntl & ~0x400));
255 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
256 (high_vid_lower_gpio_cntl & ~0x400));
257 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
258 (ctxsw_vid_lower_gpio_cntl & ~0x400));
259 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
261 r = radeon_read_bios(rdev);
264 WREG32(RADEON_VIPH_CONTROL, viph_control);
265 WREG32(RADEON_BUS_CNTL, bus_cntl);
266 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
267 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
268 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
269 WREG32(R600_ROM_CNTL, rom_cntl);
270 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
271 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
272 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
273 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
274 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
275 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
279 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
281 uint32_t seprom_cntl1;
282 uint32_t viph_control;
284 uint32_t d1vga_control;
285 uint32_t d2vga_control;
286 uint32_t vga_render_control;
289 uint32_t gpiopad_mask;
292 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
293 viph_control = RREG32(RADEON_VIPH_CONTROL);
294 bus_cntl = RREG32(RADEON_BUS_CNTL);
295 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
296 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
297 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
298 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
299 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
300 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
302 WREG32(RADEON_SEPROM_CNTL1,
303 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
304 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
305 WREG32(RADEON_GPIOPAD_A, 0);
306 WREG32(RADEON_GPIOPAD_EN, 0);
307 WREG32(RADEON_GPIOPAD_MASK, 0);
310 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
313 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
315 /* Disable VGA mode */
316 WREG32(AVIVO_D1VGA_CONTROL,
317 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
318 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
319 WREG32(AVIVO_D2VGA_CONTROL,
320 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
321 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
322 WREG32(AVIVO_VGA_RENDER_CONTROL,
323 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
325 r = radeon_read_bios(rdev);
328 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
329 WREG32(RADEON_VIPH_CONTROL, viph_control);
330 WREG32(RADEON_BUS_CNTL, bus_cntl);
331 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
332 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
333 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
334 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
335 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
336 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
340 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
342 uint32_t seprom_cntl1;
343 uint32_t viph_control;
345 uint32_t crtc_gen_cntl;
346 uint32_t crtc2_gen_cntl;
347 uint32_t crtc_ext_cntl;
348 uint32_t fp2_gen_cntl;
351 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
352 viph_control = RREG32(RADEON_VIPH_CONTROL);
353 bus_cntl = RREG32(RADEON_BUS_CNTL);
354 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
356 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
359 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
360 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
363 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
364 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
367 WREG32(RADEON_SEPROM_CNTL1,
368 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
369 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
372 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
375 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
377 /* Turn off mem requests and CRTC for both controllers */
378 WREG32(RADEON_CRTC_GEN_CNTL,
379 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
380 (RADEON_CRTC_DISP_REQ_EN_B |
381 RADEON_CRTC_EXT_DISP_EN)));
382 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
383 WREG32(RADEON_CRTC2_GEN_CNTL,
384 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
385 RADEON_CRTC2_DISP_REQ_EN_B));
388 WREG32(RADEON_CRTC_EXT_CNTL,
389 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
390 (RADEON_CRTC_SYNC_TRISTAT |
391 RADEON_CRTC_DISPLAY_DIS)));
393 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
394 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
397 r = radeon_read_bios(rdev);
400 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
401 WREG32(RADEON_VIPH_CONTROL, viph_control);
402 WREG32(RADEON_BUS_CNTL, bus_cntl);
403 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
404 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
405 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
407 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
408 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
409 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
414 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
416 if (rdev->flags & RADEON_IS_IGP)
417 return igp_read_bios_from_vram(rdev);
418 else if (rdev->family >= CHIP_RV770)
419 return r700_read_disabled_bios(rdev);
420 else if (rdev->family >= CHIP_R600)
421 return r600_read_disabled_bios(rdev);
422 else if (rdev->family >= CHIP_RS600)
423 return avivo_read_disabled_bios(rdev);
425 return legacy_read_disabled_bios(rdev);
429 bool radeon_get_bios(struct radeon_device *rdev)
434 r = radeon_atrm_get_bios(rdev);
436 r = igp_read_bios_from_vram(rdev);
438 r = radeon_read_bios(rdev);
440 r = radeon_read_disabled_bios(rdev);
442 if (r == false || rdev->bios == NULL) {
443 DRM_ERROR("Unable to locate a BIOS ROM\n");
447 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
448 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
453 if (RBIOS8(tmp + 0x14) != 0x0) {
454 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
458 rdev->bios_header_start = RBIOS16(0x48);
459 if (!rdev->bios_header_start) {
462 tmp = rdev->bios_header_start + 4;
463 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
464 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
465 rdev->is_atom_bios = true;
467 rdev->is_atom_bios = false;
470 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");