2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
158 offset = check_offset;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
163 offset = check_offset;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
168 offset = check_offset;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
173 offset = check_offset;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
178 offset = check_offset;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
183 offset = check_offset;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
188 offset = check_offset;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
193 offset = check_offset;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
198 offset = check_offset;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
203 offset = check_offset;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
208 offset = check_offset;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
213 offset = check_offset;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
218 offset = check_offset;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
223 offset = check_offset;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
228 offset = check_offset;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
233 offset = check_offset;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
238 offset = check_offset;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
243 offset = check_offset;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
248 offset = check_offset;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
253 offset = check_offset;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
258 offset = check_offset;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
263 offset = check_offset;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
268 offset = check_offset;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
273 offset = check_offset;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
278 offset = check_offset;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
283 offset = check_offset;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
288 offset = check_offset;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
293 offset = check_offset;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
298 offset = check_offset;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
303 offset = check_offset;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
308 offset = check_offset;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
313 offset = check_offset;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
318 offset = check_offset;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
323 offset = check_offset;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
330 rev = RBIOS8(check_offset);
332 check_offset = RBIOS16(check_offset + 0x3);
334 offset = check_offset;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
342 rev = RBIOS8(check_offset);
344 check_offset = RBIOS16(check_offset + 0x5);
346 offset = check_offset;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
354 rev = RBIOS8(check_offset);
356 check_offset = RBIOS16(check_offset + 0x7);
358 offset = check_offset;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
366 rev = RBIOS8(check_offset);
368 check_offset = RBIOS16(check_offset + 0x9);
370 offset = check_offset;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
378 while (RBIOS8(check_offset++));
381 offset = check_offset;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
388 check_offset = RBIOS16(check_offset + 0x11);
390 offset = check_offset;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
397 check_offset = RBIOS16(check_offset + 0x13);
399 offset = check_offset;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
406 check_offset = RBIOS16(check_offset + 0x15);
408 offset = check_offset;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
415 check_offset = RBIOS16(check_offset + 0x17);
417 offset = check_offset;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
424 check_offset = RBIOS16(check_offset + 0x2);
426 offset = check_offset;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
433 check_offset = RBIOS16(check_offset + 0x4);
435 offset = check_offset;
446 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
449 struct radeon_i2c_bus_rec i2c;
451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
489 if (rdev->family < CHIP_R200)
490 i2c.hw_capable = false;
493 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC:
495 i2c.hw_capable = true;
497 case RADEON_GPIO_MONID:
498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
499 * reliably on some pre-r4xx hardware; not sure why.
501 i2c.hw_capable = false;
504 i2c.hw_capable = false;
519 bool radeon_combios_get_clock_info(struct drm_device *dev)
521 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_pll *p1pll = &rdev->clock.p1pll;
524 struct radeon_pll *p2pll = &rdev->clock.p2pll;
525 struct radeon_pll *spll = &rdev->clock.spll;
526 struct radeon_pll *mpll = &rdev->clock.mpll;
530 if (rdev->bios == NULL)
533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
535 rev = RBIOS8(pll_info);
538 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
539 p1pll->reference_div = RBIOS16(pll_info + 0x10);
540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
547 p1pll->pll_in_min = 40;
548 p1pll->pll_in_max = 500;
553 spll->reference_freq = RBIOS16(pll_info + 0x1a);
554 spll->reference_div = RBIOS16(pll_info + 0x1c);
555 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
556 spll->pll_out_max = RBIOS32(pll_info + 0x22);
559 spll->pll_in_min = RBIOS32(pll_info + 0x48);
560 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
563 spll->pll_in_min = 40;
564 spll->pll_in_max = 500;
568 mpll->reference_freq = RBIOS16(pll_info + 0x26);
569 mpll->reference_div = RBIOS16(pll_info + 0x28);
570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
578 mpll->pll_in_min = 40;
579 mpll->pll_in_max = 500;
582 /* default sclk/mclk */
583 sclk = RBIOS16(pll_info + 0xa);
584 mclk = RBIOS16(pll_info + 0x8);
590 rdev->clock.default_sclk = sclk;
591 rdev->clock.default_mclk = mclk;
598 bool radeon_combios_sideport_present(struct radeon_device *rdev)
600 struct drm_device *dev = rdev->ddev;
603 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
606 if (RBIOS16(igp_info + 0x4))
612 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
613 0x00000808, /* r100 */
614 0x00000808, /* rv100 */
615 0x00000808, /* rs100 */
616 0x00000808, /* rv200 */
617 0x00000808, /* rs200 */
618 0x00000808, /* r200 */
619 0x00000808, /* rv250 */
620 0x00000000, /* rs300 */
621 0x00000808, /* rv280 */
622 0x00000808, /* r300 */
623 0x00000808, /* r350 */
624 0x00000808, /* rv350 */
625 0x00000808, /* rv380 */
626 0x00000808, /* r420 */
627 0x00000808, /* r423 */
628 0x00000808, /* rv410 */
629 0x00000000, /* rs400 */
630 0x00000000, /* rs480 */
633 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
634 struct radeon_encoder_primary_dac *p_dac)
636 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
640 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
644 struct drm_device *dev = encoder->base.dev;
645 struct radeon_device *rdev = dev->dev_private;
647 uint8_t rev, bg, dac;
648 struct radeon_encoder_primary_dac *p_dac = NULL;
651 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
657 if (rdev->bios == NULL)
660 /* check CRT table */
661 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
663 rev = RBIOS8(dac_info) & 0x3;
665 bg = RBIOS8(dac_info + 0x2) & 0xf;
666 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
669 bg = RBIOS8(dac_info + 0x2) & 0xf;
670 dac = RBIOS8(dac_info + 0x3) & 0xf;
671 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
677 if (!found) /* fallback to defaults */
678 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
684 radeon_combios_get_tv_info(struct radeon_device *rdev)
686 struct drm_device *dev = rdev->ddev;
688 enum radeon_tv_std tv_std = TV_STD_NTSC;
690 if (rdev->bios == NULL)
693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
695 if (RBIOS8(tv_info + 6) == 'T') {
696 switch (RBIOS8(tv_info + 7) & 0xf) {
698 tv_std = TV_STD_NTSC;
699 DRM_INFO("Default TV standard: NTSC\n");
703 DRM_INFO("Default TV standard: PAL\n");
706 tv_std = TV_STD_PAL_M;
707 DRM_INFO("Default TV standard: PAL-M\n");
710 tv_std = TV_STD_PAL_60;
711 DRM_INFO("Default TV standard: PAL-60\n");
714 tv_std = TV_STD_NTSC_J;
715 DRM_INFO("Default TV standard: NTSC-J\n");
718 tv_std = TV_STD_SCART_PAL;
719 DRM_INFO("Default TV standard: SCART-PAL\n");
722 tv_std = TV_STD_NTSC;
724 ("Unknown TV standard; defaulting to NTSC\n");
728 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
730 DRM_INFO("29.498928713 MHz TV ref clk\n");
733 DRM_INFO("28.636360000 MHz TV ref clk\n");
736 DRM_INFO("14.318180000 MHz TV ref clk\n");
739 DRM_INFO("27.000000000 MHz TV ref clk\n");
749 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
750 0x00000000, /* r100 */
751 0x00280000, /* rv100 */
752 0x00000000, /* rs100 */
753 0x00880000, /* rv200 */
754 0x00000000, /* rs200 */
755 0x00000000, /* r200 */
756 0x00770000, /* rv250 */
757 0x00290000, /* rs300 */
758 0x00560000, /* rv280 */
759 0x00780000, /* r300 */
760 0x00770000, /* r350 */
761 0x00780000, /* rv350 */
762 0x00780000, /* rv380 */
763 0x01080000, /* r420 */
764 0x01080000, /* r423 */
765 0x01080000, /* rv410 */
766 0x00780000, /* rs400 */
767 0x00780000, /* rs480 */
770 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
771 struct radeon_encoder_tv_dac *tv_dac)
773 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
774 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
775 tv_dac->ps2_tvdac_adj = 0x00880000;
776 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
777 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
781 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
785 struct drm_device *dev = encoder->base.dev;
786 struct radeon_device *rdev = dev->dev_private;
788 uint8_t rev, bg, dac;
789 struct radeon_encoder_tv_dac *tv_dac = NULL;
792 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
796 if (rdev->bios == NULL)
799 /* first check TV table */
800 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
802 rev = RBIOS8(dac_info + 0x3);
804 bg = RBIOS8(dac_info + 0xc) & 0xf;
805 dac = RBIOS8(dac_info + 0xd) & 0xf;
806 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
808 bg = RBIOS8(dac_info + 0xe) & 0xf;
809 dac = RBIOS8(dac_info + 0xf) & 0xf;
810 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
812 bg = RBIOS8(dac_info + 0x10) & 0xf;
813 dac = RBIOS8(dac_info + 0x11) & 0xf;
814 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
816 } else if (rev > 1) {
817 bg = RBIOS8(dac_info + 0xc) & 0xf;
818 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
819 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
821 bg = RBIOS8(dac_info + 0xd) & 0xf;
822 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
823 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
825 bg = RBIOS8(dac_info + 0xe) & 0xf;
826 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
827 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
830 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
833 /* then check CRT table */
835 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
837 rev = RBIOS8(dac_info) & 0x3;
839 bg = RBIOS8(dac_info + 0x3) & 0xf;
840 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
841 tv_dac->ps2_tvdac_adj =
842 (bg << 16) | (dac << 20);
843 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
844 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
847 bg = RBIOS8(dac_info + 0x4) & 0xf;
848 dac = RBIOS8(dac_info + 0x5) & 0xf;
849 tv_dac->ps2_tvdac_adj =
850 (bg << 16) | (dac << 20);
851 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
852 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
856 DRM_INFO("No TV DAC info found in BIOS\n");
861 if (!found) /* fallback to defaults */
862 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
867 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
871 struct radeon_encoder_lvds *lvds = NULL;
872 uint32_t fp_vert_stretch, fp_horz_stretch;
873 uint32_t ppll_div_sel, ppll_val;
874 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
876 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
881 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
882 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
884 /* These should be fail-safe defaults, fingers crossed */
885 lvds->panel_pwr_delay = 200;
886 lvds->panel_vcc_delay = 2000;
888 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
889 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
890 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
892 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
893 lvds->native_mode.vdisplay =
894 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
895 RADEON_VERT_PANEL_SHIFT) + 1;
897 lvds->native_mode.vdisplay =
898 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
900 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
901 lvds->native_mode.hdisplay =
902 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
903 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
905 lvds->native_mode.hdisplay =
906 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
908 if ((lvds->native_mode.hdisplay < 640) ||
909 (lvds->native_mode.vdisplay < 480)) {
910 lvds->native_mode.hdisplay = 640;
911 lvds->native_mode.vdisplay = 480;
914 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
915 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
916 if ((ppll_val & 0x000707ff) == 0x1bb)
917 lvds->use_bios_dividers = false;
919 lvds->panel_ref_divider =
920 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
921 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
922 lvds->panel_fb_divider = ppll_val & 0x7ff;
924 if ((lvds->panel_ref_divider != 0) &&
925 (lvds->panel_fb_divider > 3))
926 lvds->use_bios_dividers = true;
928 lvds->panel_vcc_delay = 200;
930 DRM_INFO("Panel info derived from registers\n");
931 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
932 lvds->native_mode.vdisplay);
937 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
940 struct drm_device *dev = encoder->base.dev;
941 struct radeon_device *rdev = dev->dev_private;
943 uint32_t panel_setup;
946 struct radeon_encoder_lvds *lvds = NULL;
948 if (rdev->bios == NULL) {
949 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
953 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
956 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
961 for (i = 0; i < 24; i++)
962 stmp[i] = RBIOS8(lcd_info + i + 1);
965 DRM_INFO("Panel ID String: %s\n", stmp);
967 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
968 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
970 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
971 lvds->native_mode.vdisplay);
973 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
974 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
975 lvds->panel_vcc_delay = 2000;
977 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
978 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
979 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
981 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
982 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
983 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
984 if ((lvds->panel_ref_divider != 0) &&
985 (lvds->panel_fb_divider > 3))
986 lvds->use_bios_dividers = true;
988 panel_setup = RBIOS32(lcd_info + 0x39);
989 lvds->lvds_gen_cntl = 0xff00;
990 if (panel_setup & 0x1)
991 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
993 if ((panel_setup >> 4) & 0x1)
994 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
996 switch ((panel_setup >> 8) & 0x7) {
998 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1001 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1004 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1010 if ((panel_setup >> 16) & 0x1)
1011 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1013 if ((panel_setup >> 17) & 0x1)
1014 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1016 if ((panel_setup >> 18) & 0x1)
1017 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1019 if ((panel_setup >> 23) & 0x1)
1020 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1022 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1024 for (i = 0; i < 32; i++) {
1025 tmp = RBIOS16(lcd_info + 64 + i * 2);
1029 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1030 (RBIOS16(tmp + 2) ==
1031 lvds->native_mode.vdisplay)) {
1032 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1033 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1034 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1035 RBIOS16(tmp + 21)) * 8;
1037 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1038 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1039 lvds->native_mode.vsync_end =
1040 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1041 (RBIOS16(tmp + 28) & 0x7ff);
1043 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1044 lvds->native_mode.flags = 0;
1045 /* set crtc values */
1046 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1051 DRM_INFO("No panel info found in BIOS\n");
1052 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1056 encoder->native_mode = lvds->native_mode;
1060 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1061 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1062 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1063 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1064 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1065 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1066 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1067 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1068 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1069 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1070 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1071 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1072 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1073 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1074 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1075 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1076 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1077 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1078 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1081 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1082 struct radeon_encoder_int_tmds *tmds)
1084 struct drm_device *dev = encoder->base.dev;
1085 struct radeon_device *rdev = dev->dev_private;
1088 for (i = 0; i < 4; i++) {
1089 tmds->tmds_pll[i].value =
1090 default_tmds_pll[rdev->family][i].value;
1091 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1097 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1098 struct radeon_encoder_int_tmds *tmds)
1100 struct drm_device *dev = encoder->base.dev;
1101 struct radeon_device *rdev = dev->dev_private;
1106 if (rdev->bios == NULL)
1109 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1112 ver = RBIOS8(tmds_info);
1113 DRM_INFO("DFP table revision: %d\n", ver);
1115 n = RBIOS8(tmds_info + 5) + 1;
1118 for (i = 0; i < n; i++) {
1119 tmds->tmds_pll[i].value =
1120 RBIOS32(tmds_info + i * 10 + 0x08);
1121 tmds->tmds_pll[i].freq =
1122 RBIOS16(tmds_info + i * 10 + 0x10);
1123 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1124 tmds->tmds_pll[i].freq,
1125 tmds->tmds_pll[i].value);
1127 } else if (ver == 4) {
1129 n = RBIOS8(tmds_info + 5) + 1;
1132 for (i = 0; i < n; i++) {
1133 tmds->tmds_pll[i].value =
1134 RBIOS32(tmds_info + stride + 0x08);
1135 tmds->tmds_pll[i].freq =
1136 RBIOS16(tmds_info + stride + 0x10);
1141 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1142 tmds->tmds_pll[i].freq,
1143 tmds->tmds_pll[i].value);
1147 DRM_INFO("No TMDS info found in BIOS\n");
1153 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1154 struct radeon_encoder_ext_tmds *tmds)
1156 struct drm_device *dev = encoder->base.dev;
1157 struct radeon_device *rdev = dev->dev_private;
1158 struct radeon_i2c_bus_rec i2c_bus;
1160 /* default for macs */
1161 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1162 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1164 /* XXX some macs have duallink chips */
1165 switch (rdev->mode_info.connector_table) {
1166 case CT_POWERBOOK_EXTERNAL:
1167 case CT_MINI_EXTERNAL:
1169 tmds->dvo_chip = DVO_SIL164;
1170 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1177 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1178 struct radeon_encoder_ext_tmds *tmds)
1180 struct drm_device *dev = encoder->base.dev;
1181 struct radeon_device *rdev = dev->dev_private;
1183 uint8_t ver, id, blocks, clk, data;
1185 enum radeon_combios_ddc gpio;
1186 struct radeon_i2c_bus_rec i2c_bus;
1188 if (rdev->bios == NULL)
1191 tmds->i2c_bus = NULL;
1192 if (rdev->flags & RADEON_IS_IGP) {
1193 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1195 ver = RBIOS8(offset);
1196 DRM_INFO("GPIO Table revision: %d\n", ver);
1197 blocks = RBIOS8(offset + 2);
1198 for (i = 0; i < blocks; i++) {
1199 id = RBIOS8(offset + 3 + (i * 5) + 0);
1201 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1202 data = RBIOS8(offset + 3 + (i * 5) + 4);
1203 i2c_bus.valid = true;
1204 i2c_bus.mask_clk_mask = (1 << clk);
1205 i2c_bus.mask_data_mask = (1 << data);
1206 i2c_bus.a_clk_mask = (1 << clk);
1207 i2c_bus.a_data_mask = (1 << data);
1208 i2c_bus.en_clk_mask = (1 << clk);
1209 i2c_bus.en_data_mask = (1 << data);
1210 i2c_bus.y_clk_mask = (1 << clk);
1211 i2c_bus.y_data_mask = (1 << data);
1212 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1213 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1214 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1215 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1216 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1217 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1218 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1219 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1220 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1221 tmds->dvo_chip = DVO_SIL164;
1222 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1228 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1230 ver = RBIOS8(offset);
1231 DRM_INFO("External TMDS Table revision: %d\n", ver);
1232 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1233 tmds->slave_addr >>= 1; /* 7 bit addressing */
1234 gpio = RBIOS8(offset + 4 + 3);
1237 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1238 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1241 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1242 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1245 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1246 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1249 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1250 if (rdev->family >= CHIP_R300)
1251 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1253 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1254 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1256 case DDC_LCD: /* MM i2c */
1257 DRM_ERROR("MM i2c requires hw i2c engine\n");
1260 DRM_ERROR("Unsupported gpio %d\n", gpio);
1266 if (!tmds->i2c_bus) {
1267 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1274 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1276 struct radeon_device *rdev = dev->dev_private;
1277 struct radeon_i2c_bus_rec ddc_i2c;
1278 struct radeon_hpd hpd;
1280 rdev->mode_info.connector_table = radeon_connector_table;
1281 if (rdev->mode_info.connector_table == CT_NONE) {
1282 #ifdef CONFIG_PPC_PMAC
1283 if (machine_is_compatible("PowerBook3,3")) {
1284 /* powerbook with VGA */
1285 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1286 } else if (machine_is_compatible("PowerBook3,4") ||
1287 machine_is_compatible("PowerBook3,5")) {
1288 /* powerbook with internal tmds */
1289 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1290 } else if (machine_is_compatible("PowerBook5,1") ||
1291 machine_is_compatible("PowerBook5,2") ||
1292 machine_is_compatible("PowerBook5,3") ||
1293 machine_is_compatible("PowerBook5,4") ||
1294 machine_is_compatible("PowerBook5,5")) {
1295 /* powerbook with external single link tmds (sil164) */
1296 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1297 } else if (machine_is_compatible("PowerBook5,6")) {
1298 /* powerbook with external dual or single link tmds */
1299 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1300 } else if (machine_is_compatible("PowerBook5,7") ||
1301 machine_is_compatible("PowerBook5,8") ||
1302 machine_is_compatible("PowerBook5,9")) {
1303 /* PowerBook6,2 ? */
1304 /* powerbook with external dual link tmds (sil1178?) */
1305 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1306 } else if (machine_is_compatible("PowerBook4,1") ||
1307 machine_is_compatible("PowerBook4,2") ||
1308 machine_is_compatible("PowerBook4,3") ||
1309 machine_is_compatible("PowerBook6,3") ||
1310 machine_is_compatible("PowerBook6,5") ||
1311 machine_is_compatible("PowerBook6,7")) {
1313 rdev->mode_info.connector_table = CT_IBOOK;
1314 } else if (machine_is_compatible("PowerMac4,4")) {
1316 rdev->mode_info.connector_table = CT_EMAC;
1317 } else if (machine_is_compatible("PowerMac10,1")) {
1318 /* mini with internal tmds */
1319 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1320 } else if (machine_is_compatible("PowerMac10,2")) {
1321 /* mini with external tmds */
1322 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1323 } else if (machine_is_compatible("PowerMac12,1")) {
1325 /* imac g5 isight */
1326 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1328 #endif /* CONFIG_PPC_PMAC */
1329 rdev->mode_info.connector_table = CT_GENERIC;
1332 switch (rdev->mode_info.connector_table) {
1334 DRM_INFO("Connector Table: %d (generic)\n",
1335 rdev->mode_info.connector_table);
1336 /* these are the most common settings */
1337 if (rdev->flags & RADEON_SINGLE_CRTC) {
1338 /* VGA - primary dac */
1339 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1340 hpd.hpd = RADEON_HPD_NONE;
1341 radeon_add_legacy_encoder(dev,
1342 radeon_get_encoder_id(dev,
1343 ATOM_DEVICE_CRT1_SUPPORT,
1345 ATOM_DEVICE_CRT1_SUPPORT);
1346 radeon_add_legacy_connector(dev, 0,
1347 ATOM_DEVICE_CRT1_SUPPORT,
1348 DRM_MODE_CONNECTOR_VGA,
1350 CONNECTOR_OBJECT_ID_VGA,
1352 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1354 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1355 hpd.hpd = RADEON_HPD_NONE;
1356 radeon_add_legacy_encoder(dev,
1357 radeon_get_encoder_id(dev,
1358 ATOM_DEVICE_LCD1_SUPPORT,
1360 ATOM_DEVICE_LCD1_SUPPORT);
1361 radeon_add_legacy_connector(dev, 0,
1362 ATOM_DEVICE_LCD1_SUPPORT,
1363 DRM_MODE_CONNECTOR_LVDS,
1365 CONNECTOR_OBJECT_ID_LVDS,
1368 /* VGA - primary dac */
1369 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1370 hpd.hpd = RADEON_HPD_NONE;
1371 radeon_add_legacy_encoder(dev,
1372 radeon_get_encoder_id(dev,
1373 ATOM_DEVICE_CRT1_SUPPORT,
1375 ATOM_DEVICE_CRT1_SUPPORT);
1376 radeon_add_legacy_connector(dev, 1,
1377 ATOM_DEVICE_CRT1_SUPPORT,
1378 DRM_MODE_CONNECTOR_VGA,
1380 CONNECTOR_OBJECT_ID_VGA,
1383 /* DVI-I - tv dac, int tmds */
1384 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1385 hpd.hpd = RADEON_HPD_1;
1386 radeon_add_legacy_encoder(dev,
1387 radeon_get_encoder_id(dev,
1388 ATOM_DEVICE_DFP1_SUPPORT,
1390 ATOM_DEVICE_DFP1_SUPPORT);
1391 radeon_add_legacy_encoder(dev,
1392 radeon_get_encoder_id(dev,
1393 ATOM_DEVICE_CRT2_SUPPORT,
1395 ATOM_DEVICE_CRT2_SUPPORT);
1396 radeon_add_legacy_connector(dev, 0,
1397 ATOM_DEVICE_DFP1_SUPPORT |
1398 ATOM_DEVICE_CRT2_SUPPORT,
1399 DRM_MODE_CONNECTOR_DVII,
1401 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1404 /* VGA - primary dac */
1405 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1406 hpd.hpd = RADEON_HPD_NONE;
1407 radeon_add_legacy_encoder(dev,
1408 radeon_get_encoder_id(dev,
1409 ATOM_DEVICE_CRT1_SUPPORT,
1411 ATOM_DEVICE_CRT1_SUPPORT);
1412 radeon_add_legacy_connector(dev, 1,
1413 ATOM_DEVICE_CRT1_SUPPORT,
1414 DRM_MODE_CONNECTOR_VGA,
1416 CONNECTOR_OBJECT_ID_VGA,
1420 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1422 ddc_i2c.valid = false;
1423 hpd.hpd = RADEON_HPD_NONE;
1424 radeon_add_legacy_encoder(dev,
1425 radeon_get_encoder_id(dev,
1426 ATOM_DEVICE_TV1_SUPPORT,
1428 ATOM_DEVICE_TV1_SUPPORT);
1429 radeon_add_legacy_connector(dev, 2,
1430 ATOM_DEVICE_TV1_SUPPORT,
1431 DRM_MODE_CONNECTOR_SVIDEO,
1433 CONNECTOR_OBJECT_ID_SVIDEO,
1438 DRM_INFO("Connector Table: %d (ibook)\n",
1439 rdev->mode_info.connector_table);
1441 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1442 hpd.hpd = RADEON_HPD_NONE;
1443 radeon_add_legacy_encoder(dev,
1444 radeon_get_encoder_id(dev,
1445 ATOM_DEVICE_LCD1_SUPPORT,
1447 ATOM_DEVICE_LCD1_SUPPORT);
1448 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1449 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1450 CONNECTOR_OBJECT_ID_LVDS,
1453 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1454 hpd.hpd = RADEON_HPD_NONE;
1455 radeon_add_legacy_encoder(dev,
1456 radeon_get_encoder_id(dev,
1457 ATOM_DEVICE_CRT2_SUPPORT,
1459 ATOM_DEVICE_CRT2_SUPPORT);
1460 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1461 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1462 CONNECTOR_OBJECT_ID_VGA,
1465 ddc_i2c.valid = false;
1466 hpd.hpd = RADEON_HPD_NONE;
1467 radeon_add_legacy_encoder(dev,
1468 radeon_get_encoder_id(dev,
1469 ATOM_DEVICE_TV1_SUPPORT,
1471 ATOM_DEVICE_TV1_SUPPORT);
1472 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1473 DRM_MODE_CONNECTOR_SVIDEO,
1475 CONNECTOR_OBJECT_ID_SVIDEO,
1478 case CT_POWERBOOK_EXTERNAL:
1479 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1480 rdev->mode_info.connector_table);
1482 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1483 hpd.hpd = RADEON_HPD_NONE;
1484 radeon_add_legacy_encoder(dev,
1485 radeon_get_encoder_id(dev,
1486 ATOM_DEVICE_LCD1_SUPPORT,
1488 ATOM_DEVICE_LCD1_SUPPORT);
1489 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1490 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1491 CONNECTOR_OBJECT_ID_LVDS,
1493 /* DVI-I - primary dac, ext tmds */
1494 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1495 hpd.hpd = RADEON_HPD_2; /* ??? */
1496 radeon_add_legacy_encoder(dev,
1497 radeon_get_encoder_id(dev,
1498 ATOM_DEVICE_DFP2_SUPPORT,
1500 ATOM_DEVICE_DFP2_SUPPORT);
1501 radeon_add_legacy_encoder(dev,
1502 radeon_get_encoder_id(dev,
1503 ATOM_DEVICE_CRT1_SUPPORT,
1505 ATOM_DEVICE_CRT1_SUPPORT);
1506 /* XXX some are SL */
1507 radeon_add_legacy_connector(dev, 1,
1508 ATOM_DEVICE_DFP2_SUPPORT |
1509 ATOM_DEVICE_CRT1_SUPPORT,
1510 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1511 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1514 ddc_i2c.valid = false;
1515 hpd.hpd = RADEON_HPD_NONE;
1516 radeon_add_legacy_encoder(dev,
1517 radeon_get_encoder_id(dev,
1518 ATOM_DEVICE_TV1_SUPPORT,
1520 ATOM_DEVICE_TV1_SUPPORT);
1521 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1522 DRM_MODE_CONNECTOR_SVIDEO,
1524 CONNECTOR_OBJECT_ID_SVIDEO,
1527 case CT_POWERBOOK_INTERNAL:
1528 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1529 rdev->mode_info.connector_table);
1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1532 hpd.hpd = RADEON_HPD_NONE;
1533 radeon_add_legacy_encoder(dev,
1534 radeon_get_encoder_id(dev,
1535 ATOM_DEVICE_LCD1_SUPPORT,
1537 ATOM_DEVICE_LCD1_SUPPORT);
1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1540 CONNECTOR_OBJECT_ID_LVDS,
1542 /* DVI-I - primary dac, int tmds */
1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1544 hpd.hpd = RADEON_HPD_1; /* ??? */
1545 radeon_add_legacy_encoder(dev,
1546 radeon_get_encoder_id(dev,
1547 ATOM_DEVICE_DFP1_SUPPORT,
1549 ATOM_DEVICE_DFP1_SUPPORT);
1550 radeon_add_legacy_encoder(dev,
1551 radeon_get_encoder_id(dev,
1552 ATOM_DEVICE_CRT1_SUPPORT,
1554 ATOM_DEVICE_CRT1_SUPPORT);
1555 radeon_add_legacy_connector(dev, 1,
1556 ATOM_DEVICE_DFP1_SUPPORT |
1557 ATOM_DEVICE_CRT1_SUPPORT,
1558 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1559 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1562 ddc_i2c.valid = false;
1563 hpd.hpd = RADEON_HPD_NONE;
1564 radeon_add_legacy_encoder(dev,
1565 radeon_get_encoder_id(dev,
1566 ATOM_DEVICE_TV1_SUPPORT,
1568 ATOM_DEVICE_TV1_SUPPORT);
1569 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1570 DRM_MODE_CONNECTOR_SVIDEO,
1572 CONNECTOR_OBJECT_ID_SVIDEO,
1575 case CT_POWERBOOK_VGA:
1576 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1577 rdev->mode_info.connector_table);
1579 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1580 hpd.hpd = RADEON_HPD_NONE;
1581 radeon_add_legacy_encoder(dev,
1582 radeon_get_encoder_id(dev,
1583 ATOM_DEVICE_LCD1_SUPPORT,
1585 ATOM_DEVICE_LCD1_SUPPORT);
1586 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1587 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1588 CONNECTOR_OBJECT_ID_LVDS,
1590 /* VGA - primary dac */
1591 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1592 hpd.hpd = RADEON_HPD_NONE;
1593 radeon_add_legacy_encoder(dev,
1594 radeon_get_encoder_id(dev,
1595 ATOM_DEVICE_CRT1_SUPPORT,
1597 ATOM_DEVICE_CRT1_SUPPORT);
1598 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1599 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1600 CONNECTOR_OBJECT_ID_VGA,
1603 ddc_i2c.valid = false;
1604 hpd.hpd = RADEON_HPD_NONE;
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_id(dev,
1607 ATOM_DEVICE_TV1_SUPPORT,
1609 ATOM_DEVICE_TV1_SUPPORT);
1610 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1611 DRM_MODE_CONNECTOR_SVIDEO,
1613 CONNECTOR_OBJECT_ID_SVIDEO,
1616 case CT_MINI_EXTERNAL:
1617 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1618 rdev->mode_info.connector_table);
1619 /* DVI-I - tv dac, ext tmds */
1620 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1621 hpd.hpd = RADEON_HPD_2; /* ??? */
1622 radeon_add_legacy_encoder(dev,
1623 radeon_get_encoder_id(dev,
1624 ATOM_DEVICE_DFP2_SUPPORT,
1626 ATOM_DEVICE_DFP2_SUPPORT);
1627 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_id(dev,
1629 ATOM_DEVICE_CRT2_SUPPORT,
1631 ATOM_DEVICE_CRT2_SUPPORT);
1632 /* XXX are any DL? */
1633 radeon_add_legacy_connector(dev, 0,
1634 ATOM_DEVICE_DFP2_SUPPORT |
1635 ATOM_DEVICE_CRT2_SUPPORT,
1636 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1637 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1640 ddc_i2c.valid = false;
1641 hpd.hpd = RADEON_HPD_NONE;
1642 radeon_add_legacy_encoder(dev,
1643 radeon_get_encoder_id(dev,
1644 ATOM_DEVICE_TV1_SUPPORT,
1646 ATOM_DEVICE_TV1_SUPPORT);
1647 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1648 DRM_MODE_CONNECTOR_SVIDEO,
1650 CONNECTOR_OBJECT_ID_SVIDEO,
1653 case CT_MINI_INTERNAL:
1654 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1655 rdev->mode_info.connector_table);
1656 /* DVI-I - tv dac, int tmds */
1657 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1658 hpd.hpd = RADEON_HPD_1; /* ??? */
1659 radeon_add_legacy_encoder(dev,
1660 radeon_get_encoder_id(dev,
1661 ATOM_DEVICE_DFP1_SUPPORT,
1663 ATOM_DEVICE_DFP1_SUPPORT);
1664 radeon_add_legacy_encoder(dev,
1665 radeon_get_encoder_id(dev,
1666 ATOM_DEVICE_CRT2_SUPPORT,
1668 ATOM_DEVICE_CRT2_SUPPORT);
1669 radeon_add_legacy_connector(dev, 0,
1670 ATOM_DEVICE_DFP1_SUPPORT |
1671 ATOM_DEVICE_CRT2_SUPPORT,
1672 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1673 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1676 ddc_i2c.valid = false;
1677 hpd.hpd = RADEON_HPD_NONE;
1678 radeon_add_legacy_encoder(dev,
1679 radeon_get_encoder_id(dev,
1680 ATOM_DEVICE_TV1_SUPPORT,
1682 ATOM_DEVICE_TV1_SUPPORT);
1683 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1684 DRM_MODE_CONNECTOR_SVIDEO,
1686 CONNECTOR_OBJECT_ID_SVIDEO,
1689 case CT_IMAC_G5_ISIGHT:
1690 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1691 rdev->mode_info.connector_table);
1692 /* DVI-D - int tmds */
1693 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1694 hpd.hpd = RADEON_HPD_1; /* ??? */
1695 radeon_add_legacy_encoder(dev,
1696 radeon_get_encoder_id(dev,
1697 ATOM_DEVICE_DFP1_SUPPORT,
1699 ATOM_DEVICE_DFP1_SUPPORT);
1700 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1701 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1702 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1705 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1706 hpd.hpd = RADEON_HPD_NONE;
1707 radeon_add_legacy_encoder(dev,
1708 radeon_get_encoder_id(dev,
1709 ATOM_DEVICE_CRT2_SUPPORT,
1711 ATOM_DEVICE_CRT2_SUPPORT);
1712 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1713 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1714 CONNECTOR_OBJECT_ID_VGA,
1717 ddc_i2c.valid = false;
1718 hpd.hpd = RADEON_HPD_NONE;
1719 radeon_add_legacy_encoder(dev,
1720 radeon_get_encoder_id(dev,
1721 ATOM_DEVICE_TV1_SUPPORT,
1723 ATOM_DEVICE_TV1_SUPPORT);
1724 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1725 DRM_MODE_CONNECTOR_SVIDEO,
1727 CONNECTOR_OBJECT_ID_SVIDEO,
1731 DRM_INFO("Connector Table: %d (emac)\n",
1732 rdev->mode_info.connector_table);
1733 /* VGA - primary dac */
1734 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1735 hpd.hpd = RADEON_HPD_NONE;
1736 radeon_add_legacy_encoder(dev,
1737 radeon_get_encoder_id(dev,
1738 ATOM_DEVICE_CRT1_SUPPORT,
1740 ATOM_DEVICE_CRT1_SUPPORT);
1741 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1742 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1743 CONNECTOR_OBJECT_ID_VGA,
1746 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1747 hpd.hpd = RADEON_HPD_NONE;
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_id(dev,
1750 ATOM_DEVICE_CRT2_SUPPORT,
1752 ATOM_DEVICE_CRT2_SUPPORT);
1753 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1754 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1755 CONNECTOR_OBJECT_ID_VGA,
1758 ddc_i2c.valid = false;
1759 hpd.hpd = RADEON_HPD_NONE;
1760 radeon_add_legacy_encoder(dev,
1761 radeon_get_encoder_id(dev,
1762 ATOM_DEVICE_TV1_SUPPORT,
1764 ATOM_DEVICE_TV1_SUPPORT);
1765 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1766 DRM_MODE_CONNECTOR_SVIDEO,
1768 CONNECTOR_OBJECT_ID_SVIDEO,
1772 DRM_INFO("Connector table: %d (invalid)\n",
1773 rdev->mode_info.connector_table);
1777 radeon_link_encoder_connector(dev);
1782 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1784 enum radeon_combios_connector
1786 struct radeon_i2c_bus_rec *ddc_i2c,
1787 struct radeon_hpd *hpd)
1789 struct radeon_device *rdev = dev->dev_private;
1791 /* XPRESS DDC quirks */
1792 if ((rdev->family == CHIP_RS400 ||
1793 rdev->family == CHIP_RS480) &&
1794 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1795 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1796 else if ((rdev->family == CHIP_RS400 ||
1797 rdev->family == CHIP_RS480) &&
1798 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1799 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1800 ddc_i2c->mask_clk_mask = (0x20 << 8);
1801 ddc_i2c->mask_data_mask = 0x80;
1802 ddc_i2c->a_clk_mask = (0x20 << 8);
1803 ddc_i2c->a_data_mask = 0x80;
1804 ddc_i2c->en_clk_mask = (0x20 << 8);
1805 ddc_i2c->en_data_mask = 0x80;
1806 ddc_i2c->y_clk_mask = (0x20 << 8);
1807 ddc_i2c->y_data_mask = 0x80;
1810 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1811 if ((rdev->family >= CHIP_R300) &&
1812 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1813 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1815 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1816 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1817 if (dev->pdev->device == 0x515e &&
1818 dev->pdev->subsystem_vendor == 0x1014) {
1819 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1820 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1824 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1825 if (dev->pdev->device == 0x5159 &&
1826 dev->pdev->subsystem_vendor == 0x1002 &&
1827 dev->pdev->subsystem_device == 0x013a) {
1828 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1829 *legacy_connector = CONNECTOR_CRT_LEGACY;
1833 /* X300 card with extra non-existent DVI port */
1834 if (dev->pdev->device == 0x5B60 &&
1835 dev->pdev->subsystem_vendor == 0x17af &&
1836 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1837 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1844 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1846 /* Acer 5102 has non-existent TV port */
1847 if (dev->pdev->device == 0x5975 &&
1848 dev->pdev->subsystem_vendor == 0x1025 &&
1849 dev->pdev->subsystem_device == 0x009f)
1852 /* HP dc5750 has non-existent TV port */
1853 if (dev->pdev->device == 0x5974 &&
1854 dev->pdev->subsystem_vendor == 0x103c &&
1855 dev->pdev->subsystem_device == 0x280a)
1858 /* MSI S270 has non-existent TV port */
1859 if (dev->pdev->device == 0x5955 &&
1860 dev->pdev->subsystem_vendor == 0x1462 &&
1861 dev->pdev->subsystem_device == 0x0131)
1867 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1869 struct radeon_device *rdev = dev->dev_private;
1870 uint32_t ext_tmds_info;
1872 if (rdev->flags & RADEON_IS_IGP) {
1874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1878 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1879 if (ext_tmds_info) {
1880 uint8_t rev = RBIOS8(ext_tmds_info);
1881 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1884 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1886 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1890 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1892 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1897 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1899 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1902 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1904 struct radeon_device *rdev = dev->dev_private;
1905 uint32_t conn_info, entry, devices;
1906 uint16_t tmp, connector_object_id;
1907 enum radeon_combios_ddc ddc_type;
1908 enum radeon_combios_connector connector;
1910 struct radeon_i2c_bus_rec ddc_i2c;
1911 struct radeon_hpd hpd;
1913 if (rdev->bios == NULL)
1916 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1918 for (i = 0; i < 4; i++) {
1919 entry = conn_info + 2 + i * 2;
1921 if (!RBIOS16(entry))
1924 tmp = RBIOS16(entry);
1926 connector = (tmp >> 12) & 0xf;
1928 ddc_type = (tmp >> 8) & 0xf;
1932 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1936 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1940 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1944 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1950 switch (connector) {
1951 case CONNECTOR_PROPRIETARY_LEGACY:
1952 case CONNECTOR_DVI_I_LEGACY:
1953 case CONNECTOR_DVI_D_LEGACY:
1954 if ((tmp >> 4) & 0x1)
1955 hpd.hpd = RADEON_HPD_2;
1957 hpd.hpd = RADEON_HPD_1;
1960 hpd.hpd = RADEON_HPD_NONE;
1964 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1968 switch (connector) {
1969 case CONNECTOR_PROPRIETARY_LEGACY:
1970 if ((tmp >> 4) & 0x1)
1971 devices = ATOM_DEVICE_DFP2_SUPPORT;
1973 devices = ATOM_DEVICE_DFP1_SUPPORT;
1974 radeon_add_legacy_encoder(dev,
1975 radeon_get_encoder_id
1978 radeon_add_legacy_connector(dev, i, devices,
1979 legacy_connector_convert
1982 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1985 case CONNECTOR_CRT_LEGACY:
1987 devices = ATOM_DEVICE_CRT2_SUPPORT;
1988 radeon_add_legacy_encoder(dev,
1989 radeon_get_encoder_id
1991 ATOM_DEVICE_CRT2_SUPPORT,
1993 ATOM_DEVICE_CRT2_SUPPORT);
1995 devices = ATOM_DEVICE_CRT1_SUPPORT;
1996 radeon_add_legacy_encoder(dev,
1997 radeon_get_encoder_id
1999 ATOM_DEVICE_CRT1_SUPPORT,
2001 ATOM_DEVICE_CRT1_SUPPORT);
2003 radeon_add_legacy_connector(dev,
2006 legacy_connector_convert
2009 CONNECTOR_OBJECT_ID_VGA,
2012 case CONNECTOR_DVI_I_LEGACY:
2015 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2016 radeon_add_legacy_encoder(dev,
2017 radeon_get_encoder_id
2019 ATOM_DEVICE_CRT2_SUPPORT,
2021 ATOM_DEVICE_CRT2_SUPPORT);
2023 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_id
2027 ATOM_DEVICE_CRT1_SUPPORT,
2029 ATOM_DEVICE_CRT1_SUPPORT);
2031 if ((tmp >> 4) & 0x1) {
2032 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2033 radeon_add_legacy_encoder(dev,
2034 radeon_get_encoder_id
2036 ATOM_DEVICE_DFP2_SUPPORT,
2038 ATOM_DEVICE_DFP2_SUPPORT);
2039 connector_object_id = combios_check_dl_dvi(dev, 0);
2041 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_id
2045 ATOM_DEVICE_DFP1_SUPPORT,
2047 ATOM_DEVICE_DFP1_SUPPORT);
2048 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2050 radeon_add_legacy_connector(dev,
2053 legacy_connector_convert
2056 connector_object_id,
2059 case CONNECTOR_DVI_D_LEGACY:
2060 if ((tmp >> 4) & 0x1) {
2061 devices = ATOM_DEVICE_DFP2_SUPPORT;
2062 connector_object_id = combios_check_dl_dvi(dev, 1);
2064 devices = ATOM_DEVICE_DFP1_SUPPORT;
2065 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2067 radeon_add_legacy_encoder(dev,
2068 radeon_get_encoder_id
2071 radeon_add_legacy_connector(dev, i, devices,
2072 legacy_connector_convert
2075 connector_object_id,
2078 case CONNECTOR_CTV_LEGACY:
2079 case CONNECTOR_STV_LEGACY:
2080 radeon_add_legacy_encoder(dev,
2081 radeon_get_encoder_id
2083 ATOM_DEVICE_TV1_SUPPORT,
2085 ATOM_DEVICE_TV1_SUPPORT);
2086 radeon_add_legacy_connector(dev, i,
2087 ATOM_DEVICE_TV1_SUPPORT,
2088 legacy_connector_convert
2091 CONNECTOR_OBJECT_ID_SVIDEO,
2095 DRM_ERROR("Unknown connector type: %d\n",
2102 uint16_t tmds_info =
2103 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2105 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2107 radeon_add_legacy_encoder(dev,
2108 radeon_get_encoder_id(dev,
2109 ATOM_DEVICE_CRT1_SUPPORT,
2111 ATOM_DEVICE_CRT1_SUPPORT);
2112 radeon_add_legacy_encoder(dev,
2113 radeon_get_encoder_id(dev,
2114 ATOM_DEVICE_DFP1_SUPPORT,
2116 ATOM_DEVICE_DFP1_SUPPORT);
2118 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2119 hpd.hpd = RADEON_HPD_NONE;
2120 radeon_add_legacy_connector(dev,
2122 ATOM_DEVICE_CRT1_SUPPORT |
2123 ATOM_DEVICE_DFP1_SUPPORT,
2124 DRM_MODE_CONNECTOR_DVII,
2126 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2130 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2131 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2133 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_id(dev,
2135 ATOM_DEVICE_CRT1_SUPPORT,
2137 ATOM_DEVICE_CRT1_SUPPORT);
2138 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2139 hpd.hpd = RADEON_HPD_NONE;
2140 radeon_add_legacy_connector(dev,
2142 ATOM_DEVICE_CRT1_SUPPORT,
2143 DRM_MODE_CONNECTOR_VGA,
2145 CONNECTOR_OBJECT_ID_VGA,
2148 DRM_DEBUG("No connector info found\n");
2154 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2156 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2158 uint16_t lcd_ddc_info =
2159 combios_get_table_offset(dev,
2160 COMBIOS_LCD_DDC_INFO_TABLE);
2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_id(dev,
2164 ATOM_DEVICE_LCD1_SUPPORT,
2166 ATOM_DEVICE_LCD1_SUPPORT);
2169 ddc_type = RBIOS8(lcd_ddc_info + 2);
2173 combios_setup_i2c_bus
2174 (rdev, RADEON_GPIO_MONID);
2178 combios_setup_i2c_bus
2179 (rdev, RADEON_GPIO_DVI_DDC);
2183 combios_setup_i2c_bus
2184 (rdev, RADEON_GPIO_VGA_DDC);
2188 combios_setup_i2c_bus
2189 (rdev, RADEON_GPIO_CRT2_DDC);
2193 combios_setup_i2c_bus
2194 (rdev, RADEON_GPIOPAD_MASK);
2195 ddc_i2c.mask_clk_mask =
2196 RBIOS32(lcd_ddc_info + 3);
2197 ddc_i2c.mask_data_mask =
2198 RBIOS32(lcd_ddc_info + 7);
2199 ddc_i2c.a_clk_mask =
2200 RBIOS32(lcd_ddc_info + 3);
2201 ddc_i2c.a_data_mask =
2202 RBIOS32(lcd_ddc_info + 7);
2203 ddc_i2c.en_clk_mask =
2204 RBIOS32(lcd_ddc_info + 3);
2205 ddc_i2c.en_data_mask =
2206 RBIOS32(lcd_ddc_info + 7);
2207 ddc_i2c.y_clk_mask =
2208 RBIOS32(lcd_ddc_info + 3);
2209 ddc_i2c.y_data_mask =
2210 RBIOS32(lcd_ddc_info + 7);
2214 combios_setup_i2c_bus
2215 (rdev, RADEON_MDGPIO_MASK);
2216 ddc_i2c.mask_clk_mask =
2217 RBIOS32(lcd_ddc_info + 3);
2218 ddc_i2c.mask_data_mask =
2219 RBIOS32(lcd_ddc_info + 7);
2220 ddc_i2c.a_clk_mask =
2221 RBIOS32(lcd_ddc_info + 3);
2222 ddc_i2c.a_data_mask =
2223 RBIOS32(lcd_ddc_info + 7);
2224 ddc_i2c.en_clk_mask =
2225 RBIOS32(lcd_ddc_info + 3);
2226 ddc_i2c.en_data_mask =
2227 RBIOS32(lcd_ddc_info + 7);
2228 ddc_i2c.y_clk_mask =
2229 RBIOS32(lcd_ddc_info + 3);
2230 ddc_i2c.y_data_mask =
2231 RBIOS32(lcd_ddc_info + 7);
2234 ddc_i2c.valid = false;
2237 DRM_DEBUG("LCD DDC Info Table found!\n");
2239 ddc_i2c.valid = false;
2241 hpd.hpd = RADEON_HPD_NONE;
2242 radeon_add_legacy_connector(dev,
2244 ATOM_DEVICE_LCD1_SUPPORT,
2245 DRM_MODE_CONNECTOR_LVDS,
2247 CONNECTOR_OBJECT_ID_LVDS,
2252 /* check TV table */
2253 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2255 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2257 if (RBIOS8(tv_info + 6) == 'T') {
2258 if (radeon_apply_legacy_tv_quirks(dev)) {
2259 hpd.hpd = RADEON_HPD_NONE;
2260 radeon_add_legacy_encoder(dev,
2261 radeon_get_encoder_id
2263 ATOM_DEVICE_TV1_SUPPORT,
2265 ATOM_DEVICE_TV1_SUPPORT);
2266 radeon_add_legacy_connector(dev, 6,
2267 ATOM_DEVICE_TV1_SUPPORT,
2268 DRM_MODE_CONNECTOR_SVIDEO,
2270 CONNECTOR_OBJECT_ID_SVIDEO,
2277 radeon_link_encoder_connector(dev);
2282 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2285 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2290 switch (tmds->dvo_chip) {
2293 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2294 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2297 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2300 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2303 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2306 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2309 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2312 /* sil 1178 - untested */
2331 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2333 struct drm_device *dev = encoder->dev;
2334 struct radeon_device *rdev = dev->dev_private;
2335 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2337 uint8_t blocks, slave_addr, rev;
2339 uint32_t reg, val, and_mask, or_mask;
2340 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2342 if (rdev->bios == NULL)
2348 if (rdev->flags & RADEON_IS_IGP) {
2349 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2350 rev = RBIOS8(offset);
2352 rev = RBIOS8(offset);
2354 blocks = RBIOS8(offset + 3);
2356 while (blocks > 0) {
2357 id = RBIOS16(index);
2361 reg = (id & 0x1fff) * 4;
2362 val = RBIOS32(index);
2367 reg = (id & 0x1fff) * 4;
2368 and_mask = RBIOS32(index);
2370 or_mask = RBIOS32(index);
2373 val = (val & and_mask) | or_mask;
2377 val = RBIOS16(index);
2382 val = RBIOS16(index);
2387 slave_addr = id & 0xff;
2388 slave_addr >>= 1; /* 7 bit addressing */
2390 reg = RBIOS8(index);
2392 val = RBIOS8(index);
2394 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2395 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2398 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2401 DRM_ERROR("Unknown id %d\n", id >> 13);
2410 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2412 index = offset + 10;
2413 id = RBIOS16(index);
2414 while (id != 0xffff) {
2418 reg = (id & 0x1fff) * 4;
2419 val = RBIOS32(index);
2423 reg = (id & 0x1fff) * 4;
2424 and_mask = RBIOS32(index);
2426 or_mask = RBIOS32(index);
2429 val = (val & and_mask) | or_mask;
2433 val = RBIOS16(index);
2439 and_mask = RBIOS32(index);
2441 or_mask = RBIOS32(index);
2443 val = RREG32_PLL(reg);
2444 val = (val & and_mask) | or_mask;
2445 WREG32_PLL(reg, val);
2449 val = RBIOS8(index);
2451 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2452 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2455 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2458 DRM_ERROR("Unknown id %d\n", id >> 13);
2461 id = RBIOS16(index);
2469 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2471 struct radeon_device *rdev = dev->dev_private;
2474 while (RBIOS16(offset)) {
2475 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2476 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2477 uint32_t val, and_mask, or_mask;
2483 val = RBIOS32(offset);
2488 val = RBIOS32(offset);
2493 and_mask = RBIOS32(offset);
2495 or_mask = RBIOS32(offset);
2503 and_mask = RBIOS32(offset);
2505 or_mask = RBIOS32(offset);
2513 val = RBIOS16(offset);
2518 val = RBIOS16(offset);
2525 (RADEON_CLK_PWRMGT_CNTL) &
2532 if ((RREG32(RADEON_MC_STATUS) &
2548 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2550 struct radeon_device *rdev = dev->dev_private;
2553 while (RBIOS8(offset)) {
2554 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2555 uint8_t addr = (RBIOS8(offset) & 0x3f);
2556 uint32_t val, shift, tmp;
2557 uint32_t and_mask, or_mask;
2562 val = RBIOS32(offset);
2564 WREG32_PLL(addr, val);
2567 shift = RBIOS8(offset) * 8;
2569 and_mask = RBIOS8(offset) << shift;
2570 and_mask |= ~(0xff << shift);
2572 or_mask = RBIOS8(offset) << shift;
2574 tmp = RREG32_PLL(addr);
2577 WREG32_PLL(addr, tmp);
2593 (RADEON_CLK_PWRMGT_CNTL) &
2601 (RADEON_CLK_PWRMGT_CNTL) &
2608 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2609 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2611 uint32_t mclk_cntl =
2614 mclk_cntl &= 0xffff0000;
2615 /*mclk_cntl |= 0x00001111;*//* ??? */
2616 WREG32_PLL(RADEON_MCLK_CNTL,
2621 (RADEON_CLK_PWRMGT_CNTL,
2623 ~RADEON_CG_NO1_DEBUG_0);
2638 static void combios_parse_ram_reset_table(struct drm_device *dev,
2641 struct radeon_device *rdev = dev->dev_private;
2645 uint8_t val = RBIOS8(offset);
2646 while (val != 0xff) {
2650 uint32_t channel_complete_mask;
2652 if (ASIC_IS_R300(rdev))
2653 channel_complete_mask =
2654 R300_MEM_PWRUP_COMPLETE;
2656 channel_complete_mask =
2657 RADEON_MEM_PWRUP_COMPLETE;
2660 if ((RREG32(RADEON_MEM_STR_CNTL) &
2661 channel_complete_mask) ==
2662 channel_complete_mask)
2666 uint32_t or_mask = RBIOS16(offset);
2669 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2670 tmp &= RADEON_SDRAM_MODE_MASK;
2672 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2674 or_mask = val << 24;
2675 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2676 tmp &= RADEON_B3MEM_RESET_MASK;
2678 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2680 val = RBIOS8(offset);
2685 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2686 int mem_addr_mapping)
2688 struct radeon_device *rdev = dev->dev_private;
2693 mem_cntl = RREG32(RADEON_MEM_CNTL);
2694 if (mem_cntl & RV100_HALF_MODE)
2697 mem_cntl &= ~(0xff << 8);
2698 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2699 WREG32(RADEON_MEM_CNTL, mem_cntl);
2700 RREG32(RADEON_MEM_CNTL);
2704 /* something like this???? */
2706 addr = ram * 1024 * 1024;
2707 /* write to each page */
2708 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2709 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2710 /* read back and verify */
2711 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2712 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2719 static void combios_write_ram_size(struct drm_device *dev)
2721 struct radeon_device *rdev = dev->dev_private;
2724 uint32_t mem_size = 0;
2725 uint32_t mem_cntl = 0;
2727 /* should do something smarter here I guess... */
2728 if (rdev->flags & RADEON_IS_IGP)
2731 /* first check detected mem table */
2732 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2734 rev = RBIOS8(offset);
2736 mem_cntl = RBIOS32(offset + 1);
2737 mem_size = RBIOS16(offset + 5);
2738 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2739 ((dev->pdev->device != 0x515e)
2740 && (dev->pdev->device != 0x5969)))
2741 WREG32(RADEON_MEM_CNTL, mem_cntl);
2747 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2749 rev = RBIOS8(offset - 1);
2751 if (((rdev->flags & RADEON_FAMILY_MASK) <
2753 && ((dev->pdev->device != 0x515e)
2754 && (dev->pdev->device != 0x5969))) {
2756 int mem_addr_mapping = 0;
2758 while (RBIOS8(offset)) {
2759 ram = RBIOS8(offset);
2762 if (mem_addr_mapping != 0x25)
2765 combios_detect_ram(dev, ram,
2772 mem_size = RBIOS8(offset);
2774 mem_size = RBIOS8(offset);
2775 mem_size *= 2; /* convert to MB */
2780 mem_size *= (1024 * 1024); /* convert to bytes */
2781 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2784 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2786 uint16_t dyn_clk_info =
2787 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2790 combios_parse_pll_table(dev, dyn_clk_info);
2793 void radeon_combios_asic_init(struct drm_device *dev)
2795 struct radeon_device *rdev = dev->dev_private;
2798 /* port hardcoded mac stuff from radeonfb */
2799 if (rdev->bios == NULL)
2803 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2805 combios_parse_mmio_table(dev, table);
2808 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2810 combios_parse_pll_table(dev, table);
2813 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2815 combios_parse_mmio_table(dev, table);
2817 if (!(rdev->flags & RADEON_IS_IGP)) {
2820 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2822 combios_parse_mmio_table(dev, table);
2825 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2827 combios_parse_ram_reset_table(dev, table);
2831 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2833 combios_parse_mmio_table(dev, table);
2835 /* write CONFIG_MEMSIZE */
2836 combios_write_ram_size(dev);
2840 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2842 combios_parse_pll_table(dev, table);
2846 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2848 struct radeon_device *rdev = dev->dev_private;
2849 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2851 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2852 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2853 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2855 /* let the bios control the backlight */
2856 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2858 /* tell the bios not to handle mode switching */
2859 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2860 RADEON_ACC_MODE_CHANGE);
2862 /* tell the bios a driver is loaded */
2863 bios_7_scratch |= RADEON_DRV_LOADED;
2865 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2866 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2867 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2870 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2872 struct drm_device *dev = encoder->dev;
2873 struct radeon_device *rdev = dev->dev_private;
2874 uint32_t bios_6_scratch;
2876 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2879 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2881 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2883 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2887 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2888 struct drm_encoder *encoder,
2891 struct drm_device *dev = connector->dev;
2892 struct radeon_device *rdev = dev->dev_private;
2893 struct radeon_connector *radeon_connector =
2894 to_radeon_connector(connector);
2895 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2896 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2897 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2899 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2900 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2902 DRM_DEBUG("TV1 connected\n");
2904 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2905 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2906 bios_5_scratch |= RADEON_TV1_ON;
2907 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2909 DRM_DEBUG("TV1 disconnected\n");
2910 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2911 bios_5_scratch &= ~RADEON_TV1_ON;
2912 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2915 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2916 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2918 DRM_DEBUG("LCD1 connected\n");
2919 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2920 bios_5_scratch |= RADEON_LCD1_ON;
2921 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2923 DRM_DEBUG("LCD1 disconnected\n");
2924 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2925 bios_5_scratch &= ~RADEON_LCD1_ON;
2926 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2929 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2930 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2932 DRM_DEBUG("CRT1 connected\n");
2933 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2934 bios_5_scratch |= RADEON_CRT1_ON;
2935 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2937 DRM_DEBUG("CRT1 disconnected\n");
2938 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2939 bios_5_scratch &= ~RADEON_CRT1_ON;
2940 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2943 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2944 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2946 DRM_DEBUG("CRT2 connected\n");
2947 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2948 bios_5_scratch |= RADEON_CRT2_ON;
2949 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2951 DRM_DEBUG("CRT2 disconnected\n");
2952 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2953 bios_5_scratch &= ~RADEON_CRT2_ON;
2954 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2957 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2958 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2960 DRM_DEBUG("DFP1 connected\n");
2961 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2962 bios_5_scratch |= RADEON_DFP1_ON;
2963 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2965 DRM_DEBUG("DFP1 disconnected\n");
2966 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2967 bios_5_scratch &= ~RADEON_DFP1_ON;
2968 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2971 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2972 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2974 DRM_DEBUG("DFP2 connected\n");
2975 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2976 bios_5_scratch |= RADEON_DFP2_ON;
2977 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2979 DRM_DEBUG("DFP2 disconnected\n");
2980 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2981 bios_5_scratch &= ~RADEON_DFP2_ON;
2982 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2985 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2986 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2990 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2992 struct drm_device *dev = encoder->dev;
2993 struct radeon_device *rdev = dev->dev_private;
2994 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2995 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2997 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2998 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2999 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3001 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3002 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3003 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3005 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3006 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3007 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3009 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3010 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3011 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3013 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3014 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3015 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3017 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3018 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3019 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3021 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3025 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3027 struct drm_device *dev = encoder->dev;
3028 struct radeon_device *rdev = dev->dev_private;
3029 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3030 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3032 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3034 bios_6_scratch |= RADEON_TV_DPMS_ON;
3036 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3038 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3040 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3042 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3044 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3046 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3048 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3050 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3052 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3054 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3056 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);