drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  43                         uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info, size;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         size = EDID_LENGTH * (raw[0x7e] + 1);
 460         edid = kmalloc(size, GFP_KERNEL);
 461         if (edid == NULL)
 462                 return false;
 463
 464         memcpy((unsigned char *)edid, raw, size);
 465
 466         if (!drm_edid_is_valid(edid)) {
 467                 kfree(edid);
 468                 return false;
 469         }
 470
 471         rdev->mode_info.bios_hardcoded_edid = edid;
 472         rdev->mode_info.bios_hardcoded_edid_size = size;
 473         return true;
 474 }
 475
 476 /* this is used for atom LCDs as well */
 477 struct edid *
 478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 479 {
 480         struct edid *edid;
 481
 482         if (rdev->mode_info.bios_hardcoded_edid) {
 483                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 484                 if (edid) {
 485                         memcpy((unsigned char *)edid,
 486                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 487                                rdev->mode_info.bios_hardcoded_edid_size);
 488                         return edid;
 489                 }
 490         }
 491         return NULL;
 492 }
 493
 494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 495                                                        enum radeon_combios_ddc ddc,
 496                                                        u32 clk_mask,
 497                                                        u32 data_mask)
 498 {
 499         struct radeon_i2c_bus_rec i2c;
 500         int ddc_line = 0;
 501
 502         /* ddc id            = mask reg
 503          * DDC_NONE_DETECTED = none
 504          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 505          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 506          * DDC_LCD           = RADEON_GPIOPAD_MASK
 507          * DDC_GPIO          = RADEON_MDGPIO_MASK
 508          * r1xx
 509          * DDC_MONID         = RADEON_GPIO_MONID
 510          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 511          * r200
 512          * DDC_MONID         = RADEON_GPIO_MONID
 513          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 514          * r300/r350
 515          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 516          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 517          * rv2xx/rv3xx
 518          * DDC_MONID         = RADEON_GPIO_MONID
 519          * DDC_CRT2          = RADEON_GPIO_MONID
 520          * rs3xx/rs4xx
 521          * DDC_MONID         = RADEON_GPIOPAD_MASK
 522          * DDC_CRT2          = RADEON_GPIO_MONID
 523          */
 524         switch (ddc) {
 525         case DDC_NONE_DETECTED:
 526         default:
 527                 ddc_line = 0;
 528                 break;
 529         case DDC_DVI:
 530                 ddc_line = RADEON_GPIO_DVI_DDC;
 531                 break;
 532         case DDC_VGA:
 533                 ddc_line = RADEON_GPIO_VGA_DDC;
 534                 break;
 535         case DDC_LCD:
 536                 ddc_line = RADEON_GPIOPAD_MASK;
 537                 break;
 538         case DDC_GPIO:
 539                 ddc_line = RADEON_MDGPIO_MASK;
 540                 break;
 541         case DDC_MONID:
 542                 if (rdev->family == CHIP_RS300 ||
 543                     rdev->family == CHIP_RS400 ||
 544                     rdev->family == CHIP_RS480)
 545                         ddc_line = RADEON_GPIOPAD_MASK;
 546                 else if (rdev->family == CHIP_R300 ||
 547                          rdev->family == CHIP_R350) {
 548                         ddc_line = RADEON_GPIO_DVI_DDC;
 549                         ddc = DDC_DVI;
 550                 } else
 551                         ddc_line = RADEON_GPIO_MONID;
 552                 break;
 553         case DDC_CRT2:
 554                 if (rdev->family == CHIP_R200 ||
 555                     rdev->family == CHIP_R300 ||
 556                     rdev->family == CHIP_R350) {
 557                         ddc_line = RADEON_GPIO_DVI_DDC;
 558                         ddc = DDC_DVI;
 559                 } else if (rdev->family == CHIP_RS300 ||
 560                            rdev->family == CHIP_RS400 ||
 561                            rdev->family == CHIP_RS480)
 562                         ddc_line = RADEON_GPIO_MONID;
 563                 else if (rdev->family >= CHIP_RV350) {
 564                         ddc_line = RADEON_GPIO_MONID;
 565                         ddc = DDC_MONID;
 566                 } else
 567                         ddc_line = RADEON_GPIO_CRT2_DDC;
 568                 break;
 569         }
 570
 571         if (ddc_line == RADEON_GPIOPAD_MASK) {
 572                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 573                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 574                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 575                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 576                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 577                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 578                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 579                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 580         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 581                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 582                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 583                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 584                 i2c.a_data_reg = RADEON_MDGPIO_A;
 585                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 586                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 587                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 588                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 589         } else {
 590                 i2c.mask_clk_reg = ddc_line;
 591                 i2c.mask_data_reg = ddc_line;
 592                 i2c.a_clk_reg = ddc_line;
 593                 i2c.a_data_reg = ddc_line;
 594                 i2c.en_clk_reg = ddc_line;
 595                 i2c.en_data_reg = ddc_line;
 596                 i2c.y_clk_reg = ddc_line;
 597                 i2c.y_data_reg = ddc_line;
 598         }
 599
 600         if (clk_mask && data_mask) {
 601                 /* system specific masks */
 602                 i2c.mask_clk_mask = clk_mask;
 603                 i2c.mask_data_mask = data_mask;
 604                 i2c.a_clk_mask = clk_mask;
 605                 i2c.a_data_mask = data_mask;
 606                 i2c.en_clk_mask = clk_mask;
 607                 i2c.en_data_mask = data_mask;
 608                 i2c.y_clk_mask = clk_mask;
 609                 i2c.y_data_mask = data_mask;
 610         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 611                    (ddc_line == RADEON_MDGPIO_MASK)) {
 612                 /* default gpiopad masks */
 613                 i2c.mask_clk_mask = (0x20 << 8);
 614                 i2c.mask_data_mask = 0x80;
 615                 i2c.a_clk_mask = (0x20 << 8);
 616                 i2c.a_data_mask = 0x80;
 617                 i2c.en_clk_mask = (0x20 << 8);
 618                 i2c.en_data_mask = 0x80;
 619                 i2c.y_clk_mask = (0x20 << 8);
 620                 i2c.y_data_mask = 0x80;
 621         } else {
 622                 /* default masks for ddc pads */
 623                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 624                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 625                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 626                 i2c.a_data_mask = RADEON_GPIO_A_0;
 627                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 628                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 629                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 630                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 631         }
 632
 633         switch (rdev->family) {
 634         case CHIP_R100:
 635         case CHIP_RV100:
 636         case CHIP_RS100:
 637         case CHIP_RV200:
 638         case CHIP_RS200:
 639         case CHIP_RS300:
 640                 switch (ddc_line) {
 641                 case RADEON_GPIO_DVI_DDC:
 642                         i2c.hw_capable = true;
 643                         break;
 644                 default:
 645                         i2c.hw_capable = false;
 646                         break;
 647                 }
 648                 break;
 649         case CHIP_R200:
 650                 switch (ddc_line) {
 651                 case RADEON_GPIO_DVI_DDC:
 652                 case RADEON_GPIO_MONID:
 653                         i2c.hw_capable = true;
 654                         break;
 655                 default:
 656                         i2c.hw_capable = false;
 657                         break;
 658                 }
 659                 break;
 660         case CHIP_RV250:
 661         case CHIP_RV280:
 662                 switch (ddc_line) {
 663                 case RADEON_GPIO_VGA_DDC:
 664                 case RADEON_GPIO_DVI_DDC:
 665                 case RADEON_GPIO_CRT2_DDC:
 666                         i2c.hw_capable = true;
 667                         break;
 668                 default:
 669                         i2c.hw_capable = false;
 670                         break;
 671                 }
 672                 break;
 673         case CHIP_R300:
 674         case CHIP_R350:
 675                 switch (ddc_line) {
 676                 case RADEON_GPIO_VGA_DDC:
 677                 case RADEON_GPIO_DVI_DDC:
 678                         i2c.hw_capable = true;
 679                         break;
 680                 default:
 681                         i2c.hw_capable = false;
 682                         break;
 683                 }
 684                 break;
 685         case CHIP_RV350:
 686         case CHIP_RV380:
 687         case CHIP_RS400:
 688         case CHIP_RS480:
 689                 switch (ddc_line) {
 690                 case RADEON_GPIO_VGA_DDC:
 691                 case RADEON_GPIO_DVI_DDC:
 692                         i2c.hw_capable = true;
 693                         break;
 694                 case RADEON_GPIO_MONID:
 695                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 696                          * reliably on some pre-r4xx hardware; not sure why.
 697                          */
 698                         i2c.hw_capable = false;
 699                         break;
 700                 default:
 701                         i2c.hw_capable = false;
 702                         break;
 703                 }
 704                 break;
 705         default:
 706                 i2c.hw_capable = false;
 707                 break;
 708         }
 709         i2c.mm_i2c = false;
 710
 711         i2c.i2c_id = ddc;
 712         i2c.hpd = RADEON_HPD_NONE;
 713
 714         if (ddc_line)
 715                 i2c.valid = true;
 716         else
 717                 i2c.valid = false;
 718
 719         return i2c;
 720 }
 721
 722 void radeon_combios_i2c_init(struct radeon_device *rdev)
 723 {
 724         struct drm_device *dev = rdev->ddev;
 725         struct radeon_i2c_bus_rec i2c;
 726
 727         /* actual hw pads
 728          * r1xx/rs2xx/rs3xx
 729          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 730          * r200
 731          * 0x60, 0x64, 0x68, mm
 732          * r300/r350
 733          * 0x60, 0x64, mm
 734          * rv2xx/rv3xx/rs4xx
 735          * 0x60, 0x64, 0x68, gpiopads, mm
 736          */
 737
 738         /* 0x60 */
 739         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 740         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 741         /* 0x64 */
 742         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 743         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 744
 745         /* mm i2c */
 746         i2c.valid = true;
 747         i2c.hw_capable = true;
 748         i2c.mm_i2c = true;
 749         i2c.i2c_id = 0xa0;
 750         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 751
 752         if (rdev->family == CHIP_R300 ||
 753             rdev->family == CHIP_R350) {
 754                 /* only 2 sw i2c pads */
 755         } else if (rdev->family == CHIP_RS300 ||
 756                    rdev->family == CHIP_RS400 ||
 757                    rdev->family == CHIP_RS480) {
 758                 u16 offset;
 759                 u8 id, blocks, clk, data;
 760                 int i;
 761
 762                 /* 0x68 */
 763                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 764                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 765
 766                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 767                 if (offset) {
 768                         blocks = RBIOS8(offset + 2);
 769                         for (i = 0; i < blocks; i++) {
 770                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
 771                                 if (id == 136) {
 772                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
 773                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
 774                                         /* gpiopad */
 775                                         i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 776                                                                     (1 << clk), (1 << data));
 777                                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         } else if ((rdev->family == CHIP_R200) ||
 783                    (rdev->family >= CHIP_R300)) {
 784                 /* 0x68 */
 785                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 786                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 787         } else {
 788                 /* 0x68 */
 789                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 790                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 791                 /* 0x6c */
 792                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 793                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 794         }
 795 }
 796
 797 bool radeon_combios_get_clock_info(struct drm_device *dev)
 798 {
 799         struct radeon_device *rdev = dev->dev_private;
 800         uint16_t pll_info;
 801         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 802         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 803         struct radeon_pll *spll = &rdev->clock.spll;
 804         struct radeon_pll *mpll = &rdev->clock.mpll;
 805         int8_t rev;
 806         uint16_t sclk, mclk;
 807
 808         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 809         if (pll_info) {
 810                 rev = RBIOS8(pll_info);
 811
 812                 /* pixel clocks */
 813                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 814                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 815                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 816                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 817                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 818                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 819
 820                 if (rev > 9) {
 821                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 822                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 823                 } else {
 824                         p1pll->pll_in_min = 40;
 825                         p1pll->pll_in_max = 500;
 826                 }
 827                 *p2pll = *p1pll;
 828
 829                 /* system clock */
 830                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 831                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 832                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 833                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 834
 835                 if (rev > 10) {
 836                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 837                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 838                 } else {
 839                         /* ??? */
 840                         spll->pll_in_min = 40;
 841                         spll->pll_in_max = 500;
 842                 }
 843
 844                 /* memory clock */
 845                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 846                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 847                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 848                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 849
 850                 if (rev > 10) {
 851                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 852                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 853                 } else {
 854                         /* ??? */
 855                         mpll->pll_in_min = 40;
 856                         mpll->pll_in_max = 500;
 857                 }
 858
 859                 /* default sclk/mclk */
 860                 sclk = RBIOS16(pll_info + 0xa);
 861                 mclk = RBIOS16(pll_info + 0x8);
 862                 if (sclk == 0)
 863                         sclk = 200 * 100;
 864                 if (mclk == 0)
 865                         mclk = 200 * 100;
 866
 867                 rdev->clock.default_sclk = sclk;
 868                 rdev->clock.default_mclk = mclk;
 869
 870                 if (RBIOS32(pll_info + 0x16))
 871                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 872                 else
 873                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 874
 875                 return true;
 876         }
 877         return false;
 878 }
 879
 880 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 881 {
 882         struct drm_device *dev = rdev->ddev;
 883         u16 igp_info;
 884
 885         /* sideport is AMD only */
 886         if (rdev->family == CHIP_RS400)
 887                 return false;
 888
 889         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 890
 891         if (igp_info) {
 892                 if (RBIOS16(igp_info + 0x4))
 893                         return true;
 894         }
 895         return false;
 896 }
 897
 898 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 899         0x00000808,             /* r100  */
 900         0x00000808,             /* rv100 */
 901         0x00000808,             /* rs100 */
 902         0x00000808,             /* rv200 */
 903         0x00000808,             /* rs200 */
 904         0x00000808,             /* r200  */
 905         0x00000808,             /* rv250 */
 906         0x00000000,             /* rs300 */
 907         0x00000808,             /* rv280 */
 908         0x00000808,             /* r300  */
 909         0x00000808,             /* r350  */
 910         0x00000808,             /* rv350 */
 911         0x00000808,             /* rv380 */
 912         0x00000808,             /* r420  */
 913         0x00000808,             /* r423  */
 914         0x00000808,             /* rv410 */
 915         0x00000000,             /* rs400 */
 916         0x00000000,             /* rs480 */
 917 };
 918
 919 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 920                                                           struct radeon_encoder_primary_dac *p_dac)
 921 {
 922         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 923         return;
 924 }
 925
 926 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 927                                                                        radeon_encoder
 928                                                                        *encoder)
 929 {
 930         struct drm_device *dev = encoder->base.dev;
 931         struct radeon_device *rdev = dev->dev_private;
 932         uint16_t dac_info;
 933         uint8_t rev, bg, dac;
 934         struct radeon_encoder_primary_dac *p_dac = NULL;
 935         int found = 0;
 936
 937         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 938                         GFP_KERNEL);
 939
 940         if (!p_dac)
 941                 return NULL;
 942
 943         /* check CRT table */
 944         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 945         if (dac_info) {
 946                 rev = RBIOS8(dac_info) & 0x3;
 947                 if (rev < 2) {
 948                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 949                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 950                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 951                 } else {
 952                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 953                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 954                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 955                 }
 956                 /* if the values are all zeros, use the table */
 957                 if (p_dac->ps2_pdac_adj)
 958                         found = 1;
 959         }
 960
 961         if (!found) /* fallback to defaults */
 962                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 963
 964         return p_dac;
 965 }
 966
 967 enum radeon_tv_std
 968 radeon_combios_get_tv_info(struct radeon_device *rdev)
 969 {
 970         struct drm_device *dev = rdev->ddev;
 971         uint16_t tv_info;
 972         enum radeon_tv_std tv_std = TV_STD_NTSC;
 973
 974         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 975         if (tv_info) {
 976                 if (RBIOS8(tv_info + 6) == 'T') {
 977                         switch (RBIOS8(tv_info + 7) & 0xf) {
 978                         case 1:
 979                                 tv_std = TV_STD_NTSC;
 980                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 981                                 break;
 982                         case 2:
 983                                 tv_std = TV_STD_PAL;
 984                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 985                                 break;
 986                         case 3:
 987                                 tv_std = TV_STD_PAL_M;
 988                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 989                                 break;
 990                         case 4:
 991                                 tv_std = TV_STD_PAL_60;
 992                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 993                                 break;
 994                         case 5:
 995                                 tv_std = TV_STD_NTSC_J;
 996                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 997                                 break;
 998                         case 6:
 999                                 tv_std = TV_STD_SCART_PAL;
1000                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1001                                 break;
1002                         default:
1003                                 tv_std = TV_STD_NTSC;
1004                                 DRM_DEBUG_KMS
1005                                     ("Unknown TV standard; defaulting to NTSC\n");
1006                                 break;
1007                         }
1008
1009                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1010                         case 0:
1011                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1012                                 break;
1013                         case 1:
1014                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1015                                 break;
1016                         case 2:
1017                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1018                                 break;
1019                         case 3:
1020                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1021                                 break;
1022                         default:
1023                                 break;
1024                         }
1025                 }
1026         }
1027         return tv_std;
1028 }
1029
1030 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1031         0x00000000,             /* r100  */
1032         0x00280000,             /* rv100 */
1033         0x00000000,             /* rs100 */
1034         0x00880000,             /* rv200 */
1035         0x00000000,             /* rs200 */
1036         0x00000000,             /* r200  */
1037         0x00770000,             /* rv250 */
1038         0x00290000,             /* rs300 */
1039         0x00560000,             /* rv280 */
1040         0x00780000,             /* r300  */
1041         0x00770000,             /* r350  */
1042         0x00780000,             /* rv350 */
1043         0x00780000,             /* rv380 */
1044         0x01080000,             /* r420  */
1045         0x01080000,             /* r423  */
1046         0x01080000,             /* rv410 */
1047         0x00780000,             /* rs400 */
1048         0x00780000,             /* rs480 */
1049 };
1050
1051 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1052                                                      struct radeon_encoder_tv_dac *tv_dac)
1053 {
1054         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1055         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1056                 tv_dac->ps2_tvdac_adj = 0x00880000;
1057         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1059         return;
1060 }
1061
1062 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1063                                                              radeon_encoder
1064                                                              *encoder)
1065 {
1066         struct drm_device *dev = encoder->base.dev;
1067         struct radeon_device *rdev = dev->dev_private;
1068         uint16_t dac_info;
1069         uint8_t rev, bg, dac;
1070         struct radeon_encoder_tv_dac *tv_dac = NULL;
1071         int found = 0;
1072
1073         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1074         if (!tv_dac)
1075                 return NULL;
1076
1077         /* first check TV table */
1078         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1079         if (dac_info) {
1080                 rev = RBIOS8(dac_info + 0x3);
1081                 if (rev > 4) {
1082                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1083                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1084                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1085
1086                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1087                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1088                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1089
1090                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1091                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1092                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1093                         /* if the values are all zeros, use the table */
1094                         if (tv_dac->ps2_tvdac_adj)
1095                                 found = 1;
1096                 } else if (rev > 1) {
1097                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1098                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1099                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1100
1101                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1102                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1103                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1104
1105                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1106                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1107                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1108                         /* if the values are all zeros, use the table */
1109                         if (tv_dac->ps2_tvdac_adj)
1110                                 found = 1;
1111                 }
1112                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1113         }
1114         if (!found) {
1115                 /* then check CRT table */
1116                 dac_info =
1117                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1118                 if (dac_info) {
1119                         rev = RBIOS8(dac_info) & 0x3;
1120                         if (rev < 2) {
1121                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1122                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1123                                 tv_dac->ps2_tvdac_adj =
1124                                     (bg << 16) | (dac << 20);
1125                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1126                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1127                                 /* if the values are all zeros, use the table */
1128                                 if (tv_dac->ps2_tvdac_adj)
1129                                         found = 1;
1130                         } else {
1131                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1132                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1133                                 tv_dac->ps2_tvdac_adj =
1134                                     (bg << 16) | (dac << 20);
1135                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1136                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1137                                 /* if the values are all zeros, use the table */
1138                                 if (tv_dac->ps2_tvdac_adj)
1139                                         found = 1;
1140                         }
1141                 } else {
1142                         DRM_INFO("No TV DAC info found in BIOS\n");
1143                 }
1144         }
1145
1146         if (!found) /* fallback to defaults */
1147                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1148
1149         return tv_dac;
1150 }
1151
1152 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1153                                                                          radeon_device
1154                                                                          *rdev)
1155 {
1156         struct radeon_encoder_lvds *lvds = NULL;
1157         uint32_t fp_vert_stretch, fp_horz_stretch;
1158         uint32_t ppll_div_sel, ppll_val;
1159         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1160
1161         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1162
1163         if (!lvds)
1164                 return NULL;
1165
1166         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1167         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1168
1169         /* These should be fail-safe defaults, fingers crossed */
1170         lvds->panel_pwr_delay = 200;
1171         lvds->panel_vcc_delay = 2000;
1172
1173         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1174         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1175         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1176
1177         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1178                 lvds->native_mode.vdisplay =
1179                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1180                      RADEON_VERT_PANEL_SHIFT) + 1;
1181         else
1182                 lvds->native_mode.vdisplay =
1183                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1184
1185         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1186                 lvds->native_mode.hdisplay =
1187                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1188                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1189         else
1190                 lvds->native_mode.hdisplay =
1191                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1192
1193         if ((lvds->native_mode.hdisplay < 640) ||
1194             (lvds->native_mode.vdisplay < 480)) {
1195                 lvds->native_mode.hdisplay = 640;
1196                 lvds->native_mode.vdisplay = 480;
1197         }
1198
1199         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1200         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1201         if ((ppll_val & 0x000707ff) == 0x1bb)
1202                 lvds->use_bios_dividers = false;
1203         else {
1204                 lvds->panel_ref_divider =
1205                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1206                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1207                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1208
1209                 if ((lvds->panel_ref_divider != 0) &&
1210                     (lvds->panel_fb_divider > 3))
1211                         lvds->use_bios_dividers = true;
1212         }
1213         lvds->panel_vcc_delay = 200;
1214
1215         DRM_INFO("Panel info derived from registers\n");
1216         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1217                  lvds->native_mode.vdisplay);
1218
1219         return lvds;
1220 }
1221
1222 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1223                                                          *encoder)
1224 {
1225         struct drm_device *dev = encoder->base.dev;
1226         struct radeon_device *rdev = dev->dev_private;
1227         uint16_t lcd_info;
1228         uint32_t panel_setup;
1229         char stmp[30];
1230         int tmp, i;
1231         struct radeon_encoder_lvds *lvds = NULL;
1232
1233         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1234
1235         if (lcd_info) {
1236                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1237
1238                 if (!lvds)
1239                         return NULL;
1240
1241                 for (i = 0; i < 24; i++)
1242                         stmp[i] = RBIOS8(lcd_info + i + 1);
1243                 stmp[24] = 0;
1244
1245                 DRM_INFO("Panel ID String: %s\n", stmp);
1246
1247                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1248                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1249
1250                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1251                          lvds->native_mode.vdisplay);
1252
1253                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1254                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1255
1256                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1257                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1258                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1259
1260                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1261                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1262                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1263                 if ((lvds->panel_ref_divider != 0) &&
1264                     (lvds->panel_fb_divider > 3))
1265                         lvds->use_bios_dividers = true;
1266
1267                 panel_setup = RBIOS32(lcd_info + 0x39);
1268                 lvds->lvds_gen_cntl = 0xff00;
1269                 if (panel_setup & 0x1)
1270                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1271
1272                 if ((panel_setup >> 4) & 0x1)
1273                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1274
1275                 switch ((panel_setup >> 8) & 0x7) {
1276                 case 0:
1277                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1278                         break;
1279                 case 1:
1280                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1281                         break;
1282                 case 2:
1283                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1284                         break;
1285                 default:
1286                         break;
1287                 }
1288
1289                 if ((panel_setup >> 16) & 0x1)
1290                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1291
1292                 if ((panel_setup >> 17) & 0x1)
1293                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1294
1295                 if ((panel_setup >> 18) & 0x1)
1296                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1297
1298                 if ((panel_setup >> 23) & 0x1)
1299                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1300
1301                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1302
1303                 for (i = 0; i < 32; i++) {
1304                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1305                         if (tmp == 0)
1306                                 break;
1307
1308                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1309                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1310                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1311                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1312                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1313                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1314                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1315                                         (RBIOS8(tmp + 23) * 8);
1316
1317                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1318                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1319                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1320                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1321                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1322                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1323
1324                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1325                                 lvds->native_mode.flags = 0;
1326                                 /* set crtc values */
1327                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1328
1329                         }
1330                 }
1331         } else {
1332                 DRM_INFO("No panel info found in BIOS\n");
1333                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1334         }
1335
1336         if (lvds)
1337                 encoder->native_mode = lvds->native_mode;
1338         return lvds;
1339 }
1340
1341 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1342         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1343         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1344         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1345         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1346         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1347         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1348         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1349         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1350         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1351         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1352         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1353         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1354         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1355         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1356         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1357         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1358         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1359         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1360 };
1361
1362 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1363                                             struct radeon_encoder_int_tmds *tmds)
1364 {
1365         struct drm_device *dev = encoder->base.dev;
1366         struct radeon_device *rdev = dev->dev_private;
1367         int i;
1368
1369         for (i = 0; i < 4; i++) {
1370                 tmds->tmds_pll[i].value =
1371                         default_tmds_pll[rdev->family][i].value;
1372                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1373         }
1374
1375         return true;
1376 }
1377
1378 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1379                                               struct radeon_encoder_int_tmds *tmds)
1380 {
1381         struct drm_device *dev = encoder->base.dev;
1382         struct radeon_device *rdev = dev->dev_private;
1383         uint16_t tmds_info;
1384         int i, n;
1385         uint8_t ver;
1386
1387         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1388
1389         if (tmds_info) {
1390                 ver = RBIOS8(tmds_info);
1391                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1392                 if (ver == 3) {
1393                         n = RBIOS8(tmds_info + 5) + 1;
1394                         if (n > 4)
1395                                 n = 4;
1396                         for (i = 0; i < n; i++) {
1397                                 tmds->tmds_pll[i].value =
1398                                     RBIOS32(tmds_info + i * 10 + 0x08);
1399                                 tmds->tmds_pll[i].freq =
1400                                     RBIOS16(tmds_info + i * 10 + 0x10);
1401                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1402                                           tmds->tmds_pll[i].freq,
1403                                           tmds->tmds_pll[i].value);
1404                         }
1405                 } else if (ver == 4) {
1406                         int stride = 0;
1407                         n = RBIOS8(tmds_info + 5) + 1;
1408                         if (n > 4)
1409                                 n = 4;
1410                         for (i = 0; i < n; i++) {
1411                                 tmds->tmds_pll[i].value =
1412                                     RBIOS32(tmds_info + stride + 0x08);
1413                                 tmds->tmds_pll[i].freq =
1414                                     RBIOS16(tmds_info + stride + 0x10);
1415                                 if (i == 0)
1416                                         stride += 10;
1417                                 else
1418                                         stride += 6;
1419                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1420                                           tmds->tmds_pll[i].freq,
1421                                           tmds->tmds_pll[i].value);
1422                         }
1423                 }
1424         } else {
1425                 DRM_INFO("No TMDS info found in BIOS\n");
1426                 return false;
1427         }
1428         return true;
1429 }
1430
1431 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1432                                                 struct radeon_encoder_ext_tmds *tmds)
1433 {
1434         struct drm_device *dev = encoder->base.dev;
1435         struct radeon_device *rdev = dev->dev_private;
1436         struct radeon_i2c_bus_rec i2c_bus;
1437
1438         /* default for macs */
1439         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1440         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1441
1442         /* XXX some macs have duallink chips */
1443         switch (rdev->mode_info.connector_table) {
1444         case CT_POWERBOOK_EXTERNAL:
1445         case CT_MINI_EXTERNAL:
1446         default:
1447                 tmds->dvo_chip = DVO_SIL164;
1448                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1449                 break;
1450         }
1451
1452         return true;
1453 }
1454
1455 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1456                                                   struct radeon_encoder_ext_tmds *tmds)
1457 {
1458         struct drm_device *dev = encoder->base.dev;
1459         struct radeon_device *rdev = dev->dev_private;
1460         uint16_t offset;
1461         uint8_t ver;
1462         enum radeon_combios_ddc gpio;
1463         struct radeon_i2c_bus_rec i2c_bus;
1464
1465         tmds->i2c_bus = NULL;
1466         if (rdev->flags & RADEON_IS_IGP) {
1467                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1468                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1469                 tmds->dvo_chip = DVO_SIL164;
1470                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1471         } else {
1472                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1473                 if (offset) {
1474                         ver = RBIOS8(offset);
1475                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1476                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1477                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1478                         gpio = RBIOS8(offset + 4 + 3);
1479                         if (gpio == DDC_LCD) {
1480                                 /* MM i2c */
1481                                 i2c_bus.valid = true;
1482                                 i2c_bus.hw_capable = true;
1483                                 i2c_bus.mm_i2c = true;
1484                                 i2c_bus.i2c_id = 0xa0;
1485                         } else
1486                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1487                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1488                 }
1489         }
1490
1491         if (!tmds->i2c_bus) {
1492                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1493                 return false;
1494         }
1495
1496         return true;
1497 }
1498
1499 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1500 {
1501         struct radeon_device *rdev = dev->dev_private;
1502         struct radeon_i2c_bus_rec ddc_i2c;
1503         struct radeon_hpd hpd;
1504
1505         rdev->mode_info.connector_table = radeon_connector_table;
1506         if (rdev->mode_info.connector_table == CT_NONE) {
1507 #ifdef CONFIG_PPC_PMAC
1508                 if (of_machine_is_compatible("PowerBook3,3")) {
1509                         /* powerbook with VGA */
1510                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1511                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1512                            of_machine_is_compatible("PowerBook3,5")) {
1513                         /* powerbook with internal tmds */
1514                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1515                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1516                            of_machine_is_compatible("PowerBook5,2") ||
1517                            of_machine_is_compatible("PowerBook5,3") ||
1518                            of_machine_is_compatible("PowerBook5,4") ||
1519                            of_machine_is_compatible("PowerBook5,5")) {
1520                         /* powerbook with external single link tmds (sil164) */
1521                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1522                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1523                         /* powerbook with external dual or single link tmds */
1524                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1525                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1526                            of_machine_is_compatible("PowerBook5,8") ||
1527                            of_machine_is_compatible("PowerBook5,9")) {
1528                         /* PowerBook6,2 ? */
1529                         /* powerbook with external dual link tmds (sil1178?) */
1530                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1531                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1532                            of_machine_is_compatible("PowerBook4,2") ||
1533                            of_machine_is_compatible("PowerBook4,3") ||
1534                            of_machine_is_compatible("PowerBook6,3") ||
1535                            of_machine_is_compatible("PowerBook6,5") ||
1536                            of_machine_is_compatible("PowerBook6,7")) {
1537                         /* ibook */
1538                         rdev->mode_info.connector_table = CT_IBOOK;
1539                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1540                         /* emac */
1541                         rdev->mode_info.connector_table = CT_EMAC;
1542                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1543                         /* mini with internal tmds */
1544                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1545                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1546                         /* mini with external tmds */
1547                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1548                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1549                         /* PowerMac8,1 ? */
1550                         /* imac g5 isight */
1551                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1552                 } else if ((rdev->pdev->device == 0x4a48) &&
1553                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1554                            (rdev->pdev->subsystem_device == 0x4a48)) {
1555                         /* Mac X800 */
1556                         rdev->mode_info.connector_table = CT_MAC_X800;
1557                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1558                             of_machine_is_compatible("PowerMac7,3")) &&
1559                            (rdev->pdev->device == 0x4150) &&
1560                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1561                            (rdev->pdev->subsystem_device == 0x4150)) {
1562                         /* Mac G5 tower 9600 */
1563                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1564                 } else
1565 #endif /* CONFIG_PPC_PMAC */
1566 #ifdef CONFIG_PPC64
1567                 if (ASIC_IS_RN50(rdev))
1568                         rdev->mode_info.connector_table = CT_RN50_POWER;
1569                 else
1570 #endif
1571                         rdev->mode_info.connector_table = CT_GENERIC;
1572         }
1573
1574         switch (rdev->mode_info.connector_table) {
1575         case CT_GENERIC:
1576                 DRM_INFO("Connector Table: %d (generic)\n",
1577                          rdev->mode_info.connector_table);
1578                 /* these are the most common settings */
1579                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1580                         /* VGA - primary dac */
1581                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1582                         hpd.hpd = RADEON_HPD_NONE;
1583                         radeon_add_legacy_encoder(dev,
1584                                                   radeon_get_encoder_enum(dev,
1585                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1586                                                                         1),
1587                                                   ATOM_DEVICE_CRT1_SUPPORT);
1588                         radeon_add_legacy_connector(dev, 0,
1589                                                     ATOM_DEVICE_CRT1_SUPPORT,
1590                                                     DRM_MODE_CONNECTOR_VGA,
1591                                                     &ddc_i2c,
1592                                                     CONNECTOR_OBJECT_ID_VGA,
1593                                                     &hpd);
1594                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1595                         /* LVDS */
1596                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1597                         hpd.hpd = RADEON_HPD_NONE;
1598                         radeon_add_legacy_encoder(dev,
1599                                                   radeon_get_encoder_enum(dev,
1600                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1601                                                                         0),
1602                                                   ATOM_DEVICE_LCD1_SUPPORT);
1603                         radeon_add_legacy_connector(dev, 0,
1604                                                     ATOM_DEVICE_LCD1_SUPPORT,
1605                                                     DRM_MODE_CONNECTOR_LVDS,
1606                                                     &ddc_i2c,
1607                                                     CONNECTOR_OBJECT_ID_LVDS,
1608                                                     &hpd);
1609
1610                         /* VGA - primary dac */
1611                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1612                         hpd.hpd = RADEON_HPD_NONE;
1613                         radeon_add_legacy_encoder(dev,
1614                                                   radeon_get_encoder_enum(dev,
1615                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1616                                                                         1),
1617                                                   ATOM_DEVICE_CRT1_SUPPORT);
1618                         radeon_add_legacy_connector(dev, 1,
1619                                                     ATOM_DEVICE_CRT1_SUPPORT,
1620                                                     DRM_MODE_CONNECTOR_VGA,
1621                                                     &ddc_i2c,
1622                                                     CONNECTOR_OBJECT_ID_VGA,
1623                                                     &hpd);
1624                 } else {
1625                         /* DVI-I - tv dac, int tmds */
1626                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1627                         hpd.hpd = RADEON_HPD_1;
1628                         radeon_add_legacy_encoder(dev,
1629                                                   radeon_get_encoder_enum(dev,
1630                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1631                                                                         0),
1632                                                   ATOM_DEVICE_DFP1_SUPPORT);
1633                         radeon_add_legacy_encoder(dev,
1634                                                   radeon_get_encoder_enum(dev,
1635                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1636                                                                         2),
1637                                                   ATOM_DEVICE_CRT2_SUPPORT);
1638                         radeon_add_legacy_connector(dev, 0,
1639                                                     ATOM_DEVICE_DFP1_SUPPORT |
1640                                                     ATOM_DEVICE_CRT2_SUPPORT,
1641                                                     DRM_MODE_CONNECTOR_DVII,
1642                                                     &ddc_i2c,
1643                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1644                                                     &hpd);
1645
1646                         /* VGA - primary dac */
1647                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1648                         hpd.hpd = RADEON_HPD_NONE;
1649                         radeon_add_legacy_encoder(dev,
1650                                                   radeon_get_encoder_enum(dev,
1651                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1652                                                                         1),
1653                                                   ATOM_DEVICE_CRT1_SUPPORT);
1654                         radeon_add_legacy_connector(dev, 1,
1655                                                     ATOM_DEVICE_CRT1_SUPPORT,
1656                                                     DRM_MODE_CONNECTOR_VGA,
1657                                                     &ddc_i2c,
1658                                                     CONNECTOR_OBJECT_ID_VGA,
1659                                                     &hpd);
1660                 }
1661
1662                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1663                         /* TV - tv dac */
1664                         ddc_i2c.valid = false;
1665                         hpd.hpd = RADEON_HPD_NONE;
1666                         radeon_add_legacy_encoder(dev,
1667                                                   radeon_get_encoder_enum(dev,
1668                                                                         ATOM_DEVICE_TV1_SUPPORT,
1669                                                                         2),
1670                                                   ATOM_DEVICE_TV1_SUPPORT);
1671                         radeon_add_legacy_connector(dev, 2,
1672                                                     ATOM_DEVICE_TV1_SUPPORT,
1673                                                     DRM_MODE_CONNECTOR_SVIDEO,
1674                                                     &ddc_i2c,
1675                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1676                                                     &hpd);
1677                 }
1678                 break;
1679         case CT_IBOOK:
1680                 DRM_INFO("Connector Table: %d (ibook)\n",
1681                          rdev->mode_info.connector_table);
1682                 /* LVDS */
1683                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1684                 hpd.hpd = RADEON_HPD_NONE;
1685                 radeon_add_legacy_encoder(dev,
1686                                           radeon_get_encoder_enum(dev,
1687                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1688                                                                 0),
1689                                           ATOM_DEVICE_LCD1_SUPPORT);
1690                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1691                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1692                                             CONNECTOR_OBJECT_ID_LVDS,
1693                                             &hpd);
1694                 /* VGA - TV DAC */
1695                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1696                 hpd.hpd = RADEON_HPD_NONE;
1697                 radeon_add_legacy_encoder(dev,
1698                                           radeon_get_encoder_enum(dev,
1699                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1700                                                                 2),
1701                                           ATOM_DEVICE_CRT2_SUPPORT);
1702                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1703                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1704                                             CONNECTOR_OBJECT_ID_VGA,
1705                                             &hpd);
1706                 /* TV - TV DAC */
1707                 ddc_i2c.valid = false;
1708                 hpd.hpd = RADEON_HPD_NONE;
1709                 radeon_add_legacy_encoder(dev,
1710                                           radeon_get_encoder_enum(dev,
1711                                                                 ATOM_DEVICE_TV1_SUPPORT,
1712                                                                 2),
1713                                           ATOM_DEVICE_TV1_SUPPORT);
1714                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1715                                             DRM_MODE_CONNECTOR_SVIDEO,
1716                                             &ddc_i2c,
1717                                             CONNECTOR_OBJECT_ID_SVIDEO,
1718                                             &hpd);
1719                 break;
1720         case CT_POWERBOOK_EXTERNAL:
1721                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1722                          rdev->mode_info.connector_table);
1723                 /* LVDS */
1724                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1725                 hpd.hpd = RADEON_HPD_NONE;
1726                 radeon_add_legacy_encoder(dev,
1727                                           radeon_get_encoder_enum(dev,
1728                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1729                                                                 0),
1730                                           ATOM_DEVICE_LCD1_SUPPORT);
1731                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1732                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1733                                             CONNECTOR_OBJECT_ID_LVDS,
1734                                             &hpd);
1735                 /* DVI-I - primary dac, ext tmds */
1736                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1737                 hpd.hpd = RADEON_HPD_2; /* ??? */
1738                 radeon_add_legacy_encoder(dev,
1739                                           radeon_get_encoder_enum(dev,
1740                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1741                                                                 0),
1742                                           ATOM_DEVICE_DFP2_SUPPORT);
1743                 radeon_add_legacy_encoder(dev,
1744                                           radeon_get_encoder_enum(dev,
1745                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1746                                                                 1),
1747                                           ATOM_DEVICE_CRT1_SUPPORT);
1748                 /* XXX some are SL */
1749                 radeon_add_legacy_connector(dev, 1,
1750                                             ATOM_DEVICE_DFP2_SUPPORT |
1751                                             ATOM_DEVICE_CRT1_SUPPORT,
1752                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1753                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1754                                             &hpd);
1755                 /* TV - TV DAC */
1756                 ddc_i2c.valid = false;
1757                 hpd.hpd = RADEON_HPD_NONE;
1758                 radeon_add_legacy_encoder(dev,
1759                                           radeon_get_encoder_enum(dev,
1760                                                                 ATOM_DEVICE_TV1_SUPPORT,
1761                                                                 2),
1762                                           ATOM_DEVICE_TV1_SUPPORT);
1763                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1764                                             DRM_MODE_CONNECTOR_SVIDEO,
1765                                             &ddc_i2c,
1766                                             CONNECTOR_OBJECT_ID_SVIDEO,
1767                                             &hpd);
1768                 break;
1769         case CT_POWERBOOK_INTERNAL:
1770                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1771                          rdev->mode_info.connector_table);
1772                 /* LVDS */
1773                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1774                 hpd.hpd = RADEON_HPD_NONE;
1775                 radeon_add_legacy_encoder(dev,
1776                                           radeon_get_encoder_enum(dev,
1777                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1778                                                                 0),
1779                                           ATOM_DEVICE_LCD1_SUPPORT);
1780                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1781                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1782                                             CONNECTOR_OBJECT_ID_LVDS,
1783                                             &hpd);
1784                 /* DVI-I - primary dac, int tmds */
1785                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1786                 hpd.hpd = RADEON_HPD_1; /* ??? */
1787                 radeon_add_legacy_encoder(dev,
1788                                           radeon_get_encoder_enum(dev,
1789                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1790                                                                 0),
1791                                           ATOM_DEVICE_DFP1_SUPPORT);
1792                 radeon_add_legacy_encoder(dev,
1793                                           radeon_get_encoder_enum(dev,
1794                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1795                                                                 1),
1796                                           ATOM_DEVICE_CRT1_SUPPORT);
1797                 radeon_add_legacy_connector(dev, 1,
1798                                             ATOM_DEVICE_DFP1_SUPPORT |
1799                                             ATOM_DEVICE_CRT1_SUPPORT,
1800                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1801                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1802                                             &hpd);
1803                 /* TV - TV DAC */
1804                 ddc_i2c.valid = false;
1805                 hpd.hpd = RADEON_HPD_NONE;
1806                 radeon_add_legacy_encoder(dev,
1807                                           radeon_get_encoder_enum(dev,
1808                                                                 ATOM_DEVICE_TV1_SUPPORT,
1809                                                                 2),
1810                                           ATOM_DEVICE_TV1_SUPPORT);
1811                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1812                                             DRM_MODE_CONNECTOR_SVIDEO,
1813                                             &ddc_i2c,
1814                                             CONNECTOR_OBJECT_ID_SVIDEO,
1815                                             &hpd);
1816                 break;
1817         case CT_POWERBOOK_VGA:
1818                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1819                          rdev->mode_info.connector_table);
1820                 /* LVDS */
1821                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1822                 hpd.hpd = RADEON_HPD_NONE;
1823                 radeon_add_legacy_encoder(dev,
1824                                           radeon_get_encoder_enum(dev,
1825                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1826                                                                 0),
1827                                           ATOM_DEVICE_LCD1_SUPPORT);
1828                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1829                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1830                                             CONNECTOR_OBJECT_ID_LVDS,
1831                                             &hpd);
1832                 /* VGA - primary dac */
1833                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1834                 hpd.hpd = RADEON_HPD_NONE;
1835                 radeon_add_legacy_encoder(dev,
1836                                           radeon_get_encoder_enum(dev,
1837                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1838                                                                 1),
1839                                           ATOM_DEVICE_CRT1_SUPPORT);
1840                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1841                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1842                                             CONNECTOR_OBJECT_ID_VGA,
1843                                             &hpd);
1844                 /* TV - TV DAC */
1845                 ddc_i2c.valid = false;
1846                 hpd.hpd = RADEON_HPD_NONE;
1847                 radeon_add_legacy_encoder(dev,
1848                                           radeon_get_encoder_enum(dev,
1849                                                                 ATOM_DEVICE_TV1_SUPPORT,
1850                                                                 2),
1851                                           ATOM_DEVICE_TV1_SUPPORT);
1852                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1853                                             DRM_MODE_CONNECTOR_SVIDEO,
1854                                             &ddc_i2c,
1855                                             CONNECTOR_OBJECT_ID_SVIDEO,
1856                                             &hpd);
1857                 break;
1858         case CT_MINI_EXTERNAL:
1859                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1860                          rdev->mode_info.connector_table);
1861                 /* DVI-I - tv dac, ext tmds */
1862                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1863                 hpd.hpd = RADEON_HPD_2; /* ??? */
1864                 radeon_add_legacy_encoder(dev,
1865                                           radeon_get_encoder_enum(dev,
1866                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1867                                                                 0),
1868                                           ATOM_DEVICE_DFP2_SUPPORT);
1869                 radeon_add_legacy_encoder(dev,
1870                                           radeon_get_encoder_enum(dev,
1871                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1872                                                                 2),
1873                                           ATOM_DEVICE_CRT2_SUPPORT);
1874                 /* XXX are any DL? */
1875                 radeon_add_legacy_connector(dev, 0,
1876                                             ATOM_DEVICE_DFP2_SUPPORT |
1877                                             ATOM_DEVICE_CRT2_SUPPORT,
1878                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1879                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1880                                             &hpd);
1881                 /* TV - TV DAC */
1882                 ddc_i2c.valid = false;
1883                 hpd.hpd = RADEON_HPD_NONE;
1884                 radeon_add_legacy_encoder(dev,
1885                                           radeon_get_encoder_enum(dev,
1886                                                                 ATOM_DEVICE_TV1_SUPPORT,
1887                                                                 2),
1888                                           ATOM_DEVICE_TV1_SUPPORT);
1889                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1890                                             DRM_MODE_CONNECTOR_SVIDEO,
1891                                             &ddc_i2c,
1892                                             CONNECTOR_OBJECT_ID_SVIDEO,
1893                                             &hpd);
1894                 break;
1895         case CT_MINI_INTERNAL:
1896                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1897                          rdev->mode_info.connector_table);
1898                 /* DVI-I - tv dac, int tmds */
1899                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1900                 hpd.hpd = RADEON_HPD_1; /* ??? */
1901                 radeon_add_legacy_encoder(dev,
1902                                           radeon_get_encoder_enum(dev,
1903                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1904                                                                 0),
1905                                           ATOM_DEVICE_DFP1_SUPPORT);
1906                 radeon_add_legacy_encoder(dev,
1907                                           radeon_get_encoder_enum(dev,
1908                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1909                                                                 2),
1910                                           ATOM_DEVICE_CRT2_SUPPORT);
1911                 radeon_add_legacy_connector(dev, 0,
1912                                             ATOM_DEVICE_DFP1_SUPPORT |
1913                                             ATOM_DEVICE_CRT2_SUPPORT,
1914                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1915                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1916                                             &hpd);
1917                 /* TV - TV DAC */
1918                 ddc_i2c.valid = false;
1919                 hpd.hpd = RADEON_HPD_NONE;
1920                 radeon_add_legacy_encoder(dev,
1921                                           radeon_get_encoder_enum(dev,
1922                                                                 ATOM_DEVICE_TV1_SUPPORT,
1923                                                                 2),
1924                                           ATOM_DEVICE_TV1_SUPPORT);
1925                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1926                                             DRM_MODE_CONNECTOR_SVIDEO,
1927                                             &ddc_i2c,
1928                                             CONNECTOR_OBJECT_ID_SVIDEO,
1929                                             &hpd);
1930                 break;
1931         case CT_IMAC_G5_ISIGHT:
1932                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1933                          rdev->mode_info.connector_table);
1934                 /* DVI-D - int tmds */
1935                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1936                 hpd.hpd = RADEON_HPD_1; /* ??? */
1937                 radeon_add_legacy_encoder(dev,
1938                                           radeon_get_encoder_enum(dev,
1939                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1940                                                                 0),
1941                                           ATOM_DEVICE_DFP1_SUPPORT);
1942                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1943                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1944                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1945                                             &hpd);
1946                 /* VGA - tv dac */
1947                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1948                 hpd.hpd = RADEON_HPD_NONE;
1949                 radeon_add_legacy_encoder(dev,
1950                                           radeon_get_encoder_enum(dev,
1951                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1952                                                                 2),
1953                                           ATOM_DEVICE_CRT2_SUPPORT);
1954                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1955                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1956                                             CONNECTOR_OBJECT_ID_VGA,
1957                                             &hpd);
1958                 /* TV - TV DAC */
1959                 ddc_i2c.valid = false;
1960                 hpd.hpd = RADEON_HPD_NONE;
1961                 radeon_add_legacy_encoder(dev,
1962                                           radeon_get_encoder_enum(dev,
1963                                                                 ATOM_DEVICE_TV1_SUPPORT,
1964                                                                 2),
1965                                           ATOM_DEVICE_TV1_SUPPORT);
1966                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1967                                             DRM_MODE_CONNECTOR_SVIDEO,
1968                                             &ddc_i2c,
1969                                             CONNECTOR_OBJECT_ID_SVIDEO,
1970                                             &hpd);
1971                 break;
1972         case CT_EMAC:
1973                 DRM_INFO("Connector Table: %d (emac)\n",
1974                          rdev->mode_info.connector_table);
1975                 /* VGA - primary dac */
1976                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1977                 hpd.hpd = RADEON_HPD_NONE;
1978                 radeon_add_legacy_encoder(dev,
1979                                           radeon_get_encoder_enum(dev,
1980                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1981                                                                 1),
1982                                           ATOM_DEVICE_CRT1_SUPPORT);
1983                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1984                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1985                                             CONNECTOR_OBJECT_ID_VGA,
1986                                             &hpd);
1987                 /* VGA - tv dac */
1988                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1989                 hpd.hpd = RADEON_HPD_NONE;
1990                 radeon_add_legacy_encoder(dev,
1991                                           radeon_get_encoder_enum(dev,
1992                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1993                                                                 2),
1994                                           ATOM_DEVICE_CRT2_SUPPORT);
1995                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1996                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1997                                             CONNECTOR_OBJECT_ID_VGA,
1998                                             &hpd);
1999                 /* TV - TV DAC */
2000                 ddc_i2c.valid = false;
2001                 hpd.hpd = RADEON_HPD_NONE;
2002                 radeon_add_legacy_encoder(dev,
2003                                           radeon_get_encoder_enum(dev,
2004                                                                 ATOM_DEVICE_TV1_SUPPORT,
2005                                                                 2),
2006                                           ATOM_DEVICE_TV1_SUPPORT);
2007                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2008                                             DRM_MODE_CONNECTOR_SVIDEO,
2009                                             &ddc_i2c,
2010                                             CONNECTOR_OBJECT_ID_SVIDEO,
2011                                             &hpd);
2012                 break;
2013         case CT_RN50_POWER:
2014                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2015                          rdev->mode_info.connector_table);
2016                 /* VGA - primary dac */
2017                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2018                 hpd.hpd = RADEON_HPD_NONE;
2019                 radeon_add_legacy_encoder(dev,
2020                                           radeon_get_encoder_enum(dev,
2021                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2022                                                                 1),
2023                                           ATOM_DEVICE_CRT1_SUPPORT);
2024                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2025                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2026                                             CONNECTOR_OBJECT_ID_VGA,
2027                                             &hpd);
2028                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2029                 hpd.hpd = RADEON_HPD_NONE;
2030                 radeon_add_legacy_encoder(dev,
2031                                           radeon_get_encoder_enum(dev,
2032                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2033                                                                 2),
2034                                           ATOM_DEVICE_CRT2_SUPPORT);
2035                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2036                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2037                                             CONNECTOR_OBJECT_ID_VGA,
2038                                             &hpd);
2039                 break;
2040         case CT_MAC_X800:
2041                 DRM_INFO("Connector Table: %d (mac x800)\n",
2042                          rdev->mode_info.connector_table);
2043                 /* DVI - primary dac, internal tmds */
2044                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2045                 hpd.hpd = RADEON_HPD_1; /* ??? */
2046                 radeon_add_legacy_encoder(dev,
2047                                           radeon_get_encoder_enum(dev,
2048                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2049                                                                   0),
2050                                           ATOM_DEVICE_DFP1_SUPPORT);
2051                 radeon_add_legacy_encoder(dev,
2052                                           radeon_get_encoder_enum(dev,
2053                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2054                                                                   1),
2055                                           ATOM_DEVICE_CRT1_SUPPORT);
2056                 radeon_add_legacy_connector(dev, 0,
2057                                             ATOM_DEVICE_DFP1_SUPPORT |
2058                                             ATOM_DEVICE_CRT1_SUPPORT,
2059                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2060                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2061                                             &hpd);
2062                 /* DVI - tv dac, dvo */
2063                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2064                 hpd.hpd = RADEON_HPD_2; /* ??? */
2065                 radeon_add_legacy_encoder(dev,
2066                                           radeon_get_encoder_enum(dev,
2067                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2068                                                                   0),
2069                                           ATOM_DEVICE_DFP2_SUPPORT);
2070                 radeon_add_legacy_encoder(dev,
2071                                           radeon_get_encoder_enum(dev,
2072                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2073                                                                   2),
2074                                           ATOM_DEVICE_CRT2_SUPPORT);
2075                 radeon_add_legacy_connector(dev, 1,
2076                                             ATOM_DEVICE_DFP2_SUPPORT |
2077                                             ATOM_DEVICE_CRT2_SUPPORT,
2078                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2079                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2080                                             &hpd);
2081                 break;
2082         case CT_MAC_G5_9600:
2083                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2084                          rdev->mode_info.connector_table);
2085                 /* DVI - tv dac, dvo */
2086                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2087                 hpd.hpd = RADEON_HPD_1; /* ??? */
2088                 radeon_add_legacy_encoder(dev,
2089                                           radeon_get_encoder_enum(dev,
2090                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2091                                                                   0),
2092                                           ATOM_DEVICE_DFP2_SUPPORT);
2093                 radeon_add_legacy_encoder(dev,
2094                                           radeon_get_encoder_enum(dev,
2095                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2096                                                                   2),
2097                                           ATOM_DEVICE_CRT2_SUPPORT);
2098                 radeon_add_legacy_connector(dev, 0,
2099                                             ATOM_DEVICE_DFP2_SUPPORT |
2100                                             ATOM_DEVICE_CRT2_SUPPORT,
2101                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2102                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2103                                             &hpd);
2104                 /* ADC - primary dac, internal tmds */
2105                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2106                 hpd.hpd = RADEON_HPD_2; /* ??? */
2107                 radeon_add_legacy_encoder(dev,
2108                                           radeon_get_encoder_enum(dev,
2109                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2110                                                                   0),
2111                                           ATOM_DEVICE_DFP1_SUPPORT);
2112                 radeon_add_legacy_encoder(dev,
2113                                           radeon_get_encoder_enum(dev,
2114                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2115                                                                   1),
2116                                           ATOM_DEVICE_CRT1_SUPPORT);
2117                 radeon_add_legacy_connector(dev, 1,
2118                                             ATOM_DEVICE_DFP1_SUPPORT |
2119                                             ATOM_DEVICE_CRT1_SUPPORT,
2120                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2121                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2122                                             &hpd);
2123                 /* TV - TV DAC */
2124                 ddc_i2c.valid = false;
2125                 hpd.hpd = RADEON_HPD_NONE;
2126                 radeon_add_legacy_encoder(dev,
2127                                           radeon_get_encoder_enum(dev,
2128                                                                 ATOM_DEVICE_TV1_SUPPORT,
2129                                                                 2),
2130                                           ATOM_DEVICE_TV1_SUPPORT);
2131                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2132                                             DRM_MODE_CONNECTOR_SVIDEO,
2133                                             &ddc_i2c,
2134                                             CONNECTOR_OBJECT_ID_SVIDEO,
2135                                             &hpd);
2136                 break;
2137         default:
2138                 DRM_INFO("Connector table: %d (invalid)\n",
2139                          rdev->mode_info.connector_table);
2140                 return false;
2141         }
2142
2143         radeon_link_encoder_connector(dev);
2144
2145         return true;
2146 }
2147
2148 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2149                                        int bios_index,
2150                                        enum radeon_combios_connector
2151                                        *legacy_connector,
2152                                        struct radeon_i2c_bus_rec *ddc_i2c,
2153                                        struct radeon_hpd *hpd)
2154 {
2155
2156         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2157            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2158         if (dev->pdev->device == 0x515e &&
2159             dev->pdev->subsystem_vendor == 0x1014) {
2160                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2161                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2162                         return false;
2163         }
2164
2165         /* X300 card with extra non-existent DVI port */
2166         if (dev->pdev->device == 0x5B60 &&
2167             dev->pdev->subsystem_vendor == 0x17af &&
2168             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2169                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2170                         return false;
2171         }
2172
2173         return true;
2174 }
2175
2176 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2177 {
2178         /* Acer 5102 has non-existent TV port */
2179         if (dev->pdev->device == 0x5975 &&
2180             dev->pdev->subsystem_vendor == 0x1025 &&
2181             dev->pdev->subsystem_device == 0x009f)
2182                 return false;
2183
2184         /* HP dc5750 has non-existent TV port */
2185         if (dev->pdev->device == 0x5974 &&
2186             dev->pdev->subsystem_vendor == 0x103c &&
2187             dev->pdev->subsystem_device == 0x280a)
2188                 return false;
2189
2190         /* MSI S270 has non-existent TV port */
2191         if (dev->pdev->device == 0x5955 &&
2192             dev->pdev->subsystem_vendor == 0x1462 &&
2193             dev->pdev->subsystem_device == 0x0131)
2194                 return false;
2195
2196         return true;
2197 }
2198
2199 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2200 {
2201         struct radeon_device *rdev = dev->dev_private;
2202         uint32_t ext_tmds_info;
2203
2204         if (rdev->flags & RADEON_IS_IGP) {
2205                 if (is_dvi_d)
2206                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2207                 else
2208                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2209         }
2210         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2211         if (ext_tmds_info) {
2212                 uint8_t rev = RBIOS8(ext_tmds_info);
2213                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2214                 if (rev >= 3) {
2215                         if (is_dvi_d)
2216                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2217                         else
2218                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2219                 } else {
2220                         if (flags & 1) {
2221                                 if (is_dvi_d)
2222                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2223                                 else
2224                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2225                         }
2226                 }
2227         }
2228         if (is_dvi_d)
2229                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2230         else
2231                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2232 }
2233
2234 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2235 {
2236         struct radeon_device *rdev = dev->dev_private;
2237         uint32_t conn_info, entry, devices;
2238         uint16_t tmp, connector_object_id;
2239         enum radeon_combios_ddc ddc_type;
2240         enum radeon_combios_connector connector;
2241         int i = 0;
2242         struct radeon_i2c_bus_rec ddc_i2c;
2243         struct radeon_hpd hpd;
2244
2245         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2246         if (conn_info) {
2247                 for (i = 0; i < 4; i++) {
2248                         entry = conn_info + 2 + i * 2;
2249
2250                         if (!RBIOS16(entry))
2251                                 break;
2252
2253                         tmp = RBIOS16(entry);
2254
2255                         connector = (tmp >> 12) & 0xf;
2256
2257                         ddc_type = (tmp >> 8) & 0xf;
2258                         ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2259
2260                         switch (connector) {
2261                         case CONNECTOR_PROPRIETARY_LEGACY:
2262                         case CONNECTOR_DVI_I_LEGACY:
2263                         case CONNECTOR_DVI_D_LEGACY:
2264                                 if ((tmp >> 4) & 0x1)
2265                                         hpd.hpd = RADEON_HPD_2;
2266                                 else
2267                                         hpd.hpd = RADEON_HPD_1;
2268                                 break;
2269                         default:
2270                                 hpd.hpd = RADEON_HPD_NONE;
2271                                 break;
2272                         }
2273
2274                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2275                                                         &ddc_i2c, &hpd))
2276                                 continue;
2277
2278                         switch (connector) {
2279                         case CONNECTOR_PROPRIETARY_LEGACY:
2280                                 if ((tmp >> 4) & 0x1)
2281                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2282                                 else
2283                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2284                                 radeon_add_legacy_encoder(dev,
2285                                                           radeon_get_encoder_enum
2286                                                           (dev, devices, 0),
2287                                                           devices);
2288                                 radeon_add_legacy_connector(dev, i, devices,
2289                                                             legacy_connector_convert
2290                                                             [connector],
2291                                                             &ddc_i2c,
2292                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2293                                                             &hpd);
2294                                 break;
2295                         case CONNECTOR_CRT_LEGACY:
2296                                 if (tmp & 0x1) {
2297                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2298                                         radeon_add_legacy_encoder(dev,
2299                                                                   radeon_get_encoder_enum
2300                                                                   (dev,
2301                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2302                                                                    2),
2303                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2304                                 } else {
2305                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2306                                         radeon_add_legacy_encoder(dev,
2307                                                                   radeon_get_encoder_enum
2308                                                                   (dev,
2309                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2310                                                                    1),
2311                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2312                                 }
2313                                 radeon_add_legacy_connector(dev,
2314                                                             i,
2315                                                             devices,
2316                                                             legacy_connector_convert
2317                                                             [connector],
2318                                                             &ddc_i2c,
2319                                                             CONNECTOR_OBJECT_ID_VGA,
2320                                                             &hpd);
2321                                 break;
2322                         case CONNECTOR_DVI_I_LEGACY:
2323                                 devices = 0;
2324                                 if (tmp & 0x1) {
2325                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2326                                         radeon_add_legacy_encoder(dev,
2327                                                                   radeon_get_encoder_enum
2328                                                                   (dev,
2329                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2330                                                                    2),
2331                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2332                                 } else {
2333                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2334                                         radeon_add_legacy_encoder(dev,
2335                                                                   radeon_get_encoder_enum
2336                                                                   (dev,
2337                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2338                                                                    1),
2339                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2340                                 }
2341                                 if ((tmp >> 4) & 0x1) {
2342                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2343                                         radeon_add_legacy_encoder(dev,
2344                                                                   radeon_get_encoder_enum
2345                                                                   (dev,
2346                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2347                                                                    0),
2348                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2349                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2350                                 } else {
2351                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2352                                         radeon_add_legacy_encoder(dev,
2353                                                                   radeon_get_encoder_enum
2354                                                                   (dev,
2355                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2356                                                                    0),
2357                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2358                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2359                                 }
2360                                 radeon_add_legacy_connector(dev,
2361                                                             i,
2362                                                             devices,
2363                                                             legacy_connector_convert
2364                                                             [connector],
2365                                                             &ddc_i2c,
2366                                                             connector_object_id,
2367                                                             &hpd);
2368                                 break;
2369                         case CONNECTOR_DVI_D_LEGACY:
2370                                 if ((tmp >> 4) & 0x1) {
2371                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2372                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2373                                 } else {
2374                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2375                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2376                                 }
2377                                 radeon_add_legacy_encoder(dev,
2378                                                           radeon_get_encoder_enum
2379                                                           (dev, devices, 0),
2380                                                           devices);
2381                                 radeon_add_legacy_connector(dev, i, devices,
2382                                                             legacy_connector_convert
2383                                                             [connector],
2384                                                             &ddc_i2c,
2385                                                             connector_object_id,
2386                                                             &hpd);
2387                                 break;
2388                         case CONNECTOR_CTV_LEGACY:
2389                         case CONNECTOR_STV_LEGACY:
2390                                 radeon_add_legacy_encoder(dev,
2391                                                           radeon_get_encoder_enum
2392                                                           (dev,
2393                                                            ATOM_DEVICE_TV1_SUPPORT,
2394                                                            2),
2395                                                           ATOM_DEVICE_TV1_SUPPORT);
2396                                 radeon_add_legacy_connector(dev, i,
2397                                                             ATOM_DEVICE_TV1_SUPPORT,
2398                                                             legacy_connector_convert
2399                                                             [connector],
2400                                                             &ddc_i2c,
2401                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2402                                                             &hpd);
2403                                 break;
2404                         default:
2405                                 DRM_ERROR("Unknown connector type: %d\n",
2406                                           connector);
2407                                 continue;
2408                         }
2409
2410                 }
2411         } else {
2412                 uint16_t tmds_info =
2413                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2414                 if (tmds_info) {
2415                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2416
2417                         radeon_add_legacy_encoder(dev,
2418                                                   radeon_get_encoder_enum(dev,
2419                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2420                                                                         1),
2421                                                   ATOM_DEVICE_CRT1_SUPPORT);
2422                         radeon_add_legacy_encoder(dev,
2423                                                   radeon_get_encoder_enum(dev,
2424                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2425                                                                         0),
2426                                                   ATOM_DEVICE_DFP1_SUPPORT);
2427
2428                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2429                         hpd.hpd = RADEON_HPD_1;
2430                         radeon_add_legacy_connector(dev,
2431                                                     0,
2432                                                     ATOM_DEVICE_CRT1_SUPPORT |
2433                                                     ATOM_DEVICE_DFP1_SUPPORT,
2434                                                     DRM_MODE_CONNECTOR_DVII,
2435                                                     &ddc_i2c,
2436                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2437                                                     &hpd);
2438                 } else {
2439                         uint16_t crt_info =
2440                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2441                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2442                         if (crt_info) {
2443                                 radeon_add_legacy_encoder(dev,
2444                                                           radeon_get_encoder_enum(dev,
2445                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2446                                                                                 1),
2447                                                           ATOM_DEVICE_CRT1_SUPPORT);
2448                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2449                                 hpd.hpd = RADEON_HPD_NONE;
2450                                 radeon_add_legacy_connector(dev,
2451                                                             0,
2452                                                             ATOM_DEVICE_CRT1_SUPPORT,
2453                                                             DRM_MODE_CONNECTOR_VGA,
2454                                                             &ddc_i2c,
2455                                                             CONNECTOR_OBJECT_ID_VGA,
2456                                                             &hpd);
2457                         } else {
2458                                 DRM_DEBUG_KMS("No connector info found\n");
2459                                 return false;
2460                         }
2461                 }
2462         }
2463
2464         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2465                 uint16_t lcd_info =
2466                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2467                 if (lcd_info) {
2468                         uint16_t lcd_ddc_info =
2469                             combios_get_table_offset(dev,
2470                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2471
2472                         radeon_add_legacy_encoder(dev,
2473                                                   radeon_get_encoder_enum(dev,
2474                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2475                                                                         0),
2476                                                   ATOM_DEVICE_LCD1_SUPPORT);
2477
2478                         if (lcd_ddc_info) {
2479                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2480                                 switch (ddc_type) {
2481                                 case DDC_LCD:
2482                                         ddc_i2c =
2483                                                 combios_setup_i2c_bus(rdev,
2484                                                                       DDC_LCD,
2485                                                                       RBIOS32(lcd_ddc_info + 3),
2486                                                                       RBIOS32(lcd_ddc_info + 7));
2487                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2488                                         break;
2489                                 case DDC_GPIO:
2490                                         ddc_i2c =
2491                                                 combios_setup_i2c_bus(rdev,
2492                                                                       DDC_GPIO,
2493                                                                       RBIOS32(lcd_ddc_info + 3),
2494                                                                       RBIOS32(lcd_ddc_info + 7));
2495                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2496                                         break;
2497                                 default:
2498                                         ddc_i2c =
2499                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2500                                         break;
2501                                 }
2502                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2503                         } else
2504                                 ddc_i2c.valid = false;
2505
2506                         hpd.hpd = RADEON_HPD_NONE;
2507                         radeon_add_legacy_connector(dev,
2508                                                     5,
2509                                                     ATOM_DEVICE_LCD1_SUPPORT,
2510                                                     DRM_MODE_CONNECTOR_LVDS,
2511                                                     &ddc_i2c,
2512                                                     CONNECTOR_OBJECT_ID_LVDS,
2513                                                     &hpd);
2514                 }
2515         }
2516
2517         /* check TV table */
2518         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2519                 uint32_t tv_info =
2520                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2521                 if (tv_info) {
2522                         if (RBIOS8(tv_info + 6) == 'T') {
2523                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2524                                         hpd.hpd = RADEON_HPD_NONE;
2525                                         ddc_i2c.valid = false;
2526                                         radeon_add_legacy_encoder(dev,
2527                                                                   radeon_get_encoder_enum
2528                                                                   (dev,
2529                                                                    ATOM_DEVICE_TV1_SUPPORT,
2530                                                                    2),
2531                                                                   ATOM_DEVICE_TV1_SUPPORT);
2532                                         radeon_add_legacy_connector(dev, 6,
2533                                                                     ATOM_DEVICE_TV1_SUPPORT,
2534                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2535                                                                     &ddc_i2c,
2536                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2537                                                                     &hpd);
2538                                 }
2539                         }
2540                 }
2541         }
2542
2543         radeon_link_encoder_connector(dev);
2544
2545         return true;
2546 }
2547
2548 static const char *thermal_controller_names[] = {
2549         "NONE",
2550         "lm63",
2551         "adm1032",
2552 };
2553
2554 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2555 {
2556         struct drm_device *dev = rdev->ddev;
2557         u16 offset, misc, misc2 = 0;
2558         u8 rev, blocks, tmp;
2559         int state_index = 0;
2560         struct radeon_i2c_bus_rec i2c_bus;
2561
2562         rdev->pm.default_power_state_index = -1;
2563
2564         /* allocate 2 power states */
2565         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2566         if (!rdev->pm.power_state) {
2567                 rdev->pm.default_power_state_index = state_index;
2568                 rdev->pm.num_power_states = 0;
2569
2570                 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2571                 rdev->pm.current_clock_mode_index = 0;
2572                 return;
2573         }
2574
2575         /* check for a thermal chip */
2576         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2577         if (offset) {
2578                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2579
2580                 rev = RBIOS8(offset);
2581
2582                 if (rev == 0) {
2583                         thermal_controller = RBIOS8(offset + 3);
2584                         gpio = RBIOS8(offset + 4) & 0x3f;
2585                         i2c_addr = RBIOS8(offset + 5);
2586                 } else if (rev == 1) {
2587                         thermal_controller = RBIOS8(offset + 4);
2588                         gpio = RBIOS8(offset + 5) & 0x3f;
2589                         i2c_addr = RBIOS8(offset + 6);
2590                 } else if (rev == 2) {
2591                         thermal_controller = RBIOS8(offset + 4);
2592                         gpio = RBIOS8(offset + 5) & 0x3f;
2593                         i2c_addr = RBIOS8(offset + 6);
2594                         clk_bit = RBIOS8(offset + 0xa);
2595                         data_bit = RBIOS8(offset + 0xb);
2596                 }
2597                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2598                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2599                                  thermal_controller_names[thermal_controller],
2600                                  i2c_addr >> 1);
2601                         if (gpio == DDC_LCD) {
2602                                 /* MM i2c */
2603                                 i2c_bus.valid = true;
2604                                 i2c_bus.hw_capable = true;
2605                                 i2c_bus.mm_i2c = true;
2606                                 i2c_bus.i2c_id = 0xa0;
2607                         } else if (gpio == DDC_GPIO)
2608                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2609                         else
2610                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2611                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2612                         if (rdev->pm.i2c_bus) {
2613                                 struct i2c_board_info info = { };
2614                                 const char *name = thermal_controller_names[thermal_controller];
2615                                 info.addr = i2c_addr >> 1;
2616                                 strlcpy(info.type, name, sizeof(info.type));
2617                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2618                         }
2619                 }
2620         } else {
2621                 /* boards with a thermal chip, but no overdrive table */
2622
2623                 /* Asus 9600xt has an f75375 on the monid bus */
2624                 if ((dev->pdev->device == 0x4152) &&
2625                     (dev->pdev->subsystem_vendor == 0x1043) &&
2626                     (dev->pdev->subsystem_device == 0xc002)) {
2627                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2628                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2629                         if (rdev->pm.i2c_bus) {
2630                                 struct i2c_board_info info = { };
2631                                 const char *name = "f75375";
2632                                 info.addr = 0x28;
2633                                 strlcpy(info.type, name, sizeof(info.type));
2634                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2635                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2636                                          name, info.addr);
2637                         }
2638                 }
2639         }
2640
2641         if (rdev->flags & RADEON_IS_MOBILITY) {
2642                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2643                 if (offset) {
2644                         rev = RBIOS8(offset);
2645                         blocks = RBIOS8(offset + 0x2);
2646                         /* power mode 0 tends to be the only valid one */
2647                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2648                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2649                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2650                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2651                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2652                                 goto default_mode;
2653                         rdev->pm.power_state[state_index].type =
2654                                 POWER_STATE_TYPE_BATTERY;
2655                         misc = RBIOS16(offset + 0x5 + 0x0);
2656                         if (rev > 4)
2657                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2658                         rdev->pm.power_state[state_index].misc = misc;
2659                         rdev->pm.power_state[state_index].misc2 = misc2;
2660                         if (misc & 0x4) {
2661                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2662                                 if (misc & 0x8)
2663                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2664                                                 true;
2665                                 else
2666                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2667                                                 false;
2668                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2669                                 if (rev < 6) {
2670                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2671                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2672                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2673                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2674                                 } else {
2675                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2676                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2677                                         if (entries && voltage_table_offset) {
2678                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2679                                                         RBIOS16(voltage_table_offset) * 4;
2680                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2681                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2682                                         } else
2683                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2684                                 }
2685                                 switch ((misc2 & 0x700) >> 8) {
2686                                 case 0:
2687                                 default:
2688                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2689                                         break;
2690                                 case 1:
2691                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2692                                         break;
2693                                 case 2:
2694                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2695                                         break;
2696                                 case 3:
2697                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2698                                         break;
2699                                 case 4:
2700                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2701                                         break;
2702                                 }
2703                         } else
2704                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2705                         if (rev > 6)
2706                                 rdev->pm.power_state[state_index].pcie_lanes =
2707                                         RBIOS8(offset + 0x5 + 0x10);
2708                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2709                         state_index++;
2710                 } else {
2711                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2712                 }
2713         } else {
2714                 /* XXX figure out some good default low power mode for desktop cards */
2715         }
2716
2717 default_mode:
2718         /* add the default mode */
2719         rdev->pm.power_state[state_index].type =
2720                 POWER_STATE_TYPE_DEFAULT;
2721         rdev->pm.power_state[state_index].num_clock_modes = 1;
2722         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2723         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2724         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2725         if ((state_index > 0) &&
2726             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2727                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2728                         rdev->pm.power_state[0].clock_info[0].voltage;
2729         else
2730                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2731         rdev->pm.power_state[state_index].pcie_lanes = 16;
2732         rdev->pm.power_state[state_index].flags = 0;
2733         rdev->pm.default_power_state_index = state_index;
2734         rdev->pm.num_power_states = state_index + 1;
2735
2736         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2737         rdev->pm.current_clock_mode_index = 0;
2738 }
2739
2740 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2741 {
2742         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2743         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2744
2745         if (!tmds)
2746                 return;
2747
2748         switch (tmds->dvo_chip) {
2749         case DVO_SIL164:
2750                 /* sil 164 */
2751                 radeon_i2c_put_byte(tmds->i2c_bus,
2752                                     tmds->slave_addr,
2753                                     0x08, 0x30);
2754                 radeon_i2c_put_byte(tmds->i2c_bus,
2755                                        tmds->slave_addr,
2756                                        0x09, 0x00);
2757                 radeon_i2c_put_byte(tmds->i2c_bus,
2758                                     tmds->slave_addr,
2759                                     0x0a, 0x90);
2760                 radeon_i2c_put_byte(tmds->i2c_bus,
2761                                     tmds->slave_addr,
2762                                     0x0c, 0x89);
2763                 radeon_i2c_put_byte(tmds->i2c_bus,
2764                                        tmds->slave_addr,
2765                                        0x08, 0x3b);
2766                 break;
2767         case DVO_SIL1178:
2768                 /* sil 1178 - untested */
2769                 /*
2770                  * 0x0f, 0x44
2771                  * 0x0f, 0x4c
2772                  * 0x0e, 0x01
2773                  * 0x0a, 0x80
2774                  * 0x09, 0x30
2775                  * 0x0c, 0xc9
2776                  * 0x0d, 0x70
2777                  * 0x08, 0x32
2778                  * 0x08, 0x33
2779                  */
2780                 break;
2781         default:
2782                 break;
2783         }
2784
2785 }
2786
2787 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2788 {
2789         struct drm_device *dev = encoder->dev;
2790         struct radeon_device *rdev = dev->dev_private;
2791         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2792         uint16_t offset;
2793         uint8_t blocks, slave_addr, rev;
2794         uint32_t index, id;
2795         uint32_t reg, val, and_mask, or_mask;
2796         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2797
2798         if (!tmds)
2799                 return false;
2800
2801         if (rdev->flags & RADEON_IS_IGP) {
2802                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2803                 rev = RBIOS8(offset);
2804                 if (offset) {
2805                         rev = RBIOS8(offset);
2806                         if (rev > 1) {
2807                                 blocks = RBIOS8(offset + 3);
2808                                 index = offset + 4;
2809                                 while (blocks > 0) {
2810                                         id = RBIOS16(index);
2811                                         index += 2;
2812                                         switch (id >> 13) {
2813                                         case 0:
2814                                                 reg = (id & 0x1fff) * 4;
2815                                                 val = RBIOS32(index);
2816                                                 index += 4;
2817                                                 WREG32(reg, val);
2818                                                 break;
2819                                         case 2:
2820                                                 reg = (id & 0x1fff) * 4;
2821                                                 and_mask = RBIOS32(index);
2822                                                 index += 4;
2823                                                 or_mask = RBIOS32(index);
2824                                                 index += 4;
2825                                                 val = RREG32(reg);
2826                                                 val = (val & and_mask) | or_mask;
2827                                                 WREG32(reg, val);
2828                                                 break;
2829                                         case 3:
2830                                                 val = RBIOS16(index);
2831                                                 index += 2;
2832                                                 udelay(val);
2833                                                 break;
2834                                         case 4:
2835                                                 val = RBIOS16(index);
2836                                                 index += 2;
2837                                                 udelay(val * 1000);
2838                                                 break;
2839                                         case 6:
2840                                                 slave_addr = id & 0xff;
2841                                                 slave_addr >>= 1; /* 7 bit addressing */
2842                                                 index++;
2843                                                 reg = RBIOS8(index);
2844                                                 index++;
2845                                                 val = RBIOS8(index);
2846                                                 index++;
2847                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2848                                                                     slave_addr,
2849                                                                     reg, val);
2850                                                 break;
2851                                         default:
2852                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2853                                                 break;
2854                                         }
2855                                         blocks--;
2856                                 }
2857                                 return true;
2858                         }
2859                 }
2860         } else {
2861                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2862                 if (offset) {
2863                         index = offset + 10;
2864                         id = RBIOS16(index);
2865                         while (id != 0xffff) {
2866                                 index += 2;
2867                                 switch (id >> 13) {
2868                                 case 0:
2869                                         reg = (id & 0x1fff) * 4;
2870                                         val = RBIOS32(index);
2871                                         WREG32(reg, val);
2872                                         break;
2873                                 case 2:
2874                                         reg = (id & 0x1fff) * 4;
2875                                         and_mask = RBIOS32(index);
2876                                         index += 4;
2877                                         or_mask = RBIOS32(index);
2878                                         index += 4;
2879                                         val = RREG32(reg);
2880                                         val = (val & and_mask) | or_mask;
2881                                         WREG32(reg, val);
2882                                         break;
2883                                 case 4:
2884                                         val = RBIOS16(index);
2885                                         index += 2;
2886                                         udelay(val);
2887                                         break;
2888                                 case 5:
2889                                         reg = id & 0x1fff;
2890                                         and_mask = RBIOS32(index);
2891                                         index += 4;
2892                                         or_mask = RBIOS32(index);
2893                                         index += 4;
2894                                         val = RREG32_PLL(reg);
2895                                         val = (val & and_mask) | or_mask;
2896                                         WREG32_PLL(reg, val);
2897                                         break;
2898                                 case 6:
2899                                         reg = id & 0x1fff;
2900                                         val = RBIOS8(index);
2901                                         index += 1;
2902                                         radeon_i2c_put_byte(tmds->i2c_bus,
2903                                                             tmds->slave_addr,
2904                                                             reg, val);
2905                                         break;
2906                                 default:
2907                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2908                                         break;
2909                                 }
2910                                 id = RBIOS16(index);
2911                         }
2912                         return true;
2913                 }
2914         }
2915         return false;
2916 }
2917
2918 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2919 {
2920         struct radeon_device *rdev = dev->dev_private;
2921
2922         if (offset) {
2923                 while (RBIOS16(offset)) {
2924                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2925                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2926                         uint32_t val, and_mask, or_mask;
2927                         uint32_t tmp;
2928
2929                         offset += 2;
2930                         switch (cmd) {
2931                         case 0:
2932                                 val = RBIOS32(offset);
2933                                 offset += 4;
2934                                 WREG32(addr, val);
2935                                 break;
2936                         case 1:
2937                                 val = RBIOS32(offset);
2938                                 offset += 4;
2939                                 WREG32(addr, val);
2940                                 break;
2941                         case 2:
2942                                 and_mask = RBIOS32(offset);
2943                                 offset += 4;
2944                                 or_mask = RBIOS32(offset);
2945                                 offset += 4;
2946                                 tmp = RREG32(addr);
2947                                 tmp &= and_mask;
2948                                 tmp |= or_mask;
2949                                 WREG32(addr, tmp);
2950                                 break;
2951                         case 3:
2952                                 and_mask = RBIOS32(offset);
2953                                 offset += 4;
2954                                 or_mask = RBIOS32(offset);
2955                                 offset += 4;
2956                                 tmp = RREG32(addr);
2957                                 tmp &= and_mask;
2958                                 tmp |= or_mask;
2959                                 WREG32(addr, tmp);
2960                                 break;
2961                         case 4:
2962                                 val = RBIOS16(offset);
2963                                 offset += 2;
2964                                 udelay(val);
2965                                 break;
2966                         case 5:
2967                                 val = RBIOS16(offset);
2968                                 offset += 2;
2969                                 switch (addr) {
2970                                 case 8:
2971                                         while (val--) {
2972                                                 if (!
2973                                                     (RREG32_PLL
2974                                                      (RADEON_CLK_PWRMGT_CNTL) &
2975                                                      RADEON_MC_BUSY))
2976                                                         break;
2977                                         }
2978                                         break;
2979                                 case 9:
2980                                         while (val--) {
2981                                                 if ((RREG32(RADEON_MC_STATUS) &
2982                                                      RADEON_MC_IDLE))
2983                                                         break;
2984                                         }
2985                                         break;
2986                                 default:
2987                                         break;
2988                                 }
2989                                 break;
2990                         default:
2991                                 break;
2992                         }
2993                 }
2994         }
2995 }
2996
2997 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2998 {
2999         struct radeon_device *rdev = dev->dev_private;
3000
3001         if (offset) {
3002                 while (RBIOS8(offset)) {
3003                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3004                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3005                         uint32_t val, shift, tmp;
3006                         uint32_t and_mask, or_mask;
3007
3008                         offset++;
3009                         switch (cmd) {
3010                         case 0:
3011                                 val = RBIOS32(offset);
3012                                 offset += 4;
3013                                 WREG32_PLL(addr, val);
3014                                 break;
3015                         case 1:
3016                                 shift = RBIOS8(offset) * 8;
3017                                 offset++;
3018                                 and_mask = RBIOS8(offset) << shift;
3019                                 and_mask |= ~(0xff << shift);
3020                                 offset++;
3021                                 or_mask = RBIOS8(offset) << shift;
3022                                 offset++;
3023                                 tmp = RREG32_PLL(addr);
3024                                 tmp &= and_mask;
3025                                 tmp |= or_mask;
3026                                 WREG32_PLL(addr, tmp);
3027                                 break;
3028                         case 2:
3029                         case 3:
3030                                 tmp = 1000;
3031                                 switch (addr) {
3032                                 case 1:
3033                                         udelay(150);
3034                                         break;
3035                                 case 2:
3036                                         udelay(1000);
3037                                         break;
3038                                 case 3:
3039                                         while (tmp--) {
3040                                                 if (!
3041                                                     (RREG32_PLL
3042                                                      (RADEON_CLK_PWRMGT_CNTL) &
3043                                                      RADEON_MC_BUSY))
3044                                                         break;
3045                                         }
3046                                         break;
3047                                 case 4:
3048                                         while (tmp--) {
3049                                                 if (RREG32_PLL
3050                                                     (RADEON_CLK_PWRMGT_CNTL) &
3051                                                     RADEON_DLL_READY)
3052                                                         break;
3053                                         }
3054                                         break;
3055                                 case 5:
3056                                         tmp =
3057                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3058                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3059 #if 0
3060                                                 uint32_t mclk_cntl =
3061                                                     RREG32_PLL
3062                                                     (RADEON_MCLK_CNTL);
3063                                                 mclk_cntl &= 0xffff0000;
3064                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3065                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3066                                                            mclk_cntl);
3067                                                 udelay(10000);
3068 #endif
3069                                                 WREG32_PLL
3070                                                     (RADEON_CLK_PWRMGT_CNTL,
3071                                                      tmp &
3072                                                      ~RADEON_CG_NO1_DEBUG_0);
3073                                                 udelay(10000);
3074                                         }
3075                                         break;
3076                                 default:
3077                                         break;
3078                                 }
3079                                 break;
3080                         default:
3081                                 break;
3082                         }
3083                 }
3084         }
3085 }
3086
3087 static void combios_parse_ram_reset_table(struct drm_device *dev,
3088                                           uint16_t offset)
3089 {
3090         struct radeon_device *rdev = dev->dev_private;
3091         uint32_t tmp;
3092
3093         if (offset) {
3094                 uint8_t val = RBIOS8(offset);
3095                 while (val != 0xff) {
3096                         offset++;
3097
3098                         if (val == 0x0f) {
3099                                 uint32_t channel_complete_mask;
3100
3101                                 if (ASIC_IS_R300(rdev))
3102                                         channel_complete_mask =
3103                                             R300_MEM_PWRUP_COMPLETE;
3104                                 else
3105                                         channel_complete_mask =
3106                                             RADEON_MEM_PWRUP_COMPLETE;
3107                                 tmp = 20000;
3108                                 while (tmp--) {
3109                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3110                                              channel_complete_mask) ==
3111                                             channel_complete_mask)
3112                                                 break;
3113                                 }
3114                         } else {
3115                                 uint32_t or_mask = RBIOS16(offset);
3116                                 offset += 2;
3117
3118                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3119                                 tmp &= RADEON_SDRAM_MODE_MASK;
3120                                 tmp |= or_mask;
3121                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3122
3123                                 or_mask = val << 24;
3124                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3125                                 tmp &= RADEON_B3MEM_RESET_MASK;
3126                                 tmp |= or_mask;
3127                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3128                         }
3129                         val = RBIOS8(offset);
3130                 }
3131         }
3132 }
3133
3134 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3135                                    int mem_addr_mapping)
3136 {
3137         struct radeon_device *rdev = dev->dev_private;
3138         uint32_t mem_cntl;
3139         uint32_t mem_size;
3140         uint32_t addr = 0;
3141
3142         mem_cntl = RREG32(RADEON_MEM_CNTL);
3143         if (mem_cntl & RV100_HALF_MODE)
3144                 ram /= 2;
3145         mem_size = ram;
3146         mem_cntl &= ~(0xff << 8);
3147         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3148         WREG32(RADEON_MEM_CNTL, mem_cntl);
3149         RREG32(RADEON_MEM_CNTL);
3150
3151         /* sdram reset ? */
3152
3153         /* something like this????  */
3154         while (ram--) {
3155                 addr = ram * 1024 * 1024;
3156                 /* write to each page */
3157                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3158                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3159                 /* read back and verify */
3160                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3161                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3162                         return 0;
3163         }
3164
3165         return mem_size;
3166 }
3167
3168 static void combios_write_ram_size(struct drm_device *dev)
3169 {
3170         struct radeon_device *rdev = dev->dev_private;
3171         uint8_t rev;
3172         uint16_t offset;
3173         uint32_t mem_size = 0;
3174         uint32_t mem_cntl = 0;
3175
3176         /* should do something smarter here I guess... */
3177         if (rdev->flags & RADEON_IS_IGP)
3178                 return;
3179
3180         /* first check detected mem table */
3181         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3182         if (offset) {
3183                 rev = RBIOS8(offset);
3184                 if (rev < 3) {
3185                         mem_cntl = RBIOS32(offset + 1);
3186                         mem_size = RBIOS16(offset + 5);
3187                         if ((rdev->family < CHIP_R200) &&
3188                             !ASIC_IS_RN50(rdev))
3189                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3190                 }
3191         }
3192
3193         if (!mem_size) {
3194                 offset =
3195                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3196                 if (offset) {
3197                         rev = RBIOS8(offset - 1);
3198                         if (rev < 1) {
3199                                 if ((rdev->family < CHIP_R200)
3200                                     && !ASIC_IS_RN50(rdev)) {
3201                                         int ram = 0;
3202                                         int mem_addr_mapping = 0;
3203
3204                                         while (RBIOS8(offset)) {
3205                                                 ram = RBIOS8(offset);
3206                                                 mem_addr_mapping =
3207                                                     RBIOS8(offset + 1);
3208                                                 if (mem_addr_mapping != 0x25)
3209                                                         ram *= 2;
3210                                                 mem_size =
3211                                                     combios_detect_ram(dev, ram,
3212                                                                        mem_addr_mapping);
3213                                                 if (mem_size)
3214                                                         break;
3215                                                 offset += 2;
3216                                         }
3217                                 } else
3218                                         mem_size = RBIOS8(offset);
3219                         } else {
3220                                 mem_size = RBIOS8(offset);
3221                                 mem_size *= 2;  /* convert to MB */
3222                         }
3223                 }
3224         }
3225
3226         mem_size *= (1024 * 1024);      /* convert to bytes */
3227         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3228 }
3229
3230 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3231 {
3232         uint16_t dyn_clk_info =
3233             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3234
3235         if (dyn_clk_info)
3236                 combios_parse_pll_table(dev, dyn_clk_info);
3237 }
3238
3239 void radeon_combios_asic_init(struct drm_device *dev)
3240 {
3241         struct radeon_device *rdev = dev->dev_private;
3242         uint16_t table;
3243
3244         /* port hardcoded mac stuff from radeonfb */
3245         if (rdev->bios == NULL)
3246                 return;
3247
3248         /* ASIC INIT 1 */
3249         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3250         if (table)
3251                 combios_parse_mmio_table(dev, table);
3252
3253         /* PLL INIT */
3254         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3255         if (table)
3256                 combios_parse_pll_table(dev, table);
3257
3258         /* ASIC INIT 2 */
3259         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3260         if (table)
3261                 combios_parse_mmio_table(dev, table);
3262
3263         if (!(rdev->flags & RADEON_IS_IGP)) {
3264                 /* ASIC INIT 4 */
3265                 table =
3266                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3267                 if (table)
3268                         combios_parse_mmio_table(dev, table);
3269
3270                 /* RAM RESET */
3271                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3272                 if (table)
3273                         combios_parse_ram_reset_table(dev, table);
3274
3275                 /* ASIC INIT 3 */
3276                 table =
3277                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3278                 if (table)
3279                         combios_parse_mmio_table(dev, table);
3280
3281                 /* write CONFIG_MEMSIZE */
3282                 combios_write_ram_size(dev);
3283         }
3284
3285         /* quirk for rs4xx HP nx6125 laptop to make it resume
3286          * - it hangs on resume inside the dynclk 1 table.
3287          */
3288         if (rdev->family == CHIP_RS480 &&
3289             rdev->pdev->subsystem_vendor == 0x103c &&
3290             rdev->pdev->subsystem_device == 0x308b)
3291                 return;
3292
3293         /* quirk for rs4xx HP dv5000 laptop to make it resume
3294          * - it hangs on resume inside the dynclk 1 table.
3295          */
3296         if (rdev->family == CHIP_RS480 &&
3297             rdev->pdev->subsystem_vendor == 0x103c &&
3298             rdev->pdev->subsystem_device == 0x30a4)
3299                 return;
3300
3301         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3302          * - it hangs on resume inside the dynclk 1 table.
3303          */
3304         if (rdev->family == CHIP_RS480 &&
3305             rdev->pdev->subsystem_vendor == 0x103c &&
3306             rdev->pdev->subsystem_device == 0x30ae)
3307                 return;
3308
3309         /* DYN CLK 1 */
3310         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3311         if (table)
3312                 combios_parse_pll_table(dev, table);
3313
3314 }
3315
3316 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3317 {
3318         struct radeon_device *rdev = dev->dev_private;
3319         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3320
3321         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3322         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3323         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3324
3325         /* let the bios control the backlight */
3326         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3327
3328         /* tell the bios not to handle mode switching */
3329         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3330                            RADEON_ACC_MODE_CHANGE);
3331
3332         /* tell the bios a driver is loaded */
3333         bios_7_scratch |= RADEON_DRV_LOADED;
3334
3335         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3336         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3337         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3338 }
3339
3340 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3341 {
3342         struct drm_device *dev = encoder->dev;
3343         struct radeon_device *rdev = dev->dev_private;
3344         uint32_t bios_6_scratch;
3345
3346         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3347
3348         if (lock)
3349                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3350         else
3351                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3352
3353         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3354 }
3355
3356 void
3357 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3358                                       struct drm_encoder *encoder,
3359                                       bool connected)
3360 {
3361         struct drm_device *dev = connector->dev;
3362         struct radeon_device *rdev = dev->dev_private;
3363         struct radeon_connector *radeon_connector =
3364             to_radeon_connector(connector);
3365         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3366         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3367         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3368
3369         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3370             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3371                 if (connected) {
3372                         DRM_DEBUG_KMS("TV1 connected\n");
3373                         /* fix me */
3374                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3375                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3376                         bios_5_scratch |= RADEON_TV1_ON;
3377                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3378                 } else {
3379                         DRM_DEBUG_KMS("TV1 disconnected\n");
3380                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3381                         bios_5_scratch &= ~RADEON_TV1_ON;
3382                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3383                 }
3384         }
3385         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3386             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3387                 if (connected) {
3388                         DRM_DEBUG_KMS("LCD1 connected\n");
3389                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3390                         bios_5_scratch |= RADEON_LCD1_ON;
3391                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3392                 } else {
3393                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3394                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3395                         bios_5_scratch &= ~RADEON_LCD1_ON;
3396                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3397                 }
3398         }
3399         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3400             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3401                 if (connected) {
3402                         DRM_DEBUG_KMS("CRT1 connected\n");
3403                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3404                         bios_5_scratch |= RADEON_CRT1_ON;
3405                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3406                 } else {
3407                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3408                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3409                         bios_5_scratch &= ~RADEON_CRT1_ON;
3410                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3411                 }
3412         }
3413         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3414             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3415                 if (connected) {
3416                         DRM_DEBUG_KMS("CRT2 connected\n");
3417                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3418                         bios_5_scratch |= RADEON_CRT2_ON;
3419                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3420                 } else {
3421                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3422                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3423                         bios_5_scratch &= ~RADEON_CRT2_ON;
3424                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3425                 }
3426         }
3427         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3428             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3429                 if (connected) {
3430                         DRM_DEBUG_KMS("DFP1 connected\n");
3431                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3432                         bios_5_scratch |= RADEON_DFP1_ON;
3433                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3434                 } else {
3435                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3436                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3437                         bios_5_scratch &= ~RADEON_DFP1_ON;
3438                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3439                 }
3440         }
3441         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3442             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3443                 if (connected) {
3444                         DRM_DEBUG_KMS("DFP2 connected\n");
3445                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3446                         bios_5_scratch |= RADEON_DFP2_ON;
3447                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3448                 } else {
3449                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3450                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3451                         bios_5_scratch &= ~RADEON_DFP2_ON;
3452                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3453                 }
3454         }
3455         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3456         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3457 }
3458
3459 void
3460 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3461 {
3462         struct drm_device *dev = encoder->dev;
3463         struct radeon_device *rdev = dev->dev_private;
3464         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3465         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3466
3467         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3468                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3469                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3470         }
3471         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3472                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3473                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3474         }
3475         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3476                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3477                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3478         }
3479         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3480                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3481                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3482         }
3483         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3484                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3485                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3486         }
3487         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3488                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3489                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3490         }
3491         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3492 }
3493
3494 void
3495 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3496 {
3497         struct drm_device *dev = encoder->dev;
3498         struct radeon_device *rdev = dev->dev_private;
3499         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3500         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3501
3502         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3503                 if (on)
3504                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3505                 else
3506                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3507         }
3508         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3509                 if (on)
3510                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3511                 else
3512                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3513         }
3514         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3515                 if (on)
3516                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3517                 else
3518                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3519         }
3520         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3521                 if (on)
3522                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3523                 else
3524                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3525         }
3526         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3527 }