2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
158 offset = check_offset;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
163 offset = check_offset;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
168 offset = check_offset;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
173 offset = check_offset;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
178 offset = check_offset;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
183 offset = check_offset;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
188 offset = check_offset;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
193 offset = check_offset;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
198 offset = check_offset;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
203 offset = check_offset;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
208 offset = check_offset;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
213 offset = check_offset;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
218 offset = check_offset;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
223 offset = check_offset;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
228 offset = check_offset;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
233 offset = check_offset;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
238 offset = check_offset;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
243 offset = check_offset;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
248 offset = check_offset;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
253 offset = check_offset;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
258 offset = check_offset;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
263 offset = check_offset;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
268 offset = check_offset;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
273 offset = check_offset;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
278 offset = check_offset;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
283 offset = check_offset;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
288 offset = check_offset;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
293 offset = check_offset;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
298 offset = check_offset;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
303 offset = check_offset;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
308 offset = check_offset;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
313 offset = check_offset;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
318 offset = check_offset;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
323 offset = check_offset;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
330 rev = RBIOS8(check_offset);
332 check_offset = RBIOS16(check_offset + 0x3);
334 offset = check_offset;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
342 rev = RBIOS8(check_offset);
344 check_offset = RBIOS16(check_offset + 0x5);
346 offset = check_offset;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
354 rev = RBIOS8(check_offset);
356 check_offset = RBIOS16(check_offset + 0x7);
358 offset = check_offset;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
366 rev = RBIOS8(check_offset);
368 check_offset = RBIOS16(check_offset + 0x9);
370 offset = check_offset;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
378 while (RBIOS8(check_offset++));
381 offset = check_offset;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
388 check_offset = RBIOS16(check_offset + 0x11);
390 offset = check_offset;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
397 check_offset = RBIOS16(check_offset + 0x13);
399 offset = check_offset;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
406 check_offset = RBIOS16(check_offset + 0x15);
408 offset = check_offset;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
415 check_offset = RBIOS16(check_offset + 0x17);
417 offset = check_offset;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
424 check_offset = RBIOS16(check_offset + 0x2);
426 offset = check_offset;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
433 check_offset = RBIOS16(check_offset + 0x4);
435 offset = check_offset;
446 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
449 struct radeon_i2c_bus_rec i2c;
451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
489 if (rdev->family < CHIP_R200)
490 i2c.hw_capable = false;
493 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC:
495 i2c.hw_capable = true;
497 case RADEON_GPIO_MONID:
498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
499 * reliably on some pre-r4xx hardware; not sure why.
501 i2c.hw_capable = false;
504 i2c.hw_capable = false;
519 bool radeon_combios_get_clock_info(struct drm_device *dev)
521 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_pll *p1pll = &rdev->clock.p1pll;
524 struct radeon_pll *p2pll = &rdev->clock.p2pll;
525 struct radeon_pll *spll = &rdev->clock.spll;
526 struct radeon_pll *mpll = &rdev->clock.mpll;
530 if (rdev->bios == NULL)
533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
535 rev = RBIOS8(pll_info);
538 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
539 p1pll->reference_div = RBIOS16(pll_info + 0x10);
540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
547 p1pll->pll_in_min = 40;
548 p1pll->pll_in_max = 500;
553 spll->reference_freq = RBIOS16(pll_info + 0x1a);
554 spll->reference_div = RBIOS16(pll_info + 0x1c);
555 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
556 spll->pll_out_max = RBIOS32(pll_info + 0x22);
559 spll->pll_in_min = RBIOS32(pll_info + 0x48);
560 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
563 spll->pll_in_min = 40;
564 spll->pll_in_max = 500;
568 mpll->reference_freq = RBIOS16(pll_info + 0x26);
569 mpll->reference_div = RBIOS16(pll_info + 0x28);
570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
578 mpll->pll_in_min = 40;
579 mpll->pll_in_max = 500;
582 /* default sclk/mclk */
583 sclk = RBIOS16(pll_info + 0xa);
584 mclk = RBIOS16(pll_info + 0x8);
590 rdev->clock.default_sclk = sclk;
591 rdev->clock.default_mclk = mclk;
598 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
602 struct drm_device *dev = encoder->base.dev;
603 struct radeon_device *rdev = dev->dev_private;
605 uint8_t rev, bg, dac;
606 struct radeon_encoder_primary_dac *p_dac = NULL;
608 if (rdev->bios == NULL)
611 /* check CRT table */
612 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
615 kzalloc(sizeof(struct radeon_encoder_primary_dac),
621 rev = RBIOS8(dac_info) & 0x3;
623 bg = RBIOS8(dac_info + 0x2) & 0xf;
624 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
625 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
627 bg = RBIOS8(dac_info + 0x2) & 0xf;
628 dac = RBIOS8(dac_info + 0x3) & 0xf;
629 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
637 static enum radeon_tv_std
638 radeon_combios_get_tv_info(struct radeon_encoder *encoder)
640 struct drm_device *dev = encoder->base.dev;
641 struct radeon_device *rdev = dev->dev_private;
643 enum radeon_tv_std tv_std = TV_STD_NTSC;
645 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
647 if (RBIOS8(tv_info + 6) == 'T') {
648 switch (RBIOS8(tv_info + 7) & 0xf) {
650 tv_std = TV_STD_NTSC;
651 DRM_INFO("Default TV standard: NTSC\n");
655 DRM_INFO("Default TV standard: PAL\n");
658 tv_std = TV_STD_PAL_M;
659 DRM_INFO("Default TV standard: PAL-M\n");
662 tv_std = TV_STD_PAL_60;
663 DRM_INFO("Default TV standard: PAL-60\n");
666 tv_std = TV_STD_NTSC_J;
667 DRM_INFO("Default TV standard: NTSC-J\n");
670 tv_std = TV_STD_SCART_PAL;
671 DRM_INFO("Default TV standard: SCART-PAL\n");
674 tv_std = TV_STD_NTSC;
676 ("Unknown TV standard; defaulting to NTSC\n");
680 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
682 DRM_INFO("29.498928713 MHz TV ref clk\n");
685 DRM_INFO("28.636360000 MHz TV ref clk\n");
688 DRM_INFO("14.318180000 MHz TV ref clk\n");
691 DRM_INFO("27.000000000 MHz TV ref clk\n");
701 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
702 0x00000000, /* r100 */
703 0x00280000, /* rv100 */
704 0x00000000, /* rs100 */
705 0x00880000, /* rv200 */
706 0x00000000, /* rs200 */
707 0x00000000, /* r200 */
708 0x00770000, /* rv250 */
709 0x00290000, /* rs300 */
710 0x00560000, /* rv280 */
711 0x00780000, /* r300 */
712 0x00770000, /* r350 */
713 0x00780000, /* rv350 */
714 0x00780000, /* rv380 */
715 0x01080000, /* r420 */
716 0x01080000, /* r423 */
717 0x01080000, /* rv410 */
718 0x00780000, /* rs400 */
719 0x00780000, /* rs480 */
722 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
723 struct radeon_encoder_tv_dac *tv_dac)
725 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
726 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
727 tv_dac->ps2_tvdac_adj = 0x00880000;
728 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
729 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
733 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_tv_dac *tv_dac = NULL;
744 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
748 if (rdev->bios == NULL)
751 /* first check TV table */
752 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
754 rev = RBIOS8(dac_info + 0x3);
756 bg = RBIOS8(dac_info + 0xc) & 0xf;
757 dac = RBIOS8(dac_info + 0xd) & 0xf;
758 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
760 bg = RBIOS8(dac_info + 0xe) & 0xf;
761 dac = RBIOS8(dac_info + 0xf) & 0xf;
762 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
764 bg = RBIOS8(dac_info + 0x10) & 0xf;
765 dac = RBIOS8(dac_info + 0x11) & 0xf;
766 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
768 } else if (rev > 1) {
769 bg = RBIOS8(dac_info + 0xc) & 0xf;
770 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
771 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
773 bg = RBIOS8(dac_info + 0xd) & 0xf;
774 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
775 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
777 bg = RBIOS8(dac_info + 0xe) & 0xf;
778 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
779 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
782 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
785 /* then check CRT table */
787 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
789 rev = RBIOS8(dac_info) & 0x3;
791 bg = RBIOS8(dac_info + 0x3) & 0xf;
792 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
793 tv_dac->ps2_tvdac_adj =
794 (bg << 16) | (dac << 20);
795 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
796 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
799 bg = RBIOS8(dac_info + 0x4) & 0xf;
800 dac = RBIOS8(dac_info + 0x5) & 0xf;
801 tv_dac->ps2_tvdac_adj =
802 (bg << 16) | (dac << 20);
803 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
804 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
808 DRM_INFO("No TV DAC info found in BIOS\n");
813 if (!found) /* fallback to defaults */
814 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
819 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
823 struct radeon_encoder_lvds *lvds = NULL;
824 uint32_t fp_vert_stretch, fp_horz_stretch;
825 uint32_t ppll_div_sel, ppll_val;
826 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
828 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
833 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
834 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
836 /* These should be fail-safe defaults, fingers crossed */
837 lvds->panel_pwr_delay = 200;
838 lvds->panel_vcc_delay = 2000;
840 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
841 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
842 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
844 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
845 lvds->native_mode.vdisplay =
846 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
847 RADEON_VERT_PANEL_SHIFT) + 1;
849 lvds->native_mode.vdisplay =
850 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
852 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
853 lvds->native_mode.hdisplay =
854 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
855 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
857 lvds->native_mode.hdisplay =
858 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
860 if ((lvds->native_mode.hdisplay < 640) ||
861 (lvds->native_mode.vdisplay < 480)) {
862 lvds->native_mode.hdisplay = 640;
863 lvds->native_mode.vdisplay = 480;
866 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
867 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
868 if ((ppll_val & 0x000707ff) == 0x1bb)
869 lvds->use_bios_dividers = false;
871 lvds->panel_ref_divider =
872 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
873 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
874 lvds->panel_fb_divider = ppll_val & 0x7ff;
876 if ((lvds->panel_ref_divider != 0) &&
877 (lvds->panel_fb_divider > 3))
878 lvds->use_bios_dividers = true;
880 lvds->panel_vcc_delay = 200;
882 DRM_INFO("Panel info derived from registers\n");
883 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
884 lvds->native_mode.vdisplay);
889 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
892 struct drm_device *dev = encoder->base.dev;
893 struct radeon_device *rdev = dev->dev_private;
895 uint32_t panel_setup;
898 struct radeon_encoder_lvds *lvds = NULL;
900 if (rdev->bios == NULL) {
901 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
905 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
908 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
913 for (i = 0; i < 24; i++)
914 stmp[i] = RBIOS8(lcd_info + i + 1);
917 DRM_INFO("Panel ID String: %s\n", stmp);
919 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
920 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
922 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
923 lvds->native_mode.vdisplay);
925 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
926 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
927 lvds->panel_vcc_delay = 2000;
929 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
930 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
931 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
933 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
934 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
935 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
936 if ((lvds->panel_ref_divider != 0) &&
937 (lvds->panel_fb_divider > 3))
938 lvds->use_bios_dividers = true;
940 panel_setup = RBIOS32(lcd_info + 0x39);
941 lvds->lvds_gen_cntl = 0xff00;
942 if (panel_setup & 0x1)
943 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
945 if ((panel_setup >> 4) & 0x1)
946 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
948 switch ((panel_setup >> 8) & 0x7) {
950 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
953 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
956 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
962 if ((panel_setup >> 16) & 0x1)
963 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
965 if ((panel_setup >> 17) & 0x1)
966 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
968 if ((panel_setup >> 18) & 0x1)
969 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
971 if ((panel_setup >> 23) & 0x1)
972 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
974 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
976 for (i = 0; i < 32; i++) {
977 tmp = RBIOS16(lcd_info + 64 + i * 2);
981 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
983 lvds->native_mode.vdisplay)) {
984 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
985 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
986 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
987 RBIOS16(tmp + 21)) * 8;
989 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
990 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
991 lvds->native_mode.vsync_end =
992 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
993 (RBIOS16(tmp + 28) & 0x7ff);
995 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
996 lvds->native_mode.flags = 0;
997 /* set crtc values */
998 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1003 DRM_INFO("No panel info found in BIOS\n");
1004 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1008 encoder->native_mode = lvds->native_mode;
1012 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1013 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1014 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1015 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1016 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1017 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1018 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1019 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1020 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1021 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1022 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1023 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1024 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1025 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1026 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1027 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1028 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1029 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1030 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1033 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1034 struct radeon_encoder_int_tmds *tmds)
1036 struct drm_device *dev = encoder->base.dev;
1037 struct radeon_device *rdev = dev->dev_private;
1040 for (i = 0; i < 4; i++) {
1041 tmds->tmds_pll[i].value =
1042 default_tmds_pll[rdev->family][i].value;
1043 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1049 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1050 struct radeon_encoder_int_tmds *tmds)
1052 struct drm_device *dev = encoder->base.dev;
1053 struct radeon_device *rdev = dev->dev_private;
1058 if (rdev->bios == NULL)
1061 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1064 ver = RBIOS8(tmds_info);
1065 DRM_INFO("DFP table revision: %d\n", ver);
1067 n = RBIOS8(tmds_info + 5) + 1;
1070 for (i = 0; i < n; i++) {
1071 tmds->tmds_pll[i].value =
1072 RBIOS32(tmds_info + i * 10 + 0x08);
1073 tmds->tmds_pll[i].freq =
1074 RBIOS16(tmds_info + i * 10 + 0x10);
1075 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1076 tmds->tmds_pll[i].freq,
1077 tmds->tmds_pll[i].value);
1079 } else if (ver == 4) {
1081 n = RBIOS8(tmds_info + 5) + 1;
1084 for (i = 0; i < n; i++) {
1085 tmds->tmds_pll[i].value =
1086 RBIOS32(tmds_info + stride + 0x08);
1087 tmds->tmds_pll[i].freq =
1088 RBIOS16(tmds_info + stride + 0x10);
1093 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1094 tmds->tmds_pll[i].freq,
1095 tmds->tmds_pll[i].value);
1099 DRM_INFO("No TMDS info found in BIOS\n");
1105 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1106 struct radeon_encoder_ext_tmds *tmds)
1108 struct drm_device *dev = encoder->base.dev;
1109 struct radeon_device *rdev = dev->dev_private;
1110 struct radeon_i2c_bus_rec i2c_bus;
1112 /* default for macs */
1113 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1114 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1116 /* XXX some macs have duallink chips */
1117 switch (rdev->mode_info.connector_table) {
1118 case CT_POWERBOOK_EXTERNAL:
1119 case CT_MINI_EXTERNAL:
1121 tmds->dvo_chip = DVO_SIL164;
1122 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1129 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1130 struct radeon_encoder_ext_tmds *tmds)
1132 struct drm_device *dev = encoder->base.dev;
1133 struct radeon_device *rdev = dev->dev_private;
1135 uint8_t ver, id, blocks, clk, data;
1137 enum radeon_combios_ddc gpio;
1138 struct radeon_i2c_bus_rec i2c_bus;
1140 if (rdev->bios == NULL)
1143 tmds->i2c_bus = NULL;
1144 if (rdev->flags & RADEON_IS_IGP) {
1145 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1147 ver = RBIOS8(offset);
1148 DRM_INFO("GPIO Table revision: %d\n", ver);
1149 blocks = RBIOS8(offset + 2);
1150 for (i = 0; i < blocks; i++) {
1151 id = RBIOS8(offset + 3 + (i * 5) + 0);
1153 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1154 data = RBIOS8(offset + 3 + (i * 5) + 4);
1155 i2c_bus.valid = true;
1156 i2c_bus.mask_clk_mask = (1 << clk);
1157 i2c_bus.mask_data_mask = (1 << data);
1158 i2c_bus.a_clk_mask = (1 << clk);
1159 i2c_bus.a_data_mask = (1 << data);
1160 i2c_bus.en_clk_mask = (1 << clk);
1161 i2c_bus.en_data_mask = (1 << data);
1162 i2c_bus.y_clk_mask = (1 << clk);
1163 i2c_bus.y_data_mask = (1 << data);
1164 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1165 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1166 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1167 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1168 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1169 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1170 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1171 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1172 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1173 tmds->dvo_chip = DVO_SIL164;
1174 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1180 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1182 ver = RBIOS8(offset);
1183 DRM_INFO("External TMDS Table revision: %d\n", ver);
1184 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1185 tmds->slave_addr >>= 1; /* 7 bit addressing */
1186 gpio = RBIOS8(offset + 4 + 3);
1189 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1190 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1193 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1194 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1197 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1198 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1201 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1202 if (rdev->family >= CHIP_R300)
1203 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1205 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1206 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1208 case DDC_LCD: /* MM i2c */
1209 DRM_ERROR("MM i2c requires hw i2c engine\n");
1212 DRM_ERROR("Unsupported gpio %d\n", gpio);
1218 if (!tmds->i2c_bus) {
1219 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1226 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1228 struct radeon_device *rdev = dev->dev_private;
1229 struct radeon_i2c_bus_rec ddc_i2c;
1230 struct radeon_hpd hpd;
1232 rdev->mode_info.connector_table = radeon_connector_table;
1233 if (rdev->mode_info.connector_table == CT_NONE) {
1234 #ifdef CONFIG_PPC_PMAC
1235 if (machine_is_compatible("PowerBook3,3")) {
1236 /* powerbook with VGA */
1237 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1238 } else if (machine_is_compatible("PowerBook3,4") ||
1239 machine_is_compatible("PowerBook3,5")) {
1240 /* powerbook with internal tmds */
1241 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1242 } else if (machine_is_compatible("PowerBook5,1") ||
1243 machine_is_compatible("PowerBook5,2") ||
1244 machine_is_compatible("PowerBook5,3") ||
1245 machine_is_compatible("PowerBook5,4") ||
1246 machine_is_compatible("PowerBook5,5")) {
1247 /* powerbook with external single link tmds (sil164) */
1248 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1249 } else if (machine_is_compatible("PowerBook5,6")) {
1250 /* powerbook with external dual or single link tmds */
1251 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1252 } else if (machine_is_compatible("PowerBook5,7") ||
1253 machine_is_compatible("PowerBook5,8") ||
1254 machine_is_compatible("PowerBook5,9")) {
1255 /* PowerBook6,2 ? */
1256 /* powerbook with external dual link tmds (sil1178?) */
1257 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1258 } else if (machine_is_compatible("PowerBook4,1") ||
1259 machine_is_compatible("PowerBook4,2") ||
1260 machine_is_compatible("PowerBook4,3") ||
1261 machine_is_compatible("PowerBook6,3") ||
1262 machine_is_compatible("PowerBook6,5") ||
1263 machine_is_compatible("PowerBook6,7")) {
1265 rdev->mode_info.connector_table = CT_IBOOK;
1266 } else if (machine_is_compatible("PowerMac4,4")) {
1268 rdev->mode_info.connector_table = CT_EMAC;
1269 } else if (machine_is_compatible("PowerMac10,1")) {
1270 /* mini with internal tmds */
1271 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1272 } else if (machine_is_compatible("PowerMac10,2")) {
1273 /* mini with external tmds */
1274 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1275 } else if (machine_is_compatible("PowerMac12,1")) {
1277 /* imac g5 isight */
1278 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1280 #endif /* CONFIG_PPC_PMAC */
1281 rdev->mode_info.connector_table = CT_GENERIC;
1284 switch (rdev->mode_info.connector_table) {
1286 DRM_INFO("Connector Table: %d (generic)\n",
1287 rdev->mode_info.connector_table);
1288 /* these are the most common settings */
1289 if (rdev->flags & RADEON_SINGLE_CRTC) {
1290 /* VGA - primary dac */
1291 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1292 hpd.hpd = RADEON_HPD_NONE;
1293 radeon_add_legacy_encoder(dev,
1294 radeon_get_encoder_id(dev,
1295 ATOM_DEVICE_CRT1_SUPPORT,
1297 ATOM_DEVICE_CRT1_SUPPORT);
1298 radeon_add_legacy_connector(dev, 0,
1299 ATOM_DEVICE_CRT1_SUPPORT,
1300 DRM_MODE_CONNECTOR_VGA,
1302 CONNECTOR_OBJECT_ID_VGA,
1304 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1306 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1307 hpd.hpd = RADEON_HPD_NONE;
1308 radeon_add_legacy_encoder(dev,
1309 radeon_get_encoder_id(dev,
1310 ATOM_DEVICE_LCD1_SUPPORT,
1312 ATOM_DEVICE_LCD1_SUPPORT);
1313 radeon_add_legacy_connector(dev, 0,
1314 ATOM_DEVICE_LCD1_SUPPORT,
1315 DRM_MODE_CONNECTOR_LVDS,
1317 CONNECTOR_OBJECT_ID_LVDS,
1320 /* VGA - primary dac */
1321 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1322 hpd.hpd = RADEON_HPD_NONE;
1323 radeon_add_legacy_encoder(dev,
1324 radeon_get_encoder_id(dev,
1325 ATOM_DEVICE_CRT1_SUPPORT,
1327 ATOM_DEVICE_CRT1_SUPPORT);
1328 radeon_add_legacy_connector(dev, 1,
1329 ATOM_DEVICE_CRT1_SUPPORT,
1330 DRM_MODE_CONNECTOR_VGA,
1332 CONNECTOR_OBJECT_ID_VGA,
1335 /* DVI-I - tv dac, int tmds */
1336 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1337 hpd.hpd = RADEON_HPD_1;
1338 radeon_add_legacy_encoder(dev,
1339 radeon_get_encoder_id(dev,
1340 ATOM_DEVICE_DFP1_SUPPORT,
1342 ATOM_DEVICE_DFP1_SUPPORT);
1343 radeon_add_legacy_encoder(dev,
1344 radeon_get_encoder_id(dev,
1345 ATOM_DEVICE_CRT2_SUPPORT,
1347 ATOM_DEVICE_CRT2_SUPPORT);
1348 radeon_add_legacy_connector(dev, 0,
1349 ATOM_DEVICE_DFP1_SUPPORT |
1350 ATOM_DEVICE_CRT2_SUPPORT,
1351 DRM_MODE_CONNECTOR_DVII,
1353 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1356 /* VGA - primary dac */
1357 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1358 hpd.hpd = RADEON_HPD_NONE;
1359 radeon_add_legacy_encoder(dev,
1360 radeon_get_encoder_id(dev,
1361 ATOM_DEVICE_CRT1_SUPPORT,
1363 ATOM_DEVICE_CRT1_SUPPORT);
1364 radeon_add_legacy_connector(dev, 1,
1365 ATOM_DEVICE_CRT1_SUPPORT,
1366 DRM_MODE_CONNECTOR_VGA,
1368 CONNECTOR_OBJECT_ID_VGA,
1372 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1374 ddc_i2c.valid = false;
1375 hpd.hpd = RADEON_HPD_NONE;
1376 radeon_add_legacy_encoder(dev,
1377 radeon_get_encoder_id(dev,
1378 ATOM_DEVICE_TV1_SUPPORT,
1380 ATOM_DEVICE_TV1_SUPPORT);
1381 radeon_add_legacy_connector(dev, 2,
1382 ATOM_DEVICE_TV1_SUPPORT,
1383 DRM_MODE_CONNECTOR_SVIDEO,
1385 CONNECTOR_OBJECT_ID_SVIDEO,
1390 DRM_INFO("Connector Table: %d (ibook)\n",
1391 rdev->mode_info.connector_table);
1393 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1394 hpd.hpd = RADEON_HPD_NONE;
1395 radeon_add_legacy_encoder(dev,
1396 radeon_get_encoder_id(dev,
1397 ATOM_DEVICE_LCD1_SUPPORT,
1399 ATOM_DEVICE_LCD1_SUPPORT);
1400 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1401 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1402 CONNECTOR_OBJECT_ID_LVDS,
1405 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1406 hpd.hpd = RADEON_HPD_NONE;
1407 radeon_add_legacy_encoder(dev,
1408 radeon_get_encoder_id(dev,
1409 ATOM_DEVICE_CRT2_SUPPORT,
1411 ATOM_DEVICE_CRT2_SUPPORT);
1412 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1413 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1414 CONNECTOR_OBJECT_ID_VGA,
1417 ddc_i2c.valid = false;
1418 hpd.hpd = RADEON_HPD_NONE;
1419 radeon_add_legacy_encoder(dev,
1420 radeon_get_encoder_id(dev,
1421 ATOM_DEVICE_TV1_SUPPORT,
1423 ATOM_DEVICE_TV1_SUPPORT);
1424 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1425 DRM_MODE_CONNECTOR_SVIDEO,
1427 CONNECTOR_OBJECT_ID_SVIDEO,
1430 case CT_POWERBOOK_EXTERNAL:
1431 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1432 rdev->mode_info.connector_table);
1434 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1435 hpd.hpd = RADEON_HPD_NONE;
1436 radeon_add_legacy_encoder(dev,
1437 radeon_get_encoder_id(dev,
1438 ATOM_DEVICE_LCD1_SUPPORT,
1440 ATOM_DEVICE_LCD1_SUPPORT);
1441 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1442 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1443 CONNECTOR_OBJECT_ID_LVDS,
1445 /* DVI-I - primary dac, ext tmds */
1446 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1447 hpd.hpd = RADEON_HPD_2; /* ??? */
1448 radeon_add_legacy_encoder(dev,
1449 radeon_get_encoder_id(dev,
1450 ATOM_DEVICE_DFP2_SUPPORT,
1452 ATOM_DEVICE_DFP2_SUPPORT);
1453 radeon_add_legacy_encoder(dev,
1454 radeon_get_encoder_id(dev,
1455 ATOM_DEVICE_CRT1_SUPPORT,
1457 ATOM_DEVICE_CRT1_SUPPORT);
1458 /* XXX some are SL */
1459 radeon_add_legacy_connector(dev, 1,
1460 ATOM_DEVICE_DFP2_SUPPORT |
1461 ATOM_DEVICE_CRT1_SUPPORT,
1462 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1463 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1466 ddc_i2c.valid = false;
1467 hpd.hpd = RADEON_HPD_NONE;
1468 radeon_add_legacy_encoder(dev,
1469 radeon_get_encoder_id(dev,
1470 ATOM_DEVICE_TV1_SUPPORT,
1472 ATOM_DEVICE_TV1_SUPPORT);
1473 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1474 DRM_MODE_CONNECTOR_SVIDEO,
1476 CONNECTOR_OBJECT_ID_SVIDEO,
1479 case CT_POWERBOOK_INTERNAL:
1480 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1481 rdev->mode_info.connector_table);
1483 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1484 hpd.hpd = RADEON_HPD_NONE;
1485 radeon_add_legacy_encoder(dev,
1486 radeon_get_encoder_id(dev,
1487 ATOM_DEVICE_LCD1_SUPPORT,
1489 ATOM_DEVICE_LCD1_SUPPORT);
1490 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1491 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1492 CONNECTOR_OBJECT_ID_LVDS,
1494 /* DVI-I - primary dac, int tmds */
1495 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1496 hpd.hpd = RADEON_HPD_1; /* ??? */
1497 radeon_add_legacy_encoder(dev,
1498 radeon_get_encoder_id(dev,
1499 ATOM_DEVICE_DFP1_SUPPORT,
1501 ATOM_DEVICE_DFP1_SUPPORT);
1502 radeon_add_legacy_encoder(dev,
1503 radeon_get_encoder_id(dev,
1504 ATOM_DEVICE_CRT1_SUPPORT,
1506 ATOM_DEVICE_CRT1_SUPPORT);
1507 radeon_add_legacy_connector(dev, 1,
1508 ATOM_DEVICE_DFP1_SUPPORT |
1509 ATOM_DEVICE_CRT1_SUPPORT,
1510 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1511 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1514 ddc_i2c.valid = false;
1515 hpd.hpd = RADEON_HPD_NONE;
1516 radeon_add_legacy_encoder(dev,
1517 radeon_get_encoder_id(dev,
1518 ATOM_DEVICE_TV1_SUPPORT,
1520 ATOM_DEVICE_TV1_SUPPORT);
1521 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1522 DRM_MODE_CONNECTOR_SVIDEO,
1524 CONNECTOR_OBJECT_ID_SVIDEO,
1527 case CT_POWERBOOK_VGA:
1528 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1529 rdev->mode_info.connector_table);
1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1532 hpd.hpd = RADEON_HPD_NONE;
1533 radeon_add_legacy_encoder(dev,
1534 radeon_get_encoder_id(dev,
1535 ATOM_DEVICE_LCD1_SUPPORT,
1537 ATOM_DEVICE_LCD1_SUPPORT);
1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1540 CONNECTOR_OBJECT_ID_LVDS,
1542 /* VGA - primary dac */
1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1544 hpd.hpd = RADEON_HPD_NONE;
1545 radeon_add_legacy_encoder(dev,
1546 radeon_get_encoder_id(dev,
1547 ATOM_DEVICE_CRT1_SUPPORT,
1549 ATOM_DEVICE_CRT1_SUPPORT);
1550 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1551 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1552 CONNECTOR_OBJECT_ID_VGA,
1555 ddc_i2c.valid = false;
1556 hpd.hpd = RADEON_HPD_NONE;
1557 radeon_add_legacy_encoder(dev,
1558 radeon_get_encoder_id(dev,
1559 ATOM_DEVICE_TV1_SUPPORT,
1561 ATOM_DEVICE_TV1_SUPPORT);
1562 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1563 DRM_MODE_CONNECTOR_SVIDEO,
1565 CONNECTOR_OBJECT_ID_SVIDEO,
1568 case CT_MINI_EXTERNAL:
1569 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1570 rdev->mode_info.connector_table);
1571 /* DVI-I - tv dac, ext tmds */
1572 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1573 hpd.hpd = RADEON_HPD_2; /* ??? */
1574 radeon_add_legacy_encoder(dev,
1575 radeon_get_encoder_id(dev,
1576 ATOM_DEVICE_DFP2_SUPPORT,
1578 ATOM_DEVICE_DFP2_SUPPORT);
1579 radeon_add_legacy_encoder(dev,
1580 radeon_get_encoder_id(dev,
1581 ATOM_DEVICE_CRT2_SUPPORT,
1583 ATOM_DEVICE_CRT2_SUPPORT);
1584 /* XXX are any DL? */
1585 radeon_add_legacy_connector(dev, 0,
1586 ATOM_DEVICE_DFP2_SUPPORT |
1587 ATOM_DEVICE_CRT2_SUPPORT,
1588 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1589 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1592 ddc_i2c.valid = false;
1593 hpd.hpd = RADEON_HPD_NONE;
1594 radeon_add_legacy_encoder(dev,
1595 radeon_get_encoder_id(dev,
1596 ATOM_DEVICE_TV1_SUPPORT,
1598 ATOM_DEVICE_TV1_SUPPORT);
1599 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1600 DRM_MODE_CONNECTOR_SVIDEO,
1602 CONNECTOR_OBJECT_ID_SVIDEO,
1605 case CT_MINI_INTERNAL:
1606 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1607 rdev->mode_info.connector_table);
1608 /* DVI-I - tv dac, int tmds */
1609 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1610 hpd.hpd = RADEON_HPD_1; /* ??? */
1611 radeon_add_legacy_encoder(dev,
1612 radeon_get_encoder_id(dev,
1613 ATOM_DEVICE_DFP1_SUPPORT,
1615 ATOM_DEVICE_DFP1_SUPPORT);
1616 radeon_add_legacy_encoder(dev,
1617 radeon_get_encoder_id(dev,
1618 ATOM_DEVICE_CRT2_SUPPORT,
1620 ATOM_DEVICE_CRT2_SUPPORT);
1621 radeon_add_legacy_connector(dev, 0,
1622 ATOM_DEVICE_DFP1_SUPPORT |
1623 ATOM_DEVICE_CRT2_SUPPORT,
1624 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1625 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1628 ddc_i2c.valid = false;
1629 hpd.hpd = RADEON_HPD_NONE;
1630 radeon_add_legacy_encoder(dev,
1631 radeon_get_encoder_id(dev,
1632 ATOM_DEVICE_TV1_SUPPORT,
1634 ATOM_DEVICE_TV1_SUPPORT);
1635 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1636 DRM_MODE_CONNECTOR_SVIDEO,
1638 CONNECTOR_OBJECT_ID_SVIDEO,
1641 case CT_IMAC_G5_ISIGHT:
1642 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1643 rdev->mode_info.connector_table);
1644 /* DVI-D - int tmds */
1645 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1646 hpd.hpd = RADEON_HPD_1; /* ??? */
1647 radeon_add_legacy_encoder(dev,
1648 radeon_get_encoder_id(dev,
1649 ATOM_DEVICE_DFP1_SUPPORT,
1651 ATOM_DEVICE_DFP1_SUPPORT);
1652 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1653 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1654 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1657 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1658 hpd.hpd = RADEON_HPD_NONE;
1659 radeon_add_legacy_encoder(dev,
1660 radeon_get_encoder_id(dev,
1661 ATOM_DEVICE_CRT2_SUPPORT,
1663 ATOM_DEVICE_CRT2_SUPPORT);
1664 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1665 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1666 CONNECTOR_OBJECT_ID_VGA,
1669 ddc_i2c.valid = false;
1670 hpd.hpd = RADEON_HPD_NONE;
1671 radeon_add_legacy_encoder(dev,
1672 radeon_get_encoder_id(dev,
1673 ATOM_DEVICE_TV1_SUPPORT,
1675 ATOM_DEVICE_TV1_SUPPORT);
1676 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1677 DRM_MODE_CONNECTOR_SVIDEO,
1679 CONNECTOR_OBJECT_ID_SVIDEO,
1683 DRM_INFO("Connector Table: %d (emac)\n",
1684 rdev->mode_info.connector_table);
1685 /* VGA - primary dac */
1686 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1687 hpd.hpd = RADEON_HPD_NONE;
1688 radeon_add_legacy_encoder(dev,
1689 radeon_get_encoder_id(dev,
1690 ATOM_DEVICE_CRT1_SUPPORT,
1692 ATOM_DEVICE_CRT1_SUPPORT);
1693 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1694 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1695 CONNECTOR_OBJECT_ID_VGA,
1698 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1699 hpd.hpd = RADEON_HPD_NONE;
1700 radeon_add_legacy_encoder(dev,
1701 radeon_get_encoder_id(dev,
1702 ATOM_DEVICE_CRT2_SUPPORT,
1704 ATOM_DEVICE_CRT2_SUPPORT);
1705 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1706 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1707 CONNECTOR_OBJECT_ID_VGA,
1710 ddc_i2c.valid = false;
1711 hpd.hpd = RADEON_HPD_NONE;
1712 radeon_add_legacy_encoder(dev,
1713 radeon_get_encoder_id(dev,
1714 ATOM_DEVICE_TV1_SUPPORT,
1716 ATOM_DEVICE_TV1_SUPPORT);
1717 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1718 DRM_MODE_CONNECTOR_SVIDEO,
1720 CONNECTOR_OBJECT_ID_SVIDEO,
1724 DRM_INFO("Connector table: %d (invalid)\n",
1725 rdev->mode_info.connector_table);
1729 radeon_link_encoder_connector(dev);
1734 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1736 enum radeon_combios_connector
1738 struct radeon_i2c_bus_rec *ddc_i2c,
1739 struct radeon_hpd *hpd)
1741 struct radeon_device *rdev = dev->dev_private;
1743 /* XPRESS DDC quirks */
1744 if ((rdev->family == CHIP_RS400 ||
1745 rdev->family == CHIP_RS480) &&
1746 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1747 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1748 else if ((rdev->family == CHIP_RS400 ||
1749 rdev->family == CHIP_RS480) &&
1750 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1751 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1752 ddc_i2c->mask_clk_mask = (0x20 << 8);
1753 ddc_i2c->mask_data_mask = 0x80;
1754 ddc_i2c->a_clk_mask = (0x20 << 8);
1755 ddc_i2c->a_data_mask = 0x80;
1756 ddc_i2c->en_clk_mask = (0x20 << 8);
1757 ddc_i2c->en_data_mask = 0x80;
1758 ddc_i2c->y_clk_mask = (0x20 << 8);
1759 ddc_i2c->y_data_mask = 0x80;
1762 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1763 if ((rdev->family >= CHIP_R300) &&
1764 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1765 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1767 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1768 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1769 if (dev->pdev->device == 0x515e &&
1770 dev->pdev->subsystem_vendor == 0x1014) {
1771 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1772 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1776 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1777 if (dev->pdev->device == 0x5159 &&
1778 dev->pdev->subsystem_vendor == 0x1002 &&
1779 dev->pdev->subsystem_device == 0x013a) {
1780 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1781 *legacy_connector = CONNECTOR_CRT_LEGACY;
1785 /* X300 card with extra non-existent DVI port */
1786 if (dev->pdev->device == 0x5B60 &&
1787 dev->pdev->subsystem_vendor == 0x17af &&
1788 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1789 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1796 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1798 /* Acer 5102 has non-existent TV port */
1799 if (dev->pdev->device == 0x5975 &&
1800 dev->pdev->subsystem_vendor == 0x1025 &&
1801 dev->pdev->subsystem_device == 0x009f)
1804 /* HP dc5750 has non-existent TV port */
1805 if (dev->pdev->device == 0x5974 &&
1806 dev->pdev->subsystem_vendor == 0x103c &&
1807 dev->pdev->subsystem_device == 0x280a)
1810 /* MSI S270 has non-existent TV port */
1811 if (dev->pdev->device == 0x5955 &&
1812 dev->pdev->subsystem_vendor == 0x1462 &&
1813 dev->pdev->subsystem_device == 0x0131)
1819 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1821 struct radeon_device *rdev = dev->dev_private;
1822 uint32_t ext_tmds_info;
1824 if (rdev->flags & RADEON_IS_IGP) {
1826 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1828 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1830 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1831 if (ext_tmds_info) {
1832 uint8_t rev = RBIOS8(ext_tmds_info);
1833 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1836 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1838 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1842 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1844 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1849 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1851 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1854 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1856 struct radeon_device *rdev = dev->dev_private;
1857 uint32_t conn_info, entry, devices;
1858 uint16_t tmp, connector_object_id;
1859 enum radeon_combios_ddc ddc_type;
1860 enum radeon_combios_connector connector;
1862 struct radeon_i2c_bus_rec ddc_i2c;
1863 struct radeon_hpd hpd;
1865 if (rdev->bios == NULL)
1868 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1870 for (i = 0; i < 4; i++) {
1871 entry = conn_info + 2 + i * 2;
1873 if (!RBIOS16(entry))
1876 tmp = RBIOS16(entry);
1878 connector = (tmp >> 12) & 0xf;
1880 ddc_type = (tmp >> 8) & 0xf;
1884 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1888 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1892 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1896 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1902 switch (connector) {
1903 case CONNECTOR_PROPRIETARY_LEGACY:
1904 case CONNECTOR_DVI_I_LEGACY:
1905 case CONNECTOR_DVI_D_LEGACY:
1906 if ((tmp >> 4) & 0x1)
1907 hpd.hpd = RADEON_HPD_2;
1909 hpd.hpd = RADEON_HPD_1;
1912 hpd.hpd = RADEON_HPD_NONE;
1916 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1920 switch (connector) {
1921 case CONNECTOR_PROPRIETARY_LEGACY:
1922 if ((tmp >> 4) & 0x1)
1923 devices = ATOM_DEVICE_DFP2_SUPPORT;
1925 devices = ATOM_DEVICE_DFP1_SUPPORT;
1926 radeon_add_legacy_encoder(dev,
1927 radeon_get_encoder_id
1930 radeon_add_legacy_connector(dev, i, devices,
1931 legacy_connector_convert
1934 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1937 case CONNECTOR_CRT_LEGACY:
1939 devices = ATOM_DEVICE_CRT2_SUPPORT;
1940 radeon_add_legacy_encoder(dev,
1941 radeon_get_encoder_id
1943 ATOM_DEVICE_CRT2_SUPPORT,
1945 ATOM_DEVICE_CRT2_SUPPORT);
1947 devices = ATOM_DEVICE_CRT1_SUPPORT;
1948 radeon_add_legacy_encoder(dev,
1949 radeon_get_encoder_id
1951 ATOM_DEVICE_CRT1_SUPPORT,
1953 ATOM_DEVICE_CRT1_SUPPORT);
1955 radeon_add_legacy_connector(dev,
1958 legacy_connector_convert
1961 CONNECTOR_OBJECT_ID_VGA,
1964 case CONNECTOR_DVI_I_LEGACY:
1967 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1968 radeon_add_legacy_encoder(dev,
1969 radeon_get_encoder_id
1971 ATOM_DEVICE_CRT2_SUPPORT,
1973 ATOM_DEVICE_CRT2_SUPPORT);
1975 devices |= ATOM_DEVICE_CRT1_SUPPORT;
1976 radeon_add_legacy_encoder(dev,
1977 radeon_get_encoder_id
1979 ATOM_DEVICE_CRT1_SUPPORT,
1981 ATOM_DEVICE_CRT1_SUPPORT);
1983 if ((tmp >> 4) & 0x1) {
1984 devices |= ATOM_DEVICE_DFP2_SUPPORT;
1985 radeon_add_legacy_encoder(dev,
1986 radeon_get_encoder_id
1988 ATOM_DEVICE_DFP2_SUPPORT,
1990 ATOM_DEVICE_DFP2_SUPPORT);
1991 connector_object_id = combios_check_dl_dvi(dev, 0);
1993 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1994 radeon_add_legacy_encoder(dev,
1995 radeon_get_encoder_id
1997 ATOM_DEVICE_DFP1_SUPPORT,
1999 ATOM_DEVICE_DFP1_SUPPORT);
2000 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2002 radeon_add_legacy_connector(dev,
2005 legacy_connector_convert
2008 connector_object_id,
2011 case CONNECTOR_DVI_D_LEGACY:
2012 if ((tmp >> 4) & 0x1) {
2013 devices = ATOM_DEVICE_DFP2_SUPPORT;
2014 connector_object_id = combios_check_dl_dvi(dev, 1);
2016 devices = ATOM_DEVICE_DFP1_SUPPORT;
2017 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2019 radeon_add_legacy_encoder(dev,
2020 radeon_get_encoder_id
2023 radeon_add_legacy_connector(dev, i, devices,
2024 legacy_connector_convert
2027 connector_object_id,
2030 case CONNECTOR_CTV_LEGACY:
2031 case CONNECTOR_STV_LEGACY:
2032 radeon_add_legacy_encoder(dev,
2033 radeon_get_encoder_id
2035 ATOM_DEVICE_TV1_SUPPORT,
2037 ATOM_DEVICE_TV1_SUPPORT);
2038 radeon_add_legacy_connector(dev, i,
2039 ATOM_DEVICE_TV1_SUPPORT,
2040 legacy_connector_convert
2043 CONNECTOR_OBJECT_ID_SVIDEO,
2047 DRM_ERROR("Unknown connector type: %d\n",
2054 uint16_t tmds_info =
2055 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2057 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2059 radeon_add_legacy_encoder(dev,
2060 radeon_get_encoder_id(dev,
2061 ATOM_DEVICE_CRT1_SUPPORT,
2063 ATOM_DEVICE_CRT1_SUPPORT);
2064 radeon_add_legacy_encoder(dev,
2065 radeon_get_encoder_id(dev,
2066 ATOM_DEVICE_DFP1_SUPPORT,
2068 ATOM_DEVICE_DFP1_SUPPORT);
2070 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2071 hpd.hpd = RADEON_HPD_NONE;
2072 radeon_add_legacy_connector(dev,
2074 ATOM_DEVICE_CRT1_SUPPORT |
2075 ATOM_DEVICE_DFP1_SUPPORT,
2076 DRM_MODE_CONNECTOR_DVII,
2078 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2082 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2083 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2085 radeon_add_legacy_encoder(dev,
2086 radeon_get_encoder_id(dev,
2087 ATOM_DEVICE_CRT1_SUPPORT,
2089 ATOM_DEVICE_CRT1_SUPPORT);
2090 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2091 hpd.hpd = RADEON_HPD_NONE;
2092 radeon_add_legacy_connector(dev,
2094 ATOM_DEVICE_CRT1_SUPPORT,
2095 DRM_MODE_CONNECTOR_VGA,
2097 CONNECTOR_OBJECT_ID_VGA,
2100 DRM_DEBUG("No connector info found\n");
2106 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2108 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2110 uint16_t lcd_ddc_info =
2111 combios_get_table_offset(dev,
2112 COMBIOS_LCD_DDC_INFO_TABLE);
2114 radeon_add_legacy_encoder(dev,
2115 radeon_get_encoder_id(dev,
2116 ATOM_DEVICE_LCD1_SUPPORT,
2118 ATOM_DEVICE_LCD1_SUPPORT);
2121 ddc_type = RBIOS8(lcd_ddc_info + 2);
2125 combios_setup_i2c_bus
2126 (rdev, RADEON_GPIO_MONID);
2130 combios_setup_i2c_bus
2131 (rdev, RADEON_GPIO_DVI_DDC);
2135 combios_setup_i2c_bus
2136 (rdev, RADEON_GPIO_VGA_DDC);
2140 combios_setup_i2c_bus
2141 (rdev, RADEON_GPIO_CRT2_DDC);
2145 combios_setup_i2c_bus
2146 (rdev, RADEON_GPIOPAD_MASK);
2147 ddc_i2c.mask_clk_mask =
2148 RBIOS32(lcd_ddc_info + 3);
2149 ddc_i2c.mask_data_mask =
2150 RBIOS32(lcd_ddc_info + 7);
2151 ddc_i2c.a_clk_mask =
2152 RBIOS32(lcd_ddc_info + 3);
2153 ddc_i2c.a_data_mask =
2154 RBIOS32(lcd_ddc_info + 7);
2155 ddc_i2c.en_clk_mask =
2156 RBIOS32(lcd_ddc_info + 3);
2157 ddc_i2c.en_data_mask =
2158 RBIOS32(lcd_ddc_info + 7);
2159 ddc_i2c.y_clk_mask =
2160 RBIOS32(lcd_ddc_info + 3);
2161 ddc_i2c.y_data_mask =
2162 RBIOS32(lcd_ddc_info + 7);
2166 combios_setup_i2c_bus
2167 (rdev, RADEON_MDGPIO_MASK);
2168 ddc_i2c.mask_clk_mask =
2169 RBIOS32(lcd_ddc_info + 3);
2170 ddc_i2c.mask_data_mask =
2171 RBIOS32(lcd_ddc_info + 7);
2172 ddc_i2c.a_clk_mask =
2173 RBIOS32(lcd_ddc_info + 3);
2174 ddc_i2c.a_data_mask =
2175 RBIOS32(lcd_ddc_info + 7);
2176 ddc_i2c.en_clk_mask =
2177 RBIOS32(lcd_ddc_info + 3);
2178 ddc_i2c.en_data_mask =
2179 RBIOS32(lcd_ddc_info + 7);
2180 ddc_i2c.y_clk_mask =
2181 RBIOS32(lcd_ddc_info + 3);
2182 ddc_i2c.y_data_mask =
2183 RBIOS32(lcd_ddc_info + 7);
2186 ddc_i2c.valid = false;
2189 DRM_DEBUG("LCD DDC Info Table found!\n");
2191 ddc_i2c.valid = false;
2193 hpd.hpd = RADEON_HPD_NONE;
2194 radeon_add_legacy_connector(dev,
2196 ATOM_DEVICE_LCD1_SUPPORT,
2197 DRM_MODE_CONNECTOR_LVDS,
2199 CONNECTOR_OBJECT_ID_LVDS,
2204 /* check TV table */
2205 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2207 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2209 if (RBIOS8(tv_info + 6) == 'T') {
2210 if (radeon_apply_legacy_tv_quirks(dev)) {
2211 hpd.hpd = RADEON_HPD_NONE;
2212 radeon_add_legacy_encoder(dev,
2213 radeon_get_encoder_id
2215 ATOM_DEVICE_TV1_SUPPORT,
2217 ATOM_DEVICE_TV1_SUPPORT);
2218 radeon_add_legacy_connector(dev, 6,
2219 ATOM_DEVICE_TV1_SUPPORT,
2220 DRM_MODE_CONNECTOR_SVIDEO,
2222 CONNECTOR_OBJECT_ID_SVIDEO,
2229 radeon_link_encoder_connector(dev);
2234 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2237 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2242 switch (tmds->dvo_chip) {
2245 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2246 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2249 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2252 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2255 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2258 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2261 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2264 /* sil 1178 - untested */
2283 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2285 struct drm_device *dev = encoder->dev;
2286 struct radeon_device *rdev = dev->dev_private;
2287 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2289 uint8_t blocks, slave_addr, rev;
2291 uint32_t reg, val, and_mask, or_mask;
2292 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2294 if (rdev->bios == NULL)
2300 if (rdev->flags & RADEON_IS_IGP) {
2301 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2302 rev = RBIOS8(offset);
2304 rev = RBIOS8(offset);
2306 blocks = RBIOS8(offset + 3);
2308 while (blocks > 0) {
2309 id = RBIOS16(index);
2313 reg = (id & 0x1fff) * 4;
2314 val = RBIOS32(index);
2319 reg = (id & 0x1fff) * 4;
2320 and_mask = RBIOS32(index);
2322 or_mask = RBIOS32(index);
2325 val = (val & and_mask) | or_mask;
2329 val = RBIOS16(index);
2334 val = RBIOS16(index);
2339 slave_addr = id & 0xff;
2340 slave_addr >>= 1; /* 7 bit addressing */
2342 reg = RBIOS8(index);
2344 val = RBIOS8(index);
2346 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2347 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2350 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2353 DRM_ERROR("Unknown id %d\n", id >> 13);
2362 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2364 index = offset + 10;
2365 id = RBIOS16(index);
2366 while (id != 0xffff) {
2370 reg = (id & 0x1fff) * 4;
2371 val = RBIOS32(index);
2375 reg = (id & 0x1fff) * 4;
2376 and_mask = RBIOS32(index);
2378 or_mask = RBIOS32(index);
2381 val = (val & and_mask) | or_mask;
2385 val = RBIOS16(index);
2391 and_mask = RBIOS32(index);
2393 or_mask = RBIOS32(index);
2395 val = RREG32_PLL(reg);
2396 val = (val & and_mask) | or_mask;
2397 WREG32_PLL(reg, val);
2401 val = RBIOS8(index);
2403 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2404 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2407 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2410 DRM_ERROR("Unknown id %d\n", id >> 13);
2413 id = RBIOS16(index);
2421 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2423 struct radeon_device *rdev = dev->dev_private;
2426 while (RBIOS16(offset)) {
2427 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2428 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2429 uint32_t val, and_mask, or_mask;
2435 val = RBIOS32(offset);
2440 val = RBIOS32(offset);
2445 and_mask = RBIOS32(offset);
2447 or_mask = RBIOS32(offset);
2455 and_mask = RBIOS32(offset);
2457 or_mask = RBIOS32(offset);
2465 val = RBIOS16(offset);
2470 val = RBIOS16(offset);
2477 (RADEON_CLK_PWRMGT_CNTL) &
2484 if ((RREG32(RADEON_MC_STATUS) &
2500 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2502 struct radeon_device *rdev = dev->dev_private;
2505 while (RBIOS8(offset)) {
2506 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2507 uint8_t addr = (RBIOS8(offset) & 0x3f);
2508 uint32_t val, shift, tmp;
2509 uint32_t and_mask, or_mask;
2514 val = RBIOS32(offset);
2516 WREG32_PLL(addr, val);
2519 shift = RBIOS8(offset) * 8;
2521 and_mask = RBIOS8(offset) << shift;
2522 and_mask |= ~(0xff << shift);
2524 or_mask = RBIOS8(offset) << shift;
2526 tmp = RREG32_PLL(addr);
2529 WREG32_PLL(addr, tmp);
2545 (RADEON_CLK_PWRMGT_CNTL) &
2553 (RADEON_CLK_PWRMGT_CNTL) &
2560 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2561 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2563 uint32_t mclk_cntl =
2566 mclk_cntl &= 0xffff0000;
2567 /*mclk_cntl |= 0x00001111;*//* ??? */
2568 WREG32_PLL(RADEON_MCLK_CNTL,
2573 (RADEON_CLK_PWRMGT_CNTL,
2575 ~RADEON_CG_NO1_DEBUG_0);
2590 static void combios_parse_ram_reset_table(struct drm_device *dev,
2593 struct radeon_device *rdev = dev->dev_private;
2597 uint8_t val = RBIOS8(offset);
2598 while (val != 0xff) {
2602 uint32_t channel_complete_mask;
2604 if (ASIC_IS_R300(rdev))
2605 channel_complete_mask =
2606 R300_MEM_PWRUP_COMPLETE;
2608 channel_complete_mask =
2609 RADEON_MEM_PWRUP_COMPLETE;
2612 if ((RREG32(RADEON_MEM_STR_CNTL) &
2613 channel_complete_mask) ==
2614 channel_complete_mask)
2618 uint32_t or_mask = RBIOS16(offset);
2621 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2622 tmp &= RADEON_SDRAM_MODE_MASK;
2624 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2626 or_mask = val << 24;
2627 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2628 tmp &= RADEON_B3MEM_RESET_MASK;
2630 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2632 val = RBIOS8(offset);
2637 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2638 int mem_addr_mapping)
2640 struct radeon_device *rdev = dev->dev_private;
2645 mem_cntl = RREG32(RADEON_MEM_CNTL);
2646 if (mem_cntl & RV100_HALF_MODE)
2649 mem_cntl &= ~(0xff << 8);
2650 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2651 WREG32(RADEON_MEM_CNTL, mem_cntl);
2652 RREG32(RADEON_MEM_CNTL);
2656 /* something like this???? */
2658 addr = ram * 1024 * 1024;
2659 /* write to each page */
2660 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2661 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2662 /* read back and verify */
2663 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2664 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2671 static void combios_write_ram_size(struct drm_device *dev)
2673 struct radeon_device *rdev = dev->dev_private;
2676 uint32_t mem_size = 0;
2677 uint32_t mem_cntl = 0;
2679 /* should do something smarter here I guess... */
2680 if (rdev->flags & RADEON_IS_IGP)
2683 /* first check detected mem table */
2684 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2686 rev = RBIOS8(offset);
2688 mem_cntl = RBIOS32(offset + 1);
2689 mem_size = RBIOS16(offset + 5);
2690 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2691 ((dev->pdev->device != 0x515e)
2692 && (dev->pdev->device != 0x5969)))
2693 WREG32(RADEON_MEM_CNTL, mem_cntl);
2699 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2701 rev = RBIOS8(offset - 1);
2703 if (((rdev->flags & RADEON_FAMILY_MASK) <
2705 && ((dev->pdev->device != 0x515e)
2706 && (dev->pdev->device != 0x5969))) {
2708 int mem_addr_mapping = 0;
2710 while (RBIOS8(offset)) {
2711 ram = RBIOS8(offset);
2714 if (mem_addr_mapping != 0x25)
2717 combios_detect_ram(dev, ram,
2724 mem_size = RBIOS8(offset);
2726 mem_size = RBIOS8(offset);
2727 mem_size *= 2; /* convert to MB */
2732 mem_size *= (1024 * 1024); /* convert to bytes */
2733 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2736 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2738 uint16_t dyn_clk_info =
2739 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2742 combios_parse_pll_table(dev, dyn_clk_info);
2745 void radeon_combios_asic_init(struct drm_device *dev)
2747 struct radeon_device *rdev = dev->dev_private;
2750 /* port hardcoded mac stuff from radeonfb */
2751 if (rdev->bios == NULL)
2755 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2757 combios_parse_mmio_table(dev, table);
2760 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2762 combios_parse_pll_table(dev, table);
2765 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2767 combios_parse_mmio_table(dev, table);
2769 if (!(rdev->flags & RADEON_IS_IGP)) {
2772 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2774 combios_parse_mmio_table(dev, table);
2777 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2779 combios_parse_ram_reset_table(dev, table);
2783 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2785 combios_parse_mmio_table(dev, table);
2787 /* write CONFIG_MEMSIZE */
2788 combios_write_ram_size(dev);
2792 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2794 combios_parse_pll_table(dev, table);
2798 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2800 struct radeon_device *rdev = dev->dev_private;
2801 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2803 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2804 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2805 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2807 /* let the bios control the backlight */
2808 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2810 /* tell the bios not to handle mode switching */
2811 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2812 RADEON_ACC_MODE_CHANGE);
2814 /* tell the bios a driver is loaded */
2815 bios_7_scratch |= RADEON_DRV_LOADED;
2817 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2818 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2819 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2822 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2824 struct drm_device *dev = encoder->dev;
2825 struct radeon_device *rdev = dev->dev_private;
2826 uint32_t bios_6_scratch;
2828 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2831 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2833 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2835 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2839 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2840 struct drm_encoder *encoder,
2843 struct drm_device *dev = connector->dev;
2844 struct radeon_device *rdev = dev->dev_private;
2845 struct radeon_connector *radeon_connector =
2846 to_radeon_connector(connector);
2847 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2848 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2849 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2851 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2852 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2854 DRM_DEBUG("TV1 connected\n");
2856 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2857 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2858 bios_5_scratch |= RADEON_TV1_ON;
2859 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2861 DRM_DEBUG("TV1 disconnected\n");
2862 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2863 bios_5_scratch &= ~RADEON_TV1_ON;
2864 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2867 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2868 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2870 DRM_DEBUG("LCD1 connected\n");
2871 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2872 bios_5_scratch |= RADEON_LCD1_ON;
2873 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2875 DRM_DEBUG("LCD1 disconnected\n");
2876 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2877 bios_5_scratch &= ~RADEON_LCD1_ON;
2878 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2881 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2882 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2884 DRM_DEBUG("CRT1 connected\n");
2885 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2886 bios_5_scratch |= RADEON_CRT1_ON;
2887 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2889 DRM_DEBUG("CRT1 disconnected\n");
2890 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2891 bios_5_scratch &= ~RADEON_CRT1_ON;
2892 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2895 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2896 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2898 DRM_DEBUG("CRT2 connected\n");
2899 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2900 bios_5_scratch |= RADEON_CRT2_ON;
2901 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2903 DRM_DEBUG("CRT2 disconnected\n");
2904 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2905 bios_5_scratch &= ~RADEON_CRT2_ON;
2906 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2909 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2910 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2912 DRM_DEBUG("DFP1 connected\n");
2913 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2914 bios_5_scratch |= RADEON_DFP1_ON;
2915 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2917 DRM_DEBUG("DFP1 disconnected\n");
2918 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2919 bios_5_scratch &= ~RADEON_DFP1_ON;
2920 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2923 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2924 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2926 DRM_DEBUG("DFP2 connected\n");
2927 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2928 bios_5_scratch |= RADEON_DFP2_ON;
2929 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2931 DRM_DEBUG("DFP2 disconnected\n");
2932 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2933 bios_5_scratch &= ~RADEON_DFP2_ON;
2934 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2937 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2938 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2942 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2944 struct drm_device *dev = encoder->dev;
2945 struct radeon_device *rdev = dev->dev_private;
2946 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2947 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2949 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2950 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2951 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2953 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2954 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2955 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2957 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2958 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2959 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2961 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2962 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2963 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2965 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2966 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2967 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2969 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2970 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2971 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2973 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2977 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2979 struct drm_device *dev = encoder->dev;
2980 struct radeon_device *rdev = dev->dev_private;
2981 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2982 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2984 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2986 bios_6_scratch |= RADEON_TV_DPMS_ON;
2988 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2990 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2992 bios_6_scratch |= RADEON_CRT_DPMS_ON;
2994 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2996 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2998 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3000 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3002 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3004 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3006 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3008 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);