2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
114 enum radeon_combios_ddc {
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
149 struct radeon_device *rdev = dev->dev_private;
151 uint16_t offset = 0, check_offset;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
161 offset = check_offset;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
166 offset = check_offset;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
171 offset = check_offset;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
176 offset = check_offset;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
181 offset = check_offset;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
186 offset = check_offset;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
191 offset = check_offset;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
196 offset = check_offset;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
201 offset = check_offset;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
206 offset = check_offset;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
211 offset = check_offset;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
216 offset = check_offset;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
221 offset = check_offset;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
226 offset = check_offset;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
231 offset = check_offset;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
236 offset = check_offset;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
241 offset = check_offset;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
246 offset = check_offset;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
251 offset = check_offset;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
256 offset = check_offset;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
261 offset = check_offset;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
266 offset = check_offset;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
271 offset = check_offset;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
276 offset = check_offset;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
281 offset = check_offset;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
286 offset = check_offset;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
291 offset = check_offset;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
296 offset = check_offset;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
301 offset = check_offset;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
306 offset = check_offset;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
311 offset = check_offset;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
316 offset = check_offset;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
321 offset = check_offset;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
326 offset = check_offset;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
333 rev = RBIOS8(check_offset);
335 check_offset = RBIOS16(check_offset + 0x3);
337 offset = check_offset;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
345 rev = RBIOS8(check_offset);
347 check_offset = RBIOS16(check_offset + 0x5);
349 offset = check_offset;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
357 rev = RBIOS8(check_offset);
359 check_offset = RBIOS16(check_offset + 0x7);
361 offset = check_offset;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
369 rev = RBIOS8(check_offset);
371 check_offset = RBIOS16(check_offset + 0x9);
373 offset = check_offset;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
381 while (RBIOS8(check_offset++));
384 offset = check_offset;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
391 check_offset = RBIOS16(check_offset + 0x11);
393 offset = check_offset;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
400 check_offset = RBIOS16(check_offset + 0x13);
402 offset = check_offset;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
409 check_offset = RBIOS16(check_offset + 0x15);
411 offset = check_offset;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
418 check_offset = RBIOS16(check_offset + 0x17);
420 offset = check_offset;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
427 check_offset = RBIOS16(check_offset + 0x2);
429 offset = check_offset;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
436 check_offset = RBIOS16(check_offset + 0x4);
438 offset = check_offset;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
465 if (!drm_edid_is_valid(edid)) {
470 rdev->mode_info.bios_hardcoded_edid = edid;
475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 enum radeon_combios_ddc ddc,
487 struct radeon_i2c_bus_rec i2c;
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
507 case DDC_NONE_DETECTED:
512 ddc_line = RADEON_GPIO_DVI_DDC;
515 ddc_line = RADEON_GPIO_VGA_DDC;
518 ddc_line = RADEON_GPIOPAD_MASK;
521 ddc_line = RADEON_MDGPIO_MASK;
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
529 ddc_line = RADEON_GPIO_MONID;
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
540 ddc_line = RADEON_GPIO_CRT2_DDC;
544 if (ddc_line == RADEON_GPIOPAD_MASK) {
545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
546 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
547 i2c.a_clk_reg = RADEON_GPIOPAD_A;
548 i2c.a_data_reg = RADEON_GPIOPAD_A;
549 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
550 i2c.en_data_reg = RADEON_GPIOPAD_EN;
551 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
552 i2c.y_data_reg = RADEON_GPIOPAD_Y;
553 } else if (ddc_line == RADEON_MDGPIO_MASK) {
554 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
555 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
556 i2c.a_clk_reg = RADEON_MDGPIO_A;
557 i2c.a_data_reg = RADEON_MDGPIO_A;
558 i2c.en_clk_reg = RADEON_MDGPIO_EN;
559 i2c.en_data_reg = RADEON_MDGPIO_EN;
560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
561 i2c.y_data_reg = RADEON_MDGPIO_Y;
563 i2c.mask_clk_reg = ddc_line;
564 i2c.mask_data_reg = ddc_line;
565 i2c.a_clk_reg = ddc_line;
566 i2c.a_data_reg = ddc_line;
567 i2c.en_clk_reg = ddc_line;
568 i2c.en_data_reg = ddc_line;
569 i2c.y_clk_reg = ddc_line;
570 i2c.y_data_reg = ddc_line;
573 if (clk_mask && data_mask) {
574 /* system specific masks */
575 i2c.mask_clk_mask = clk_mask;
576 i2c.mask_data_mask = data_mask;
577 i2c.a_clk_mask = clk_mask;
578 i2c.a_data_mask = data_mask;
579 i2c.en_clk_mask = clk_mask;
580 i2c.en_data_mask = data_mask;
581 i2c.y_clk_mask = clk_mask;
582 i2c.y_data_mask = data_mask;
583 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
584 (ddc_line == RADEON_MDGPIO_MASK)) {
585 /* default gpiopad masks */
586 i2c.mask_clk_mask = (0x20 << 8);
587 i2c.mask_data_mask = 0x80;
588 i2c.a_clk_mask = (0x20 << 8);
589 i2c.a_data_mask = 0x80;
590 i2c.en_clk_mask = (0x20 << 8);
591 i2c.en_data_mask = 0x80;
592 i2c.y_clk_mask = (0x20 << 8);
593 i2c.y_data_mask = 0x80;
595 /* default masks for ddc pads */
596 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
597 i2c.mask_data_mask = RADEON_GPIO_EN_0;
598 i2c.a_clk_mask = RADEON_GPIO_A_1;
599 i2c.a_data_mask = RADEON_GPIO_A_0;
600 i2c.en_clk_mask = RADEON_GPIO_EN_1;
601 i2c.en_data_mask = RADEON_GPIO_EN_0;
602 i2c.y_clk_mask = RADEON_GPIO_Y_1;
603 i2c.y_data_mask = RADEON_GPIO_Y_0;
606 switch (rdev->family) {
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
618 i2c.hw_capable = false;
624 case RADEON_GPIO_DVI_DDC:
625 case RADEON_GPIO_MONID:
626 i2c.hw_capable = true;
629 i2c.hw_capable = false;
636 case RADEON_GPIO_VGA_DDC:
637 case RADEON_GPIO_DVI_DDC:
638 case RADEON_GPIO_CRT2_DDC:
639 i2c.hw_capable = true;
642 i2c.hw_capable = false;
649 case RADEON_GPIO_VGA_DDC:
650 case RADEON_GPIO_DVI_DDC:
651 i2c.hw_capable = true;
654 i2c.hw_capable = false;
663 case RADEON_GPIO_VGA_DDC:
664 case RADEON_GPIO_DVI_DDC:
665 i2c.hw_capable = true;
667 case RADEON_GPIO_MONID:
668 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
669 * reliably on some pre-r4xx hardware; not sure why.
671 i2c.hw_capable = false;
674 i2c.hw_capable = false;
679 i2c.hw_capable = false;
685 i2c.hpd = RADEON_HPD_NONE;
695 void radeon_combios_i2c_init(struct radeon_device *rdev)
697 struct drm_device *dev = rdev->ddev;
698 struct radeon_i2c_bus_rec i2c;
701 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
702 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
704 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
705 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
708 i2c.hw_capable = true;
711 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
713 if (rdev->family == CHIP_RS300 ||
714 rdev->family == CHIP_RS400 ||
715 rdev->family == CHIP_RS480) {
717 u8 id, blocks, clk, data;
720 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
721 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
723 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
725 blocks = RBIOS8(offset + 2);
726 for (i = 0; i < blocks; i++) {
727 id = RBIOS8(offset + 3 + (i * 5) + 0);
729 clk = RBIOS8(offset + 3 + (i * 5) + 3);
730 data = RBIOS8(offset + 3 + (i * 5) + 4);
731 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
739 } else if (rdev->family >= CHIP_R300) {
740 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
741 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
743 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
744 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
746 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
747 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
751 bool radeon_combios_get_clock_info(struct drm_device *dev)
753 struct radeon_device *rdev = dev->dev_private;
755 struct radeon_pll *p1pll = &rdev->clock.p1pll;
756 struct radeon_pll *p2pll = &rdev->clock.p2pll;
757 struct radeon_pll *spll = &rdev->clock.spll;
758 struct radeon_pll *mpll = &rdev->clock.mpll;
762 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
764 rev = RBIOS8(pll_info);
767 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
768 p1pll->reference_div = RBIOS16(pll_info + 0x10);
769 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
770 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
771 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
772 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
775 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
776 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
778 p1pll->pll_in_min = 40;
779 p1pll->pll_in_max = 500;
784 spll->reference_freq = RBIOS16(pll_info + 0x1a);
785 spll->reference_div = RBIOS16(pll_info + 0x1c);
786 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
787 spll->pll_out_max = RBIOS32(pll_info + 0x22);
790 spll->pll_in_min = RBIOS32(pll_info + 0x48);
791 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
794 spll->pll_in_min = 40;
795 spll->pll_in_max = 500;
799 mpll->reference_freq = RBIOS16(pll_info + 0x26);
800 mpll->reference_div = RBIOS16(pll_info + 0x28);
801 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
802 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
805 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
806 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
809 mpll->pll_in_min = 40;
810 mpll->pll_in_max = 500;
813 /* default sclk/mclk */
814 sclk = RBIOS16(pll_info + 0xa);
815 mclk = RBIOS16(pll_info + 0x8);
821 rdev->clock.default_sclk = sclk;
822 rdev->clock.default_mclk = mclk;
829 bool radeon_combios_sideport_present(struct radeon_device *rdev)
831 struct drm_device *dev = rdev->ddev;
834 /* sideport is AMD only */
835 if (rdev->family == CHIP_RS400)
838 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
841 if (RBIOS16(igp_info + 0x4))
847 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
848 0x00000808, /* r100 */
849 0x00000808, /* rv100 */
850 0x00000808, /* rs100 */
851 0x00000808, /* rv200 */
852 0x00000808, /* rs200 */
853 0x00000808, /* r200 */
854 0x00000808, /* rv250 */
855 0x00000000, /* rs300 */
856 0x00000808, /* rv280 */
857 0x00000808, /* r300 */
858 0x00000808, /* r350 */
859 0x00000808, /* rv350 */
860 0x00000808, /* rv380 */
861 0x00000808, /* r420 */
862 0x00000808, /* r423 */
863 0x00000808, /* rv410 */
864 0x00000000, /* rs400 */
865 0x00000000, /* rs480 */
868 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
869 struct radeon_encoder_primary_dac *p_dac)
871 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
875 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
879 struct drm_device *dev = encoder->base.dev;
880 struct radeon_device *rdev = dev->dev_private;
882 uint8_t rev, bg, dac;
883 struct radeon_encoder_primary_dac *p_dac = NULL;
886 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
892 /* check CRT table */
893 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
895 rev = RBIOS8(dac_info) & 0x3;
897 bg = RBIOS8(dac_info + 0x2) & 0xf;
898 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
899 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
901 bg = RBIOS8(dac_info + 0x2) & 0xf;
902 dac = RBIOS8(dac_info + 0x3) & 0xf;
903 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
905 /* if the values are all zeros, use the table */
906 if (p_dac->ps2_pdac_adj)
910 if (!found) /* fallback to defaults */
911 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
917 radeon_combios_get_tv_info(struct radeon_device *rdev)
919 struct drm_device *dev = rdev->ddev;
921 enum radeon_tv_std tv_std = TV_STD_NTSC;
923 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
925 if (RBIOS8(tv_info + 6) == 'T') {
926 switch (RBIOS8(tv_info + 7) & 0xf) {
928 tv_std = TV_STD_NTSC;
929 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
933 DRM_DEBUG_KMS("Default TV standard: PAL\n");
936 tv_std = TV_STD_PAL_M;
937 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
940 tv_std = TV_STD_PAL_60;
941 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
944 tv_std = TV_STD_NTSC_J;
945 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
948 tv_std = TV_STD_SCART_PAL;
949 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
952 tv_std = TV_STD_NTSC;
954 ("Unknown TV standard; defaulting to NTSC\n");
958 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
960 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
963 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
966 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
969 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
979 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
980 0x00000000, /* r100 */
981 0x00280000, /* rv100 */
982 0x00000000, /* rs100 */
983 0x00880000, /* rv200 */
984 0x00000000, /* rs200 */
985 0x00000000, /* r200 */
986 0x00770000, /* rv250 */
987 0x00290000, /* rs300 */
988 0x00560000, /* rv280 */
989 0x00780000, /* r300 */
990 0x00770000, /* r350 */
991 0x00780000, /* rv350 */
992 0x00780000, /* rv380 */
993 0x01080000, /* r420 */
994 0x01080000, /* r423 */
995 0x01080000, /* rv410 */
996 0x00780000, /* rs400 */
997 0x00780000, /* rs480 */
1000 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1001 struct radeon_encoder_tv_dac *tv_dac)
1003 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1004 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1005 tv_dac->ps2_tvdac_adj = 0x00880000;
1006 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1007 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1011 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1015 struct drm_device *dev = encoder->base.dev;
1016 struct radeon_device *rdev = dev->dev_private;
1018 uint8_t rev, bg, dac;
1019 struct radeon_encoder_tv_dac *tv_dac = NULL;
1022 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1026 /* first check TV table */
1027 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1029 rev = RBIOS8(dac_info + 0x3);
1031 bg = RBIOS8(dac_info + 0xc) & 0xf;
1032 dac = RBIOS8(dac_info + 0xd) & 0xf;
1033 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1035 bg = RBIOS8(dac_info + 0xe) & 0xf;
1036 dac = RBIOS8(dac_info + 0xf) & 0xf;
1037 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1039 bg = RBIOS8(dac_info + 0x10) & 0xf;
1040 dac = RBIOS8(dac_info + 0x11) & 0xf;
1041 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1042 /* if the values are all zeros, use the table */
1043 if (tv_dac->ps2_tvdac_adj)
1045 } else if (rev > 1) {
1046 bg = RBIOS8(dac_info + 0xc) & 0xf;
1047 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1048 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1050 bg = RBIOS8(dac_info + 0xd) & 0xf;
1051 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1052 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1054 bg = RBIOS8(dac_info + 0xe) & 0xf;
1055 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1056 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1057 /* if the values are all zeros, use the table */
1058 if (tv_dac->ps2_tvdac_adj)
1061 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1064 /* then check CRT table */
1066 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1068 rev = RBIOS8(dac_info) & 0x3;
1070 bg = RBIOS8(dac_info + 0x3) & 0xf;
1071 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1072 tv_dac->ps2_tvdac_adj =
1073 (bg << 16) | (dac << 20);
1074 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1075 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1076 /* if the values are all zeros, use the table */
1077 if (tv_dac->ps2_tvdac_adj)
1080 bg = RBIOS8(dac_info + 0x4) & 0xf;
1081 dac = RBIOS8(dac_info + 0x5) & 0xf;
1082 tv_dac->ps2_tvdac_adj =
1083 (bg << 16) | (dac << 20);
1084 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1085 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086 /* if the values are all zeros, use the table */
1087 if (tv_dac->ps2_tvdac_adj)
1091 DRM_INFO("No TV DAC info found in BIOS\n");
1095 if (!found) /* fallback to defaults */
1096 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1101 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1105 struct radeon_encoder_lvds *lvds = NULL;
1106 uint32_t fp_vert_stretch, fp_horz_stretch;
1107 uint32_t ppll_div_sel, ppll_val;
1108 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1110 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1115 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1116 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1118 /* These should be fail-safe defaults, fingers crossed */
1119 lvds->panel_pwr_delay = 200;
1120 lvds->panel_vcc_delay = 2000;
1122 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1123 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1124 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1126 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1127 lvds->native_mode.vdisplay =
1128 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1129 RADEON_VERT_PANEL_SHIFT) + 1;
1131 lvds->native_mode.vdisplay =
1132 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1134 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1135 lvds->native_mode.hdisplay =
1136 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1137 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1139 lvds->native_mode.hdisplay =
1140 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1142 if ((lvds->native_mode.hdisplay < 640) ||
1143 (lvds->native_mode.vdisplay < 480)) {
1144 lvds->native_mode.hdisplay = 640;
1145 lvds->native_mode.vdisplay = 480;
1148 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1149 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1150 if ((ppll_val & 0x000707ff) == 0x1bb)
1151 lvds->use_bios_dividers = false;
1153 lvds->panel_ref_divider =
1154 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1155 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1156 lvds->panel_fb_divider = ppll_val & 0x7ff;
1158 if ((lvds->panel_ref_divider != 0) &&
1159 (lvds->panel_fb_divider > 3))
1160 lvds->use_bios_dividers = true;
1162 lvds->panel_vcc_delay = 200;
1164 DRM_INFO("Panel info derived from registers\n");
1165 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1166 lvds->native_mode.vdisplay);
1171 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1174 struct drm_device *dev = encoder->base.dev;
1175 struct radeon_device *rdev = dev->dev_private;
1177 uint32_t panel_setup;
1180 struct radeon_encoder_lvds *lvds = NULL;
1182 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1185 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1190 for (i = 0; i < 24; i++)
1191 stmp[i] = RBIOS8(lcd_info + i + 1);
1194 DRM_INFO("Panel ID String: %s\n", stmp);
1196 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1197 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1199 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1200 lvds->native_mode.vdisplay);
1202 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1203 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1205 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1206 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1207 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1209 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1210 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1211 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1212 if ((lvds->panel_ref_divider != 0) &&
1213 (lvds->panel_fb_divider > 3))
1214 lvds->use_bios_dividers = true;
1216 panel_setup = RBIOS32(lcd_info + 0x39);
1217 lvds->lvds_gen_cntl = 0xff00;
1218 if (panel_setup & 0x1)
1219 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1221 if ((panel_setup >> 4) & 0x1)
1222 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1224 switch ((panel_setup >> 8) & 0x7) {
1226 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1232 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1238 if ((panel_setup >> 16) & 0x1)
1239 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1241 if ((panel_setup >> 17) & 0x1)
1242 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1244 if ((panel_setup >> 18) & 0x1)
1245 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1247 if ((panel_setup >> 23) & 0x1)
1248 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1250 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1252 for (i = 0; i < 32; i++) {
1253 tmp = RBIOS16(lcd_info + 64 + i * 2);
1257 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1258 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1259 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1260 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1261 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1262 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1263 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1264 (RBIOS8(tmp + 23) * 8);
1266 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1267 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1268 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1269 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1270 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1271 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1273 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1274 lvds->native_mode.flags = 0;
1275 /* set crtc values */
1276 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1281 DRM_INFO("No panel info found in BIOS\n");
1282 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1286 encoder->native_mode = lvds->native_mode;
1290 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1293 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1294 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1296 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1297 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1298 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1299 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1311 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1312 struct radeon_encoder_int_tmds *tmds)
1314 struct drm_device *dev = encoder->base.dev;
1315 struct radeon_device *rdev = dev->dev_private;
1318 for (i = 0; i < 4; i++) {
1319 tmds->tmds_pll[i].value =
1320 default_tmds_pll[rdev->family][i].value;
1321 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1327 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1328 struct radeon_encoder_int_tmds *tmds)
1330 struct drm_device *dev = encoder->base.dev;
1331 struct radeon_device *rdev = dev->dev_private;
1336 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1339 ver = RBIOS8(tmds_info);
1340 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1342 n = RBIOS8(tmds_info + 5) + 1;
1345 for (i = 0; i < n; i++) {
1346 tmds->tmds_pll[i].value =
1347 RBIOS32(tmds_info + i * 10 + 0x08);
1348 tmds->tmds_pll[i].freq =
1349 RBIOS16(tmds_info + i * 10 + 0x10);
1350 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1351 tmds->tmds_pll[i].freq,
1352 tmds->tmds_pll[i].value);
1354 } else if (ver == 4) {
1356 n = RBIOS8(tmds_info + 5) + 1;
1359 for (i = 0; i < n; i++) {
1360 tmds->tmds_pll[i].value =
1361 RBIOS32(tmds_info + stride + 0x08);
1362 tmds->tmds_pll[i].freq =
1363 RBIOS16(tmds_info + stride + 0x10);
1368 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1369 tmds->tmds_pll[i].freq,
1370 tmds->tmds_pll[i].value);
1374 DRM_INFO("No TMDS info found in BIOS\n");
1380 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1381 struct radeon_encoder_ext_tmds *tmds)
1383 struct drm_device *dev = encoder->base.dev;
1384 struct radeon_device *rdev = dev->dev_private;
1385 struct radeon_i2c_bus_rec i2c_bus;
1387 /* default for macs */
1388 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1389 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1391 /* XXX some macs have duallink chips */
1392 switch (rdev->mode_info.connector_table) {
1393 case CT_POWERBOOK_EXTERNAL:
1394 case CT_MINI_EXTERNAL:
1396 tmds->dvo_chip = DVO_SIL164;
1397 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1404 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1405 struct radeon_encoder_ext_tmds *tmds)
1407 struct drm_device *dev = encoder->base.dev;
1408 struct radeon_device *rdev = dev->dev_private;
1411 enum radeon_combios_ddc gpio;
1412 struct radeon_i2c_bus_rec i2c_bus;
1414 tmds->i2c_bus = NULL;
1415 if (rdev->flags & RADEON_IS_IGP) {
1416 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1417 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1418 tmds->dvo_chip = DVO_SIL164;
1419 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1421 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1423 ver = RBIOS8(offset);
1424 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1425 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1426 tmds->slave_addr >>= 1; /* 7 bit addressing */
1427 gpio = RBIOS8(offset + 4 + 3);
1428 if (gpio == DDC_LCD) {
1430 i2c_bus.valid = true;
1431 i2c_bus.hw_capable = true;
1432 i2c_bus.mm_i2c = true;
1433 i2c_bus.i2c_id = 0xa0;
1435 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1436 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440 if (!tmds->i2c_bus) {
1441 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1448 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1450 struct radeon_device *rdev = dev->dev_private;
1451 struct radeon_i2c_bus_rec ddc_i2c;
1452 struct radeon_hpd hpd;
1454 rdev->mode_info.connector_table = radeon_connector_table;
1455 if (rdev->mode_info.connector_table == CT_NONE) {
1456 #ifdef CONFIG_PPC_PMAC
1457 if (of_machine_is_compatible("PowerBook3,3")) {
1458 /* powerbook with VGA */
1459 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1460 } else if (of_machine_is_compatible("PowerBook3,4") ||
1461 of_machine_is_compatible("PowerBook3,5")) {
1462 /* powerbook with internal tmds */
1463 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1464 } else if (of_machine_is_compatible("PowerBook5,1") ||
1465 of_machine_is_compatible("PowerBook5,2") ||
1466 of_machine_is_compatible("PowerBook5,3") ||
1467 of_machine_is_compatible("PowerBook5,4") ||
1468 of_machine_is_compatible("PowerBook5,5")) {
1469 /* powerbook with external single link tmds (sil164) */
1470 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1471 } else if (of_machine_is_compatible("PowerBook5,6")) {
1472 /* powerbook with external dual or single link tmds */
1473 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1474 } else if (of_machine_is_compatible("PowerBook5,7") ||
1475 of_machine_is_compatible("PowerBook5,8") ||
1476 of_machine_is_compatible("PowerBook5,9")) {
1477 /* PowerBook6,2 ? */
1478 /* powerbook with external dual link tmds (sil1178?) */
1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1480 } else if (of_machine_is_compatible("PowerBook4,1") ||
1481 of_machine_is_compatible("PowerBook4,2") ||
1482 of_machine_is_compatible("PowerBook4,3") ||
1483 of_machine_is_compatible("PowerBook6,3") ||
1484 of_machine_is_compatible("PowerBook6,5") ||
1485 of_machine_is_compatible("PowerBook6,7")) {
1487 rdev->mode_info.connector_table = CT_IBOOK;
1488 } else if (of_machine_is_compatible("PowerMac4,4")) {
1490 rdev->mode_info.connector_table = CT_EMAC;
1491 } else if (of_machine_is_compatible("PowerMac10,1")) {
1492 /* mini with internal tmds */
1493 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1494 } else if (of_machine_is_compatible("PowerMac10,2")) {
1495 /* mini with external tmds */
1496 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1497 } else if (of_machine_is_compatible("PowerMac12,1")) {
1499 /* imac g5 isight */
1500 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1501 } else if ((rdev->pdev->device == 0x4a48) &&
1502 (rdev->pdev->subsystem_vendor == 0x1002) &&
1503 (rdev->pdev->subsystem_device == 0x4a48)) {
1505 rdev->mode_info.connector_table = CT_MAC_X800;
1507 #endif /* CONFIG_PPC_PMAC */
1509 if (ASIC_IS_RN50(rdev))
1510 rdev->mode_info.connector_table = CT_RN50_POWER;
1513 rdev->mode_info.connector_table = CT_GENERIC;
1516 switch (rdev->mode_info.connector_table) {
1518 DRM_INFO("Connector Table: %d (generic)\n",
1519 rdev->mode_info.connector_table);
1520 /* these are the most common settings */
1521 if (rdev->flags & RADEON_SINGLE_CRTC) {
1522 /* VGA - primary dac */
1523 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1524 hpd.hpd = RADEON_HPD_NONE;
1525 radeon_add_legacy_encoder(dev,
1526 radeon_get_encoder_enum(dev,
1527 ATOM_DEVICE_CRT1_SUPPORT,
1529 ATOM_DEVICE_CRT1_SUPPORT);
1530 radeon_add_legacy_connector(dev, 0,
1531 ATOM_DEVICE_CRT1_SUPPORT,
1532 DRM_MODE_CONNECTOR_VGA,
1534 CONNECTOR_OBJECT_ID_VGA,
1536 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1538 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1539 hpd.hpd = RADEON_HPD_NONE;
1540 radeon_add_legacy_encoder(dev,
1541 radeon_get_encoder_enum(dev,
1542 ATOM_DEVICE_LCD1_SUPPORT,
1544 ATOM_DEVICE_LCD1_SUPPORT);
1545 radeon_add_legacy_connector(dev, 0,
1546 ATOM_DEVICE_LCD1_SUPPORT,
1547 DRM_MODE_CONNECTOR_LVDS,
1549 CONNECTOR_OBJECT_ID_LVDS,
1552 /* VGA - primary dac */
1553 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1554 hpd.hpd = RADEON_HPD_NONE;
1555 radeon_add_legacy_encoder(dev,
1556 radeon_get_encoder_enum(dev,
1557 ATOM_DEVICE_CRT1_SUPPORT,
1559 ATOM_DEVICE_CRT1_SUPPORT);
1560 radeon_add_legacy_connector(dev, 1,
1561 ATOM_DEVICE_CRT1_SUPPORT,
1562 DRM_MODE_CONNECTOR_VGA,
1564 CONNECTOR_OBJECT_ID_VGA,
1567 /* DVI-I - tv dac, int tmds */
1568 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1569 hpd.hpd = RADEON_HPD_1;
1570 radeon_add_legacy_encoder(dev,
1571 radeon_get_encoder_enum(dev,
1572 ATOM_DEVICE_DFP1_SUPPORT,
1574 ATOM_DEVICE_DFP1_SUPPORT);
1575 radeon_add_legacy_encoder(dev,
1576 radeon_get_encoder_enum(dev,
1577 ATOM_DEVICE_CRT2_SUPPORT,
1579 ATOM_DEVICE_CRT2_SUPPORT);
1580 radeon_add_legacy_connector(dev, 0,
1581 ATOM_DEVICE_DFP1_SUPPORT |
1582 ATOM_DEVICE_CRT2_SUPPORT,
1583 DRM_MODE_CONNECTOR_DVII,
1585 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1588 /* VGA - primary dac */
1589 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1590 hpd.hpd = RADEON_HPD_NONE;
1591 radeon_add_legacy_encoder(dev,
1592 radeon_get_encoder_enum(dev,
1593 ATOM_DEVICE_CRT1_SUPPORT,
1595 ATOM_DEVICE_CRT1_SUPPORT);
1596 radeon_add_legacy_connector(dev, 1,
1597 ATOM_DEVICE_CRT1_SUPPORT,
1598 DRM_MODE_CONNECTOR_VGA,
1600 CONNECTOR_OBJECT_ID_VGA,
1604 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1606 ddc_i2c.valid = false;
1607 hpd.hpd = RADEON_HPD_NONE;
1608 radeon_add_legacy_encoder(dev,
1609 radeon_get_encoder_enum(dev,
1610 ATOM_DEVICE_TV1_SUPPORT,
1612 ATOM_DEVICE_TV1_SUPPORT);
1613 radeon_add_legacy_connector(dev, 2,
1614 ATOM_DEVICE_TV1_SUPPORT,
1615 DRM_MODE_CONNECTOR_SVIDEO,
1617 CONNECTOR_OBJECT_ID_SVIDEO,
1622 DRM_INFO("Connector Table: %d (ibook)\n",
1623 rdev->mode_info.connector_table);
1625 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1626 hpd.hpd = RADEON_HPD_NONE;
1627 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_enum(dev,
1629 ATOM_DEVICE_LCD1_SUPPORT,
1631 ATOM_DEVICE_LCD1_SUPPORT);
1632 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1633 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1634 CONNECTOR_OBJECT_ID_LVDS,
1637 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1638 hpd.hpd = RADEON_HPD_NONE;
1639 radeon_add_legacy_encoder(dev,
1640 radeon_get_encoder_enum(dev,
1641 ATOM_DEVICE_CRT2_SUPPORT,
1643 ATOM_DEVICE_CRT2_SUPPORT);
1644 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1645 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1646 CONNECTOR_OBJECT_ID_VGA,
1649 ddc_i2c.valid = false;
1650 hpd.hpd = RADEON_HPD_NONE;
1651 radeon_add_legacy_encoder(dev,
1652 radeon_get_encoder_enum(dev,
1653 ATOM_DEVICE_TV1_SUPPORT,
1655 ATOM_DEVICE_TV1_SUPPORT);
1656 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1657 DRM_MODE_CONNECTOR_SVIDEO,
1659 CONNECTOR_OBJECT_ID_SVIDEO,
1662 case CT_POWERBOOK_EXTERNAL:
1663 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1664 rdev->mode_info.connector_table);
1666 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1667 hpd.hpd = RADEON_HPD_NONE;
1668 radeon_add_legacy_encoder(dev,
1669 radeon_get_encoder_enum(dev,
1670 ATOM_DEVICE_LCD1_SUPPORT,
1672 ATOM_DEVICE_LCD1_SUPPORT);
1673 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1674 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1675 CONNECTOR_OBJECT_ID_LVDS,
1677 /* DVI-I - primary dac, ext tmds */
1678 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1679 hpd.hpd = RADEON_HPD_2; /* ??? */
1680 radeon_add_legacy_encoder(dev,
1681 radeon_get_encoder_enum(dev,
1682 ATOM_DEVICE_DFP2_SUPPORT,
1684 ATOM_DEVICE_DFP2_SUPPORT);
1685 radeon_add_legacy_encoder(dev,
1686 radeon_get_encoder_enum(dev,
1687 ATOM_DEVICE_CRT1_SUPPORT,
1689 ATOM_DEVICE_CRT1_SUPPORT);
1690 /* XXX some are SL */
1691 radeon_add_legacy_connector(dev, 1,
1692 ATOM_DEVICE_DFP2_SUPPORT |
1693 ATOM_DEVICE_CRT1_SUPPORT,
1694 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1695 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1698 ddc_i2c.valid = false;
1699 hpd.hpd = RADEON_HPD_NONE;
1700 radeon_add_legacy_encoder(dev,
1701 radeon_get_encoder_enum(dev,
1702 ATOM_DEVICE_TV1_SUPPORT,
1704 ATOM_DEVICE_TV1_SUPPORT);
1705 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1706 DRM_MODE_CONNECTOR_SVIDEO,
1708 CONNECTOR_OBJECT_ID_SVIDEO,
1711 case CT_POWERBOOK_INTERNAL:
1712 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1713 rdev->mode_info.connector_table);
1715 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1716 hpd.hpd = RADEON_HPD_NONE;
1717 radeon_add_legacy_encoder(dev,
1718 radeon_get_encoder_enum(dev,
1719 ATOM_DEVICE_LCD1_SUPPORT,
1721 ATOM_DEVICE_LCD1_SUPPORT);
1722 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1723 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1724 CONNECTOR_OBJECT_ID_LVDS,
1726 /* DVI-I - primary dac, int tmds */
1727 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1728 hpd.hpd = RADEON_HPD_1; /* ??? */
1729 radeon_add_legacy_encoder(dev,
1730 radeon_get_encoder_enum(dev,
1731 ATOM_DEVICE_DFP1_SUPPORT,
1733 ATOM_DEVICE_DFP1_SUPPORT);
1734 radeon_add_legacy_encoder(dev,
1735 radeon_get_encoder_enum(dev,
1736 ATOM_DEVICE_CRT1_SUPPORT,
1738 ATOM_DEVICE_CRT1_SUPPORT);
1739 radeon_add_legacy_connector(dev, 1,
1740 ATOM_DEVICE_DFP1_SUPPORT |
1741 ATOM_DEVICE_CRT1_SUPPORT,
1742 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1743 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1746 ddc_i2c.valid = false;
1747 hpd.hpd = RADEON_HPD_NONE;
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_enum(dev,
1750 ATOM_DEVICE_TV1_SUPPORT,
1752 ATOM_DEVICE_TV1_SUPPORT);
1753 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1754 DRM_MODE_CONNECTOR_SVIDEO,
1756 CONNECTOR_OBJECT_ID_SVIDEO,
1759 case CT_POWERBOOK_VGA:
1760 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1761 rdev->mode_info.connector_table);
1763 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1764 hpd.hpd = RADEON_HPD_NONE;
1765 radeon_add_legacy_encoder(dev,
1766 radeon_get_encoder_enum(dev,
1767 ATOM_DEVICE_LCD1_SUPPORT,
1769 ATOM_DEVICE_LCD1_SUPPORT);
1770 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1771 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1772 CONNECTOR_OBJECT_ID_LVDS,
1774 /* VGA - primary dac */
1775 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1776 hpd.hpd = RADEON_HPD_NONE;
1777 radeon_add_legacy_encoder(dev,
1778 radeon_get_encoder_enum(dev,
1779 ATOM_DEVICE_CRT1_SUPPORT,
1781 ATOM_DEVICE_CRT1_SUPPORT);
1782 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1783 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1784 CONNECTOR_OBJECT_ID_VGA,
1787 ddc_i2c.valid = false;
1788 hpd.hpd = RADEON_HPD_NONE;
1789 radeon_add_legacy_encoder(dev,
1790 radeon_get_encoder_enum(dev,
1791 ATOM_DEVICE_TV1_SUPPORT,
1793 ATOM_DEVICE_TV1_SUPPORT);
1794 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1795 DRM_MODE_CONNECTOR_SVIDEO,
1797 CONNECTOR_OBJECT_ID_SVIDEO,
1800 case CT_MINI_EXTERNAL:
1801 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1802 rdev->mode_info.connector_table);
1803 /* DVI-I - tv dac, ext tmds */
1804 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1805 hpd.hpd = RADEON_HPD_2; /* ??? */
1806 radeon_add_legacy_encoder(dev,
1807 radeon_get_encoder_enum(dev,
1808 ATOM_DEVICE_DFP2_SUPPORT,
1810 ATOM_DEVICE_DFP2_SUPPORT);
1811 radeon_add_legacy_encoder(dev,
1812 radeon_get_encoder_enum(dev,
1813 ATOM_DEVICE_CRT2_SUPPORT,
1815 ATOM_DEVICE_CRT2_SUPPORT);
1816 /* XXX are any DL? */
1817 radeon_add_legacy_connector(dev, 0,
1818 ATOM_DEVICE_DFP2_SUPPORT |
1819 ATOM_DEVICE_CRT2_SUPPORT,
1820 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1821 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1824 ddc_i2c.valid = false;
1825 hpd.hpd = RADEON_HPD_NONE;
1826 radeon_add_legacy_encoder(dev,
1827 radeon_get_encoder_enum(dev,
1828 ATOM_DEVICE_TV1_SUPPORT,
1830 ATOM_DEVICE_TV1_SUPPORT);
1831 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1832 DRM_MODE_CONNECTOR_SVIDEO,
1834 CONNECTOR_OBJECT_ID_SVIDEO,
1837 case CT_MINI_INTERNAL:
1838 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1839 rdev->mode_info.connector_table);
1840 /* DVI-I - tv dac, int tmds */
1841 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1842 hpd.hpd = RADEON_HPD_1; /* ??? */
1843 radeon_add_legacy_encoder(dev,
1844 radeon_get_encoder_enum(dev,
1845 ATOM_DEVICE_DFP1_SUPPORT,
1847 ATOM_DEVICE_DFP1_SUPPORT);
1848 radeon_add_legacy_encoder(dev,
1849 radeon_get_encoder_enum(dev,
1850 ATOM_DEVICE_CRT2_SUPPORT,
1852 ATOM_DEVICE_CRT2_SUPPORT);
1853 radeon_add_legacy_connector(dev, 0,
1854 ATOM_DEVICE_DFP1_SUPPORT |
1855 ATOM_DEVICE_CRT2_SUPPORT,
1856 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1857 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1860 ddc_i2c.valid = false;
1861 hpd.hpd = RADEON_HPD_NONE;
1862 radeon_add_legacy_encoder(dev,
1863 radeon_get_encoder_enum(dev,
1864 ATOM_DEVICE_TV1_SUPPORT,
1866 ATOM_DEVICE_TV1_SUPPORT);
1867 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1868 DRM_MODE_CONNECTOR_SVIDEO,
1870 CONNECTOR_OBJECT_ID_SVIDEO,
1873 case CT_IMAC_G5_ISIGHT:
1874 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1875 rdev->mode_info.connector_table);
1876 /* DVI-D - int tmds */
1877 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1878 hpd.hpd = RADEON_HPD_1; /* ??? */
1879 radeon_add_legacy_encoder(dev,
1880 radeon_get_encoder_enum(dev,
1881 ATOM_DEVICE_DFP1_SUPPORT,
1883 ATOM_DEVICE_DFP1_SUPPORT);
1884 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1885 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1886 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1889 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1890 hpd.hpd = RADEON_HPD_NONE;
1891 radeon_add_legacy_encoder(dev,
1892 radeon_get_encoder_enum(dev,
1893 ATOM_DEVICE_CRT2_SUPPORT,
1895 ATOM_DEVICE_CRT2_SUPPORT);
1896 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1897 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1898 CONNECTOR_OBJECT_ID_VGA,
1901 ddc_i2c.valid = false;
1902 hpd.hpd = RADEON_HPD_NONE;
1903 radeon_add_legacy_encoder(dev,
1904 radeon_get_encoder_enum(dev,
1905 ATOM_DEVICE_TV1_SUPPORT,
1907 ATOM_DEVICE_TV1_SUPPORT);
1908 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1909 DRM_MODE_CONNECTOR_SVIDEO,
1911 CONNECTOR_OBJECT_ID_SVIDEO,
1915 DRM_INFO("Connector Table: %d (emac)\n",
1916 rdev->mode_info.connector_table);
1917 /* VGA - primary dac */
1918 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1919 hpd.hpd = RADEON_HPD_NONE;
1920 radeon_add_legacy_encoder(dev,
1921 radeon_get_encoder_enum(dev,
1922 ATOM_DEVICE_CRT1_SUPPORT,
1924 ATOM_DEVICE_CRT1_SUPPORT);
1925 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1926 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1927 CONNECTOR_OBJECT_ID_VGA,
1930 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1931 hpd.hpd = RADEON_HPD_NONE;
1932 radeon_add_legacy_encoder(dev,
1933 radeon_get_encoder_enum(dev,
1934 ATOM_DEVICE_CRT2_SUPPORT,
1936 ATOM_DEVICE_CRT2_SUPPORT);
1937 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1938 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1939 CONNECTOR_OBJECT_ID_VGA,
1942 ddc_i2c.valid = false;
1943 hpd.hpd = RADEON_HPD_NONE;
1944 radeon_add_legacy_encoder(dev,
1945 radeon_get_encoder_enum(dev,
1946 ATOM_DEVICE_TV1_SUPPORT,
1948 ATOM_DEVICE_TV1_SUPPORT);
1949 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1950 DRM_MODE_CONNECTOR_SVIDEO,
1952 CONNECTOR_OBJECT_ID_SVIDEO,
1956 DRM_INFO("Connector Table: %d (rn50-power)\n",
1957 rdev->mode_info.connector_table);
1958 /* VGA - primary dac */
1959 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1960 hpd.hpd = RADEON_HPD_NONE;
1961 radeon_add_legacy_encoder(dev,
1962 radeon_get_encoder_enum(dev,
1963 ATOM_DEVICE_CRT1_SUPPORT,
1965 ATOM_DEVICE_CRT1_SUPPORT);
1966 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1967 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1968 CONNECTOR_OBJECT_ID_VGA,
1970 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1971 hpd.hpd = RADEON_HPD_NONE;
1972 radeon_add_legacy_encoder(dev,
1973 radeon_get_encoder_enum(dev,
1974 ATOM_DEVICE_CRT2_SUPPORT,
1976 ATOM_DEVICE_CRT2_SUPPORT);
1977 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1978 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1979 CONNECTOR_OBJECT_ID_VGA,
1983 DRM_INFO("Connector Table: %d (mac x800)\n",
1984 rdev->mode_info.connector_table);
1985 /* DVI - primary dac, internal tmds */
1986 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1987 hpd.hpd = RADEON_HPD_1; /* ??? */
1988 radeon_add_legacy_encoder(dev,
1989 radeon_get_encoder_enum(dev,
1990 ATOM_DEVICE_DFP1_SUPPORT,
1992 ATOM_DEVICE_DFP1_SUPPORT);
1993 radeon_add_legacy_encoder(dev,
1994 radeon_get_encoder_enum(dev,
1995 ATOM_DEVICE_CRT1_SUPPORT,
1997 ATOM_DEVICE_CRT1_SUPPORT);
1998 radeon_add_legacy_connector(dev, 0,
1999 ATOM_DEVICE_DFP1_SUPPORT |
2000 ATOM_DEVICE_CRT1_SUPPORT,
2001 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2002 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2004 /* DVI - tv dac, dvo */
2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2006 hpd.hpd = RADEON_HPD_2; /* ??? */
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_DFP2_SUPPORT,
2011 ATOM_DEVICE_DFP2_SUPPORT);
2012 radeon_add_legacy_encoder(dev,
2013 radeon_get_encoder_enum(dev,
2014 ATOM_DEVICE_CRT2_SUPPORT,
2016 ATOM_DEVICE_CRT2_SUPPORT);
2017 radeon_add_legacy_connector(dev, 1,
2018 ATOM_DEVICE_DFP2_SUPPORT |
2019 ATOM_DEVICE_CRT2_SUPPORT,
2020 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2021 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2025 DRM_INFO("Connector table: %d (invalid)\n",
2026 rdev->mode_info.connector_table);
2030 radeon_link_encoder_connector(dev);
2035 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2037 enum radeon_combios_connector
2039 struct radeon_i2c_bus_rec *ddc_i2c,
2040 struct radeon_hpd *hpd)
2043 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2044 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2045 if (dev->pdev->device == 0x515e &&
2046 dev->pdev->subsystem_vendor == 0x1014) {
2047 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2048 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2052 /* X300 card with extra non-existent DVI port */
2053 if (dev->pdev->device == 0x5B60 &&
2054 dev->pdev->subsystem_vendor == 0x17af &&
2055 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2056 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2063 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2065 /* Acer 5102 has non-existent TV port */
2066 if (dev->pdev->device == 0x5975 &&
2067 dev->pdev->subsystem_vendor == 0x1025 &&
2068 dev->pdev->subsystem_device == 0x009f)
2071 /* HP dc5750 has non-existent TV port */
2072 if (dev->pdev->device == 0x5974 &&
2073 dev->pdev->subsystem_vendor == 0x103c &&
2074 dev->pdev->subsystem_device == 0x280a)
2077 /* MSI S270 has non-existent TV port */
2078 if (dev->pdev->device == 0x5955 &&
2079 dev->pdev->subsystem_vendor == 0x1462 &&
2080 dev->pdev->subsystem_device == 0x0131)
2086 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2088 struct radeon_device *rdev = dev->dev_private;
2089 uint32_t ext_tmds_info;
2091 if (rdev->flags & RADEON_IS_IGP) {
2093 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2095 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2097 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2098 if (ext_tmds_info) {
2099 uint8_t rev = RBIOS8(ext_tmds_info);
2100 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2103 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2105 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2109 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2111 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2116 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2118 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2121 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2123 struct radeon_device *rdev = dev->dev_private;
2124 uint32_t conn_info, entry, devices;
2125 uint16_t tmp, connector_object_id;
2126 enum radeon_combios_ddc ddc_type;
2127 enum radeon_combios_connector connector;
2129 struct radeon_i2c_bus_rec ddc_i2c;
2130 struct radeon_hpd hpd;
2132 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2134 for (i = 0; i < 4; i++) {
2135 entry = conn_info + 2 + i * 2;
2137 if (!RBIOS16(entry))
2140 tmp = RBIOS16(entry);
2142 connector = (tmp >> 12) & 0xf;
2144 ddc_type = (tmp >> 8) & 0xf;
2145 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2147 switch (connector) {
2148 case CONNECTOR_PROPRIETARY_LEGACY:
2149 case CONNECTOR_DVI_I_LEGACY:
2150 case CONNECTOR_DVI_D_LEGACY:
2151 if ((tmp >> 4) & 0x1)
2152 hpd.hpd = RADEON_HPD_2;
2154 hpd.hpd = RADEON_HPD_1;
2157 hpd.hpd = RADEON_HPD_NONE;
2161 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2165 switch (connector) {
2166 case CONNECTOR_PROPRIETARY_LEGACY:
2167 if ((tmp >> 4) & 0x1)
2168 devices = ATOM_DEVICE_DFP2_SUPPORT;
2170 devices = ATOM_DEVICE_DFP1_SUPPORT;
2171 radeon_add_legacy_encoder(dev,
2172 radeon_get_encoder_enum
2175 radeon_add_legacy_connector(dev, i, devices,
2176 legacy_connector_convert
2179 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2182 case CONNECTOR_CRT_LEGACY:
2184 devices = ATOM_DEVICE_CRT2_SUPPORT;
2185 radeon_add_legacy_encoder(dev,
2186 radeon_get_encoder_enum
2188 ATOM_DEVICE_CRT2_SUPPORT,
2190 ATOM_DEVICE_CRT2_SUPPORT);
2192 devices = ATOM_DEVICE_CRT1_SUPPORT;
2193 radeon_add_legacy_encoder(dev,
2194 radeon_get_encoder_enum
2196 ATOM_DEVICE_CRT1_SUPPORT,
2198 ATOM_DEVICE_CRT1_SUPPORT);
2200 radeon_add_legacy_connector(dev,
2203 legacy_connector_convert
2206 CONNECTOR_OBJECT_ID_VGA,
2209 case CONNECTOR_DVI_I_LEGACY:
2212 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2213 radeon_add_legacy_encoder(dev,
2214 radeon_get_encoder_enum
2216 ATOM_DEVICE_CRT2_SUPPORT,
2218 ATOM_DEVICE_CRT2_SUPPORT);
2220 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2221 radeon_add_legacy_encoder(dev,
2222 radeon_get_encoder_enum
2224 ATOM_DEVICE_CRT1_SUPPORT,
2226 ATOM_DEVICE_CRT1_SUPPORT);
2228 if ((tmp >> 4) & 0x1) {
2229 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2230 radeon_add_legacy_encoder(dev,
2231 radeon_get_encoder_enum
2233 ATOM_DEVICE_DFP2_SUPPORT,
2235 ATOM_DEVICE_DFP2_SUPPORT);
2236 connector_object_id = combios_check_dl_dvi(dev, 0);
2238 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2239 radeon_add_legacy_encoder(dev,
2240 radeon_get_encoder_enum
2242 ATOM_DEVICE_DFP1_SUPPORT,
2244 ATOM_DEVICE_DFP1_SUPPORT);
2245 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2247 radeon_add_legacy_connector(dev,
2250 legacy_connector_convert
2253 connector_object_id,
2256 case CONNECTOR_DVI_D_LEGACY:
2257 if ((tmp >> 4) & 0x1) {
2258 devices = ATOM_DEVICE_DFP2_SUPPORT;
2259 connector_object_id = combios_check_dl_dvi(dev, 1);
2261 devices = ATOM_DEVICE_DFP1_SUPPORT;
2262 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2264 radeon_add_legacy_encoder(dev,
2265 radeon_get_encoder_enum
2268 radeon_add_legacy_connector(dev, i, devices,
2269 legacy_connector_convert
2272 connector_object_id,
2275 case CONNECTOR_CTV_LEGACY:
2276 case CONNECTOR_STV_LEGACY:
2277 radeon_add_legacy_encoder(dev,
2278 radeon_get_encoder_enum
2280 ATOM_DEVICE_TV1_SUPPORT,
2282 ATOM_DEVICE_TV1_SUPPORT);
2283 radeon_add_legacy_connector(dev, i,
2284 ATOM_DEVICE_TV1_SUPPORT,
2285 legacy_connector_convert
2288 CONNECTOR_OBJECT_ID_SVIDEO,
2292 DRM_ERROR("Unknown connector type: %d\n",
2299 uint16_t tmds_info =
2300 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2302 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2304 radeon_add_legacy_encoder(dev,
2305 radeon_get_encoder_enum(dev,
2306 ATOM_DEVICE_CRT1_SUPPORT,
2308 ATOM_DEVICE_CRT1_SUPPORT);
2309 radeon_add_legacy_encoder(dev,
2310 radeon_get_encoder_enum(dev,
2311 ATOM_DEVICE_DFP1_SUPPORT,
2313 ATOM_DEVICE_DFP1_SUPPORT);
2315 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2316 hpd.hpd = RADEON_HPD_1;
2317 radeon_add_legacy_connector(dev,
2319 ATOM_DEVICE_CRT1_SUPPORT |
2320 ATOM_DEVICE_DFP1_SUPPORT,
2321 DRM_MODE_CONNECTOR_DVII,
2323 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2327 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2328 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2330 radeon_add_legacy_encoder(dev,
2331 radeon_get_encoder_enum(dev,
2332 ATOM_DEVICE_CRT1_SUPPORT,
2334 ATOM_DEVICE_CRT1_SUPPORT);
2335 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2336 hpd.hpd = RADEON_HPD_NONE;
2337 radeon_add_legacy_connector(dev,
2339 ATOM_DEVICE_CRT1_SUPPORT,
2340 DRM_MODE_CONNECTOR_VGA,
2342 CONNECTOR_OBJECT_ID_VGA,
2345 DRM_DEBUG_KMS("No connector info found\n");
2351 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2353 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2355 uint16_t lcd_ddc_info =
2356 combios_get_table_offset(dev,
2357 COMBIOS_LCD_DDC_INFO_TABLE);
2359 radeon_add_legacy_encoder(dev,
2360 radeon_get_encoder_enum(dev,
2361 ATOM_DEVICE_LCD1_SUPPORT,
2363 ATOM_DEVICE_LCD1_SUPPORT);
2366 ddc_type = RBIOS8(lcd_ddc_info + 2);
2370 combios_setup_i2c_bus(rdev,
2372 RBIOS32(lcd_ddc_info + 3),
2373 RBIOS32(lcd_ddc_info + 7));
2374 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2378 combios_setup_i2c_bus(rdev,
2380 RBIOS32(lcd_ddc_info + 3),
2381 RBIOS32(lcd_ddc_info + 7));
2382 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2386 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2389 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2391 ddc_i2c.valid = false;
2393 hpd.hpd = RADEON_HPD_NONE;
2394 radeon_add_legacy_connector(dev,
2396 ATOM_DEVICE_LCD1_SUPPORT,
2397 DRM_MODE_CONNECTOR_LVDS,
2399 CONNECTOR_OBJECT_ID_LVDS,
2404 /* check TV table */
2405 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2407 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2409 if (RBIOS8(tv_info + 6) == 'T') {
2410 if (radeon_apply_legacy_tv_quirks(dev)) {
2411 hpd.hpd = RADEON_HPD_NONE;
2412 ddc_i2c.valid = false;
2413 radeon_add_legacy_encoder(dev,
2414 radeon_get_encoder_enum
2416 ATOM_DEVICE_TV1_SUPPORT,
2418 ATOM_DEVICE_TV1_SUPPORT);
2419 radeon_add_legacy_connector(dev, 6,
2420 ATOM_DEVICE_TV1_SUPPORT,
2421 DRM_MODE_CONNECTOR_SVIDEO,
2423 CONNECTOR_OBJECT_ID_SVIDEO,
2430 radeon_link_encoder_connector(dev);
2435 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2437 struct drm_device *dev = rdev->ddev;
2438 u16 offset, misc, misc2 = 0;
2439 u8 rev, blocks, tmp;
2440 int state_index = 0;
2442 rdev->pm.default_power_state_index = -1;
2444 if (rdev->flags & RADEON_IS_MOBILITY) {
2445 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2447 rev = RBIOS8(offset);
2448 blocks = RBIOS8(offset + 0x2);
2449 /* power mode 0 tends to be the only valid one */
2450 rdev->pm.power_state[state_index].num_clock_modes = 1;
2451 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2452 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2453 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2454 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2456 rdev->pm.power_state[state_index].type =
2457 POWER_STATE_TYPE_BATTERY;
2458 misc = RBIOS16(offset + 0x5 + 0x0);
2460 misc2 = RBIOS16(offset + 0x5 + 0xe);
2461 rdev->pm.power_state[state_index].misc = misc;
2462 rdev->pm.power_state[state_index].misc2 = misc2;
2464 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2466 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2469 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2471 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2473 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2474 RBIOS16(offset + 0x5 + 0xb) * 4;
2475 tmp = RBIOS8(offset + 0x5 + 0xd);
2476 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2478 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2479 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2480 if (entries && voltage_table_offset) {
2481 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2482 RBIOS16(voltage_table_offset) * 4;
2483 tmp = RBIOS8(voltage_table_offset + 0x2);
2484 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2486 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2488 switch ((misc2 & 0x700) >> 8) {
2491 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2494 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2497 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2500 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2503 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2507 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2509 rdev->pm.power_state[state_index].pcie_lanes =
2510 RBIOS8(offset + 0x5 + 0x10);
2511 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2514 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2517 /* XXX figure out some good default low power mode for desktop cards */
2521 /* add the default mode */
2522 rdev->pm.power_state[state_index].type =
2523 POWER_STATE_TYPE_DEFAULT;
2524 rdev->pm.power_state[state_index].num_clock_modes = 1;
2525 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2526 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2527 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2528 if ((state_index > 0) &&
2529 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2530 rdev->pm.power_state[state_index].clock_info[0].voltage =
2531 rdev->pm.power_state[0].clock_info[0].voltage;
2533 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2534 rdev->pm.power_state[state_index].pcie_lanes = 16;
2535 rdev->pm.power_state[state_index].flags = 0;
2536 rdev->pm.default_power_state_index = state_index;
2537 rdev->pm.num_power_states = state_index + 1;
2539 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2540 rdev->pm.current_clock_mode_index = 0;
2543 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2545 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2546 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2551 switch (tmds->dvo_chip) {
2554 radeon_i2c_put_byte(tmds->i2c_bus,
2557 radeon_i2c_put_byte(tmds->i2c_bus,
2560 radeon_i2c_put_byte(tmds->i2c_bus,
2563 radeon_i2c_put_byte(tmds->i2c_bus,
2566 radeon_i2c_put_byte(tmds->i2c_bus,
2571 /* sil 1178 - untested */
2590 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2592 struct drm_device *dev = encoder->dev;
2593 struct radeon_device *rdev = dev->dev_private;
2594 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2596 uint8_t blocks, slave_addr, rev;
2598 uint32_t reg, val, and_mask, or_mask;
2599 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2604 if (rdev->flags & RADEON_IS_IGP) {
2605 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2606 rev = RBIOS8(offset);
2608 rev = RBIOS8(offset);
2610 blocks = RBIOS8(offset + 3);
2612 while (blocks > 0) {
2613 id = RBIOS16(index);
2617 reg = (id & 0x1fff) * 4;
2618 val = RBIOS32(index);
2623 reg = (id & 0x1fff) * 4;
2624 and_mask = RBIOS32(index);
2626 or_mask = RBIOS32(index);
2629 val = (val & and_mask) | or_mask;
2633 val = RBIOS16(index);
2638 val = RBIOS16(index);
2643 slave_addr = id & 0xff;
2644 slave_addr >>= 1; /* 7 bit addressing */
2646 reg = RBIOS8(index);
2648 val = RBIOS8(index);
2650 radeon_i2c_put_byte(tmds->i2c_bus,
2655 DRM_ERROR("Unknown id %d\n", id >> 13);
2664 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2666 index = offset + 10;
2667 id = RBIOS16(index);
2668 while (id != 0xffff) {
2672 reg = (id & 0x1fff) * 4;
2673 val = RBIOS32(index);
2677 reg = (id & 0x1fff) * 4;
2678 and_mask = RBIOS32(index);
2680 or_mask = RBIOS32(index);
2683 val = (val & and_mask) | or_mask;
2687 val = RBIOS16(index);
2693 and_mask = RBIOS32(index);
2695 or_mask = RBIOS32(index);
2697 val = RREG32_PLL(reg);
2698 val = (val & and_mask) | or_mask;
2699 WREG32_PLL(reg, val);
2703 val = RBIOS8(index);
2705 radeon_i2c_put_byte(tmds->i2c_bus,
2710 DRM_ERROR("Unknown id %d\n", id >> 13);
2713 id = RBIOS16(index);
2721 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2723 struct radeon_device *rdev = dev->dev_private;
2726 while (RBIOS16(offset)) {
2727 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2728 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2729 uint32_t val, and_mask, or_mask;
2735 val = RBIOS32(offset);
2740 val = RBIOS32(offset);
2745 and_mask = RBIOS32(offset);
2747 or_mask = RBIOS32(offset);
2755 and_mask = RBIOS32(offset);
2757 or_mask = RBIOS32(offset);
2765 val = RBIOS16(offset);
2770 val = RBIOS16(offset);
2777 (RADEON_CLK_PWRMGT_CNTL) &
2784 if ((RREG32(RADEON_MC_STATUS) &
2800 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2802 struct radeon_device *rdev = dev->dev_private;
2805 while (RBIOS8(offset)) {
2806 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2807 uint8_t addr = (RBIOS8(offset) & 0x3f);
2808 uint32_t val, shift, tmp;
2809 uint32_t and_mask, or_mask;
2814 val = RBIOS32(offset);
2816 WREG32_PLL(addr, val);
2819 shift = RBIOS8(offset) * 8;
2821 and_mask = RBIOS8(offset) << shift;
2822 and_mask |= ~(0xff << shift);
2824 or_mask = RBIOS8(offset) << shift;
2826 tmp = RREG32_PLL(addr);
2829 WREG32_PLL(addr, tmp);
2845 (RADEON_CLK_PWRMGT_CNTL) &
2853 (RADEON_CLK_PWRMGT_CNTL) &
2860 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2861 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2863 uint32_t mclk_cntl =
2866 mclk_cntl &= 0xffff0000;
2867 /*mclk_cntl |= 0x00001111;*//* ??? */
2868 WREG32_PLL(RADEON_MCLK_CNTL,
2873 (RADEON_CLK_PWRMGT_CNTL,
2875 ~RADEON_CG_NO1_DEBUG_0);
2890 static void combios_parse_ram_reset_table(struct drm_device *dev,
2893 struct radeon_device *rdev = dev->dev_private;
2897 uint8_t val = RBIOS8(offset);
2898 while (val != 0xff) {
2902 uint32_t channel_complete_mask;
2904 if (ASIC_IS_R300(rdev))
2905 channel_complete_mask =
2906 R300_MEM_PWRUP_COMPLETE;
2908 channel_complete_mask =
2909 RADEON_MEM_PWRUP_COMPLETE;
2912 if ((RREG32(RADEON_MEM_STR_CNTL) &
2913 channel_complete_mask) ==
2914 channel_complete_mask)
2918 uint32_t or_mask = RBIOS16(offset);
2921 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2922 tmp &= RADEON_SDRAM_MODE_MASK;
2924 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2926 or_mask = val << 24;
2927 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2928 tmp &= RADEON_B3MEM_RESET_MASK;
2930 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2932 val = RBIOS8(offset);
2937 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2938 int mem_addr_mapping)
2940 struct radeon_device *rdev = dev->dev_private;
2945 mem_cntl = RREG32(RADEON_MEM_CNTL);
2946 if (mem_cntl & RV100_HALF_MODE)
2949 mem_cntl &= ~(0xff << 8);
2950 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2951 WREG32(RADEON_MEM_CNTL, mem_cntl);
2952 RREG32(RADEON_MEM_CNTL);
2956 /* something like this???? */
2958 addr = ram * 1024 * 1024;
2959 /* write to each page */
2960 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2961 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2962 /* read back and verify */
2963 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2964 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2971 static void combios_write_ram_size(struct drm_device *dev)
2973 struct radeon_device *rdev = dev->dev_private;
2976 uint32_t mem_size = 0;
2977 uint32_t mem_cntl = 0;
2979 /* should do something smarter here I guess... */
2980 if (rdev->flags & RADEON_IS_IGP)
2983 /* first check detected mem table */
2984 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2986 rev = RBIOS8(offset);
2988 mem_cntl = RBIOS32(offset + 1);
2989 mem_size = RBIOS16(offset + 5);
2990 if ((rdev->family < CHIP_R200) &&
2991 !ASIC_IS_RN50(rdev))
2992 WREG32(RADEON_MEM_CNTL, mem_cntl);
2998 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3000 rev = RBIOS8(offset - 1);
3002 if ((rdev->family < CHIP_R200)
3003 && !ASIC_IS_RN50(rdev)) {
3005 int mem_addr_mapping = 0;
3007 while (RBIOS8(offset)) {
3008 ram = RBIOS8(offset);
3011 if (mem_addr_mapping != 0x25)
3014 combios_detect_ram(dev, ram,
3021 mem_size = RBIOS8(offset);
3023 mem_size = RBIOS8(offset);
3024 mem_size *= 2; /* convert to MB */
3029 mem_size *= (1024 * 1024); /* convert to bytes */
3030 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3033 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3035 uint16_t dyn_clk_info =
3036 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3039 combios_parse_pll_table(dev, dyn_clk_info);
3042 void radeon_combios_asic_init(struct drm_device *dev)
3044 struct radeon_device *rdev = dev->dev_private;
3047 /* port hardcoded mac stuff from radeonfb */
3048 if (rdev->bios == NULL)
3052 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3054 combios_parse_mmio_table(dev, table);
3057 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3059 combios_parse_pll_table(dev, table);
3062 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3064 combios_parse_mmio_table(dev, table);
3066 if (!(rdev->flags & RADEON_IS_IGP)) {
3069 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3071 combios_parse_mmio_table(dev, table);
3074 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3076 combios_parse_ram_reset_table(dev, table);
3080 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3082 combios_parse_mmio_table(dev, table);
3084 /* write CONFIG_MEMSIZE */
3085 combios_write_ram_size(dev);
3088 /* quirk for rs4xx HP nx6125 laptop to make it resume
3089 * - it hangs on resume inside the dynclk 1 table.
3091 if (rdev->family == CHIP_RS480 &&
3092 rdev->pdev->subsystem_vendor == 0x103c &&
3093 rdev->pdev->subsystem_device == 0x308b)
3096 /* quirk for rs4xx HP dv5000 laptop to make it resume
3097 * - it hangs on resume inside the dynclk 1 table.
3099 if (rdev->family == CHIP_RS480 &&
3100 rdev->pdev->subsystem_vendor == 0x103c &&
3101 rdev->pdev->subsystem_device == 0x30a4)
3105 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3107 combios_parse_pll_table(dev, table);
3111 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3113 struct radeon_device *rdev = dev->dev_private;
3114 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3116 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3117 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3118 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3120 /* let the bios control the backlight */
3121 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3123 /* tell the bios not to handle mode switching */
3124 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3125 RADEON_ACC_MODE_CHANGE);
3127 /* tell the bios a driver is loaded */
3128 bios_7_scratch |= RADEON_DRV_LOADED;
3130 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3131 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3132 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3135 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3137 struct drm_device *dev = encoder->dev;
3138 struct radeon_device *rdev = dev->dev_private;
3139 uint32_t bios_6_scratch;
3141 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3144 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3146 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3148 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3152 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3153 struct drm_encoder *encoder,
3156 struct drm_device *dev = connector->dev;
3157 struct radeon_device *rdev = dev->dev_private;
3158 struct radeon_connector *radeon_connector =
3159 to_radeon_connector(connector);
3160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3161 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3162 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3164 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3165 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3167 DRM_DEBUG_KMS("TV1 connected\n");
3169 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3170 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3171 bios_5_scratch |= RADEON_TV1_ON;
3172 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3174 DRM_DEBUG_KMS("TV1 disconnected\n");
3175 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3176 bios_5_scratch &= ~RADEON_TV1_ON;
3177 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3180 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3181 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3183 DRM_DEBUG_KMS("LCD1 connected\n");
3184 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3185 bios_5_scratch |= RADEON_LCD1_ON;
3186 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3188 DRM_DEBUG_KMS("LCD1 disconnected\n");
3189 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3190 bios_5_scratch &= ~RADEON_LCD1_ON;
3191 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3194 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3195 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3197 DRM_DEBUG_KMS("CRT1 connected\n");
3198 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3199 bios_5_scratch |= RADEON_CRT1_ON;
3200 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3202 DRM_DEBUG_KMS("CRT1 disconnected\n");
3203 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3204 bios_5_scratch &= ~RADEON_CRT1_ON;
3205 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3208 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3209 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3211 DRM_DEBUG_KMS("CRT2 connected\n");
3212 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3213 bios_5_scratch |= RADEON_CRT2_ON;
3214 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3216 DRM_DEBUG_KMS("CRT2 disconnected\n");
3217 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3218 bios_5_scratch &= ~RADEON_CRT2_ON;
3219 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3222 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3223 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3225 DRM_DEBUG_KMS("DFP1 connected\n");
3226 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3227 bios_5_scratch |= RADEON_DFP1_ON;
3228 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3230 DRM_DEBUG_KMS("DFP1 disconnected\n");
3231 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3232 bios_5_scratch &= ~RADEON_DFP1_ON;
3233 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3236 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3237 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3239 DRM_DEBUG_KMS("DFP2 connected\n");
3240 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3241 bios_5_scratch |= RADEON_DFP2_ON;
3242 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3244 DRM_DEBUG_KMS("DFP2 disconnected\n");
3245 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3246 bios_5_scratch &= ~RADEON_DFP2_ON;
3247 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3250 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3251 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3255 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3257 struct drm_device *dev = encoder->dev;
3258 struct radeon_device *rdev = dev->dev_private;
3259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3260 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3262 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3263 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3264 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3266 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3267 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3268 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3270 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3271 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3272 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3274 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3275 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3276 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3278 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3279 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3280 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3282 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3283 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3284 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3286 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3290 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3292 struct drm_device *dev = encoder->dev;
3293 struct radeon_device *rdev = dev->dev_private;
3294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3295 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3297 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3299 bios_6_scratch |= RADEON_TV_DPMS_ON;
3301 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3303 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3305 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3307 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3309 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3311 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3313 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3315 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3317 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3319 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3321 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);