2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include "radeon_drm.h"
29 #include "radeon_reg.h"
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
61 for (j = 0; j < i; j++) {
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
79 p->relocs[i].lobj.bo = p->relocs[i].robj;
80 p->relocs[i].lobj.wdomain = r->write_domain;
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
85 radeon_bo_list_add_object(&p->relocs[i].lobj,
89 p->relocs[i].handle = 0;
91 return radeon_bo_list_validate(&p->validated);
94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
96 p->priority = priority;
100 DRM_ERROR("unknown ring id: %d\n", ring);
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
105 case RADEON_CS_RING_COMPUTE:
106 if (p->rdev->family >= CHIP_TAHITI) {
108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
112 p->ring = RADEON_RING_TYPE_GFX_INDEX;
118 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
120 bool sync_to_ring[RADEON_NUM_RINGS] = { };
121 bool need_sync = false;
124 for (i = 0; i < p->nrelocs; i++) {
125 struct radeon_fence *fence;
127 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
130 fence = p->relocs[i].robj->tbo.sync_obj;
131 if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
132 sync_to_ring[fence->ring] = true;
141 r = radeon_semaphore_create(p->rdev, &p->ib.semaphore);
146 return radeon_semaphore_sync_rings(p->rdev, p->ib.semaphore,
147 sync_to_ring, p->ring);
150 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
152 struct drm_radeon_cs *cs = data;
153 uint64_t *chunk_array_ptr;
155 u32 ring = RADEON_CS_RING_GFX;
158 if (!cs->num_chunks) {
162 INIT_LIST_HEAD(&p->validated);
165 p->ib.semaphore = NULL;
166 p->const_ib.sa_bo = NULL;
167 p->const_ib.semaphore = NULL;
168 p->chunk_ib_idx = -1;
169 p->chunk_relocs_idx = -1;
170 p->chunk_flags_idx = -1;
171 p->chunk_const_ib_idx = -1;
172 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
173 if (p->chunks_array == NULL) {
176 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
177 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
178 sizeof(uint64_t)*cs->num_chunks)) {
182 p->nchunks = cs->num_chunks;
183 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
184 if (p->chunks == NULL) {
187 for (i = 0; i < p->nchunks; i++) {
188 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
189 struct drm_radeon_cs_chunk user_chunk;
190 uint32_t __user *cdata;
192 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
193 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
194 sizeof(struct drm_radeon_cs_chunk))) {
197 p->chunks[i].length_dw = user_chunk.length_dw;
198 p->chunks[i].kdata = NULL;
199 p->chunks[i].chunk_id = user_chunk.chunk_id;
201 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
202 p->chunk_relocs_idx = i;
204 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
206 /* zero length IB isn't useful */
207 if (p->chunks[i].length_dw == 0)
210 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
211 p->chunk_const_ib_idx = i;
212 /* zero length CONST IB isn't useful */
213 if (p->chunks[i].length_dw == 0)
216 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
217 p->chunk_flags_idx = i;
218 /* zero length flags aren't useful */
219 if (p->chunks[i].length_dw == 0)
223 p->chunks[i].length_dw = user_chunk.length_dw;
224 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
226 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
227 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
228 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
229 size = p->chunks[i].length_dw * sizeof(uint32_t);
230 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
231 if (p->chunks[i].kdata == NULL) {
234 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
235 p->chunks[i].user_ptr, size)) {
238 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
239 p->cs_flags = p->chunks[i].kdata[0];
240 if (p->chunks[i].length_dw > 1)
241 ring = p->chunks[i].kdata[1];
242 if (p->chunks[i].length_dw > 2)
243 priority = (s32)p->chunks[i].kdata[2];
248 if ((p->cs_flags & RADEON_CS_USE_VM) &&
249 !p->rdev->vm_manager.enabled) {
250 DRM_ERROR("VM not active on asic!\n");
254 /* we only support VM on SI+ */
255 if ((p->rdev->family >= CHIP_TAHITI) &&
256 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
257 DRM_ERROR("VM required on SI+!\n");
261 if (radeon_cs_get_ring(p, ring, priority))
265 /* deal with non-vm */
266 if ((p->chunk_ib_idx != -1) &&
267 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
268 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
269 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
270 DRM_ERROR("cs IB too big: %d\n",
271 p->chunks[p->chunk_ib_idx].length_dw);
274 if ((p->rdev->flags & RADEON_IS_AGP)) {
275 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
276 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
277 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
278 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
279 kfree(p->chunks[i].kpage[0]);
280 kfree(p->chunks[i].kpage[1]);
284 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
285 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
286 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
287 p->chunks[p->chunk_ib_idx].last_page_index =
288 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
295 * cs_parser_fini() - clean parser states
296 * @parser: parser structure holding parsing context.
297 * @error: error number
299 * If error is set than unvalidate buffer, otherwise just free memory
300 * used by parsing context.
302 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
307 ttm_eu_fence_buffer_objects(&parser->validated,
310 ttm_eu_backoff_reservation(&parser->validated);
312 if (parser->relocs != NULL) {
313 for (i = 0; i < parser->nrelocs; i++) {
314 if (parser->relocs[i].gobj)
315 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
318 kfree(parser->track);
319 kfree(parser->relocs);
320 kfree(parser->relocs_ptr);
321 for (i = 0; i < parser->nchunks; i++) {
322 kfree(parser->chunks[i].kdata);
323 if ((parser->rdev->flags & RADEON_IS_AGP)) {
324 kfree(parser->chunks[i].kpage[0]);
325 kfree(parser->chunks[i].kpage[1]);
328 kfree(parser->chunks);
329 kfree(parser->chunks_array);
330 radeon_ib_free(parser->rdev, &parser->ib);
331 radeon_ib_free(parser->rdev, &parser->const_ib);
334 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
335 struct radeon_cs_parser *parser)
337 struct radeon_cs_chunk *ib_chunk;
340 if (parser->chunk_ib_idx == -1)
343 if (parser->cs_flags & RADEON_CS_USE_VM)
346 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
347 /* Copy the packet into the IB, the parser will read from the
348 * input memory (cached) and write to the IB (which can be
351 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
352 ib_chunk->length_dw * 4);
354 DRM_ERROR("Failed to get ib !\n");
357 parser->ib.length_dw = ib_chunk->length_dw;
358 r = radeon_cs_parse(rdev, parser->ring, parser);
359 if (r || parser->parser_error) {
360 DRM_ERROR("Invalid command stream !\n");
363 r = radeon_cs_finish_pages(parser);
365 DRM_ERROR("Invalid command stream !\n");
368 r = radeon_cs_sync_rings(parser);
370 DRM_ERROR("Failed to synchronize rings !\n");
372 parser->ib.vm_id = 0;
373 r = radeon_ib_schedule(rdev, &parser->ib);
375 DRM_ERROR("Failed to schedule IB !\n");
380 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
381 struct radeon_vm *vm)
383 struct radeon_bo_list *lobj;
384 struct radeon_bo *bo;
387 list_for_each_entry(lobj, &parser->validated, tv.head) {
389 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
397 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
398 struct radeon_cs_parser *parser)
400 struct radeon_cs_chunk *ib_chunk;
401 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
402 struct radeon_vm *vm = &fpriv->vm;
405 if (parser->chunk_ib_idx == -1)
408 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
411 if ((rdev->family >= CHIP_TAHITI) &&
412 (parser->chunk_const_ib_idx != -1)) {
413 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
414 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
415 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
418 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
419 ib_chunk->length_dw * 4);
421 DRM_ERROR("Failed to get const ib !\n");
424 parser->const_ib.is_const_ib = true;
425 parser->const_ib.length_dw = ib_chunk->length_dw;
426 /* Copy the packet into the IB */
427 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
428 ib_chunk->length_dw * 4)) {
431 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
437 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
438 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
439 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
442 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
443 ib_chunk->length_dw * 4);
445 DRM_ERROR("Failed to get ib !\n");
448 parser->ib.length_dw = ib_chunk->length_dw;
449 /* Copy the packet into the IB */
450 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
451 ib_chunk->length_dw * 4)) {
454 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
459 mutex_lock(&vm->mutex);
460 r = radeon_vm_bind(rdev, vm);
464 r = radeon_bo_vm_update_pte(parser, vm);
468 r = radeon_cs_sync_rings(parser);
470 DRM_ERROR("Failed to synchronize rings !\n");
473 if ((rdev->family >= CHIP_TAHITI) &&
474 (parser->chunk_const_ib_idx != -1)) {
475 parser->const_ib.vm_id = vm->id;
476 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
477 * offset inside the pool bo
479 parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
480 r = radeon_ib_schedule(rdev, &parser->const_ib);
485 parser->ib.vm_id = vm->id;
486 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
487 * offset inside the pool bo
489 parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
490 parser->ib.is_const_ib = false;
491 r = radeon_ib_schedule(rdev, &parser->ib);
495 radeon_fence_unref(&vm->fence);
497 vm->fence = radeon_fence_ref(parser->ib.fence);
499 mutex_unlock(&fpriv->vm.mutex);
503 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
506 r = radeon_gpu_reset(rdev);
513 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
515 struct radeon_device *rdev = dev->dev_private;
516 struct radeon_cs_parser parser;
519 radeon_mutex_lock(&rdev->cs_mutex);
520 if (!rdev->accel_working) {
521 radeon_mutex_unlock(&rdev->cs_mutex);
524 /* initialize parser */
525 memset(&parser, 0, sizeof(struct radeon_cs_parser));
528 parser.dev = rdev->dev;
529 parser.family = rdev->family;
530 r = radeon_cs_parser_init(&parser, data);
532 DRM_ERROR("Failed to initialize parser !\n");
533 radeon_cs_parser_fini(&parser, r);
534 r = radeon_cs_handle_lockup(rdev, r);
535 radeon_mutex_unlock(&rdev->cs_mutex);
538 r = radeon_cs_parser_relocs(&parser);
540 if (r != -ERESTARTSYS)
541 DRM_ERROR("Failed to parse relocation %d!\n", r);
542 radeon_cs_parser_fini(&parser, r);
543 r = radeon_cs_handle_lockup(rdev, r);
544 radeon_mutex_unlock(&rdev->cs_mutex);
547 r = radeon_cs_ib_chunk(rdev, &parser);
551 r = radeon_cs_ib_vm_chunk(rdev, &parser);
556 radeon_cs_parser_fini(&parser, r);
557 r = radeon_cs_handle_lockup(rdev, r);
558 radeon_mutex_unlock(&rdev->cs_mutex);
562 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
564 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
566 int size = PAGE_SIZE;
568 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
569 if (i == ibc->last_page_index) {
570 size = (ibc->length_dw * 4) % PAGE_SIZE;
575 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
576 ibc->user_ptr + (i * PAGE_SIZE),
583 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
586 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
588 int size = PAGE_SIZE;
589 bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
591 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
592 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
593 ibc->user_ptr + (i * PAGE_SIZE),
595 p->parser_error = -EFAULT;
600 if (pg_idx == ibc->last_page_index) {
601 size = (ibc->length_dw * 4) % PAGE_SIZE;
606 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
608 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
610 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
611 ibc->user_ptr + (pg_idx * PAGE_SIZE),
613 p->parser_error = -EFAULT;
617 /* copy to IB for non single case */
619 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
621 ibc->last_copied_page = pg_idx;
622 ibc->kpage_idx[new_page] = pg_idx;
627 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
629 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
630 u32 pg_idx, pg_offset;
634 pg_idx = (idx * 4) / PAGE_SIZE;
635 pg_offset = (idx * 4) % PAGE_SIZE;
637 if (ibc->kpage_idx[0] == pg_idx)
638 return ibc->kpage[0][pg_offset/4];
639 if (ibc->kpage_idx[1] == pg_idx)
640 return ibc->kpage[1][pg_offset/4];
642 new_page = radeon_cs_update_pages(p, pg_idx);
644 p->parser_error = new_page;
648 idx_value = ibc->kpage[new_page][pg_offset/4];