2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include <linux/vgaarb.h>
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
39 * Clear GPU surface registers.
41 void radeon_surface_init(struct radeon_device *rdev)
43 /* FIXME: check this out */
44 if (rdev->family < CHIP_R600) {
47 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
48 if (rdev->surface_regs[i].bo)
49 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
51 radeon_clear_surface_reg(rdev, i);
54 WREG32(RADEON_SURFACE_CNTL, 0);
59 * GPU scratch registers helpers function.
61 void radeon_scratch_init(struct radeon_device *rdev)
65 /* FIXME: check this out */
66 if (rdev->family < CHIP_R300) {
67 rdev->scratch.num_reg = 5;
69 rdev->scratch.num_reg = 7;
71 for (i = 0; i < rdev->scratch.num_reg; i++) {
72 rdev->scratch.free[i] = true;
73 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
77 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
81 for (i = 0; i < rdev->scratch.num_reg; i++) {
82 if (rdev->scratch.free[i]) {
83 rdev->scratch.free[i] = false;
84 *reg = rdev->scratch.reg[i];
91 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
95 for (i = 0; i < rdev->scratch.num_reg; i++) {
96 if (rdev->scratch.reg[i] == reg) {
97 rdev->scratch.free[i] = true;
104 * MC common functions
106 int radeon_mc_setup(struct radeon_device *rdev)
110 /* Some chips have an "issue" with the memory controller, the
111 * location must be aligned to the size. We just align it down,
112 * too bad if we walk over the top of system memory, we don't
113 * use DMA without a remapped anyway.
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
124 /* vram location was already setup try to put gtt after
126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
129 rdev->mc.gtt_location = tmp;
131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
132 printk(KERN_ERR "[drm] GTT too big to fit "
133 "before or after vram location.\n");
136 rdev->mc.gtt_location = 0;
138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
139 /* gtt location was already setup try to put vram before
141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
142 rdev->mc.vram_location = 0;
144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
145 tmp += (rdev->mc.mc_vram_size - 1);
146 tmp &= ~(rdev->mc.mc_vram_size - 1);
147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
148 rdev->mc.vram_location = tmp;
150 printk(KERN_ERR "[drm] vram too big to fit "
151 "before or after GTT location.\n");
156 rdev->mc.vram_location = 0;
157 tmp = rdev->mc.mc_vram_size;
158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
159 rdev->mc.gtt_location = tmp;
161 rdev->mc.vram_start = rdev->mc.vram_location;
162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
163 rdev->mc.gtt_start = rdev->mc.gtt_location;
164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
167 (unsigned)rdev->mc.vram_location,
168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
171 (unsigned)rdev->mc.gtt_location,
172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
178 * GPU helpers function.
180 bool radeon_card_posted(struct radeon_device *rdev)
184 /* first check CRTCs */
185 if (ASIC_IS_AVIVO(rdev)) {
186 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
187 RREG32(AVIVO_D2CRTC_CONTROL);
188 if (reg & AVIVO_CRTC_EN) {
192 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
193 RREG32(RADEON_CRTC2_GEN_CNTL);
194 if (reg & RADEON_CRTC_EN) {
199 /* then check MEM_SIZE, in case the crtcs are off */
200 if (rdev->family >= CHIP_R600)
201 reg = RREG32(R600_CONFIG_MEMSIZE);
203 reg = RREG32(RADEON_CONFIG_MEMSIZE);
212 bool radeon_boot_test_post_card(struct radeon_device *rdev)
214 if (radeon_card_posted(rdev))
218 DRM_INFO("GPU not posted. posting now...\n");
219 if (rdev->is_atom_bios)
220 atom_asic_init(rdev->mode_info.atom_context);
222 radeon_combios_asic_init(rdev->ddev);
225 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
230 int radeon_dummy_page_init(struct radeon_device *rdev)
232 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
233 if (rdev->dummy_page.page == NULL)
235 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
236 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
237 if (!rdev->dummy_page.addr) {
238 __free_page(rdev->dummy_page.page);
239 rdev->dummy_page.page = NULL;
245 void radeon_dummy_page_fini(struct radeon_device *rdev)
247 if (rdev->dummy_page.page == NULL)
249 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
250 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
251 __free_page(rdev->dummy_page.page);
252 rdev->dummy_page.page = NULL;
257 * Registers accessors functions.
259 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
261 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
266 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
268 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
273 void radeon_register_accessor_init(struct radeon_device *rdev)
275 rdev->mc_rreg = &radeon_invalid_rreg;
276 rdev->mc_wreg = &radeon_invalid_wreg;
277 rdev->pll_rreg = &radeon_invalid_rreg;
278 rdev->pll_wreg = &radeon_invalid_wreg;
279 rdev->pciep_rreg = &radeon_invalid_rreg;
280 rdev->pciep_wreg = &radeon_invalid_wreg;
282 /* Don't change order as we are overridding accessor. */
283 if (rdev->family < CHIP_RV515) {
284 rdev->pcie_reg_mask = 0xff;
286 rdev->pcie_reg_mask = 0x7ff;
288 /* FIXME: not sure here */
289 if (rdev->family <= CHIP_R580) {
290 rdev->pll_rreg = &r100_pll_rreg;
291 rdev->pll_wreg = &r100_pll_wreg;
293 if (rdev->family >= CHIP_R420) {
294 rdev->mc_rreg = &r420_mc_rreg;
295 rdev->mc_wreg = &r420_mc_wreg;
297 if (rdev->family >= CHIP_RV515) {
298 rdev->mc_rreg = &rv515_mc_rreg;
299 rdev->mc_wreg = &rv515_mc_wreg;
301 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
302 rdev->mc_rreg = &rs400_mc_rreg;
303 rdev->mc_wreg = &rs400_mc_wreg;
305 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
306 rdev->mc_rreg = &rs690_mc_rreg;
307 rdev->mc_wreg = &rs690_mc_wreg;
309 if (rdev->family == CHIP_RS600) {
310 rdev->mc_rreg = &rs600_mc_rreg;
311 rdev->mc_wreg = &rs600_mc_wreg;
313 if (rdev->family >= CHIP_R600) {
314 rdev->pciep_rreg = &r600_pciep_rreg;
315 rdev->pciep_wreg = &r600_pciep_wreg;
323 int radeon_asic_init(struct radeon_device *rdev)
325 radeon_register_accessor_init(rdev);
326 switch (rdev->family) {
336 rdev->asic = &r100_asic;
342 rdev->asic = &r300_asic;
343 if (rdev->flags & RADEON_IS_PCIE) {
344 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
345 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
351 rdev->asic = &r420_asic;
355 rdev->asic = &rs400_asic;
358 rdev->asic = &rs600_asic;
362 rdev->asic = &rs690_asic;
365 rdev->asic = &rv515_asic;
372 rdev->asic = &r520_asic;
382 rdev->asic = &r600_asic;
388 rdev->asic = &rv770_asic;
391 /* FIXME: not supported yet */
399 * Wrapper around modesetting bits.
401 int radeon_clocks_init(struct radeon_device *rdev)
405 r = radeon_static_clocks_init(rdev->ddev);
409 DRM_INFO("Clocks initialized !\n");
413 void radeon_clocks_fini(struct radeon_device *rdev)
417 /* ATOM accessor methods */
418 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
420 struct radeon_device *rdev = info->dev->dev_private;
423 r = rdev->pll_rreg(rdev, reg);
427 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
429 struct radeon_device *rdev = info->dev->dev_private;
431 rdev->pll_wreg(rdev, reg, val);
434 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
436 struct radeon_device *rdev = info->dev->dev_private;
439 r = rdev->mc_rreg(rdev, reg);
443 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
445 struct radeon_device *rdev = info->dev->dev_private;
447 rdev->mc_wreg(rdev, reg, val);
450 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
452 struct radeon_device *rdev = info->dev->dev_private;
457 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
459 struct radeon_device *rdev = info->dev->dev_private;
466 int radeon_atombios_init(struct radeon_device *rdev)
468 struct card_info *atom_card_info =
469 kzalloc(sizeof(struct card_info), GFP_KERNEL);
474 rdev->mode_info.atom_card_info = atom_card_info;
475 atom_card_info->dev = rdev->ddev;
476 atom_card_info->reg_read = cail_reg_read;
477 atom_card_info->reg_write = cail_reg_write;
478 atom_card_info->mc_read = cail_mc_read;
479 atom_card_info->mc_write = cail_mc_write;
480 atom_card_info->pll_read = cail_pll_read;
481 atom_card_info->pll_write = cail_pll_write;
483 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
484 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
485 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
489 void radeon_atombios_fini(struct radeon_device *rdev)
491 if (rdev->mode_info.atom_context) {
492 kfree(rdev->mode_info.atom_context->scratch);
493 kfree(rdev->mode_info.atom_context);
495 kfree(rdev->mode_info.atom_card_info);
498 int radeon_combios_init(struct radeon_device *rdev)
500 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
504 void radeon_combios_fini(struct radeon_device *rdev)
508 /* if we get transitioned to only one device, tak VGA back */
509 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
511 struct radeon_device *rdev = cookie;
512 radeon_vga_set_state(rdev, state);
514 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
515 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
517 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
520 void radeon_agp_disable(struct radeon_device *rdev)
522 rdev->flags &= ~RADEON_IS_AGP;
523 if (rdev->family >= CHIP_R600) {
524 DRM_INFO("Forcing AGP to PCIE mode\n");
525 rdev->flags |= RADEON_IS_PCIE;
526 } else if (rdev->family >= CHIP_RV515 ||
527 rdev->family == CHIP_RV380 ||
528 rdev->family == CHIP_RV410 ||
529 rdev->family == CHIP_R423) {
530 DRM_INFO("Forcing AGP to PCIE mode\n");
531 rdev->flags |= RADEON_IS_PCIE;
532 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
533 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
535 DRM_INFO("Forcing AGP to PCI mode\n");
536 rdev->flags |= RADEON_IS_PCI;
537 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
538 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
545 int radeon_device_init(struct radeon_device *rdev,
546 struct drm_device *ddev,
547 struct pci_dev *pdev,
553 DRM_INFO("radeon: Initializing kernel modesetting.\n");
554 rdev->shutdown = false;
555 rdev->dev = &pdev->dev;
559 rdev->family = flags & RADEON_FAMILY_MASK;
560 rdev->is_atom_bios = false;
561 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
562 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
563 rdev->gpu_lockup = false;
564 rdev->accel_working = false;
565 /* mutex initialization are all done here so we
566 * can recall function without having locking issues */
567 mutex_init(&rdev->cs_mutex);
568 mutex_init(&rdev->ib_pool.mutex);
569 mutex_init(&rdev->cp.mutex);
570 if (rdev->family >= CHIP_R600)
571 spin_lock_init(&rdev->ih.lock);
572 mutex_init(&rdev->gem.mutex);
573 rwlock_init(&rdev->fence_drv.lock);
574 INIT_LIST_HEAD(&rdev->gem.objects);
576 /* setup workqueue */
577 rdev->wq = create_workqueue("radeon");
578 if (rdev->wq == NULL)
581 /* Set asic functions */
582 r = radeon_asic_init(rdev);
587 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
588 radeon_agp_disable(rdev);
591 /* set DMA mask + need_dma32 flags.
592 * PCIE - can handle 40-bits.
593 * IGP - can handle 40-bits (in theory)
594 * AGP - generally dma32 is safest
597 rdev->need_dma32 = false;
598 if (rdev->flags & RADEON_IS_AGP)
599 rdev->need_dma32 = true;
600 if (rdev->flags & RADEON_IS_PCI)
601 rdev->need_dma32 = true;
603 dma_bits = rdev->need_dma32 ? 32 : 40;
604 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
606 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
609 /* Registers mapping */
610 /* TODO: block userspace mapping of io register */
611 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
612 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
613 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
614 if (rdev->rmmio == NULL) {
617 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
618 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
620 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
621 /* this will fail for cards that aren't VGA class devices, just
623 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
625 r = radeon_init(rdev);
629 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
630 /* Acceleration not working on AGP card try again
631 * with fallback to PCI or PCIE GART
633 radeon_gpu_reset(rdev);
635 radeon_agp_disable(rdev);
636 r = radeon_init(rdev);
640 if (radeon_testing) {
641 radeon_test_moves(rdev);
643 if (radeon_benchmarking) {
644 radeon_benchmark(rdev);
649 void radeon_device_fini(struct radeon_device *rdev)
651 DRM_INFO("radeon: finishing device.\n");
652 rdev->shutdown = true;
654 destroy_workqueue(rdev->wq);
655 vga_client_register(rdev->pdev, NULL, NULL, NULL);
656 iounmap(rdev->rmmio);
664 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
666 struct radeon_device *rdev = dev->dev_private;
667 struct drm_crtc *crtc;
670 if (dev == NULL || rdev == NULL) {
673 if (state.event == PM_EVENT_PRETHAW) {
676 /* unpin the front buffers */
677 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
678 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
679 struct radeon_bo *robj;
681 if (rfb == NULL || rfb->obj == NULL) {
684 robj = rfb->obj->driver_private;
685 if (robj != rdev->fbdev_rbo) {
686 r = radeon_bo_reserve(robj, false);
687 if (unlikely(r == 0)) {
688 radeon_bo_unpin(robj);
689 radeon_bo_unreserve(robj);
693 /* evict vram memory */
694 radeon_bo_evict_vram(rdev);
695 /* wait for gpu to finish processing current batch */
696 radeon_fence_wait_last(rdev);
698 radeon_save_bios_scratch_regs(rdev);
700 radeon_suspend(rdev);
701 radeon_hpd_fini(rdev);
702 /* evict remaining vram memory */
703 radeon_bo_evict_vram(rdev);
705 pci_save_state(dev->pdev);
706 if (state.event == PM_EVENT_SUSPEND) {
707 /* Shut down the device */
708 pci_disable_device(dev->pdev);
709 pci_set_power_state(dev->pdev, PCI_D3hot);
711 acquire_console_sem();
712 fb_set_suspend(rdev->fbdev_info, 1);
713 release_console_sem();
717 int radeon_resume_kms(struct drm_device *dev)
719 struct radeon_device *rdev = dev->dev_private;
721 acquire_console_sem();
722 pci_set_power_state(dev->pdev, PCI_D0);
723 pci_restore_state(dev->pdev);
724 if (pci_enable_device(dev->pdev)) {
725 release_console_sem();
728 pci_set_master(dev->pdev);
729 /* resume AGP if in use */
730 radeon_agp_resume(rdev);
732 radeon_restore_bios_scratch_regs(rdev);
733 fb_set_suspend(rdev->fbdev_info, 0);
734 release_console_sem();
736 /* reset hpd state */
737 radeon_hpd_init(rdev);
738 /* blat the mode back in */
739 drm_helper_resume_force_mode(dev);
747 struct radeon_debugfs {
748 struct drm_info_list *files;
751 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
752 static unsigned _radeon_debugfs_count = 0;
754 int radeon_debugfs_add_files(struct radeon_device *rdev,
755 struct drm_info_list *files,
760 for (i = 0; i < _radeon_debugfs_count; i++) {
761 if (_radeon_debugfs[i].files == files) {
762 /* Already registered */
766 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
767 DRM_ERROR("Reached maximum number of debugfs files.\n");
768 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
771 _radeon_debugfs[_radeon_debugfs_count].files = files;
772 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
773 _radeon_debugfs_count++;
774 #if defined(CONFIG_DEBUG_FS)
775 drm_debugfs_create_files(files, nfiles,
776 rdev->ddev->control->debugfs_root,
777 rdev->ddev->control);
778 drm_debugfs_create_files(files, nfiles,
779 rdev->ddev->primary->debugfs_root,
780 rdev->ddev->primary);
785 #if defined(CONFIG_DEBUG_FS)
786 int radeon_debugfs_init(struct drm_minor *minor)
791 void radeon_debugfs_cleanup(struct drm_minor *minor)
795 for (i = 0; i < _radeon_debugfs_count; i++) {
796 drm_debugfs_remove_files(_radeon_debugfs[i].files,
797 _radeon_debugfs[i].num_files, minor);